Power management system and method

Abstract

According to a specific implementation of the present disclosure, a power management method is disclosed. The method includes: in an active mode operation, a central processing unit calculates software instructions for a software workload, the software workload corresponding to a first operating point on a performance curve of a performance mode; transitioning from the instance of the active mode operation to the instance of the standby mode operation of the CPU, and recording each of a plurality of standby entry data points by a time tracking element; transitioning from the instance of the standby mode operation to the instance of the active mode operation of the CPU, and recording each of a plurality of standby exit data points by the time tracking element; and determining a second operating point on the performance curve of the performance mode based on the recorded standby entry data point and the recorded standby exit data point.

Description

[0001] STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with Government support under Agreement No. HR0011-17 9-0025 awarded by DARPA. The Government has certain rights in this invention. Technical Field

[0003] The present disclosure generally relates to power management systems and methods. Background Art

[0004] This section is intended to provide background information to facilitate a better understanding of the various techniques described herein. As the title of this section implies, this is a discussion of related art. The relevance of such technology does not mean that it is prior art. Related technology may or may not be prior art. Therefore, it should be understood that the statements in this section should be understood in this sense and not as an admission of prior art.

[0005] Dynamic voltage frequency scaling (DVFS) has been used to optimize dynamic power consumption in mobile / desktop application processors that are managed by an operating system. In operation, DVFS is a technique that reduces power consumption by dynamically adjusting the voltage and frequency of a computer processing unit (CPU) using discrete frequency and voltage settings of the CPU. However, despite the energy constraints imposed by small battery operation, this DVFS technique has not been widely used in embedded microcontroller units (MCUs).

[0006] In contrast, one power management approach implemented for MCUs includes power gating (with or without local state preservation). Currently, power gating has been used to reduce leakage power when the MCU is in standby mode. Furthermore, for Cortex-M systems, entry into such low leakage modes may need to be initiated by a wait for interrupt (WFI) instruction.

[0007] However, as MCUs are tasked with increasingly intense operations or "always-on" activities (e.g., voice detection), it is important to employ efficient active power management. Therefore, there is a need in the art for more optimized active power management. In addition, a particular challenge in using DVFS for MCU power management is determining when to run each frequency on the DVFS performance curve. While this consideration can be performed independently by software developers, a comprehensive hardware-based solution has not yet been developed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present technology will be further described by way of example with reference to the embodiments of the invention as shown in the accompanying drawings. However, it should be understood that the accompanying drawings only illustrate various specific implementations described herein and are not intended to limit the scope of the various techniques, methods, systems or devices described herein.

[0009] Figure 1 Diagrammatic representations of specific implementations in accordance with various techniques described herein are shown.

[0010] Figure 2 A block diagram of a system according to an implementation of the various techniques described herein is shown.

[0011] Figure 3 Flowcharts illustrating specific implementations of various techniques described herein are shown.

[0012] FIG. 4A to FIG. 4B Example diagrams illustrating specific implementations according to various techniques described herein are shown.

[0013] FIG. 5A to FIG. 5B Example diagrams illustrating specific implementations according to various techniques described herein are shown.

[0014] FIG. 6A to FIG. 6B Example diagrams illustrating specific implementations according to various techniques described herein are shown.

[0015] Figure 7 are specific illustrative aspects of methods according to implementations of the various techniques described herein.

[0016] In the following detailed description, reference is made to the accompanying drawings, which form part of the description, and throughout the description, similar numbers may represent similar parts, which are corresponding and / or similar. It should be understood that the drawings are not necessarily drawn to scale, such as for simplicity and / or clarity. For example, the dimensions of some aspects may be enlarged relative to other aspects. In addition, it should be understood that other embodiments may be used. In addition, without departing from the subject matter claimed for protection, structural and / or other changes may be made. The "claimed subject matter" mentioned throughout this specification refers to the subject matter intended to be covered by one or more claims or any part thereof, and is not necessarily intended to refer to a complete set of claims, a specific combination of claim sets (e.g., method claims, device claims, etc.) or a specific claim. It should also be noted that directions and / or references (e.g., such as upper, lower, top, bottom, etc.) can be used to facilitate discussion of the drawings and are not intended to limit the application of the claimed subject matter. Therefore, the following detailed description should not be understood as limiting the claimed subject matter and / or equivalents. DETAILED DESCRIPTION

[0017] According to a specific implementation of the present disclosure, a power management method is disclosed. The method includes: in an active mode operation, a central processing unit calculates software instructions for a software workload, the software workload corresponding to a first operating point on a performance curve of a performance mode; transitioning from the instance of the active mode operation to the instance of the standby mode operation of the CPU, and recording each of a plurality of standby entry data points by a time tracking element; transitioning from the instance of the standby mode operation to the instance of the active mode operation of the CPU, and recording each of a plurality of standby exit data points by the time tracking element; and determining a second operating point on the performance curve of the performance mode based on the recorded standby entry data point and the recorded standby exit data point.

[0018] According to another specific implementation of the present disclosure, a system is disclosed. The system includes: a central processor unit (CPU); a power management unit (PMU), the PMU coupled to the CPU; and a time tracking element, the time tracking element coupled to the CPU and the PMU. The PMU can be configured to control the time tracking element to record standby entry data points and standby exit data points of one or more code phases of a software workload. In addition, the CPU can be configured to determine an operating point on a performance curve based on the recorded standby entry data points and standby exit data points.

[0019] According to another specific implementation of the present disclosure, a method is disclosed. The method includes: sampling a standby time value of a software workload by a microcontroller device of a power management unit (PMU) when a power mode changes; and determining a performance mode corresponding to a specific operating point on a performance curve based on the sampled standby value.

[0020] According to a specific implementation of the present disclosure, a power management method is disclosed. The method includes: software instructions for calculating a software workload by a central processing unit in an active mode operation, the software workload corresponding to a first operating point on a performance curve of a performance mode; transitioning from an instance of the active mode operation to an instance of the standby mode operation of the CPU; transitioning from the instance of the standby mode operation to the instance of the active mode operation of the CPU; and determining a second operating point on the performance curve of the performance mode based on at least a portion of a plurality of standby entry data points and at least a portion of a plurality of standby exit data points. In addition, the plurality of standby entry data points may correspond to the transition from the active mode operation to the standby mode operation, and the plurality of standby exit data points may correspond to the transition from the standby mode operation to the active mode operation.

[0021] According to another specific implementation of the present disclosure, a computer system is disclosed. The computer system includes a computer processor unit (CPU) and a memory accessible to the CPU. The memory can store instructions, which can be executed by the CPU to perform operations including the following: providing a time tracking element to sample the standby time value of the software workload when the power mode changes; storing the sampled standby time value in a programmable memory; and modifying subsequent standby time values ​​based on the stored standby time value.

[0022] The specific implementation of the present disclosure is described below with reference to the accompanying drawings. In the description, common features are represented by common reference numerals throughout the drawings.

[0023] In an exemplary aspect, the systems and methods of the present disclosure provide runtime power management to optimize real-time power performance. Advantageously, in certain embodiments, based on the standby tracking characteristics, these systems and methods can automatically "adjust" (i.e., update, offset) the operating point of a particular performance mode (e.g., a DVFS mode configuration). In addition, when adjusting the operating point, the systems and methods described herein can automatically perform an "optimized" performance mode for a single-phase or multi-phase software workload. Thus, for example, when "learning" (through data point aggregation) that active power operations can run at a lower power level for a longer time interval, the system and computer-implemented methods will be guided to do so. As another advantage, these systems and methods can be implemented for embedded microcontrollers (e.g., "always-on" power controllers) and other alternative operating system-managed computer systems.

[0024] Advantageously, whether by computer-implemented software (in a central processing unit (CPU)) or by hardware (in a power management unit (PMU)), the disclosed system (and method according to the present invention) can monitor (i.e., check) and record data values ​​in real time when an embedded microcontroller (or other managed computer system) enters or "wakes up" from a sleep mode. In doing so, according to one example, within a determined period of time, the system of the present invention will gain "confidence" that a particular software workload can be run in a slower mode at a lower voltage level because the active power has not deviated from the current mode (there will be sufficient remaining standby time).

[0025] In some implementations, as described herein, DVFS can be used as a performance mode to exploit the relationship between speed and power consumption as a function of power supply voltage. For example, the speed of CMOS logic can be proportional to the power supply voltage, and the power consumption of CMOS logic can be proportional to the square of the power supply voltage (V 2 ). Therefore, by reducing the power supply voltage to an exemplary minimum level that can provide the required performance, power consumption can be significantly reduced.

[0026] refer to Figure 1 , an exemplary power management performance graph / map 100 is shown. As depicted, the power management performance map 100 (i.e., graph 100) includes a frequency range (kHz) (approximately 10 to 100,000) on the Y-axis 110 as a function of a voltage range (V) (approximately 0.3 to 1.1) on the X-axis 120. In one example, as Figure 1 As shown, a series of expected operating points 132 (i.e., a plurality of operating points) form a performance curve 130 (i.e., a performance spectrum) on the performance map 100. In various implementations, the performance curve 130 can represent different performance points of a particular power consumption mode of a computer system (e.g., an embedded microcontroller). In a first example, referring to Figure 1 , the performance curve 130 may correspond to a dynamic voltage and frequency scaling (DVFS) mode (e.g., a first performance mode). In a second example (not shown), the performance curve may correspond to a frequency scaling mode with body bias at ISO voltage (e.g., a second performance mode). In the second example, the power management performance map 100 will include a frequency range (kHz) on the Y-axis as a function of the body bias range on the X-axis. Thus, in this manner, for various performance modes, a reduction in operating frequency will prompt the determination of a new performance operating point. Thus, in some aspects, these systems and methods may also be used to determine when to operate at each specific frequency on a specific performance curve (e.g., a DVFS performance curve).

[0027] refer to Figure 2 , an exemplary system 200 is shown. The system 200 (e.g., a computer system) includes a central processor unit (e.g., CPU, CPU subsystem) 210, a power management unit (PMU) 220, and a time tracking element 230 (e.g., a standby tracking device, such as a real-time clock (RTC)). The CPU 210, the PMU 220, and the time tracking element 230 may be electrically coupled to each other. In certain specific implementations, the PMU 220 may be configured to control the time tracking element 230 to record standby entry data points and standby exit data points (i.e., statistics, metrics) for one or more code phases of a software workload. In addition, the CPU 220 may be configured to determine an operating point for a particular performance mode (e.g., an operating point 132 of a dynamic voltage frequency scaling (DVFS) curve 130) based on the recorded standby entry data points and standby exit data points.

[0028] In one implementation, a code phase may include a specific duty cycle of a software workload (e.g., one instance of an active mode (i.e., an active power mode, an active phase) and one instance of a standby mode operation (i.e., a standby power mode, a standby phase)). In another implementation, a code phase may include multiple identical active phases and standby phases of a software workload. In various cases, the software workload may be a single software workload (e.g., as described in reference to FIG. 4A to FIG. 4B ) or a multi-phase software workload (e.g., as described in reference FIG. 5A to FIG. 5B described above).

[0029] PMU 220 may be (or include) a microcontroller to manage power functions of the digital platform. PMU 220 may include firmware (to provide low-level control for hardware), software, memory, processing subsystems, input / output functions, timers (to measure time intervals), and analog-to-digital converters (to measure the voltage of the main battery or power of system 200). In some aspects, PMU 220 remains active even though system 200 may be completely shut down and may be powered by a backup battery.

[0030] In certain implementations, the PMU 220 may coordinate various functions, including: monitoring power connections and battery charging; charging the battery when needed; controlling power to other integrated circuits; shutting down unnecessary system components when idle; controlling sleep functions and power functions (e.g., on and off); and regulating a time tracking element 230 (e.g., a real-time clock (RTC)).

[0031] In operation, specifically, PMU 220 may be configured to: initialize software instructions for a particular software workload; sequence CPU 210 into an instance of standby mode operation when CPU 210 is notified that it is "sleeping" (i.e., suspended, suspended to random access memory (RAM), transitioning to standby mode); and "wake up" CPU 210 when time tracking element 230 is activated (e.g., when the RTC sounds an alarm).

[0032] In addition, according to the exemplary process, PMU 220 may also be configured to provide an operating voltage (e.g., a low operating voltage) (i.e., a "lower" VDD) and a clock signal ("Clock") to set an optimal DVFS mode to achieve an optimized performance mode. In some cases, PMU 220 may be included inside a system on chip (SOC), and in other cases, PMU 220 may be included outside the SOC.

[0033] In operation, the CPU 210 may be configured to evaluate the recorded standby entry data points and standby exit data points based on the standby periodicity and the standby regularity. In doing so, in some cases, the CPU 210 may be configured to calculate a duty cycle and a minimum time interval for a particular standby mode operation. Further, in such cases, the duty cycle may be a quotient of a weighted active time interval and a weighted standby time interval for a particular software workload.

[0034] In operation, specifically, the time tracking element 230 (e.g., standby tracking element) can be configured to track the standby time interval through one of a real-time clock (RTC), a voltage measurement device, a resistor-capacitor (RC) time constant, and a leakage (remaining time) measurement. In some implementations, an alarm triggered by the time tracking element 230 (e.g., real-time clock) can be configured ("programmed") to provide a subsequent initiation of an active mode operation ("future wakeup") of the CPU.

[0035] In some aspects, the transition to the standby mode operation may be performed in response to one of: a sleep mode or a wait for interrupt (WFI) instruction of the CPU 210. Also, in some aspects, the transition to the active mode operation is performed in response to one of: an active mode operation request of the CPU 210, activation of an alarm of the time tracking element 230 (e.g., an RTC alarm), an internal interrupt instruction, or an external interrupt instruction.

[0036] In some specific implementations, the recording of standby entry data points and the recording of standby exit data points may include: updating standby statistics, wherein updating the standby statistics may include storing the recorded standby entry data points and the recorded standby exit data points (i.e., the resulting data) in a programmable memory (e.g., a non-volatile memory (NVM), a trigger, or a static random access memory (SRAM)) of the CPU 210 or the PMU 220.

[0037] refer to Figure 3, an exemplary power management process flow diagram 300 that may be implemented using the system 200 is shown. As shown, in one exemplary operation, the power management process flow diagram 300 is depicted as a "smart" DVFS / standby cycle. At step 310, the CPU 210 may execute a software workload (SW) until a standby mode (e.g., fixed low power operation) is desired. At step 320, based on the standby mode request, the time tracking element 230 (e.g., a real-time clock (RTC) alarm) may be programmed to provide a future CPU 210 "wake-up" (i.e., transition to active mode operation). Next, at step 330, upon receiving an instruction that the CPU 210 has actually transitioned to standby mode (i.e., "the CPU is sleeping"), the PMU 220 may initiate a "sampling" of the time tracking element 230 (e.g., RTC). In doing so, the PMU 220 may record each of the standby entry data point and the standby exit data point (i.e., data metrics, data statistics) (e.g., a "grab" of sensor data readings). In some implementations, the standby entry data points and the standby exit data points may be stored and aggregated in a programmable memory (e.g., non-volatile memory (NVM) or retention SRAM) of the CPU 210 of the system 200. The "sampling" operation is further described with reference to FIG. 6. At step 340, the PMU 210 may be configured to sort the CPU 210 into standby mode operation. In some implementations, the sorting of the CPU 210 may take into account a determined length (e.g., in ms) of a particular standby mode operation interval and a determined active power (e.g., in MHz) and the length of the active mode operation interval (e.g., in ms). At step 350, when the time tracking element 230 (e.g., RTC) issues an alarm, the PMU 220 will wake up the CPU 210, sample the time tracking element 230 (e.g., RTC) again, and update the standby entry data points and the standby exit data points (i.e., standby statistics). Next, at step 360, PMU 2020 will provide an updated operating point (e.g., a "highest" DVFS operating point) while "learning" (as described in the next paragraph) (i.e., determining a "second" operating point), and will set the optimal DVFS mode (i.e., executing a performance mode based on the second operating point). After step 360, process 300 may continue back to step 310 and begin the process again.

[0038] In some implementations, the second operating point may be determined by one or more of the following steps (in the next paragraph): 1) reducing the activity performance (i.e., activity power) to a minimum level of acceptable quality of service that does not delay the next "wake-up" event (i.e., transition to the active phase); or alternatively, 2) increasing the activity performance so that optimal performance can be achieved. Thus, the second operating point may correspond to an increase or decrease relative to the first operating point (with reference to a performance mode curve (e.g., performance mode curve 130) of a performance operation map (e.g., map 100)), whereby an increase (relative to the first operating point) will correspond to a prolongation of the active phase operation (i.e., active mode operation), while a decrease (relative to the first operating point) will correspond to a shortening of the active phase operation.

[0039] These steps may include: 1) evaluating recorded standby entry data points and recorded standby exit data points (based on standby periodicity and standby regularity); 2) determining the cost (i.e., the "performance or energy overhead" of changing the DVFS operating point (e.g., reference FIG. 6A to FIG. 6B )); 3) power supply delays (i.e., DC to DC converter (DC-DC converter) (e.g., integrated voltage regulator (IVR) delays); 4) determining the time interval for software workload (i.e., the "size" of the task interval); and / or 5) determining the time interval for transitioning from active mode operation to standby mode operation, or vice versa.

[0040] In one specific implementation, evaluating the recorded standby entry data points and the recorded standby exit data points may further include calculating a duty cycle and a minimum time interval of the standby mode operation, wherein the duty cycle corresponds to a quotient of a weighted active time interval of the software workload and a weighted standby time interval.

[0041] refer to FIG. 4A to FIG. 4B , showing that before active power management according to aspects of the present invention ( Figure 4A 400) and after ( Figure 4B 450) of one or more code phases 410. As shown, a power mode (e.g., active mode 412 or standby mode operation 414) (i.e., execution of software instructions of a software workload) over a period of time (i.e., milliseconds (ms)) can be depicted for a particular sensing example. As shown, the exemplary code phases 410 can represent a repetitive single task of a single phase (e.g., a software workload) that transitions from an instance of active mode operation 412 to an instance of standby mode operation 414 (i.e., a standby phase) (e.g., a fixed low power operation) at fixed intervals.

[0042] like Figure 4A As shown, in the active power management process (e.g., process 300, 700, reference Figure 2 , Figure 3 and Figure 7 ), in one example, each of the active mode operations 412 (ie, active phases) may be run at 40 MHz for a duration of 0.1 ms. Figure 4B In the active power management process 400 (eg, reference Figure 2 , Figure 3 and Figure 7 ), the active mode operation 412 will be optimized (e.g., based on the adjustment / updated operating point of the standby data point aggregation) so that each active phase 412 can be "stretched" to the corresponding standby phase 414 (i.e., standby mode operation). Figure 4B As shown, when optimized, in a particular example, the active mode operation 412 can run at 4 MHz for a longer duration. Thus, advantageously, by monitoring the active time and standby time of a particular repetitive sensing task (e.g., recording and aggregating (storing) standby data points according to the exemplary processes 300, 700 described herein, including steps such as: "waking up" at fixed intervals; "grabbing" sensor data readings; performing sanity checks; and storing / aggregating sensor data readings), an opportunity to reduce clock operation speed by nearly 90% and reduce active energy by approximately 75% can be achieved.

[0043] Advantageously, the disclosed system (and method according to the present invention) can record (i.e., sample) and aggregate data values ​​in real time when an embedded microcontroller (or other managed computer system) enters or "wakes up" from sleep mode, either through computer-implemented software (in a central processing unit (CPU)) or through hardware (in a power management unit (PMU)). In doing so, over a determined period of time (e.g., one hour, one day), the disclosed system will gain "confidence" that the software workload can run in a slower mode at a lower voltage level because the active power has not deviated from the current mode (there will be sufficient remaining standby time).

[0044] refer to FIG. 5A to FIG. 5B , showing that before active power management according to aspects of the present invention ( Figure 5A 500) and after ( Figure 5B550 in FIG. 551 ). As shown, a power mode (e.g., active mode operation 512, 513 or standby mode operation 514, 515) (i.e., execution of software instructions of two or more software workloads) over a period of time (i.e., milliseconds (ms)) may be depicted for a particular sensing example. The exemplary code phases 510, 511 may represent a repetitive single task of multiple phases (i.e., multiple phases) (e.g., two or more software workloads) that transition from active mode operation 512, 513 to standby mode operation 514, 515 (e.g., low power operation) at different intervals.

[0045] like Figure 5A As shown, in the active power management process (e.g., process 300, 700, reference Figure 2 , Figure 3 and Figure 7 ), two or more active mode operations (eg, first active mode operation 512 and second active mode operation 513) may be run at 40 MHz for durations of 0.1 ms and 0.5 ms, respectively. Figure 5B In the active power management process (e.g., process 300, 700, reference Figure 2 , Figure 3 and Figure 7 , and based on the “worst case” phase), the active mode operations 512, 513 will be optimized (i.e., two or more operating points adjusted / updated based on the standby data point aggregation) (e.g., the first operating point and the second operating point corresponding to the respective first DVFS mode and the second DVFS mode) so that the active phases 512, 513 can be “stretched” to the respective standby phases 514, 515. Therefore, as Figure 5B As shown, when optimized, in a particular example, active mode operations 512, 513 may run at 20 MHz for durations of 0.1 ms and 0 ms, respectively.

[0046] In FIG. 5 , the power management optimization for this particular scenario corresponds to the “worst case” phase (i.e., the most active phase). Thus, to account for such scenarios, systems and methods as described herein may distinguish between different active phases based on the CPU's instruction pointer (i.e., program counter) and utilize aggregated standby data to reduce frequency (and move to a lower position on the exemplary performance curve; therefore, reduce voltage), but still ensure that one or more software workloads will meet any time deadline (e.g., the next “wake-up” followed by a transition to the active phase). Correspondingly, for example, the second DVFS mode may be configured to set the active mode operation 512 , 513 to be substantially equal to the active mode of the code phase with the longest time interval (i.e., the “worst case” code phase: which will be analyzed to provide performance that does not violate the shortest standby phase and is therefore optimized for the longest code phase). In certain specific implementations, parameters used to determine the decision threshold include, but are not limited to: 1) the performance or energy overhead (i.e., cost) of changing the DVFS level; 2) IVR latency; and 3) the size of the task interval.

[0047] Thus, advantageously, by monitoring active and standby time (e.g., recording and aggregating standby data points according to exemplary processes 300, 700 described herein) for a repetitive single task over multiple phases (i.e., multiple software workloads) (e.g., comprising the steps of: "waking up" at fixed intervals; "grabbing" sensor data readings; performing sanity checks; then storing / aggregating sensor data readings; occasionally bursting "bunches" of accumulated sensor data readings), an opportunity to reduce clock operation speed by nearly 50%, and thereby reduce active energy by approximately 40%, may be achieved.

[0048] In a specific exemplary use case, the multi-phase (i.e., one or more software workloads) may be, but is not limited to, an electrocardiogram (ECG) heart rate monitor, a conference room people counter, audio keyword spotting, etc. Multi-phase may be a more complex case compared to a single phase, for example, a designer / programmer may run the following in sequence: 100 wake / sleep samples of 20k instructions, then a single 100k instruction phase, then back to 100 wake / sleep samples of 20k instructions.

[0049] In some specific implementations, when the software workload includes a multi-phase workload, the operation will further include the following steps: 1) classifying each code phase in the code phases of the multi-phase workload, wherein each code phase can correspond to a specific software workload of the multi-phase workload; 2) tracking each code phase in the code phases by recording standby entry data points and standby exit data points corresponding to the classified software workload; and determining a different operating point on the corresponding performance curve for each code phase in the tracked code phases.

[0050] refer to FIG. 6A to FIG. 6B , in one example, Figure 5A Two or more different exemplary code phases 510, 511 in FIG. 5 are shown before active power management according to aspects of the present invention ( Fig. 6A 600) and after ( Figure 6B 650) of two or more different exemplary code phases 610, 611. As shown in the figure, Fig. 6A , power modes (e.g., active mode operations 612, 613 and standby mode operations 614, 615) (i.e., execution of software instructions of two or more software workloads) over a period of time (i.e., milliseconds (ms)) may be depicted for a particular sensing instance. The exemplary code phases 610, 611 may represent a repetitive single task of multiple phases (i.e., multiple phases) (e.g., two or more software workloads) transitioning from active mode operations 612, 613 to standby mode operations 614, 615 (e.g., low power operations) at different intervals.

[0051] Further references Figure 5A ,exist Fig. 6A In , the energy cost 630 associated with entering and exiting standby mode operation may also be considered. In some cases, due to the energy cost 630 (e.g., due to allowing the decoupling capacitors to collapse, thus potentially requiring recharging, and due to associated logic failures during the "power-up" period), the overall energy savings may only be realized after a certain "break-even" time. Fig. 6A As shown, at 640, the energy consumed by entering and exiting the standby mode operation (E entry-exit ) is shown to be much smaller than the energy saved (E save )(E entry-exit < <E save ). Therefore, if Figure 6B As shown, a transition to standby operation will be performed because energy savings will be achieved. Fig. 6A As shown, at 650, the energy consumed by entering and exiting the standby mode operation (E entry-exit ) is shown to be greater than the energy saved (E save )(E entry-exit >E save ). Therefore, if Figure 6B As shown, during optimization, the active mode operation of the second code phase 611 can be "stretched" to fully incorporate a particular standby mode operation between the second code phase 611 and the following instance of the first code phase 610. Advantageously, such optimization of the active phase can occur while adhering to quality of service (QoS) requirements. Thus, for example, if the optimized standby operation time (i.e., the post-DVFS standby time) can be predicted to be below the break-even time (e.g., E save ), then entering and exiting standby operation may not be beneficial and, therefore, this overhead (ie, cost) may be avoided.

[0052] refer to Figure 7 , shows a method 700 for automatically optimizing performance mode based on adjusting / updating operating points based on statistics of standby mode usage (ie, standby entry data points and standby exit data points, metrics) of these operating points. In some cases, the method 700 can be used for active power management of a microcontroller.

[0053] At block 710, the method 700 includes computing (i.e., executing, initializing) by a computer processing unit (CPU, CPU subsystem) in an active mode (i.e., active power mode) operation software instructions (i.e., sensing tasks) of a software workload corresponding to a first operating point of a performance mode (e.g., a DVFS mode based on a predetermined or predefined first operating point on a DVFS curve (i.e., DVFS spectrum) of an embedded microcontroller unit (MCU)). For example, referring to Figure 1 6 , the CPU 210 will execute a software workload corresponding to a first operating point of the plurality of operating points 132 for a particular performance mode (eg, DVFS mode).

[0054] At block 720, method 700 includes transitioning from an instance of active mode operation to an instance of standby mode operation of the CPU (i.e., a low power mode), and recording (i.e., sampling, "tracking / grabbing" sensor data readings, details, logs) each of a plurality of standby entry data points (i.e., metrics, states) by a time tracking element (e.g., a programmable real time clock (RTC) alarm). For example, in reference to Figure 1 6, the PMU 220 may be configured to sequence the CPU 210 from active mode operation to standby mode operation, and vice versa. Additionally, the time tracking element 230 may be configured to sample standby entry data points.

[0055] At block 730, the method includes transitioning from an instance of standby mode operation to an instance of active mode operation of the CPU (e.g., a future "wake-up"), and recording (i.e., sampling, "tracking / grabbing" sensor data readings, details, logs) each of a plurality of standby exit data points (i.e., metrics, states) by a time tracking element. For example, in reference to Figure 1 6, the PMU 220 may be configured to wake up the CPU 210 from the standby mode operation to the active mode operation, and vice versa. In addition, the time tracking element 230 may be configured to sample the standby exit data point.

[0056] At block 740, the method includes determining a second operating point of the performance mode based on the recorded standby entry data point and the recorded standby exit data point. Figure 1 In various implementations described with reference to FIG. 6 , PMU 220 may be configured to provide an updated (“optimized”) operating point (eg, a “highest” DVFS operating point).

[0057] In an exemplary implementation, the method includes determining a second operating point on a performance curve for the performance mode based on at least a portion of a plurality of standby entry data points and at least a portion of a plurality of standby exit data points, wherein the plurality of standby entry data points correspond to a transition from an active mode operation to a standby mode operation, and wherein the plurality of standby exit data points correspond to a transition from a standby mode operation to an active mode operation. Figure 1 6, the PMU 220 may be configured to sequence the CPU 210 from the active mode of operation to the standby mode of operation, and vice versa. In addition, the time tracking element 230 may be configured to sample standby entry data points and standby exit data points corresponding to respective transitions from the active mode of operation to the standby mode of operation, and vice versa.

[0058] In another exemplary aspect, the method includes executing a performance mode based on the second operating point, wherein executing the performance mode includes providing an operating voltage and a clock signal to the CPU by the PMU. Figure 1 6, the CPU 210 may be provided (ie, controlled to supply) an operating voltage (ie, a "higher" or "lower" voltage (eg, Figure 2 VDD in)) and clock signals (e.g. Figure 2 ) to execute a performance mode (eg, at step 360, setting an optimal DVFS mode).

[0059] In further exemplary aspects, determining the second operating point may include one or more of the following: 1) evaluating the recorded standby entry data points and the recorded standby exit data points based on the standby periodicity and the standby regularity; 2) determining the cost (i.e., the "performance or energy overhead" of changing the operating point (e.g., as referenced in FIG. 6A to FIG. 6B described); 3) determining power supply delays (i.e., DC to DC converter (DC-DC converter) (e.g., integrated voltage regulator (IVR) delays); 4) determining the time interval of the software workload (i.e., the "size" of the task interval); and / or 5) determining the time interval for transitioning from active mode operation to standby mode operation, or vice versa.

[0060] In further illustrative aspects, evaluating recorded standby entry data points and recorded standby exit data points (i.e., recorded statistics, recorded metrics) may include calculating a duty cycle and a minimum time interval for standby mode operation, where the duty cycle will correspond to the quotient of a weighted active time interval and a weighted standby time interval for a particular software workload.

[0061] In some implementations, the operation of the present invention may require earlier calculation results (e.g., associated with a previous operating point), even at the expense of efficiency. Advantageously, in such cases, the operation (by software) may set an override bit to disable automatic adjustment of performance. In doing so, the operation will also be configured to disable associated active mode and standby mode recording (e.g., analysis, monitoring) to avoid "polluting" statistical information collection (e.g., data point aggregation) in other code phases. Advantageously, such an implementation may be useful in a radio frequency identification (RFID) sensor network, where only one tag may be currently active, and the RFID reader may want to shut down earlier to save 1 to 2 watts of radio frequency (RF) transmission power.

[0062] Depending on the particular scheme and technology, various implementations may be performed in hardware or software. In one example, a particular hardware implementation will include an "always-on" power controller (e.g., including a processor and memory) to sample and store data values ​​(i.e., data points, measurement interrupts) when the power controller "acts" (e.g., initiates, schedules) a power mode change request (e.g., a standby entry of a wait interrupt (WFI) and an internal or external "wake-up"). In doing so, the power controller can then determine an optimization (i.e., an adjustment of the operating point of the performance mode based on the statistical value of standby mode usage) and implement the optimization. In another example, a computer-implemented software implementation may include a processor-accessible memory, wherein the memory may store instructions that are executable by the CPU to perform operations. These operations will include: providing a time tracking element (e.g., a standby tracking device) to sample the standby time value (e.g., standby time interval) of the software workload when the power mode changes (e.g., a change request); and storing the sampled standby time value (i.e., the resulting data) in a programmable memory (e.g., NVM or retention SRAM).

[0063] Aspects of the present disclosure may be combined in a system, method, and / or computer program product. A computer program product may include one or more computer-readable storage media having computer-readable program instructions thereon for causing a processor to perform various aspects of the present disclosure. A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing devices. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device (such as a punch card or a raised structure in a groove with instructions recorded thereon), and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses delivered through fiber optic cables), or electrical signals transmitted through wires. For example, the memory and / or storage device of the CPU 210 or PMU 220 in the system 200 may include a tangible, non-transitory computer-readable medium or storage device.

[0064] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network may include copper transmission cables, fiber optic transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the corresponding computing / processing device.

[0065] The computer-readable program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++ and procedural programming languages ​​such as "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer, and partially on a remote computer or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some specific implementations, an electronic circuit (including, for example, a programmable logic circuit, a field programmable gate array (FPGA) or a programmable logic array (PLA)) may execute computer-readable program instructions by personalizing the electronic circuit using the state information of the computer-readable program instructions so as to perform various aspects of the present disclosure.

[0066] Various aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart illustration and / or block diagram and the combination of blocks in the flowchart illustration and / or block diagram can be implemented by computer-readable program instructions.

[0067] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions are executed via the processor of the computer or other programmable data processing device. A machine is an example of a device for implementing the functions / actions specified in the flowchart and / or block diagram. The computer-readable program instructions may also be stored in a computer-readable storage medium, which may instruct a computer, a programmable data processing device, and / or other equipment to act in a particular manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in the flowchart and / or block diagram.

[0068] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to perform a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in the flowchart and / or block diagram.

[0069] The term "processor" is generally used herein to refer to a microprocessor or processing device integrated in a single integrated circuit or chip, which systematically performs operations in a preset order under the control of software code. The term "system on chip" (SOC) is generally used herein to refer to a processing device that integrates various functional blocks (e.g., central processing unit (CPU), memory, interface unit, digital signal processing circuit, analog signal processing circuit, etc.) in a single or several semiconductor integrated circuits (ICs) to implement an electronic system such as a computer system using a limited number of integrated circuits. The SOC may include various functions such as processor functions, multimedia functions, graphics functions, interface functions, and security functions.

[0070] The flow chart and block diagram in the figure show the possible specific implementation architecture, function and operation of the system, method and computer program product according to various specific implementations of the present disclosure. In this regard, each frame in the flow chart or block diagram may represent a module, segment or part of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative specific implementations, the function marked in the frame in the figure may not match the order marked in the figure. For example, the two frames shown in succession can be executed substantially simultaneously, or these frames can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each frame of the block diagram and / or flow chart and the combination of frames in the block diagram and / or flow chart can be implemented by a system based on special-purpose hardware, which performs specified functions or actions, or performs a combination of special-purpose hardware and computer instructions.

[0071] In the following description, numerous specific details are set forth to provide a thorough understanding of the disclosed concepts, which concepts may be implemented without some or all of these details. In other cases, details of known devices and / or processes have been omitted to avoid unnecessarily obscuring the present disclosure. Although some concepts will be described in conjunction with specific examples, it should be understood that these examples are not intended to be limiting.

[0072] Unless otherwise indicated, the terms "first," "second," and the like are used herein merely as labels and are not intended to impose ordinal, positional, or hierarchical requirements on the items to which these terms refer. Further, reference to an item, such as "second," does not require or preclude the existence of an item, such as "first," or lower-numbered, and / or an item, such as "third," or higher-numbered.

[0073] References to "one example" herein mean that one or more features, structures, or characteristics described in conjunction with the example are included in at least one specific implementation. The phrase "one example" in different places in the specification may or may not refer to the same example.

[0074] Provided below are illustrative, non-exhaustive examples according to the subject matter of the present disclosure, which examples may or may not claim protection. The different examples of the apparatus and method disclosed herein include a variety of components, features, and functions. It should be understood that the various examples of the apparatus and method disclosed herein may include any combination of any components, features, and functions of any other example of the apparatus and method disclosed herein, and all such possibilities are intended to fall within the scope of the present disclosure. The present disclosure belongs to a field of technology that will think of many modifications of the examples set forth herein, which benefit from the teachings presented in the foregoing description and associated drawings.

[0075] Therefore, it should be understood that the present disclosure is not limited to the specific examples shown, and modifications and other examples are intended to be included within the scope of the appended claims. In addition, although the foregoing description and associated drawings describe examples of the present disclosure in the context of certain illustrative combinations of elements and / or functions, it should be understood that different combinations of elements and / or functions may be provided by alternative specific implementations without departing from the scope of the appended claims. Therefore, the reference numerals in parentheses in the appended claims are presented for illustrative purposes only and are not intended to limit the scope of the claimed subject matter to the specific examples provided in the present disclosure.

Claims

1. A method for power management, the method comprising: computing, by the central processing unit CPU, software instructions for a software workload in an active mode of operation, the software workload corresponding to a first operating point on a performance curve for a performance mode; transitioning from an instance of said active mode operation to an instance of said CPU's standby mode operation; transitioning from said instance of said standby mode operation to said instance of said active mode operation of said CPU; and A second operating point on the performance curve of the performance mode is determined based on a first standby entry data point and a second standby entry data point of a plurality of standby entry data points and a first standby exit data point and a second standby exit data point of a plurality of standby exit data points, wherein: The first standby exit data point and the first standby entry data point occur successively, The second standby exit data point and the second standby entry data point occur successively, the plurality of standby entry data points corresponding to the transition from the active mode operation to the standby mode operation, The plurality of standby exit data points correspond to the transition from the standby mode operation to the active mode operation, and A difference between the first standby exit data point and the first standby entry data point is different from a difference between the second standby exit data point and the second standby entry data point.

2. The method according to claim 1, further comprising: The performance mode is executed based on the second operating point, wherein executing the performance mode includes providing an operating voltage and a clock signal to the CPU by a power management unit (PMU), and wherein the performance mode corresponds to a dynamic voltage frequency scaling (DVFS) mode or a frequency adjustment mode by body biasing at an ISO voltage.

3. The method of claim 1 , wherein the transition to the standby mode operation is performed in response to one of: a sleep mode of the CPU or a wait-for-interrupt (WFI) instruction, and wherein the transition to the active mode operation is performed in response to one of: an active mode operation request of the CPU, activation of an alarm of a time tracking element, an internal interrupt instruction, or an external interrupt instruction.

4. The method according to claim 1, further comprising: At least a portion of the plurality of standby entry data points are recorded in a programmable memory of the CPU, and at least a portion of the plurality of standby exit data points are recorded in the programmable memory of the CPU.

5. The method of claim 1 , wherein determining the second operating point comprises one or more of: evaluating at least a portion of the plurality of standby entry data points and at least a portion of the plurality of standby exit data points; determining a cost of changing the first operating point; Determine the power supply delay, determining a time interval for the software workload, and Time intervals for transitions from the active mode operation to the standby mode operation and from the standby mode operation to the active mode operation are determined.

6. The method of claim 5, wherein evaluating at least the portion of the plurality of standby entry data points and at least the portion of the plurality of standby exit data points comprises: A duty cycle and a minimum time interval of the standby mode operation are calculated, wherein the duty cycle corresponds to a quotient of a weighted active time interval and a weighted standby time interval of the software workload.

7. The method of claim 1, wherein the second operating point corresponds to a decrease from the first operating point on the performance mode curve of a relative performance operating map, and wherein the decrease corresponds to a shortening of the active mode operation.

8. The method of claim 1, wherein the software workload comprises a single-phase or multi-phase workload.

9. The method of claim 8, wherein if the software workload includes the multi-phase workload, the second operating point corresponds to a second DVFS mode configured to set the active mode operation equal to the active mode of the code phase having the longest time interval.

10. The method of claim 8, wherein if the software workload includes the multi-phase workload, the method further comprises: classifying one or more code phases of the multi-phase workload, wherein each of the one or more code phases corresponds to a specific software workload of the multi-phase workload; tracking the one or more code phases by recording the plurality of standby entry data points and the plurality of standby exit data points corresponding to respective classified software workloads; as well as A different operating point on a corresponding performance curve is determined for each of the tracked code phases.

11. The method of claim 1 , wherein a time tracking element is configured to track the transition from the active mode operation to the standby mode operation, and the transition from the standby mode operation to the active mode operation, and wherein the time tracking element comprises one of a real time clock (RTC), a voltage measurement device, a resistor-capacitor (RC) time constant, and a leakage measurement.

12. A system for power management, the system comprising: Central Processing Unit CPU; a power management unit (PMU), the PMU being coupled to the CPU; as well as a time tracking element coupled to the CPU and the PMU, wherein the PMU is configured to control the time tracking element to record successive standby entry data points and standby exit data points of one or more code phases of a software workload, wherein the CPU is configured to determine an operating point on a performance curve based on a first standby entry data point and a second standby entry data point among the standby entry data points and a first standby exit data point and a second standby exit data point among the standby exit data points, wherein: The first standby exit data point and the first standby entry data point occur successively, The second standby exit data point and the second standby entry data point occur successively, The standby entry data point corresponds to a transition from active mode operation to standby mode operation, The standby exit data point corresponds to a transition from the standby mode operation to the active mode operation, and A difference between the first standby exit data point and the first standby entry data point is different from a difference between the second standby exit data point and the second standby entry data point.

13. The system of claim 12, wherein the PMU is configured to: upon notification that the CPU is in a low power state, sequence the CPU into an instance of standby mode operation; initiate active mode operation of the CPU when the time tracking element is activated; and initialize software instructions for the software workload. 14 . The system of claim 12 , wherein the CPU is configured to evaluate the standby entry data point and the standby exit data point based on a standby periodicity and a standby regularity.

15. The system of claim 12, wherein an alarm triggered by the time tracking element is configured to provide for subsequent initialization of active mode operation of the CPU.

16. The system of claim 12, wherein the PMU is configured to provide operating voltages and clock signals to implement a second operating point. 17 . The system of claim 12 , wherein the performance curve corresponds to a dynamic voltage frequency scaling (DVFS) curve or a frequency scaling by body bias at ISO voltage curve.

18. A method of power management, the method comprising: sampling, by a microcontroller device of a power management unit PMU, successive standby time values ​​of a software workload when a power mode is changed, wherein the successive standby time values ​​correspond to at least a first standby entry data point and a second standby entry data point of a plurality of standby entry data points and a first standby exit data point and a second standby exit data point of a plurality of standby exit data points; and A performance mode corresponding to a particular operating point on a performance curve is determined based on the sampled successive standby values, wherein: The first standby exit data point and the first standby entry data point occur successively, The second standby exit data point and the second standby entry data point occur successively, the plurality of standby entry data points corresponding to transitions from active mode operation to standby mode operation, The plurality of standby exit data points correspond to transitions from the standby mode operation to the active mode operation, and A difference between the first standby exit data point and the first standby entry data point is different from a difference between the second standby exit data point and the second standby entry data point.

19. The method according to claim 18, further comprising: The performance mode is executed, wherein the performance mode includes providing an operating voltage and a clock signal to a central processing unit CPU by the PMU.

20. The method of claim 18, wherein determining the performance mode is based on one or more of: evaluating the plurality of standby entry data points and the plurality of standby exit data points; determining a cost of changing the first operating point; Determine the power supply delay, determining a time interval for the software workload, and Time intervals for transitions from the active mode operation to the standby mode operation and from the standby mode operation to the active mode operation are determined.

21. The method of claim 20, wherein evaluating the plurality of standby entry data points and the plurality of standby exit data points comprises: A duty cycle and a minimum time interval of the standby mode operation are calculated, wherein the duty cycle corresponds to a quotient of a weighted active time interval and a weighted standby time interval of the software workload.

22. The method according to claim 19, further comprising: receiving a software instruction from the CPU indicating that the CPU is in a sleep mode; sequencing the CPU to operate in a standby mode; as well as Active mode operation of the CPU is initiated upon activation of an alarm of a time tracking element.

23. A computer system, comprising: Computer Processor Unit CPU; and A memory accessible to the CPU, the memory storing instructions executable by the CPU to perform operations including: providing a time tracking element to sample successively occurring standby time values ​​of the software workload when the power mode is changed, wherein the successively occurring standby time values ​​correspond to at least a first standby entry data point and a second standby entry data point of a plurality of standby entry data points and a first standby exit data point and a second standby exit data point of a plurality of standby exit data points; storing the sampled successive standby time values ​​in a programmable memory; and Modifying subsequent successive standby time values ​​based on the stored successive standby time values, wherein: The first standby exit data point and the first standby entry data point occur successively, The second standby exit data point and the second standby entry data point occur successively, the plurality of standby entry data points corresponding to transitions from active mode operation to standby mode operation, The plurality of standby exit data points correspond to transitions from the standby mode operation to the active mode operation, and A difference between the first standby exit data point and the first standby entry data point is different from a difference between the second standby exit data point and the second standby entry data point.

24. The computer system of claim 23, wherein the operations further comprise: A performance mode corresponding to a particular operating point on the performance curve is determined based on the stored standby values.

25. The computer system of claim 24, wherein the operations further comprise: The performance mode is executed, wherein executing the performance mode includes instructing a power management unit (PMU) to provide an operating voltage and a clock signal to the CPU.

Images