Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device prevents misalignment of a joint portion of a leg portion of a lead frame. The semiconductor device further includes a vertical portion (64a) and branch portions (64b, 64c). The vertical portion (64a) extends in a vertical direction with respect to a circuit pattern (42). The branch portion (64b) is bent from a bifurcated portion (64a1) of a lower end portion of the vertical portion (64a) on a side closer to the circuit pattern (42) in a predetermined direction and extends in parallel with respect to the circuit pattern (42) to be joined to the circuit pattern (42). The branch portion (64c) is bent from the bifurcated portion (64a1) in a direction opposite to the predetermined direction and extends in parallel with respect to the circuit pattern (42) to be joined to the circuit pattern (42). In such a leg portion (64), a front surface side and a back surface side of the vertical portion (64a) are reliably supported by the branch portions (64b, 64c), respectively.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. BACKGROUND

[0002] A semiconductor device includes a semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device is provided with a heat sink, and ceramic circuit boards each of which is joined to the heat sink and in which the semiconductor element is provided. Further, in the semiconductor device, circuit patterns of the respective ceramic circuit boards are electrically connected by a lead frame. The lead frame has a main body portion, a plurality of external connection terminals connected to the main body portion, and a plurality of leg portions connected to the main body portion. The main body portion extends in a manner passing over the plurality of ceramic circuit boards. The external connection terminals are electrically connected to an external device or the like. The external connection terminals input a current to the main body portion or output a current that makes the main body portion conductive to the outside. The leg portions are in an L shape in a side view. Such leg portions are respectively connected to the main body portion along the main body portion that passes over the plurality of ceramic circuit boards. The leg portions are electrically joined to the circuit patterns of the respective ceramic circuit boards and electrically connect the respective ceramic circuit boards to the main body portion. At this time, the leg portions are joined to the circuit patterns of the ceramic circuit boards by ultrasonic joining. Such a lead frame is composed of, for example, copper or a copper alloy.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: International Publication No. 2019 / 230292 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] The leg portions of the lead frame are joined to the circuit patterns by ultrasonic joining. At the time of joining, the leg portions are sometimes joined in a manner displaced from a joining intended portion according to a vibration direction. If the ultrasonic joining of the leg portions is sequentially performed from the leg portions located at one end portion of the main body portion in the plurality of leg portions along the extending direction of the main body portion, the displacement of the leg portions with respect to the circuit patterns becomes larger as it goes to the other end side from the one end portion of the main body portion. The lead frame in which the leg portions are thus joined has a large dimensional tolerance with respect to the ceramic circuit boards, and sometimes the semiconductor device cannot be manufactured.

[0008] The present application has been made in view of such problems, and has its object to provide a semiconductor device and a manufacturing method of semiconductor device which prevent misalignment of a joint portion of a lead frame.

[0009] Technical Solution

[0010] According to one aspect of the present application, there is provided a semiconductor device including: a semiconductor chip; an insulating circuit substrate having an insulating board and a circuit pattern provided on the insulating board and electrically connected to the semiconductor chip; and a wiring member including, at one end, a leg portion to be joined to the circuit pattern, and having, at the other end, an external connection terminal, the leg portion including: a vertical portion extending in a vertical direction with respect to the circuit pattern; a first branch portion bent from a bifurcation portion of a lower end portion of the vertical portion on a side of the circuit pattern in a predetermined direction and extending in parallel with respect to the circuit pattern to be joined to the circuit pattern; and a second branch portion bent from the bifurcation portion in a direction opposite to the predetermined direction and extending in parallel with respect to the circuit pattern to be joined to the circuit pattern.

[0011] Further, according to one aspect of the present application, there is provided a manufacturing method of semiconductor device including: a preparation step of preparing an insulating circuit substrate having an insulating board and a circuit pattern provided on the insulating board, and a wiring member including, at one end, a leg portion to be joined to the circuit pattern, and having, at the other end, an external connection terminal, the leg portion including: a vertical portion extending in a vertical direction with respect to the circuit pattern; a first branch portion bent from a bifurcation portion of a lower end portion of the vertical portion on a side of the circuit pattern in a predetermined direction and extending in parallel with respect to the circuit pattern to be joined to the circuit pattern; and a second branch portion bent from the bifurcation portion in a direction opposite to the predetermined direction and extending in parallel with respect to the circuit pattern to be joined to the circuit pattern; and an ultrasonic joining step of simultaneously joining the first branch portion and the second branch portion of the leg portion to the circuit pattern by ultrasonic joining.

[0012] Effects of Invention

[0013] According to the disclosed technology, misalignment of a joint portion of a leg portion of a lead frame with respect to a circuit pattern can be prevented, and a semiconductor device can be properly manufactured.

[0014] The above and other objects, features and advantages of the present application will become more apparent from the following description taken in conjunction with the accompanying drawings, which represent preferred embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a plan view of the inside of the semiconductor device of the first embodiment.

[0016] Figure 2 is a diagram for explaining the semiconductor device of the first embodiment.

[0017] Figure 3 is a plan view of a ceramic circuit substrate included in the semiconductor device of the first embodiment.

[0018] Figure 4 is a plan view of a plurality of ceramic circuit substrates connected by a lead frame included in the semiconductor device of the first embodiment.

[0019] Figure 5 is a side view of a plurality of ceramic circuit substrates connected by a lead frame included in the semiconductor device of the first embodiment.

[0020] Figure 6 is a perspective view of a leg portion of a lead frame included in the semiconductor device of the first embodiment.

[0021] Figure 7 is a flowchart showing a manufacturing method of the semiconductor device of the first embodiment.

[0022] Figure 8 is a diagram for explaining an ultrasonic bonding process included in the manufacturing method of the semiconductor device of the first embodiment.

[0023] Figure 9 is a perspective view of a leg portion of a lead frame included in the semiconductor device of the second embodiment.

[0024] Figure 10 is a diagram for explaining another leg portion of a lead frame included in the semiconductor device of the second embodiment.

[0025] Symbol Explanation

[0026] 10 Semiconductor device

[0027] 20 Housing

[0028] 21 Lower housing portion

[0029] 21a, 21b, 21c, 21d, 21e, 21f Control terminal region

[0030] 22 Upper housing portion

[0031] 30 Heat dissipation substrate

[0032] 40, 40a to 40f Ceramic circuit substrate

[0033] 41, 51 Insulating plate

[0034] 42, 42a-42e, 52 circuit pattern

[0035] 43 metal plate

[0036] 45a, 46a first semiconductor chip

[0037] 45b, 46b second semiconductor chip

[0038] 47a-47d wire bonds

[0039] 50, 50a-50f control wiring unit

[0040] 60 lead frame

[0041] 60a positive lead frame

[0042] 60b negative lead frame

[0043] 60c output lead frame

[0044] 60d control lead frame

[0045] 61 main body portion

[0046] 62a positive external connection terminal

[0047] 62b negative external connection terminal

[0048] 62c output external connection terminal

[0049] 62d control external connection terminal

[0050] 63 connection portion

[0051] 64 leg portion

[0052] 64a vertical portion

[0053] 64a1 bifurcated portion

[0054] 64b-64e branch portion

[0055] 64b1, 64c1, 64d1, 64e1 extension portion

[0056] 64b2, 64c2, 64d2, 64e2 parallel portion

[0057] 64b3, 64c3, 64d3, 64e3 circuit pattern bonding region

[0058] 70 ultrasonic tool

[0059] 71 pressing portion

[0060] 72. Transmission Department Detailed Implementation

[0061] Hereinafter, the embodiments will be described with reference to the accompanying drawings. It should be noted that in the following description, [the following text is incomplete and requires further context]. Figure 2 In the semiconductor device 10, "front side" and "top surface" refer to the surface facing upwards. Similarly, in Figure 2 In the semiconductor device 10, "upper" indicates the upper direction. Figure 2 In the semiconductor device 10, "back side" and "lower surface" refer to the surfaces facing downwards. Similarly, in Figure 2 In the semiconductor device 10, "down" indicates the direction of the lower side. The same directionality may be indicated in other figures as needed. "Front side," "upper surface," "upper," "back side," "lower surface," "lower," and "side side" are merely expressions to facilitate the determination of relative positional relationships and do not limit the technical concept of the invention. For example, "upper" and "lower" do not necessarily indicate the vertical direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity.

[0062] [First Implementation Method]

[0063] use Figure 1 and Figure 2 The semiconductor device 10 of the first embodiment will be described. Figure 1 This is a top view of the interior of the semiconductor device according to the first embodiment. Figure 2 This is a diagram illustrating the semiconductor device of the first embodiment. It should be noted that... Figure 1 Indicates from Figure 2 A top view of the semiconductor device 10 with its housing 20 removed. Additionally, Figure 2 (A) represents a top view of semiconductor device 10. Figure 2 (B) indicates viewing from the bottom of the image. Figure 2 (A) Side view of semiconductor device 10.

[0064] like Figure 1As shown, the semiconductor device 10 includes a heat dissipation substrate 30, a plurality of ceramic circuit substrates 40a to 40f provided on the heat dissipation substrate 30, and control wiring units 50a to 50f. Note that the ceramic circuit substrates 40a to 40f are indicated as a ceramic circuit substrate 40 without distinguishing each. Also, the control wiring units 50a to 50f are indicated as a control wiring unit 50 without distinguishing each. Further, the semiconductor device 10 is provided with positive, negative, and output lead frames 60a to 60c, respectively, which are electrically connected to each of the ceramic circuit substrates 40. Note that the positive, negative, and output lead frames 60a to 60c are indicated as a lead frame 60 without distinguishing each. Such a semiconductor device 10 has a case 20 mounted on the heat dissipation substrate 30 (see FIG. 1). Figure 2 The ceramic circuit substrates 40 and the control wiring units 50 on the heat dissipation substrate 30 are covered by the case 20.

[0065] The ceramic circuit substrates 40a to 40f are arranged in one row along the long side of the heat dissipation substrate 30 on the front surface of the heat dissipation substrate 30, respectively. The ceramic circuit substrates 40 are joined to the front surface of the heat dissipation substrate 30 via, for example, solder or silver solder. The ceramic circuit substrates 40a to 40f have the first semiconductor chips 45a, 46a and the second semiconductor chips 45b, 46b described later joined thereto and are electrically connected by bonding wires. The bonding wires are composed of a material having excellent electrical conductivity. As the material, for example, gold, silver, copper, aluminum, or an alloy including at least one of these is used. Also, the diameter of the bonding wires is, for example, 100 μm or more and 500 μm or less. Note that the details of the ceramic circuit substrates 40 and the first semiconductor chips 45a, 46a and the second semiconductor chips 45b, 46b will be described later.

[0066] The control wiring units 50a, 50c, 50e are arranged on the heat dissipation substrate 30 and are arranged above the ceramic circuit substrates 40a, 40c, 40e in Figure 1 The control wiring units 50b, 50d, 50f are arranged on the heat dissipation substrate 30 and are arranged below the ceramic circuit substrates 40a, 40d, 40e in Figure 1 Such a control wiring unit 50 has an insulating plate 51, a circuit pattern 52 provided on the insulating plate 51, and a control lead frame 60d joined to the circuit pattern 52. Note that the control wiring unit 50f among the control wiring units 50 is formed with one set of the circuit pattern 52 and the control lead frame 60d. The other control wiring units 50 are formed with two sets of the circuit pattern 52 and the control lead frame 60d.

[0067] The insulating plate 51 is made of ceramic having good thermal conductivity. Such ceramic is made of, for example, a composite material having alumina and zirconia added to the alumina as main components, or a material having silicon nitride as a main component. In addition, the thickness of the insulating plate 51 is 0.5 mm or more and 2.0 mm or less. The insulating plate 51 is rectangular in plan view. In addition, the corners can also be chamfered to an R shape, a C shape.

[0068] The plurality of circuit patterns 52 are made of metal having good electrical conductivity. Such metal is, for example, silver, copper, nickel, or an alloy including at least one of these. In addition, the thickness of the plurality of circuit patterns 52 is 0.5 mm or more and 1.5 mm or less. In order to improve corrosion resistance, the surface of the plurality of circuit patterns 52 can also be subjected to plating treatment. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy. The plurality of circuit patterns 52 for the insulating plate 51 are obtained by forming a metal plate on the front surface of the insulating plate 51 and subjecting the metal plate to etching or the like. Alternatively, the plurality of circuit patterns 52 that have been cut out in advance from a metal plate can also be press-bonded to the front surface of the insulating plate 51. Note that, Figure 1 The plurality of circuit patterns 52 shown are an example. The number, shape, size, and the like of the circuit patterns 52 can also be appropriately selected as needed.

[0069] The control lead frame 60d is made of metal having good electrical conductivity. Such metal is, for example, silver, copper, nickel, or an alloy including at least one of these. In order to improve corrosion resistance, the surface of the control lead frame 60d can also be subjected to plating treatment. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy. In addition, a control external connection terminal 62d is provided at the front end portion of the control lead frame 60d.

[0070] The positive, negative, and output lead frames 60a to 60c can also be made of metal having good electrical conductivity, like the control lead frame 60d, and can also be subjected to plating treatment. In addition, the positive lead frame 60a is connected to two positive external connection terminals 62a. The negative lead frame 60b is connected to two negative external connection terminals 62b. The output lead frame 60c is connected to one output external connection terminal 62c.

[0071] The heat dissipation substrate 30 is composed of a metal having excellent thermal conductivity. Such a metal is, for example, aluminum, iron, silver, copper, or an alloy including at least one of these. In order to improve corrosion resistance, the surface of the heat dissipation substrate 30 can also be subjected to plating treatment. At this time, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. Note that a cooler (not shown) can also be attached to the back surface of the heat dissipation substrate 30 of such a semiconductor device 10 via a thermally conductive paste. Thereby, the heat dissipation property can also be improved. Note that the thermally conductive paste is, for example, silicon into which a filler of a metal oxide is mixed. The cooler in this case is composed of, for example, aluminum, iron, silver, copper, or an alloy including at least one of these, or the like. In addition, as the cooler, a heat sink, or a heat sink composed of a plurality of heat sinks, a cooling device based on water cooling, or the like can be used. In addition, the heat dissipation substrate 30 can also be composed integrally with such a cooler. In this case, it is composed of aluminum, iron, silver, copper, or an alloy including at least one of these, and has a surface on which a material such as nickel is formed by plating treatment or the like in order to improve corrosion resistance. Specifically, in addition to nickel, a nickel-phosphorus alloy, a nickel-boron alloy, or the like can be used.

[0072] The housing 20 includes a lower accommodation portion 21 and an upper accommodation portion 22. The lower accommodation portion 21 is rectangular in plan view and has a box shape. The upper accommodation portion 22 is also rectangular in plan view and has a box shape that is smaller than that of the lower accommodation portion 21. The lower accommodation portion 21 and the upper accommodation portion 22 are connected integrally and have an empty interior. Inside the empty interior of the housing 20, a ceramic circuit substrate 40, positive electrode, negative electrode, output, and control lead frames 60a to 60d, and the like are accommodated. Such a housing 20 is composed of a thermoplastic resin. As such a resin, a polyphenylene sulfide resin, a polybutylene terephthalate resin, a polybutylene succinate resin, a polyamide resin, or an acrylonitrile butadiene styrene resin, or the like is used.

[0073] On the front surface of the lower housing portion 21 along one long side, control terminal regions 21a, 21c, 21e recessed toward the back surface side of the case 20 are provided. From the control terminal regions 21a, 21c, 21e, control external connection terminals 62d of the control lead frame 60d are respectively exposed. On the front surface of the lower housing portion 21 along the other long side, control terminal regions 21b, 21d, 21f recessed toward the back surface side of the case 20 are provided. From the control terminal regions 21b, 21d, 21f, the control external connection terminals 62d of the control lead frame 60d are respectively exposed. From the front surface of the upper housing portion 22 along the long side, the output external connection terminal 62c, the positive external connection terminal 62a, the negative external connection terminal 62b, the positive external connection terminal 62a, and the negative external connection terminal 62b are respectively exposed. Note that the output external connection terminal 62c is flat, extends upward vertically from one long side of the front surface of the upper housing portion 22, and is folded back toward the front surface side. The positive external connection terminal 62a, the negative external connection terminal 62b, the positive external connection terminal 62a, and the negative external connection terminal 62b are flat, extend upward vertically from the other long side of the front surface of the upper housing portion 22, and are folded back toward the front surface side.

[0074] Next, the ceramic circuit board 40 is described. Figure 3 The ceramic circuit board 40 is described. Figure 3 is a plan view of the ceramic circuit board included in the semiconductor device of the first embodiment. Note that in Figure 3 , although the ceramic circuit board 40a is shown, the other ceramic circuit boards also have the same structure.

[0075] The ceramic circuit board 40a is provided with the first semiconductor chips 45a, 46a and the second semiconductor chips 45b, 46b, which are electrically connected by the bonding wires 47a to 47d. The first semiconductor chips 45a, 46a are switching elements composed of silicon or silicon carbide. The switching elements are, for example, IGBTs, power MOSFETs. In the case where the first semiconductor chips 45a, 46a are IGBTs, a collector electrode is provided on the back surface as a main electrode, and a gate electrode is provided on the front surface as a control electrode and an emitter electrode as a main electrode. In the case where the first semiconductor chips 45a, 46a are power MOSFETs, a drain electrode is provided on the back surface as a main electrode, and a gate electrode is provided on the front surface as a control electrode and a source electrode as a main electrode. Further, the second semiconductor chips 45b, 46b are diode elements composed of silicon or silicon carbide. The diode elements are, for example, SBDs (Schottky Barrier Diodes), PiN (P-intrinsic-N) diodes, and the like, FWDs (Free Wheeling Diodes). Such second semiconductor chips 45b, 46b have a cathode electrode provided on the back surface as a main electrode, and an anode electrode provided on the front surface as a main electrode. The back surface side of the first semiconductor chips 45a, 46a and the second semiconductor chips 45b, 46b is joined to the predetermined circuit patterns 42a, 42b by solder (not shown). The solder uses a lead-free solder. The lead-free solder uses, for example, at least one of an alloy composed of tin-silver-copper, an alloy composed of tin-zinc-bismuth, an alloy composed of tin-copper, and an alloy composed of tin-silver-indium-bismuth as a main component. Further, an additive can be contained in the solder. The additive is, for example, nickel, germanium, cobalt, or silicon. The solder can improve wettability, gloss, and bonding strength by containing the additive, and can achieve improvement in reliability. Instead of the solder, a metal sintered body can be used. Further, the thickness of the first semiconductor chips 45a, 46a and the second semiconductor chips 45b, 46b is, for example, 180 μm or more and 220 μm or less, and is about 200 μm on average.

[0076] The ceramic circuit board 40a has an insulating board 41 and a metal plate 43 formed on the back surface of the insulating board 41 (see Figure 5). Further, the ceramic circuit board 40a has circuit patterns 42a to 42e formed on the front surface of the insulating board 41, respectively. Note that, hereinafter, in the case where the circuit patterns 42a to 42e are not particularly distinguished, it is indicated as the circuit pattern 42. The insulating board 41 is composed of a ceramic having high thermal conductivity, such as alumina, aluminum nitride, silicon nitride, or the like, similarly to the insulating board 51. The metal plate 43 is composed of a metal, such as aluminum, iron, silver, copper, or an alloy including at least one of these metals, having excellent thermal conductivity. The circuit patterns 42a to 42e are composed of a metal, such as copper or a copper alloy, having excellent electrical conductivity, similarly to the circuit pattern 52. Further, in order to improve corrosion resistance, a material, such as nickel, can be formed on the surface by plating treatment or the like. Specifically, in addition to nickel, there are nickel-phosphorus alloy, nickel-boron alloy, or the like. Further, the thickness of the circuit patterns 42a to 42e is, for example, 0.1 mm or more and 1 mm or less. As the ceramic circuit board 40a having such a structure, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazed) substrate, or the like can be used. The ceramic circuit board 40a can conduct heat generated in the first semiconductor chip 45a and the second semiconductor chip 45b to the heat dissipation board 30 via the circuit patterns 42a and 42b, the insulating board 41, and the metal plate 43.

[0077] The circuit pattern 42a constitutes a collector pattern of the first arm portion A. In the circuit pattern 42a, the collectors formed on the back surfaces of the first semiconductor chip 45a and the second semiconductor chip 45b are joined via solder. The circuit pattern 42a has a substantially rectangular shape, and a portion to which the leg portion 64 of the positive electrode lead frame 60a is joined protrudes toward the lower side. Figure 3 The circuit pattern 42d constitutes a control pattern of the first arm portion A. The circuit pattern 42d is connected to the bonding wire 47a connected to the gate of the first semiconductor chip 45a. Further, the circuit pattern 42d is electrically connected to the control wiring unit 50b by a bonding wire (not shown).

[0078] The circuit pattern 42b constitutes an emitter pattern of the first arm portion A and a collector pattern of the second arm portion B. The circuit pattern 42b is connected to the bonding wire 47b connected to the output electrodes (emitters) of the first semiconductor chip 45a and the second semiconductor chip 45b on the circuit pattern 42a. Further, for the circuit pattern 42b, the collectors formed on the back surfaces of the first semiconductor chip 46a and the second semiconductor chip 46b are joined via solder. The circuit pattern 42b has a substantially rectangular shape, Figure 3The upper middle portion protrudes. The circuit pattern 42b is arranged side by side with the circuit pattern 42a. Further, the circuit pattern 42b is electrically connected to the control wiring unit 50a by a bonding wire (not shown). The circuit pattern 42e constitutes a control pattern of the second arm portion B. The circuit pattern 42e is connected to the bonding wire 47c connected to the gate electrode of the first semiconductor chip 46a.

[0079] The circuit pattern 42c constitutes an emitter pattern of the second arm portion B. The circuit pattern 42c is connected to the bonding wire 47d connected to the output electrode (emitter) of the first semiconductor chip 46a and the second semiconductor chip 46b. The circuit pattern 42c is arranged on the lower middle side of the circuit pattern 42b. Figure 3 Such a circuit pattern 42c is joined to the leg portion 64 of the negative lead frame 60b.

[0080] In the semiconductor device 10, the ceramic circuit boards 40 to which the first semiconductor chips 45a, 46a and the second semiconductor chips 45b, 46b are joined are arranged in plurality on the front surface of the heat dissipation substrate 30 along the length direction of the heat dissipation substrate 30. Further, the positive, negative, and output lead frames 60a to 60c are provided which are electrically connected to the plurality of ceramic circuit boards 40 as appropriate. By this, the semiconductor device 10 is configured. Figure 4 and Figure 5 The plurality of ceramic circuit boards 40 and the positive, negative, and output lead frames 60a to 60c will be described. Figure 4 is a plan view of the plurality of ceramic circuit boards connected by the lead frames included in the semiconductor device of the first embodiment. Figure 5 is a side view of the plurality of ceramic circuit boards connected by the lead frames included in the semiconductor device of the first embodiment. Note that, in Figure 4 , the heat dissipation substrate 30 is omitted. Figure 5 Only the side surface of the positive lead frame 60a is shown. In addition, in Figure 5 , a portion of the upper housing portion 22 in the housing 20 is shown.

[0081] As Figure 4 and Figure 5As shown, the positive electrode, negative electrode, and output lead frames 60a to 60c are appropriately electrically joined to the ceramic circuit substrates 40a to 40f arranged in one direction. The positive electrode lead frame 60a includes a main body portion 61, a positive electrode external connection terminal 62a, a connection portion 63, and a leg portion 64. The positive electrode lead frame 60a is provided with the leg portion 64 (and the connection portion 63) at a position corresponding to the ceramic circuit substrate 40 connected to the main body portion 61. The positive electrode lead frame 60a is provided with the positive electrode external connection terminal 62a corresponding to a position exposed from the case 20 with respect to the main body portion 61. In addition, the negative electrode and output lead frames 60b and 60c are also provided with the leg portions 64 (and the connection portions 63) at positions corresponding to the ceramic circuit substrates 40 connected to the main body portion 61. As shown in Figure 2 As shown, the negative electrode and output lead frames 60b and 60c are provided with the negative electrode and output external connection terminals 62b and 62c corresponding to positions exposed from the case 20 with respect to the main body portion 61. Figure 4 and Figure 5 The negative electrode and output external connection terminals 62b and 62c are omitted from the drawings in

[0082] The main body portion 61 is flat, and as shown in Figure 4 and Figure 5 is arranged in one direction, at a predetermined height from the front surface. The positive electrode, negative electrode, and output external connection terminals 62a to 62c are flat, and protrude in the vertical direction with respect to the front surface of the ceramic circuit substrate 40 and are integrally connected to the main body portion 61. Note that the positive electrode, negative electrode, and output external connection terminals 62a to 62c are arranged so as to respectively face the front surface of the upper housing portion 22 of the case 20. If the case 20 is mounted on the heat dissipation substrate 30, the positive electrode, negative electrode, and output external connection terminals 62a to 62c extend in the vertical direction from the front surface of the upper housing portion 22 of the case 20. By bending the positive electrode, negative electrode, and output external connection terminals 62a to 62c extending from the front surface of the upper housing portion 22 of the case 20, the main surfaces of the positive electrode, negative electrode, and output external connection terminals 62a to 62c are exposed to the front surface of the upper housing portion 22, as shown in Figure 2

[0083] The leg portion 64 electrically connects each of the positive electrode, negative electrode, and output lead frames 60a to 60c to the circuit patterns 42a to 42c of the respective ceramic circuit substrates 40. Note that the details of the leg portion 64 will be described later. The connection portion 63 is integrally connected to the main body portion 61 and the leg portion 64. Therefore, the connection portion 63 electrically connects the main body portion 61 to the leg portion 64.

[0084] Next, the details of the positive electrode, negative electrode, and output lead frames 60a to 60c will be described with reference to Figure 6 ​Details of the leg portions 64 of the lead frame 60a to 60c for the positive electrode, the negative electrode, and the output will be described. Figure 6 is a perspective view of a leg portion of a lead frame included in the semiconductor device of the first embodiment. Note that in Figure 6 the leg portion 64 (of the lower end portion side) of the lead frame 60 joined to the circuit pattern 42 is shown. The main body portion 61 and the connection portion 63 are omitted from the drawing of the lead frame 60.

[0085] The leg portion 64 includes a vertical portion 64a, and branch portions 64b and 64c. The width of the leg portion 64 is uniform in the vertical portion 64a and the branch portions 64b and 64c. Note that, as will be described later, it is desirable that the thickness of each of the branch portions 64b and 64c be approximately half the thickness of the vertical portion 64a. That is, the thickness of the branch portions 64b and 64c is added to become the thickness of the vertical portion 64a. The vertical portion 64a extends in the vertical direction with respect to the circuit pattern 42. The vertical portion 64a is connected to the connection portion 63 at the end of the extension. The branch portion 64b further includes a continuation portion 64b1 and a parallel portion 64b2. The continuation portion 64b1 is bent from the bifurcated portion 64a1 of the lower end portion of the vertical portion 64a on the side of the circuit pattern 42 in a predetermined direction. The predetermined direction refers to the thickness direction. Alternatively, the predetermined direction refers to the direction in which the bifurcation is made from the split, which is formed by cutting the other end portion in parallel with the width direction with respect to the one end portion (the vertical portion 64a) to be clamped as will be described later. The parallel portion 64b2 is continued from the continuation portion 64b1 and extends in parallel with respect to the circuit pattern 42, and is joined to the circuit pattern 42 through the back surface circuit pattern joining region 64b3. On the other hand, the branch portion 64c is provided on the side opposite to the branch portion 64b, and includes a continuation portion 64c1 and a parallel portion 64c2. The continuation portion 64c1 is bent from the bifurcated portion 64a1 of the lower end portion of the vertical portion 64a on the side of the circuit pattern 42 to the side opposite to the predetermined direction. The parallel portion 64c2 is continued from the continuation portion 64c1 and extends in parallel with respect to the circuit pattern 42, and is joined to the circuit pattern 42 through the back surface circuit pattern joining region 64c3.

[0086] Such a leg portion 64 is connected to the main body portion 61 via the connection portion 63, and is mounted to the circuit pattern 42 in such a manner that the predetermined direction of the branch portions 64b and 64c is parallel to the wiring direction of the main body portion 61. In the leg portion 64, the length of the branch portion 64b from the bifurcated portion 64a1 to the front end portion in the predetermined direction is equal to the length of the branch portion 64c from the bifurcated portion 64a1 to the front end portion on the side opposite to the predetermined direction. In addition, since the widths of the branch portions 64b and 64c are equal, the areas of the branch portions 64b and 64c are equal, and in particular, the areas of the parallel portions 64b2 and 64c2 are equal.

[0087] Furthermore, this foot 64 is rectangular in shape, clamping and fixing one end (vertical portion 64a) of the plate-shaped conductive plate, and forming a slit at the other end that is parallel to the width direction and cuts across the width. It branches off from this slit, and the branches are bent in opposite directions to obtain the foot 64. Therefore, the thickness of the vertical portion 64a is the sum of the thicknesses of the branches 64b and 64c. It should be noted that, in this case, it is desirable that the thicknesses of the branches 64b and 64c are each half the thickness of the vertical portion 64a. In the foot 64 thus obtained, the branches 64b and 64c are joined to the circuit pattern 42. As described later, the branches 64b and 64c are joined to the circuit pattern 42 by ultrasonic bonding. Therefore, there are no joining parts between the branches 64b and 64c and the circuit pattern 42; they are directly joined. Therefore, the foot 64 is stably joined relative to the circuit pattern 42. Furthermore, the front and back sides of the vertical portion 64a are reliably and stably supported by the branch portions 64b and 64c, respectively. In addition, the extension portions 64b1 and 64c1 do not engage with the circuit pattern 42, exhibiting elasticity between the vertical portion 64a and the branch portions 64b and 64c. Therefore, the extension portions 64b1 and 64c1 can mitigate external impacts on the foot portion 64. Thus, deformation and misalignment of the vertical portion 64a can be prevented, and the lead frame 60 can be maintained at the predetermined engagement position.

[0088] Next, using Figure 7 and Figure 8 A method for manufacturing a semiconductor device 10, including a foot 64 that is engaged with a circuit pattern 42, will be described. Figure 7 This is a flowchart illustrating a method for manufacturing a semiconductor device according to a first embodiment. Figure 8 This is a diagram illustrating the ultrasonic bonding process included in the manufacturing method of the semiconductor device according to the first embodiment.

[0089] First, a preparation process is performed, including preparing the housing 20, heat dissipation substrate 30, ceramic circuit board 40, control wiring units 50a-50e, first semiconductor chips 45a and 46a, second semiconductor chips 45b and 46b, and lead frame 60, etc. Figure 7 Step S10). At this time, the lead frame 60 is pre-formed with Figure 6 The foot shown is 64.

[0090] Next, the following loading process is performed ( Figure 7 (Step S11). On a predetermined portion of the front side of the heat sink substrate 30, a ceramic circuit board 40 and control wiring units 50a to 50e are respectively mounted by solder. Furthermore, on the circuit pattern 42 of the ceramic circuit board 40, first semiconductor chips 45a and 46a and second semiconductor chips 45b and 46b are respectively mounted by solder.

[0091] Next, in the state of step S11, the following solder bonding process is performed ( Figure 7 Step S12). First, the solder is heated to melt it. After the solder melts, it is cooled to solidify it, thereby bonding the ceramic circuit board 40 and the control wiring units 50a to 50e to the heat dissipation substrate 30 using solder. Then, the first semiconductor chips 45a and 46a and the second semiconductor chips 45b and 46b are bonded to the circuit pattern 42 of the ceramic circuit board 40 using solder.

[0092] Next, the wiring process is carried out. Figure 7 In step S13), during the wiring process, bonding wires are used to electrically connect the ceramic circuit substrate 40 to the first semiconductor chips 45a and 46a and the second semiconductor chips 45b and 46b to perform wiring. Next, an ultrasonic bonding process is performed. Figure 7 In step S14), during the ultrasonic bonding process, the leads 60 feet 64 are bonded to the circuit pattern 42 of the ceramic circuit board 40 by ultrasonic bonding. Ultrasonic bonding is performed using an ultrasonic bonding apparatus. The ultrasonic bonding apparatus includes an ultrasonic wave generating device and a means for transmitting the ultrasonic waves generated from the ultrasonic wave generating device. Figure 8 The ultrasonic tool 70 is shown. First, the circuit pattern joining areas 64b3 and 64c3 of the parallel portions 64b2 and 64c2 of the feet 64 are positioned at the joining points of the circuit pattern 42. For example... Figure 8 As shown, two ultrasonic tools 70 of the ultrasonic bonding device are respectively mounted on the parallel portions 64b2 and 64c2 of the foot 64. Each ultrasonic tool 70 is L-shaped and includes a pressing portion 71 and a transmission portion 72 connected to the pressing portion 71. The pressing portion 71 includes a flat surface that abuts against the front of the parallel portions 64b2 and 64c2 of the foot 64. The transmission portion 72 has the pressing portion 71 at one end and is connected to the ultrasonic generating device at the other end. The transmission portion 72 transmits ultrasonic vibrations generated by the ultrasonic generating device to the pressing portion 71.

[0093] By using the pressing part 71 of such an ultrasonic tool 70, the parallel portions 64b2 and 64c2 of the foot 64 are pressed while vibrating simultaneously relative to the circuit pattern 42. As a result, the parallel portions 64b2 and 64c2 deform simultaneously and parallel to the vibration direction (e.g., the bending direction of the branches 64b and 64c) due to the ultrasonic vibration. Figure 8direction. That is, since the parallel portions 64b2, 64c2 are deformed in the vibration direction as well, the parallel portions 64b2, 64c2 can be joined to the circuit pattern 42 without misalignment of the perpendicular portion 64a. Thus, even if the leg portions 64 of the lead frame 60 are sequentially joined from the ceramic circuit substrate 40a toward the ceramic circuit substrate 40f, the leg portions 64 of the lead frame 60 do not become more misaligned as the ceramic circuit substrate 40f is approached. Therefore, the lead frame 60 is appropriately joined to the predetermined joining portions of the plurality of ceramic circuit substrates 40.

[0094] In addition, the parallel portions 64b2, 64c2 of the leg portions 64 can also be pressed and joined by the pressing portion 71 of the ultrasonic tool 70 in the following manner. That is, in the lead frame 60 in which a plurality of leg portions 64 are provided, the parallel portions 64b2, 64c2 can be alternately ultrasonically joined to the ceramic circuit substrate 40 by the ultrasonic tool 70 from the leg portion 64 of one end portion to the leg portion 64 of the other end portion along the body portion 61.

[0095] For example, the case of the positive electrode lead frame 60a will be described (refer to FIG. 6A). The leg portions 64 of the lead frame 60a are sequentially joined from the ceramic circuit substrate 40a toward the ceramic circuit substrate 40f. The parallel portions 64b2, 64c2 of the leg portions 64 are alternately ultrasonically joined to the ceramic circuit substrates 40 by the ultrasonic tool 70 from the leg portion 64 of one end portion to the leg portion 64 of the other end portion along the body portion 61. Figure 4 and Figure 5). First, the parallel portion 64b2 of the foot portion 64 of the anode lead frame 60a at the most initial end is joined to the ceramic circuit substrate 40a by ultrasonic joining, and the parallel portion 64c2 of the foot portion 64 is joined to the ceramic circuit substrate 40a by ultrasonic joining. Next, the parallel portion 64b2 of the foot portion 64 of the anode lead frame 60a adjacent to the most initial end foot portion 64 is joined to the ceramic circuit substrate 40b by ultrasonic joining, and the parallel portion 64c2 of the foot portion 64 is joined to the ceramic circuit substrate 40b by ultrasonic joining. In this way, the foot portions 64 of the anode lead frame 60a are joined to the ceramic circuit substrates 40 in the order of the parallel portions 64b2, 64c2 along the main body portion 61 with respect to the ceramic circuit substrates 40. Finally, the parallel portion 64b2 of the foot portion 64 of the anode lead frame 60a at the most terminal end is joined to the ceramic circuit substrate 40f by ultrasonic joining, and the parallel portion 64c2 of the foot portion 64 is joined to the ceramic circuit substrate 40f by ultrasonic joining. Note that the case where the parallel portions 64b2, 64c2 of the foot portions 64 are alternately joined along the main body portion 61 of the lead frame 60 is not limiting, and the parallel portions 64c2, 64b2 of the foot portions 64 can be alternately joined along the main body portion 61. In these cases as well, as in the case where the parallel portions 64b2, 64c2 of the foot portions 64 are simultaneously joined, even if the foot portions 64 provided to the lead frame 60 are sequentially joined from the ceramic circuit substrate 40a toward the ceramic circuit substrate 40f, the foot portions 64 of the lead frame 60 do not become increasingly misaligned as they approach the ceramic circuit substrate 40f. Therefore, the lead frame 60 is appropriately joined with respect to the predetermined joining sites of the plurality of ceramic circuit substrates 40.

[0096] Next, the anode, cathode, output, and control external connection terminals 62a to 62d are caused to protrude from each portion of the case 20, and the case 20 is attached to the heat dissipation substrate 30 (step S15) using an adhesive. As described above, the semiconductor device 10 shown in FIG. 1 can be obtained. Figure 7 Figure 2 Next, the anode, cathode, output, and control external connection terminals 62a to 62d are caused to protrude from each portion of the case 20, and the case 20 is attached to the heat dissipation substrate 30 (step S15) using an adhesive. As described above, the semiconductor device 10 shown in FIG. 1 can be obtained.

[0097] ​The semiconductor device 10 described above includes first semiconductor chips 45a, 46a and second semiconductor chips 45b, 46b, and a ceramic circuit board 40 having an insulating board 41 and a circuit pattern 42 provided on the insulating board 41 and electrically connected to the first semiconductor chips 45a, 46a and the second semiconductor chips 45b, 46b. Further, the semiconductor device 10 includes a lead frame 60 including a leg portion 64 joined to the circuit pattern 42 at one end and provided with positive and negative and output external connection terminals 62a to 62c at the other end. At this time, the leg portion 64 is further provided with a vertical portion 64a and branch portions 64b, 64c. The vertical portion 64a extends in the vertical direction with respect to the circuit pattern 42. The branch portion 64b is bent in a predetermined direction from a bifurcated portion 64al of a lower end portion of the vertical portion 64a on the circuit pattern 42 side and extends in parallel with respect to the circuit pattern 42, thereby being joined to the circuit pattern 42. The branch portion 64c is bent in the opposite direction of the predetermined direction from the bifurcated portion 64al and extends in parallel with respect to the circuit pattern 42, thereby being joined to the circuit pattern 42.

[0098] In such a leg portion 64, the front surface side and the back surface side of the vertical portion 64a are reliably supported by the branch portions 64b, 64c, respectively. Therefore, the leg portion 64 is stably joined with respect to the circuit pattern 42. Further, since such a leg portion 64 is bifurcated in the thickness direction, each of the branch portions 64b, 64c is thinner than the vertical portion 64a, and ultrasonic wave vibration is easily transmitted to the circuit pattern joining regions 64b3, 64c3 between the parallel portions 64b2, 64c2 and the circuit pattern 42, thereby being able to be joined more firmly. Further, in such a leg portion 64, the branch portions 64b, 64c are simultaneously joined with respect to the circuit pattern 42 by ultrasonic wave vibration. Then, since the branch portions 64b, 64c are deformed in parallel with respect to the bending direction identically, the vertical portion 64a is not misaligned. Therefore, misalignment of the vertical portion 64a and the like can be prevented, and the lead frame 60 can be maintained at a predetermined joining position. As a result, the semiconductor device 10 can be appropriately manufactured.

[0099] [Second Embodiment]

[0100] In the second embodiment, a leg portion different from that of the first embodiment is used. Figure 9 The leg portion of the lead frame included in the semiconductor device of the second embodiment will be described. Figure 9 Only the leg portion 64 is shown. Instead of the leg portion 64 of the lead frame 60 of the first embodiment, the leg portion 64 of the second embodiment is provided. Therefore, the other structures of the semiconductor device of the second embodiment are formed in the same manner as those of the semiconductor device 10 of the first embodiment. Figure 9

[0101] Figure 9 ​The illustrated leg 64 includes a vertical portion 64a, and branch portions 64b, 64c. The vertical portion 64a extends in the vertical direction with respect to the circuit pattern 42. The vertical portion 64a is connected to the connecting portion 63 at the end of the extension. Unlike the first embodiment, the branch portions 64b, 64c are bifurcated by cutting at one place in a manner perpendicular to the vertical portion 64a with respect to the width direction of the vertical portion 64a. Therefore, the width obtained by adding the branch portions 64b, 64c corresponds to the width of the vertical portion 64a. The branch portion 64b further has a continuation portion 64b1, and a parallel portion 64b2. As with the first embodiment, the continuation portion 64b1 is bent in the predetermined direction from the bifurcated portion 64a1 of the lower end portion of the vertical portion 64a on the side of the circuit pattern 42. The parallel portion 64b2 is continued from the continuation portion 64b1 to extend in parallel with respect to the circuit pattern 42, and is joined to the circuit pattern 42 through the back surface circuit pattern joining region 64b3. On the other hand, the branch portion 64c is provided on the opposite side of the branch portion 64b, and has a continuation portion 64c1 and a parallel portion 64c2. The continuation portion 64c1 is bent in the opposite direction of the predetermined direction from the bifurcated portion 64a1 of the lower end portion of the vertical portion 64a on the side of the circuit pattern 42. The parallel portion 64c2 is continued from the continuation portion 64c1 to extend in parallel with respect to the circuit pattern 42, and is joined to the circuit pattern 42 through the back surface circuit pattern joining region 64c3. In addition, as with the first embodiment, such a leg 64 can be joined by pressing the parallel portions 64b2, 64c2 of the leg 64 with respect to the circuit pattern 42 with the pressing portion 71 of the ultrasonic tool 70, either by pressing while vibrating simultaneously as with the first embodiment, or by pressing while vibrating alternately.

[0102] Such a leg 64 is also connected to the main body portion 61 via the connecting portion 63, and is mounted to the circuit pattern 42 in a manner in which the predetermined direction of the branch portions 64b, 64c is parallel to the wiring direction of the main body portion 61. In the leg 64, the length of the branch portion 64b from the bifurcated portion 64a1 to the front end portion in the predetermined direction is equal to the length of the branch portion 64c from the bifurcated portion 64a1 to the front end portion on the opposite side in the predetermined direction. In addition, in the case where the branch portions 64b, 64c are bifurcated at the center of the width of the vertical portion 64a, since the respective widths are equal, the areas of the branch portions 64b, 64c are equal, and in particular, the areas of the parallel portions 64b2, 64c2 are equal.

[0103] In addition, by Figure 10 Other legs of the second embodiment will be described. Figure 10 is a view for explaining other legs of the lead frame included in the semiconductor device of the second embodiment. It should be noted that Figure 10 (A) of FIG. 64 is a perspective view of the leg 64, Figure 10 (B) of FIG. 64 is a plan view of the leg 64. InFigure 10 In (A) of FIG. 6, although not illustrated, the branch portion 64c is provided on the back side of the vertical portion 64a.

[0104] Figure 10 The foot portion 64 illustrated in FIG. 6 includes the vertical portion 64a and the branch portions 64b to 64e. The vertical portion 64a extends in the vertical direction with respect to the circuit pattern 42. The vertical portion 64a is connected to the connection portion 63 at the end of the extension. Unlike the first embodiment, the branch portions 64b to 64e are bifurcated by cutting the vertical portion 64a at three places in a perpendicular direction and at equal intervals. Therefore, the width obtained by adding the branch portions 64b to 64e corresponds to the width of the vertical portion 64a. That is, Figure 10 The foot portion 64 illustrated in FIG. 6 includes two groups Figure 9 The branch portions 64b and 64c of the foot portion 64 illustrated in FIG. 6. Note that, Figure 10 The foot portion 64 illustrated in FIG. 6 is not limited to including two groups Figure 9 The foot portion 64 illustrated in FIG. 6 can include three or more groups Figure 9 The foot portion 64 illustrated in FIG. 6.

[0105] The branch portion 64b further has a continuation portion 64b1 and a parallel portion 64b2. The continuation portion 64b1 is bent in a predetermined direction from the bifurcated portion 64a1 of the lower end portion of the vertical portion 64a on the side of the circuit pattern 42. The parallel portion 64b2 is continued from the continuation portion 64b1 and extends in parallel with respect to the circuit pattern 42, and is joined to the circuit pattern 42 by the back surface circuit pattern joining region 64b3. In addition, the branch portion 64d also further has a continuation portion 64d1 and a parallel portion 64d2. The continuation portion 64d1 is bent in a predetermined direction from the bifurcated portion 64a1 of the lower end portion of the vertical portion 64a on the side of the circuit pattern 42. The parallel portion 64d2 is continued from the continuation portion 64d1 and extends in parallel with respect to the circuit pattern 42, and is joined to the circuit pattern 42 by the back surface circuit pattern joining region 64d3.

[0106] On the other hand, the branch portion 64c is provided on the side of the vertical portion 64a opposite to the branch portions 64b and 64d, and has a continuation portion 64c1 and a parallel portion 64c2 (see Figure 9). The continuation portion 64cl is bent from the bifurcated portion 64al of the lower end portion of the vertical portion 64a on the side of the circuit pattern 42 to the side opposite to the continuation portion 64bl. The parallel portion 64c2 is continued from the continuation portion 64cl and extends in parallel with respect to the circuit pattern 42, and is joined to the circuit pattern 42 through the back surface circuit pattern joining region 64c3. In addition, the branch portion 64e is provided on the side of the vertical portion 64a opposite to the branch portions 64b and 64d, and has a continuation portion 64el and a parallel portion 64e2. The continuation portion 64el is bent from the bifurcated portion 64al of the lower end portion of the vertical portion 64a on the side of the circuit pattern 42 to the side opposite to the predetermined direction. The parallel portion 64e2 is continued from the continuation portion 64el and extends in parallel with respect to the circuit pattern 42, and is joined to the circuit pattern 42 through the back surface circuit pattern joining region 64e3.

[0107] Such a leg portion 64 is also connected to the main body portion 61 via the connection portion 63, and is mounted to the circuit pattern 42 in a manner that the predetermined directions of the branch portions 64b to 64e are parallel to the wiring direction of the main body portion 61. In the leg portion 64, the length from the bifurcated portion 64al to the front end portion in the predetermined direction of the branch portion 64b, the length from the bifurcated portion 64al to the front end portion on the side opposite to the predetermined direction of the branch portion 64c, the length from the bifurcated portion 64al to the front end portion in the predetermined direction of the branch portion 64d, and the length from the bifurcated portion 64al to the front end portion on the side opposite to the predetermined direction of the branch portion 64e are equal. In addition, the branch portions 64b to 64e are bifurcated three times at equal intervals with respect to the width of the vertical portion 64a, and the respective widths are equal, so the areas of the branch portions 64b to 64e are equal, and in particular, the areas of the parallel portions 64b2 to 64e2 are equal.

[0108] As with the first embodiment, such a leg portion 64 can also be joined to the circuit pattern 42 using the pressing portion 71 of the ultrasonic tool 70. In this case, the ultrasonic tool 70 can be prepared in accordance with the branch portions 64b to 64e of the leg portion 64, and the branch portions 64b to 64e are pressed while being vibrated simultaneously with respect to the circuit pattern 42, whereby the joining is performed.

[0109] As with the first embodiment, in the leg portion 64 of this second embodiment as well, the front side and the back side of the vertical portion 64a are reliably supported by the branch portions 64b, 64c (64b to 64e), respectively. Therefore, the leg portion 64 is stably joined with respect to the circuit pattern 42. In addition, for this leg portion 64, the branch portions 64b, 64c (64b to 64e) are simultaneously joined with respect to the circuit pattern 42 by ultrasonic vibration. Then, the branch portions 64b, 64c (64b to 64e) are deformed in the same manner with respect to the bending direction in parallel, and therefore the vertical portion 64a is not misaligned. Therefore, misalignment of the vertical portion 64a and the like can be prevented, and the lead frame 60 can be maintained at the predetermined joining position. As a result, the semiconductor device can be properly manufactured.

[0110] The foregoing merely illustrates the principles of the application. Furthermore, all examples and conditional language recited herein are principally intended to be only for pedagogical purposes to aid the reader in understanding the principles of the application and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions.

Claims

1. A semiconductor device, characterized by comprising: Possessing: a semiconductor chip; an insulating circuit substrate having an insulating board, and a circuit pattern provided to the insulating board and electrically connected to the semiconductor chip; and a wiring member including a leg portion engaged with the circuit pattern at one end, and having an external connection terminal at the other end, the leg portion possesses: a vertical portion extending in a vertical direction with respect to the circuit pattern; a first branch portion bent from a bifurcated portion of a lower end portion of the vertical portion on the side of the circuit pattern to a predetermined direction and extending in parallel with respect to the circuit pattern, and engaged with the circuit pattern; a second branch portion bent from the bifurcated portion to an opposite direction of the predetermined direction and extending in parallel with respect to the circuit pattern, and engaged with the circuit pattern, a first continuation portion connecting the bifurcated portion of the vertical portion and the first branch portion, and exhibiting elasticity; and a second continuation portion connecting the bifurcated portion of the vertical portion and the second branch portion, and exhibiting elasticity, the first branch portion extends in parallel with respect to the circuit pattern in a manner that the first continuation portion is bent, the second branch portion extends in parallel with respect to the circuit pattern in a manner that the second continuation portion is bent.

2. The semiconductor device according to claim 1, wherein the leg portion is plate-shaped, and the first branch portion and the second branch portion are bifurcated to opposite sides of the thickness direction of the leg portion, respectively.

3. The semiconductor device according to claim 2, wherein a first thickness of the first branch portion and a second thickness of the second branch portion are thicknesses obtained by halving a third thickness of the vertical portion.

4. The semiconductor device according to claim 2, wherein a first width of the first branch portion and a second width of the second branch portion are widths obtained by halving a third width of the vertical portion.

5. The semiconductor device according to claim 4, wherein a group of the first branch portion and the second branch portion is divided into a plurality of groups of the first branch portion and the second branch portion, for the leg portion.

6. The semiconductor device according to claim 4 or 5, wherein a first area of the first branch portion in plan view is equal to a second area of the second branch portion in plan view.

7. The semiconductor device according to claim 1, wherein a length from the bifurcated portion to a first front end portion in the predetermined direction of the first branch portion is the same as a length from the bifurcated portion to a second front end portion in the opposite direction of the predetermined direction of the second branch portion.

8. The semiconductor device according to claim 1, wherein the wiring member includes a plurality of the leg portions, and the wiring member further possesses a main body portion connected to upper end portions of the leg portions, the upper end portions being on the opposite side from the lower end portions.

9. The semiconductor device according to claim 8, wherein the main body portion further extends in a predetermined wiring direction, and the leg portions are arranged in parallel in the wiring direction. ​ 10. The semiconductor device according to claim 9, wherein the leg portions are connected to the body portion in a manner that the predetermined direction is parallel to the wiring direction.

11. The semiconductor device according to claim 9 or 10, further comprising a heat dissipation plate, wherein the plurality of insulating circuit boards are arranged on the heat dissipation plate in the wiring direction, and wherein the wiring member is arranged so that the body portion extends in the wiring direction across the insulating circuit boards, and the leg portions are engaged with the insulating circuit boards, respectively.

12. The semiconductor device according to claim 10, wherein the first branch portion and the second branch portion included in each of the plurality of leg portions are arranged in a row with respect to the body portion in the wiring direction.

13. The semiconductor device according to claim 1, wherein a total thickness of a thickness of the first extension portion and a thickness of the second extension portion is a same thickness as a thickness of the vertical portion. including: a preparation step of preparing an insulating circuit board having an insulating board and a circuit pattern provided to the insulating board, and a wiring member including a leg portion engaged with the circuit pattern at one end and having an external connection terminal at the other end, the leg portion including a vertical portion extending in a vertical direction with respect to the circuit pattern, a first branch portion bent from a bifurcated portion of a lower end portion of the vertical portion on a side of the circuit pattern in a predetermined direction and extending in parallel with respect to the circuit pattern and engaged with the circuit pattern, and a second branch portion bent from the bifurcated portion in a direction opposite to the predetermined direction and extending in parallel with respect to the circuit pattern and engaged with the circuit pattern; and an ultrasonic bonding step of simultaneously bonding the first branch portion and the second branch portion by ultrasonic bonding with the circuit pattern arranged with the first branch portion and the second branch portion of the leg portion, the leg portion further including: a first extension portion connecting the bifurcated portion of the vertical portion and the first branch portion and exhibiting elasticity; and 14. A method of manufacturing a semiconductor device, characterized by a second extension portion connecting the bifurcated portion of the vertical portion and the second branch portion and exhibiting elasticity, the first branch portion extending in parallel with respect to the circuit pattern in a manner that the first extension portion is bent, the second branch portion extending in parallel with respect to the circuit pattern in a manner that the second extension portion is bent.

15. The method of manufacturing a semiconductor device according to claim 14, wherein the wiring member includes a plurality of the leg portions, and the leg portions are engaged with the circuit patterns of the plurality of insulating circuit boards, respectively. including: ​ ​ ​ ​ ​ ​ 16. A method of manufacturing a semiconductor device, characterized by ​ The preparation step prepares a plurality of insulating circuit boards each having an insulating board and a circuit pattern provided to the insulating board, and a wiring member including a plurality of leg portions at one end and an external connection terminal at the other end, the plurality of leg portions each corresponding to the plurality of insulating circuit boards and being engaged with the circuit pattern, the plurality of leg portions each including a vertical portion extending in a vertical direction with respect to the circuit pattern, a first branch portion bent from a bifurcated portion of a lower end portion of the vertical portion on a side of the circuit pattern to a predetermined direction and extending in parallel with respect to the circuit pattern and being engaged with the circuit pattern, and a second branch portion bent from the bifurcated portion to a direction opposite to the predetermined direction and extending in parallel with respect to the circuit pattern and being engaged with the circuit pattern, and and the ultrasonic bonding step ultrasonically bonds the first branch portion and the second branch portion to the circuit pattern in the one direction for each of the plurality of leg portions, the leg portion further includes a first extension portion connecting the bifurcated portion of the vertical portion and the first branch portion and exhibiting elasticity, and a second extension portion connecting the bifurcated portion of the vertical portion and the second branch portion and exhibiting elasticity, the first branch portion extends in parallel with respect to the circuit pattern in a manner that the first extension portion is bent, the second branch portion extends in parallel with respect to the circuit pattern in a manner that the second extension portion is bent.

17. The method according to claim 14 or 16, wherein a total thickness of a thickness of the first extension portion and a thickness of the second extension portion is a same thickness as a thickness of the vertical portion.

Images