Random access sensor

Abstract

A circuit, such as that of a CMOS sensor, is described, having individually addressable transfer transistors and individually addressable reset transistors. Through these individually addressable transistors, pixels of the same or different sizes and / or the same or different exposure times within different regions of interest can be efficiently processed. Different regions of interest can be exposed simultaneously and read out independently.

Description

[0001] Cross-referencing of relevant cases

[0002] This application claims priority to co-pending provisional U.S. Application No. 62 / 947,579, filed December 13, 2019, entitled “Random Access Sensor”, and non-provisional U.S. Application No. 16 / 952,418, filed November 19, 2020, entitled “Random Access Sensor”. Technical Field

[0003] Various aspects of this disclosure relate to a randomly addressable sensor. Background Technology

[0004] CMOS sensors are widely used in image capture environments. The pixel array in a CMOS sensor can be exposed using different techniques, including: a global shutter, where all pixels are exposed simultaneously at the same exposure interval; and a rolling shutter, where pixels are typically exposed row by row sequentially. In photography and some video applications, rolling shutters can unnaturally distort images due to the incorporation of motion artifacts. In other applications, the ability to quickly capture and read out captured data is more important. Summary of the Invention

[0005] The following description provides a simplified summary of certain features. This description is not a broad overview and is not intended to identify the most important or critical elements.

[0006] A circuit, such as a CMOS sensor, is disclosed having individually addressable transfer transistors and individually addressable reset transistors. Through the individually addressable transistors, pixels of the same or different sizes and / or the same or different exposure times within different regions of interest can be efficiently processed. Different regions of interest can be exposed simultaneously and read out independently. Therefore, systems, apparatus, and methods for random access to a CMOS sensor are described. The CMOS sensor may include a photodiode, a floating diffusion node, and a transfer transistor connecting the photodiode to the floating diffusion node. The transfer transistor may be selected by two or more transfer selection signals. The transfer selection signals may be combined by one or more transistors connected to control the operation of the transfer transistor. By using two or more transfer selection signals, the transfer transistor can be individually addressed. The output of the CMOS sensor may include a source follower output. The CMOS sensor may include a reset transistor and / or a selection transistor, wherein the transistor can be controlled by two or more selection signals. Using a combination of selection signals, the relevant transistor can be individually addressed. The CMOS sensor may include one or more regions of interest (ROIs), wherein each ROI is handled by one or more sets of control circuitry systems.

[0007] Therefore, this disclosure includes CMOS sensors, pixels, and / or circuitry, including circuitry comprising a first transfer transistor connecting a photodiode to a floating diffusion node, wherein the first transfer transistor can be individually selected by a combination of: (i) a first transfer selection input, and (ii) a second transfer selection input; an output transistor in a source follower configuration, the gate of which is connected to the floating diffusion node; and a selection transistor connected to the output of the output transistor. In some embodiments, the circuitry further includes a first transfer selection transistor whose gate terminal is connected to (i) the first transfer selection input, or (ii) the second transfer selection input, wherein the first transfer selection transistor is connected between: (1) the gate terminal of the first transfer transistor, and (2) the other of: (a) the first transfer selection input or (b) the second transfer selection input.

[0008] In one or more aspects, the circuit further includes: a separately addressable first reset select input; a separately addressable second reset select input; a reset transistor connected between one or more potentials and a floating diffusion node; and a first reset select transistor whose gate terminal is connected to: (i) the first reset select input, or (ii) the second reset select input, wherein the first reset select transistor is additionally connected between: (1) the gate terminal of the reset transistor, and (2) the other of: (a) the first reset select input, or (b) the second reset select input. The circuit also includes a second transfer select transistor, wherein the second transfer select transistor includes a gate terminal connected to (i) the first transfer select input or (ii) the complement of the second transfer select input, wherein the second transfer select transistor is additionally connected between: (1) the gate terminal of the first transfer transistor, and (2) one or more potentials.

[0009] In some embodiments, the circuit further includes a second reset selection transistor, wherein the gate terminal of the second reset selection transistor is connected to a complement of (i) the first reset selection input or (ii) the second reset selection input, and the second reset selection transistor is additionally connected between (1) the gate terminal of the reset transistor and (2) one or more of the potentials.

[0010] A circuit is also disclosed, the circuit further comprising a transfer selection transistor whose gate terminal is connected to one of (i) the first transfer selection input or (ii) the second transfer selection input, the transfer selection transistor being additionally connected between: (1) the gate terminal of the first transfer transistor, and (2) the other of: (a) the first transfer selection input or (b) the second transfer selection input.

[0011] The circuit further includes: a separately addressable first reset select input; a separately addressable second reset select input; a reset transistor connected between at least one potential and the floating diffusion node; and a reset select transistor whose gate terminal is connected to either (i) the first reset select input or (ii) the second reset select input, the reset select transistor being additionally connected between: (1) the gate terminal of the reset transistor, and (2) the other of: (a) the first reset select input, and (b) the second reset select input. In an embodiment, the circuit includes at least one anti-corona transistor. In one or more embodiments, the circuit includes at least one transfer select control circuit configured to (i) separately address the first transfer select input, and (ii) separately address the second transfer select input.

[0012] The circuits described herein can be used, for example, in a spectrometer system, and therefore a spectrometer including the circuits described herein is also disclosed.

[0013] A CMOS sensor is also disclosed, comprising: at least one source follower output; at least one transfer selection control circuit configured to control (i) a separately addressable first transfer selection input, and (ii) a separately addressable second transfer selection input; a pixel array comprising: (a) a photodiode; (b) a floating diffusion node; (c) a transfer transistor connecting the photodiode to the floating diffusion node, wherein the transfer transistor can be individually selected by a combination of the first transfer selection input and the second transfer selection input; and (d) an output transistor in a source follower configuration connecting the floating diffusion node to an output node; and a controller configured to control the at least one transfer selection control circuit for exposure: (i) a first pixel of the pixel array lasts for a first time length, and (ii) a second pixel of the pixel array lasts for a second time length, the second time length being independent of the first time length. In some embodiments, the first time length is different from the second time length, and / or simultaneously in some embodiments, the first time length and the second time length begin at different times.

[0014] The CMOS sensor may further include: a multiplexer; and a plurality of readout circuits, wherein: a first readout circuit is connected via the multiplexer during a first readout time to read the value at the output of a first source follower, and a second readout circuit is connected via the multiplexer during a second readout time to read the value at the output of a second source follower. In an embodiment, the second readout time is independent of the first readout time.

[0015] Therefore, it can be understood that the disclosed CMOS sensor may include the following embodiments, wherein a first pixel and a second pixel are in a first row, wherein at least the first pixel is exposed for a first exposure time, and wherein at least the second pixel is exposed for a second exposure time, the second exposure time being independent of and / or different from the first exposure time. In some embodiments, the first pixel and the second pixel are in a first column, wherein at least the first pixel is exposed for a first exposure time, and wherein at least the second pixel is exposed for a second exposure time, the second exposure time being independent of and / or different from the first exposure time. In some CMOS sensors, a photodiode is arranged between a transfer transistor and a light source, and in some systems, the light source is a spectrometer. Therefore, those skilled in the art will recognize that the disclosed methods and systems are applicable to light sources emitting coherent and incoherent light, and thus the sensor can be monochromatic or color, and the applications of the sensor can include, but are not limited to, sensing applications, imaging applications, etc.

[0016] A CMOS sensor is also disclosed, comprising: at least one photodiode; at least one floating diffusion node; at least one output node; at least one individually addressable first transfer selection input; at least one individually addressable second transfer selection input; at least one transfer transistor connecting the first photodiode to the first floating diffusion node, wherein the first transfer transistor can be individually selected by a combination of: (i) one of the first transfer selection inputs, and (ii) one of the second transfer selection inputs; and at least one output transistor in a source follower configuration connecting the at least one first floating diffusion node to the at least one output node. The CMOS sensor may further include at least one first transfer selection transistor whose gate terminal is connected to: (i) one of the first transfer selection inputs, or (ii) one of the second transfer selection inputs, wherein the first transfer selection transistor is additionally connected between: (1) the gate terminal of the at least one first transfer transistor, and (2) the other of: (a) the first transfer selection input, or (b) the second transfer selection input. The CMOS sensor may further include: at least one individually addressable first reset select input; at least one individually addressable second reset select input; at least one reset transistor connected between one or more potentials and the floating diffusion node; and at least one first reset select transistor whose gate terminal is connected to: (i) one of the first reset select inputs, or (ii) one of the second reset select inputs, wherein the first reset select transistor is additionally connected between: (1) the gate terminal of one of the reset transistors, and (2) the other of: (a) the first reset select input, or (b) the second reset select input.

[0017] The disclosed CMOS sensor may further include: a second transfer selection transistor, the gate terminal of which is connected to (i) a complement of one of the first transfer selection inputs or (ii) a complement of one of the second transfer selection inputs, the second transfer selection transistor being additionally connected between: (i) the gate terminal of the first transfer transistor, and (ii) one or more potentials. In an embodiment, the CMOS sensor further includes: a second reset selection transistor, wherein the gate terminal of which is connected to a complement of (i) a first reset selection input or (ii) a complement of one of the second reset selection inputs, the second reset selection transistor being additionally connected between: (i) the gate terminal of the first reset transistor, and (ii) one or more of the potentials.

[0018] The CMOS sensor may further include: at least a first transfer selection transistor, the gate terminal of which is connected to one of (i) the first transfer selection input or (ii) the second transfer selection input, the first transfer selection transistor being additionally connected between: (i) the gate terminal of the first transfer transistor, and (ii) the other of: (a) the first transfer selection input or (b) the second transfer selection input. In an embodiment, the CMOS sensor may further include at least one transfer selection transistor, wherein the first transfer selection transistor is configured as a source follower and connected between the first photodiode and the first floating diffusion node. In some embodiments, the CMOS sensor may further include: at least one individually addressable first reset select input; at least one individually addressable second reset select input; at least one reset transistor connected between at least one potential and the floating diffusion node; and at least one reset select transistor, the gate terminal of the first reset select transistor being connected to one of (i) the first reset select input or (ii) the second reset select input, the first reset select transistor being additionally connected between: (1) the gate terminal of one of the reset transistors, and (2) the other of: (a) the first reset select input, or (b) the second reset select input.

[0019] In some implementations, the CMOS sensor further includes at least one transfer selection control circuit configured to (i) address the first transfer selection input separately, and (ii) address the second transfer selection input separately.

[0020] In one or more embodiments, the CMOS sensor includes at least one anti-halo transistor. The CMOS sensor can be used in spectrometer systems, and therefore this disclosure includes spectrometer systems utilizing the disclosed CMOS sensor.

[0021] A CMOS sensor is also disclosed, comprising: at least one output; at least one transfer selection control circuit configured to control (i) a separately addressable first transfer selection input and (ii) a separately addressable second transfer selection input; a pixel array comprising: (a) a photodiode; (b) a floating diffusion node; (c) a transfer transistor connecting the photodiode to the floating diffusion node, wherein the transfer transistor can be individually selected by a combination of the first transfer selection input and the second transfer selection input; and (d) an output transistor in a source follower configuration connecting the floating diffusion node to the at least one output; and a controller configured to control the at least one transfer selection control circuit for exposure: (1) a first pixel of the pixel array lasts for a first time length, and (2) a second pixel of the pixel array lasts for a second time length, the second time length being independent of the first time length. In some embodiments, the first time length is different from the second time length, and / or the first time length and the second time length begin at different times.

[0022] In one or more embodiments, the CMOS sensor further includes: a multiplexer; and a plurality of readout circuits (e.g., a plurality of single analog-to-digital converter channels), wherein: a first readout circuit is connected via the multiplexer during a first readout time to read a value on the output of a first source follower, and a second readout circuit is connected via the multiplexer during a second readout time to read a value on the output of a second source follower. The second readout time may be independent of the first readout time.

[0023] In some embodiments, a first pixel and a second pixel are in a first row, wherein at least the first pixel is exposed for a first exposure time, and at least the second pixel is exposed for a second exposure time, the second exposure time being independent of the first exposure time. The first pixel and / or the second pixel may be in a first column, wherein at least the first pixel is exposed for the first exposure time, and at least the second pixel is exposed for a second exposure time, the second exposure time being independent of the first exposure time. In embodiments, a photodiode is arranged between the transfer transistor and the light source, wherein in some embodiments, the light from the light source is modified by optical components of a spectrometer. These and other features and advantages are described in more detail below. Attached Figure Description

[0024] Some features are shown in the accompanying drawings by way of example rather than limitation. In the drawings, the same numbers refer to similar elements.

[0025] Figure 1 The circuit / pixel of a CMOS sensor with three transistors is shown.

[0026] Figure 2 The circuit / pixel of a CMOS sensor with four transistors is shown.

[0027] Figure 3 The circuit / pixel of a CMOS sensor with anti-halo transistors is shown.

[0028] Figure 4 The circuit / pixel of a CMOS sensor with two transfer selection signals and an optional anti-corona transistor is shown.

[0029] Figure 5 An example timing diagram of a CMOS sensor with two transfer selection signals is shown.

[0030] Figure 6 An example logic table is shown illustrating the operation of a transfer transistor using two transfer select signals.

[0031] Figure 7 The circuit / pixel of a CMOS sensor with two transfer select signals and two reset select signals, as well as an optional anti-corona transistor, is shown.

[0032] Figure 8 An example timing diagram of a CMOS sensor with two transfer select signals and two reset select signals is shown.

[0033] Figure 9A An example logic table is shown illustrating the operation of a reset transistor using two reset select signals. Figure 9B An example logic table is shown illustrating the operation of a transfer transistor using two transfer select signals.

[0034] Figure 10A The circuit / pixel of a CMOS sensor with independent transistors controlling the operation of the transfer transistor and the reset transistor is shown. Figure 10B Shown with additional annotations Figure 10A An alternative view of the circuit / pixel.

[0035] Figure 11 It shows Figure 10B An example timing diagram of a CMOS sensor.

[0036] Figure 12A It shows Figure 10B Example logic table of the operation of the reset transistor. Figure 12B It shows Figure 10B Example logic table of the operation of the transfer transistor.

[0037] Figure 13A A circuit / pixel with a transfer transistor controlled by two transistors is shown. Figure 13B Shown with additional annotations Figure 13A An alternative view of the circuit / pixel.

[0038] Figure 14 It shows Figure 13B Example timing diagram of pixels.

[0039] Figure 15A It shows Figure 13B Example logic table of the reset transistor. Figure 15B It shows Figure 13B Example logic table of transfer transistors.

[0040] Figure 16A A circuit / pixel with two transfer transistors is shown. Figure 16B Shown with additional annotations Figure 16A An alternative view of the circuit / pixel.

[0041] Figure 17 It shows Figure 16B An example timing diagram of pixels.

[0042] Figure 18A It shows Figure 16B Example logic table of the reset transistor. Figure 18B It shows Figure 16B The logic table of the transfer transistor.

[0043] Figure 19 An illustrative timing diagram of a reset and transfer transistor with multiple reset and transfer selection signals is shown.

[0044] Figure 20 Example timing diagrams of two ROIs with different exposure times are shown.

[0045] Figure 21 A block diagram of the control circuit system and a CMOS pixel array with multiple ROIs is shown.

[0046] Figure 22 The diagram shows a circuit with six pixels in a region of interest (ROI).

[0047] Figure 23 A block diagram of the control circuit system and a CMOS array having ROIs managed by different control circuit systems is shown.

[0048] Figure 24 A block diagram of the control circuit system and the CMOS array responsible for sharing the ROI among the different control circuit systems is shown.

[0049] Figure 25 The diagram shows a circuit diagram of six pixels in the ROI controlled by different groups of control circuit systems.

[0050] Figure 26A pixel with multiple transfer selection signals, multiple reset selection signals, and multiple output selection transistors is shown.

[0051] Figure 27 The scheduling process when an ROI is activated is shown.

[0052] Figure 28 A block diagram of the hardware computing device is shown.

[0053] In view of the benefits of this disclosure, those skilled in the art will recognize that the precise arrangement, size, and positioning of the components in the figures are not necessarily drawn to scale or required to be so. A particular size and angle of one component relative to another component can be varied to provide a desired response or output from said component or a spectrometer system including said component. Detailed Implementation

[0054] The accompanying drawings, which form part of this disclosure, illustrate examples of this disclosure. It should be understood that the examples shown in the drawings and / or discussed herein are non-exclusive, and there are other examples that may illustrate how this disclosure can be practiced.

[0055] Optical sensors are used in a wide variety of applications and can be applied across industries. Charge-coupled devices (CCDs) have been used since the 1970s. Recently, CMOS sensors have become more prevalent because they are faster and generally cheaper than CCD sensors.

[0056] Random access CMOS sensors can be used in a variety of environments, including those requiring high-speed sensing of regions of interest (ROIs). For example, random access CMOS sensors can be used in diagnostic or testing equipment, including but not limited to spectrometers, high-speed cameras, and remote sensors. For spectrometers, random access CMOS sensors can be used to capture light at multiple wavelengths. Because the location of the light output from the spectrometer may be known in advance (e.g., based on the spectrometer's configuration), the ROI can be limited to specific areas where light is expected to be received by the pixel array.

[0057] When properly exposed, CMOS pixels, like other light-sensing devices, can be used as light intensity measurement devices. Overexposure or underexposure of a pixel can prevent it from accurately measuring light. Using the techniques shown in the figures and described in the accompanying text, random access CMOS pixels allow one or more variable exposure times and / or the use of different ROIs in high-speed environments. For illustrative purposes, the term "pixel" is used to describe an image element in a sensor array, where each pixel includes a photodiode or other photosensitive device. The term "circuit" is used to describe a combination of components. For example, the term "circuit" can be used to describe an addressable set of devices in a sensor array, where the set of devices may or may not include photodiodes or other photosensitive devices.

[0058] Figure 1 This includes a photodiode 101 connected between a potential (e.g., ground) and an output transistor in a source follower configuration. The gate of the output transistor 108 (in this disclosure, it will be understood that all references to "output transistor" may refer to a transistor in a source follower configuration) is connected to a terminal of the photodiode 101 and the drain of a reset transistor 105, wherein the reset transistor 105 is controlled by a reset signal 106 connected to its gate. The source of the reset transistor 105 is connected to what is shown as V... RST A potential of 102. In Figure 1 In this configuration, the floating diffusion node 104 is located at the gate of the output transistor 108. The select transistor 109 connects the terminals (source / drain) of the output transistor 108 to one or more output lines (one or more output nodes) leading to a readout circuit (not shown). It should be understood herein that the readout circuit corresponds to a single analog-to-digital converter (“ADC”) channel. The select transistor 109 can be controlled by a select signal 110 connected to the gate of the select transistor 109. Figure 1 In the remaining figures of this disclosure, transistors can be similar or different types (including p-type, n-type, or combinations thereof). For the purposes of this document, the term "gate" is intended to refer to the gate terminal of a transistor when used relative to a terminal of the transistor. Furthermore, the term "output node" can be used to describe the output of a selection transistor (e.g., selection transistor 109 or other selection transistors described herein). Therefore, it can be understood that the selection signal 110 can be a signal associated with, for example, row selection in a pixel array, while the readout circuit signal can be a signal that can be associated with, for example, a column in a pixel array, and vice versa.

[0059] Figure 1 The CMOS pixel can be described as having various operating states, including: a reset state (B), in which the charge on the output of photodiode 101 and / or the floating diffusion node 104 is reset; an exposure state (Exp), during which photodiode 101 is allowed to charge the terminals of output transistor 108; and a readout state (RO), during which output transistor 108 will charge V DD The potential difference between 107 and photodiode 101 is transferred to the terminals (e.g., source / drain) of selection transistor 109. Selection transistor 109 can be operated to allow a readout circuit to read the potential (based on the accumulated charge on the gate of output transistor 108) selectively supplied to selection transistor 109 by output transistor 108.

[0060] The accompanying drawings of the disclosed methods and systems include the use of one or more potentials, and it will be understood that these potentials may be different; however, in some embodiments they may be the same.

[0061] Figure 2 It shows something similar to Figure 1 The circuit includes an additional transfer transistor 202 located between the floating diffusion node 204 and the photodiode 201, which in turn is connected to a potential (e.g., ground). The transfer transistor 202 can be controlled by a transfer signal 203 connected to its gate. The transfer transistor 202 connects the photodiode 201 to the floating diffusion node 204. A reset transistor 205 can connect the floating diffusion node 204 to a constant potential (in...). Figure 2 The middle is represented as V DD 207) is connected. The reset transistor 205 can be controlled by a reset signal 206 connected to the gate of the reset transistor 205. The gate of the output transistor 208 can be connected to the floating diffusion node 204, and the terminals of the output transistor 208 (e.g., source / drain) can be connected to the terminals of the select transistor 209. The other terminal of the output transistor 208 can be connected to a constant potential (here, V). DD 207). Select transistor 209 connects the terminals of output transistor 208 to one or more output lines leading to a readout circuit (not shown). Select transistor 209 can be controlled by a select signal 210 connected to the gate of select transistor 209. Output transistor 208 (also as...) Figure 1 As shown, 108) provides high impedance to the floating diffusion node 204, thereby allowing for more consistent readout operations across the pixel array. The addition of the transfer transistor 202 allows for the inclusion of another reset state (e.g., reset state (F)) in which the floating diffusion node 204 is reset (e.g., to remove dark current, parasitic sensitivity, etc.). Therefore, the four states can be used... Figure 2 The states are identified as: Reset state (B) (during which the charge on the output of photodiode 201 and / or floating diffusion node 204 is reset), Exposure state (Exp) (during which the photodiode 201 is allowed to accumulate charge), Reset state (F) (during which the floating diffusion node is reset), and Readout state (RO) (during which the charge accumulated by photodiode 201 is transferred to the floating diffusion node).

[0062] Figure 3 It shows that according to Figure 1 The pixels, but with anti-corona connection. The anti-corona transistor 310 can be connected to the photodiode 301 with a constant voltage potential (here, V). DD Between 307). The anti-corona signal 311 can be connected to the gate of the anti-corona transistor 310.

[0063] In some applications, an entire pixel array can be operated to obtain an image that illuminates the array. In other applications, it may be desirable to monitor only a specific region of interest (ROI). The effective speed of a CMOS sensor can be improved by reducing the number of pixels to be activated during operation and the corresponding state control for each pixel (e.g., reset, exposure, readout). For example, in some applications, an entire row can be selected for exposure. The row can be exposed as part of a global shutter or a rolling shutter. One problem with exposing an entire row, for example, is that other pixels on the same row cannot be subsequently exposed for different time periods. A similar problem exists, for example, when attempting to read pixels sharing the same column, because attempting to read two pixels in the same column simultaneously can create a "conflict" between the readout states of the pixels (i.e., charges from both pixels are simultaneously fed into the common column, preventing the readout circuitry from distinguishing the charges of the two pixels). A similar problem can exist when attempting to read data from pixels in the same row.

[0064] Such as about Figure 4 As described in the following figures, the disclosed systems and methods include CMOS sensor arrays that allow for individualized pixel control. Figure 4 As shown, such a system, method, and / or circuitry can achieve this by using a rolling shutter that exposes a selected portion of a CMOS sensor array when the transfer transistors and / or reset transistors can be controlled by more than one transfer selection signal or more than one reset selection signal. Therefore, the rolling shutters for individual pixels may have overlapping or non-overlapping exposure times. Depending on the control circuitry, readout intervals may be cascaded or allowed to overlap. For example, for a given ROI, similar waveforms can be used to control the individual transfer, reset, and selection transistors. Those similar waveforms may or may not be time-shifted.

[0065] Figure 4 A pixel is shown with the gate of a transfer transistor controlled by two transfer selection signals TXx 411 and TXy 412. Figure 4 This includes a photodiode 401 connected between a potential (e.g., ground) and a transfer transistor 402. The transfer transistor 402 can be controlled by a transfer signal connected to its gate. As shown, two or more transfer selection signals (TXx 411 and TXy 412) driving the gate of the transfer transistor 402 are thus used in combination to control the transfer transistor 402 and therefore independently of the function of other pixels (including those that may be in the same row and / or column). Figure 4As shown, functionally, two or more transfer selection signals TXx 411 and TXy 412 can be understood as equivalents input to the AND logic gate 403, but it is understood that this function can be implemented in many different ways, and Figure 4 The AND gate 403 is merely a representation of this function. The transfer transistor 402 connects the photodiode 401 to the floating diffusion node 404. An optional anti-corona transistor 413 can connect the photodiode 401 to a potential (e.g., V). DD 407), and the gate of the anti-corona transistor 413 can be driven by the anti-corona selection signal 414. The reset transistor 405 can set the floating diffusion node 404 to a constant potential (in Figure 4 The middle is represented as V DD 407) is connected to the gate of the reset transistor 405. The gate of the output transistor 408 can be connected to the floating diffusion node 404, and the terminals of the output transistor 408 (e.g., source / drain) can be connected to the terminals of the select transistor 409. The other terminal of the output transistor 408 can be connected to a constant potential (here, V). DD 407). Select transistor 409 connects the terminals of output transistor 408 to one or more output lines leading to a read circuit (not shown). Select transistor 409 can be controlled by a select signal 410 connected to the gate of select transistor 409.

[0066] The benefits of having multiple transfer selection lines include one or more of the following: individual pixel control, allowing for individual addressing of each pixel; increased flexibility in when a particular ROI can be reset, exposed, reset, and readout; control of conflicts during these operations by allowing the state of each ROI to be sorted across the CMOS sensor; increased flexibility of ROIs on the CMOS sensor by allowing ROIs to have different sizes, positions, and exposure times; increased flexibility in readout time for each ROI; and increased flexibility in the number of available states for each ROI.

[0067] Figure 5 It shows that according to Figure 4 An example timing diagram of a CMOS sensor. Figure 5 It includes a reset signal 406, a first transfer selection signal TXx 411, and a second transfer selection signal TXy 412. Figure 5 The operation of reset transistor 405 in response to reset signal 406 is also shown. When reset signal 406 changes from a first level to a second level (in... Figure 5 (As shown in the diagram, when the voltage changes from a low voltage state to a high voltage state, the reset transistor is turned on.)

[0068] Figure 5The operation of the transfer transistor 402 in response to a combination of a first transfer selection signal TXx 411 and a second transfer selection signal TXy 412 is also illustrated. The transfer transistor is turned on when both the first transfer selection signal TXx 411 and the second transfer selection signal TXy 412 are in a high voltage state. However, the transfer transistor is turned off when one or both of the transfer selection signals TXx 411 and TXy 412 are in a low voltage state.

[0069] The transistors shown in the figures and described in the specification can be edge-triggered, level-triggered, or a combination of both. Therefore, for example, regarding... Figure 5 The reset transistor and / or transfer transistor can only be turned on by the corresponding triggering method.

[0070] Figure 6 It shows Figure 4 Example logic table showing the operation of a transfer transistor using two transfer select signals. The first TXx transfer select signal has two possible values ​​{0, 1}. Figure 6 The table shows the row identifiers, and the two possible values ​​{0,1} of the second TXy transfer selection signal are in... Figure 6 The values ​​are shown as column identifiers in the table. The transfer transistor is off when at least one transfer select signal is {0}. The transfer transistor is on when both transfer select signals are {1}.

[0071] Figure 7 The diagram illustrates a pixel, which may be, for example, a CMOS sensor, in which the gate of a transfer transistor 702 is controlled by two transfer select signals and the gate of a reset transistor 705 is controlled by two reset select signals, thereby allowing for personalized transfer and reset of the pixel relative to other pixels in the array. Figure 7 This includes a photodiode 701 connected between a potential (e.g., ground) and a transfer transistor 702. Optionally, the photodiode 701 may be additionally connected to an anti-corona transistor 715 that can be driven by an anti-corona selection signal 716. The transfer transistor 702 can be driven by a transfer signal connected to the gate of the transfer transistor 702 (in... Figure 7 Functionally represented as an AND logic gate 703, this controls the process. Transfer transistor 702 connects photodiode 701 to floating diffusion node 704. Reset transistor 705 can connect floating diffusion node 704 to a constant potential (at...). Figure 7 The middle is represented as V DD 707) is connected in series. The reset transistor 705 can be activated by a reset signal connected to its gate (in the...). Figure 7Functionally represented as an AND logic gate 706, this is controlled by the output transistor 708. The gate of the output transistor 708 can be connected to the floating diffusion node 704, and the terminals of the output transistor 708 (e.g., source / drain) can be connected to the terminals of the select transistor 709. The other terminal of the output transistor 708 can be connected to a constant potential (here, V). DD 707). Select transistor 709 connects the terminals of output transistor 708 to one or more output lines leading to a read circuit (not shown). Select transistor 709 can be controlled by a select signal 710 connected to the gate of select transistor 709. AND gate 703 can receive two or more transfer select signals as inputs, represented by a first transfer select signal TXx 711 and a second transfer select signal TXy 712. By using two or more transfer select signals for a given transfer transistor, the transfer transistor can be addressed individually compared to addressing only the entire row (or column) of the transfer transistor. Figure 7 The reset selection AND gate 706 can receive two or more reset selection signals, represented by a first reset selection signal RSTx 713 and a second reset selection signal RSTy 714, as inputs. By using two or more reset selection signals on a given reset transistor, the reset transistor can be addressed individually compared to addressing only the entire row (or column) of the reset transistor.

[0072] Figure 8 A circuit with two transfer select signals and two reset select signals is shown (e.g., according to...). Figure 7 An example timing diagram of the pixels of a CMOS sensor. (Reference) Figure 7 The circuit, Figure 8 This includes a first reset select signal RSTx 713, a second reset select signal RSTy 714 with a different width than the first reset signal RSTx 713 (or in a "high" state for different (e.g., longer or shorter) time periods), a first transfer select signal TXx 711, and a second transfer select signal TXy 712 with a different width than the first transfer select signal TXx 711 (or in a "high" state for different time periods). However, it is understood that the first reset select signal RSTx and the second reset select signal RSTy, as well as the first transfer select signal TXx and the second transfer select signal TXy, can have the same width / duration (or be "high" for the same amount of time), or different (e.g., relatively "longer" or "shorter") width / duration (e.g., RST transistor relative to Tx transistor or RSTx / TXx transistor relative to RSTy / TXy transistor). Therefore, the timing is consistent with the various example timings provided herein. Figure 1 As can be seen, other variations of sequence diagrams may be more suitable for specific applications, and this disclosure should not be limited to these sequence diagram examples.

[0073] Figure 8 The operation of reset transistor 705 in response to the first reset signal RSTx 713 and the second reset signal RSTy 714 is shown. As illustrated, the reset transistor is turned on when both reset selection signals RSTx 713 and RSTy 714 are in a high voltage state. However, the reset transistor is turned off when one or both of the reset selection signals RSTx 713 and RSTy 714 are in a low voltage state. In situations such as... Figure 7 and Figure 8 In some implementations of the example implementation, it can be determined that TXx is higher over a longer period than TXy, and similarly, RSTx is higher over a longer period than RSTy.

[0074] Figure 8 The operation of the transfer transistor 702 in response to a combination of transfer selection signals TXx 711 and TXy 712 is also shown. The transfer transistor is turned on when both transfer selection signals TXx 711 and TXy 712 are in a high voltage state. However, the transfer transistor is turned off when one or both of the transfer selection signals TXx 711 and TXy 712 are in a low voltage state.

[0075] Figure 9A An example logic table is shown, illustrating the operation of the reset transistor in response to the first reset select signal 713 and the second reset select signal 714. The two values ​​{0, 1} of the RSTx reset select signal are... Figure 9A The table shows the row identifiers, and the two values ​​{0,1} of the RSTy reset select signal are in... Figure 9A The values ​​are shown as column identifiers in the table. The reset transistor is off when at least one reset select signal is {0}. The reset transistor is on when both reset select signals are {1}.

[0076] Figure 9B An example logic table is shown, illustrating the operation of the transfer transistor in response to the transfer select signal. The two values ​​{0, 1} of the TXx transfer select signal are... Figure 9B The table shows the row identifiers, and the two values ​​{0,1} of the TXy transfer selection signal are in... Figure 9B The values ​​are shown as column identifiers in the table. The transfer transistor is off when at least one transfer select signal is {0}. The transfer transistor is on when both transfer select signals are {1}.

[0077] Figure 10A It shows that according to Figure 7 The circuitry, such as the pixels of a CMOS sensor, however, uses transistors instead of AND gates. Figure 10AIn the implementation scheme, separate transistors control the operation of transfer transistor 1002 and reset transistor 1005. As will be described herein, in Figure 10A In the implementation scheme, the transfer transistor 1002 and the reset transistor 1005 are "floating". Figure 10A The system includes a photodiode 1001 connected between a potential (e.g., VSS) and a transfer transistor 1002. The transfer transistor 1002 is connected between the photodiode 1001 and a floating diffusion node 1004. The gate of the transfer transistor 1002 is connected to the output of a transfer selection transistor 1003. The gate of the transfer selection transistor 1003 receives a first transfer selection signal TXx. The transfer selection transistor 1003 is connected between the gate of the transfer transistor 1002 and a second transfer selection signal TXy. Similarly, a reset transistor 1005 is connected between the floating diffusion node 1004 and a potential (e.g., VDDrst). The gate of the reset selection transistor 1006 receives a first reset selection signal RSTx. The reset selection transistor 1006 is connected between the gate of the reset transistor 1005 and a second reset selection signal RSTy. An output transistor 1008 is connected between a potential (e.g., VDDpix) and a selection transistor 1009. The gate of the output transistor 1008 is connected to the floating diffusion node 1004. Select transistor 1009 is connected between output transistor 1008 and readout circuitry (not shown). The gate of select transistor 1009 receives a select signal SEL. An optional anti-corona transistor 1016 is connected between photodiode 1001 and a potential (e.g., VDDpix). The gate of anti-corona transistor 1016 receives an anti-corona select signal AB.

[0078] Figure 10B Shown with additional annotations Figure 10A An alternative view of the pixels. Figure 10B This includes a photodiode 1001 connected between a potential (e.g., ground) and a transfer transistor 1002. The transfer transistor 1002 can be controlled by the output of a transfer selection signal 1003 connected to the gate of the transfer transistor 1002. The transfer transistor 1002 connects the photodiode 1001 to a floating diffusion node 1004. A reset transistor 1005 can connect the floating diffusion node 1004 to a constant potential (at ground). Figure 10BThe output transistor 1008 (represented as VDDrst 1007) is connected to the gate of the select transistor 1009. The gate of the output transistor 1008 can be connected to the floating diffusion node 1004, and the terminals of the output transistor 1008 (e.g., source / drain) can be connected to the terminals of the select transistor 1009. Another terminal of the output transistor 1008 can be connected to a constant potential (here, VDDsf 1015). The constant potentials VDDrst 1007 and VDDsf 1015 can be the same or different. The select transistor 1009 connects the terminals of the output transistor 1008 to one or more output lines leading to a readout circuit (not shown). The select transistor 1009 can be controlled by a select signal 1010 connected to the gate of the select transistor 1009. The transfer select transistor 1003 can receive two or more transfer select signals, represented by transfer select signals TXx 1011 and TXy 1012, as inputs. For example, the gate of transfer selection transistor 1003 can receive transfer selection signal TXx 1011 and connect its remaining terminals (e.g., the other of the source / drain terminals not connected to the gate of transfer transistor 1002) to transfer selection signal TXy 1012. By using two or more transfer selection signals 1003 for a given transfer selection transistor, transfer transistor 1002 can be addressed individually compared to addressing only the entire row of transfer transistors. Reset selection transistor 1006 can receive two or more reset selection signals represented by reset selection signals RSTx 1013 and RSTy 1014 as inputs. For example, the gate of reset selection transistor 1006 can receive reset selection signal RSTx 1013 and connect its remaining terminals (e.g., the other of the source / drain terminals not connected to the gate of reset transistor 1005) to reset selection signal RSTy 1014. By using two or more reset selection signals for a given reset transistor, reset transistor 1005 can be addressed individually compared to addressing only the entire row of reset transistors. Figure 10B It also includes an optional anti-corona transistor 1016 connected to the photodiode 1001. The other end of the anti-corona transistor 1016 can be connected to a constant potential (e.g., VDDsf1015). The gate of the anti-corona transistor 1016 can receive an anti-corona signal AB 1017.

[0079] Figure 11 An example timing diagram of a circuit (e.g., a CMOS sensor) according to FIG10 is shown, which has a first transfer selection signal 1011 and a second transfer selection signal 1012, and a first reset selection signal 1013 and a second reset selection signal 1014. Figure 11This includes the reset selection signal RSTx 1013, the reset selection signal RSTy 1014, the transfer selection signal TXx 1011, and the transfer selection signal TXy 1012. Figure 11 The operation of reset transistor 1005 in response to a reset signal (the output of reset select transistor 1006) is illustrated. The reset transistor is turned on when both reset select signals RSTx 1013 and RSTy 1014 are high. However, the transfer transistor is turned off when one or both of the reset select signals RSTx 1013 and RSTy 1014 are low.

[0080] Figure 11 The operation of the transfer transistor 1002 in response to a combination of transfer selection signals TXx 1011 and TXy 1012 is also shown. The transfer transistor is turned on when both TXx 1011 and TXy 1012 are in a high voltage state. However, the transfer transistor is turned off when one or both of the transfer selection signals TXx 1011 and TXy 1012 are in a low voltage state.

[0081] For according to Figure 10A and Figure 10B For circuits, such as pixels, it is understood that example RSTx is shown as having the same width as TXx (e.g., being in a high state for the same amount of time), and RSTy is shown as having the same width as TXy, but such implementations are merely illustrative and various other relationships between the TX and RST signals can be used, as determined by the use of the circuit. Furthermore, for example implementations, such as... Figure 11 As shown, the RSTx connected to the gate of the reset selection transistor 1006 may be longer than the signal RSTy connected to the source of the reset selection transistor 1006 (e.g., high for a longer period of time), but such an example implementation is merely illustrative. Similarly, as... Figure 11 As shown, the TXx connected to the gate of the transfer selection transistor 1003 may be longer than the signal TXy connected to the source of the transfer selection transistor 1003 (e.g., it may be in a high state for a longer period of time).

[0082] Figure 12A An example logic table is shown illustrating the reset select transistor and thus the operation of the reset transistor using the first and second reset select signals. The two values ​​{0, 1} of the RSTx reset select signal are... Figure 12A The table shows, for example, row identifiers, and the two values ​​{0,1} of the RSTy reset select signal are in... Figure 12AThe table shows, for example, column identifiers. When the RSTx signal is {0}, the reset select transistor floats. When the RSTx signal is {1} and the RSTy signal is {0}, the reset select transistor is off (represented by {0}). When both reset select signals are {1}, the reset select transistor and therefore the reset transistor are on (represented by {1}).

[0083] Figure 12B An example logic table is shown illustrating the operation of the transfer select transistor using the first and second transfer select signals. Figure 12B It shows Figure 10B An example of a logic table showing the operation of a transfer select transistor using first and second transfer select signals. The two values ​​{0, 1} of the TXx transfer select signal are... Figure 12B The table shows, for example, row identifiers, and the two values ​​{0,1} of the TXy transition selection signal are in... Figure 12B The table shows, for example, column identifiers. When the TXx signal is {0}, the transfer selection transistor floats. When the TXx signal is {1} and the TXy signal is {0}, the transfer selection transistor is off (represented by {0}). When both transfer selection signals are {1}, the transfer selection transistor and therefore the transfer transistor are on (represented by {1}).

[0084] Figure 13A An implementation of a circuit (e.g., a pixel of a CMOS sensor) is shown, the circuit being similar to Figure 10A However, the transfer and reset transistors are biased, not floating. For example... Figure 13A As shown, there is a transfer transistor 1302 controlled by two transfer selection transistors 1303a and 1303b, and a reset transistor 1305 controlled by two reset selection transistors 1306a and 1306b. Figure 13AA photodiode 1301 is connected between a potential (e.g., VSS) and a transfer transistor 1302. The transfer transistor 1302 is connected between the photodiode 1301 and a floating diffusion node 1304. The gate of the transfer transistor 1302 is connected to the output of a first transfer selection transistor 1303a. The gate of the first transfer selection transistor 1303a receives a first transfer selection signal TXx. The first transfer selection transistor 1303a is connected between the gate of the transfer transistor 1302 and a second transfer selection signal TXy. A second transfer selection transistor 1303b is connected between the gate of the transfer transistor 1302 and a potential (e.g., VSS). The second transfer selection transistor 1303b is connected to the complement of the first transfer selection signal (e.g., TXx_n). A reset transistor 1305 is also shown connected between the floating diffusion node 1304 and a potential (e.g., VDDrst). The gate of a first reset selection transistor 1306a receives a first reset selection signal RSTx. A first reset select transistor 1306a is connected between the gate of reset transistor 1305 and a second reset select signal RSTy. A second reset select transistor 1306b is connected between the gate of reset transistor 1305 and a potential (e.g., VSS). The second reset select transistor 1306b is connected to the complement of the first reset select signal (e.g., RSTx_n). An output transistor 1308 is connected between a potential (e.g., VDDpix) and a select transistor 1309. The gate of output transistor 1308 is connected to a floating diffusion node 1304. Select transistor 1309 is connected between output transistor 1308 and a readout circuit system (not shown). The gate of select transistor 1309 receives a first signal SEL. An optional anti-corona transistor 1316 is connected between photodiode 1301 and a potential (e.g., VDDpix). The gate of anti-corona transistor 1316 receives an anti-corona select signal AB.

[0085] Figure 13B Shown with additional annotations Figure 13A An alternative view of the circuitry (e.g., pixels). Figure 13B This includes a photodiode 1301 connected between a potential (e.g., ground) and a transfer transistor 1302. The transfer transistor 1302 can be controlled by the output of a transfer selection signal 1303a connected to the gate of the transfer transistor 1302. The transfer transistor 1302 connects the photodiode 1301 to a floating diffusion node 1304. A reset transistor 1305 can connect the floating diffusion node 1304 to a constant potential (at ground). Figure 13BThe output transistor 1308 (represented as VDDrst 1307) is connected to the gate of the select transistor 1309. The gate of the output transistor 1308 can be connected to the floating diffusion node 1304, and the terminals of the output transistor 1308 (e.g., source / drain) can be connected to the terminals of the select transistor 1309. Another terminal of the output transistor 1308 can be connected to a constant potential (here, VDDsf 1315). The constant potentials VDDrst 1307 and VDDsf 1315 can be the same or different. The select transistor 1309 connects the terminals of the output transistor 1308 to one or more output lines leading to a readout circuit (not shown). The select transistor 1309 can be controlled by a select signal 1310 connected to the gate of the select transistor 1309. The transfer select transistor 1303a can receive two or more transfer select signals, represented by transfer select signals TXx 1311a and TXy 1312, as inputs. For example, the gate of transfer select transistor 1303a can be connected to transfer select signal TXx 1311a and its remaining terminals (e.g., the other of the source / drain terminals not connected to the gate of transfer transistor 1302) can be connected to transfer select signal TXy 1312. Figure 13B This includes another transfer selection transistor 1303b connected between the gate of transfer transistor 1302 and a constant potential (e.g., ground). The gate of transfer selection transistor 1303b can be connected to the complement of transfer selection signal TXx 1311a (i.e., transfer selection signal / TXx 1311b). By using two or more transfer selection signals for a given transfer transistor, the transfer transistor can be addressed individually compared to addressing only the entire row (or column) of the transfer transistor.

[0086] The transfer selection transistors 1303a and 1303b can be the same type of transistor (p-type or n-type). Alternatively, the transfer selection transistors 1303a and 1303b can be different types of transistors (one p-type and one n-type). By making the transfer selection transistors 1303a and 1303b different types of transistors, the same transfer selection signal TXx1311a can be applied to the gates of both transfer selection transistors. With a high gate voltage, one is on and the other is off. Similarly, with a low gate voltage, one is off and the other is on. This method reduces the need for adding a separate inverter to create a complementary / TXx1311b signal.

[0087] The reset selection transistor 1306a can be connected to two or more reset selection signals represented by reset selection signals RSTx 1313a and RSTy 1314. For example, the gate of the reset selection transistor 1306a can be connected to the reset selection signal RSTx 1313a and its remaining terminals (e.g., another of the source / drain terminals not connected to the gate of the reset transistor 1305) can be connected to the reset selection signal RSTy 1314. Figure 13B This includes another reset selection transistor 1306b connected between the gate of reset transistor 1305 and a constant potential (e.g., ground). The gate of reset selection transistor 1306b can be connected to the complement of reset selection signal RSTx 1313a (i.e., reset selection signal / RSTx 1313b). By using two or more reset selection signals for a given reset transistor, the reset transistor can be addressed individually compared to addressing only the entire row (or column) of the reset transistor.

[0088] Reset select transistors 1306a and 1306b can be the same type of transistor (p-type or n-type). Alternatively, reset select transistors 1306a and 1306b can be different types of transistors (one p-type and one n-type). By making reset select transistors 1306a and 1306b different types of transistors, the same reset select signal RSTx1313a can be applied to the gates of both reset select transistors. With a high gate voltage, one is on and the other is off. Similarly, with a low gate voltage, one is off and the other is on. This method reduces the need for adding a separate inverter to create complementary / RSTx1313b signals.

[0089] Figure 13B It also includes an optional anti-corona transistor 1316 connected to the photodiode 1301. The other end of the anti-corona transistor 1316 can be connected to a constant potential (e.g., VDDsf 1315). The gate of the anti-corona transistor 1316 can receive an anti-corona signal AB 1317.

[0090] Figure 14 It shows that according to Figure 13B An example timing diagram of a circuit (e.g., a CMOS sensor) with two transfer select signals and two reset select signals. Figure 14 This includes the reset selection signal represented by RSTx and its complement / RSTx, the reset selection signal RSTy, the transfer selection signal represented by TXx and its complement / TXx, and the transfer selection signal TXy. Figure 14The operation of reset transistor 1305 in response to reset signals (the outputs of reset selection transistors 1306a and 1306b) is illustrated. When reset selection signals RSTx 1313a and RSTy 1314 are high and reset selection signal / RSTx 1313b is low, the reset transistor is turned on. However, when reset selection signal RSTx is low and reset selection signal / RSTx is high, reset transistor 1305 is turned off. Similarly, when reset selection signal RSTy is low, reset transistor 1305 is turned off.

[0091] Figure 14 The operation of transfer transistor 1302 in response to transfer signals (the outputs of transfer selection transistors 1303a and 1303b) is also shown. When transfer selection signals TXx 1311a and TXy 1312 are high and transfer selection signal / TXx 1311b is low, the transfer transistor is turned on. However, when transfer selection signal TXx is low and transfer selection signal / TXx is high, transfer transistor 1302 is turned off. Similarly, when transfer selection signal TXy is low, the transfer transistor is turned off. It can be understood that although... Figure 14 The diagram shows that the transfer selection signals TXx and TXy have the same length / duration in a high voltage / potential state, but this equality of duration is not required, and the two signals may differ.

[0092] Figure 15A An example logic table illustrating the operation of the reset transistor using reset select signals is shown. For illustrative purposes, a complete logic table is shown for the reset select signals RSTx 1313a, / RSTx 1313b, and RSTy 1314, each with a value {0,1}. When RSTx is {0} and / RSTx is {1}, the reset transistor is off (represented by {0}). When RSTx is {1}, / RSTx is {0}, and RSTy is {0}, the reset transistor is off (represented by {0}). When both RSTx and RSTy are {1} and / RSTx is {0}, the reset transistor is on (represented by {1}). Rows where RSTx and / RSTx have the same value include a single asterisk "*" after each value to indicate that the signals supplied to the gates of the reset select transistors 1306a and 1306b are not always complementary (i.e., they may be the same, for example, when they come from different sources). In these rows, the reset transistor is marked as floating. Additionally, in the rows marked with double asterisks "**", both reset select transistors 1306a and 1306b are on and may result in high current consumption.

[0093] Figure 15B An example logic table illustrating the operation of the transfer transistors using transfer select signals is shown. For illustrative purposes, a complete logic table is shown for the transfer select signals TXx 1311a, / TXx 1311b, and TXy 1312, each with a value {0,1}. The transfer transistor is off (represented by {0}) when TXx is {0} and / TXx is {1}. The transfer transistor is off (represented by {0}) when TXx is {1}, / TXx is {0}, and TXy is {0}. The transfer transistor is on (represented by {1}) when both TXx and TXy are {1} and / TXx is {0}. Rows where TXx and / TXx have the same value include a single asterisk "*" after each value to indicate that the signals supplied to the gates of transfer select transistors 1303a and 1303b are not always complementary (i.e., they may be the same, for example, when from different sources). In these rows, the transfer transistors are identified as floating. Furthermore, in the rows marked with double asterisks "**", both transfer selection transistors 1303a and 1303b are turned on and may result in high current consumption.

[0094] Figure 16A Another embodiment of the circuit (e.g., a pixel) is shown, which is similar to Figure 13A The circuit shown is only illustrated with the transfer transistors represented by the first transfer circuit 1602, whose functionality is shown for illustrative purposes as having two transfer transistors 1603a and 1603b. It will be understood that in embodiments, the transfer circuit 1602 can be implemented using a single transistor with two gate pins. Figure 16A This includes a photodiode 1601 connected between a potential (e.g., VSS) and a transfer circuit 1602. The transfer circuit 1602 is connected between the photodiode 1601 and a floating diffusion node 1604. The transfer circuit 1602 can be one or more transfer transistors, each controlled by a transfer selection signal. For example, the transfer circuit 1602 (in...) Figure 16AThe area shown (defined by dashed lines) may include a first transfer circuit selection transistor 1603a and a second transfer circuit selection transistor 1603b connected in series. The first transfer circuit selection transistor 1603a may receive a transfer selection signal TXx at its gate. The second transfer circuit selection transistor 1603b may receive a transfer selection signal TXy at its gate. A reset transistor 1605 is connected between the floating diffusion node 1604 and a potential (e.g., VDDrst). The gate of the reset selection transistor 1606 receives a first reset selection signal RSTx. The reset selection transistor 1606 is connected between the gate of the reset transistor 1605 and a second reset selection signal RSTy. An output transistor 1608 is connected between a potential (e.g., VDDpix) and a selection transistor 1609. The gate of the output transistor 1608 is connected to the floating diffusion node 1604. The selection transistor 1609 is connected between the output transistor 1608 and a readout circuit system (not shown). The gate of the selection transistor 1609 receives a selection signal SEL. An optional anti-corona transistor 1616 is connected between the photodiode 1601 and a potential (e.g., VDDpix). The gate of the anti-corona transistor 1616 receives an anti-corona selection signal AB.

[0095] Figure 16B For those with additional annotations Figure 16A An alternative view of the circuitry (e.g., pixels). Figure 16B This includes a photodiode 1601 connected between a potential (e.g., ground) and a transfer circuit 1602. The transfer circuit 1602 connects the photodiode 1601 to a floating diffusion node 1604. A reset transistor 1605 can connect the floating diffusion node 1604 to a constant potential (at ground). Figure 16B The output transistor 1608 (represented as VDDrst 1607) is connected to the gate of the select transistor 1609. The gate of the output transistor 1608 can be connected to the floating diffusion node 1604, and the terminals of the output transistor 1608 (e.g., source / drain) can be connected to the terminals of the select transistor 1609. Another terminal of the output transistor 1608 can be connected to a constant potential (here, VDDsf 1615). The constant potentials VDDrst 1607 and VDDsf 1615 can be the same or different. The select transistor 1609 connects the terminals of the output transistor 1608 to one or more output lines leading to a readout circuit (not shown). The select transistor 1609 can be controlled by a select signal 1610 connected to the gate of the select transistor 1609.

[0096] The second transfer circuit selection transistor 1603b can receive the transfer selection signal TXx 1611 at its gate, and as previously described, the first transfer circuit selection transistor 1603a can receive the transfer selection signal TXy 1612 at its gate. By using two or more transfer selection signals for a given transfer transistor, the transfer transistor can be addressed individually compared to addressing only an entire row (or column) of the transfer transistor.

[0097] Reset select transistor 1606 can receive two or more reset select signals, represented by reset select signals RSTx 1613 and RSTy 1614, as inputs. For example, the gate of reset select transistor 1606 can receive reset select signal RSTx 1613 and connect its remaining terminals (e.g., another of the source / drain terminals not connected to the gate of reset transistor 1605) to reset select signal RSTy 1614. Alternatively, reset transistor 1605 can be a reset circuit comprising two reset transistors, configured similarly to transfer circuit 1602. By using two or more reset select signals for a given reset transistor, the reset transistor can be addressed individually compared to addressing only an entire row (or column) of reset transistors.

[0098] Figure 16B It also includes an optional anti-corona transistor 1616 connected to the photodiode 1601. The other end of the anti-corona transistor 1616 can be connected to a constant potential (e.g., VDDsf 1615). The gate of the anti-corona transistor 1616 can receive an anti-corona signal AB 1617.

[0099] Alternatively, the reset transistor 1605 may be a reset circuit (similar to the transfer circuit 1602), wherein a dual-gate reset select transistor may be connected in series between the floating diffusion node 1604 and the potential VDDrst 1607, wherein one of the gates of the reset select transistor is controlled by RSTx 1613 and the other by RSTy 1614.

[0100] Figure 17 It shows that according to Figure 16B Example timing diagram of a circuit (e.g., a CMOS sensor) with two transfer select signals and two reset select signals. Figure 17 This includes the reset selection signal RSTx, the reset selection signal RSTy, the transfer selection signal TXx, and the transfer selection signal TXy. Figure 17The operation of the reset transistor in response to a reset signal, which is a combination of a reset selection signal RSTx and a reset selection signal RSTy, is illustrated. When both reset selection signals RSTx and RSTy are high, the reset transistor is turned on. However, when one or both of the reset selection signals RSTx and RSTy are low, the transfer transistor is turned off.

[0101] Figure 17 The operation of the transfer transistor in response to a combination of transfer select signals TXx and TXy is also shown. The transfer transistor is turned on when both transfer select signals TXx and TXy are in a high voltage state. However, the transfer transistor is turned off when one or both of the transfer select signals TXx and TXy are in a low voltage state.

[0102] Figure 18A As shown Figure 16B The example logic table shown illustrates the operation of the reset transistor using two reset select signals. The two values ​​{0, 1} of the RSTx reset select signal are... Figure 18A The table shows the row identifiers, and the two values ​​{0,1} of the RSTy reset select signal are in... Figure 18A The values ​​are shown as column identifiers in the table. When the RSTx signal is {0}, the reset transistor floats. When the RSTx signal is {1} and the RSTy signal is {0}, the reset transistor is off (represented by {0}). When both reset select signals are {1}, the reset transistor is on (represented by {1}).

[0103] Figure 18B As shown Figure 16B The example logic table shown illustrates the operation of the transfer transistor using two transfer select signals. The two values ​​{0, 1} of the transfer select signal TXx are... Figure 18B The table shows the row identifiers, and the two values ​​{0,1} of the transition selection signal TXy are in... Figure 18B The values ​​are shown as column identifiers in the table. When the TXx signal is {0}, the transfer transistor is off (represented by {0}). When the TXx signal is {1} and the TXy signal is {0}, the reset transistor is off. When both transfer select signals are {1}, the transfer transistor is on (represented by {1}).

[0104] Figure 19 An exemplary timing diagram of a reset and transfer transistor with multiple reset and transfer selection signals is shown. Figure 19 This shows a Region of Interest (ROI) with four pixels across four rows and one common column. ROI 1 includes pixels in each of rows J, J+1, J+2, and J+3. A rolling shutter is used to expose the pixels. Figure 19The timing diagram shows the reset select signal and transfer select signal for each of the four pixels. When RSTx <j>,TXx <j>、RSTy <cols>and TXy <cols>When the signal is high, the first pixel (in row J) enters the B reset state. When RSTx<J+1> ,TXx<J+1> 、RSTy <cols>and TXy <cols>When the signal is high, the second pixel (in row J+1) enters the B reset state. When RSTx<J+2> ,TXx<J+2> 、RSTy <cols>and TXy <cols>When the signal is high, the third pixel (in row J+2) enters the B reset state. When RSTx<J+3> ,TXx<J+3> 、RSTy <cols>and TXy <cols>When the signal is high, the fourth pixel (in row J+3) enters the B reset state. The B reset state of different pixel rows begins at different times.

[0105] To enter the Exp (exposure) state, the line-dependent selection signal is lowered to a low voltage level. When RSTx <j>and TXx <j>When the signal is low, the first pixel (in row J) enters the Exp state. When RSTx<J+1> and TXx<J+1> When the signal is low, the second pixel (in row J+1) enters the Exp state. When RSTx<J+2> and TXx<J+2> When the signal is low, the third pixel (in row J+2) enters the Exp state. When RSTx<J+3> and TXx<J+3> When the signal is low, the fourth pixel (in row J+3) enters the Exp state. Regardless of RSTy <cols>and TXy <cols>Regardless of the signal level, pixels will enter the Exp exposure state. Therefore, RSTy <cols>and TXy <cols>The signal is used to transfer RSTy <cols>and TXy <cols>The remaining pixels are reset before being set to a low voltage level. The Exp state for different pixel rows starts at different times.

[0106] To enter the F reset state, the reset select signal rises high, while the row-related transfer select signal remains low. When RSTx <j>The signal is high and RSTy <cols>When the signal is high, the first pixel (in row J) enters the F reset state. When RSTx<J+1> The signal is high and RSTy <cols>When RSTx is high, the second pixel (in row J+1) enters the F reset state.<J+2> The signal is high and RSTy <cols>When RSTx is high, the third pixel (in row J+2) enters the F reset state.<J+3> The signal is high and RSTy <cols>When the value is high, the fourth pixel (in row J+3) enters the F reset state. The F reset state for different pixel rows begins at different times.

[0107] To enter RO (readout) state, the row-dependent reset select signal goes low, while the row-dependent transfer select signal rises high. When RSTx <j>Signal is low, TXx <j>The signal is high and TXy <cols>When the signal is high, the first pixel (in row J) enters the RO state. When RSTx<J+1> Signal is low, TXx<J+1> The signal is high and TXy <cols>When the signal is high, the second pixel (in row J+1) enters the RO state. When RSTx<J+2> Signal is low, TXx<J+2> The signal is high and TXy <cols>When the signal is high, the third pixel (in row J+2) enters the RO state. When RSTx<J+3> Signal is low, TXx<J+3> The signal is high and TXy <cols>When the signal is high, the fourth pixel (in row J+3) enters the RO state. The RO state of different pixel rows begins at different times.

[0108] Figure 20 An exemplary timing diagram of two Regions of Interest (ROIs) with different exposure lengths is shown. The first ROI 0 comprises pixels in two rows (row k and row k+1). The second ROI 1 comprises pixels in four rows (row m, row m+1, row m+2, and row m+3). The exposure time of pixels in ROI 0 is longer than that of pixels in ROI 1. Other states in ROI 1 (including Reset B, Reset F, and Readout RO) are also shorter than their corresponding states in ROI 0. Alternatively, other states in ROI 1 (Reset B, Reset F, and Readout RO) may be the same or longer than their corresponding states in ROI 0. The Exp states of individual pixels in ROI 0 and ROI 1 may begin at different times, or two or more may begin simultaneously. The exposure time lengths between ROI 0 and ROI 1 may be the same or different.

[0109] Figure 21 An example block diagram of a control circuit system and a CMOS array with multiple ROIs is shown. Figure 21 The CMOS pixel array 2101 includes eight Regions of Interest (ROIs) (shown as ROI 0 to ROI 7), some of which (e.g., ROI 0, ROI 2, ROI 4, and ROI 6) appear on the left side of the CMOS pixel array 2101, and other ROIs (e.g., ROI 1, ROI 3, ROI 5, and ROI 7) appear on the right side of the CMOS pixel array 2101. The ROIs can be arranged to correspond to the CMOS pixel array region to be monitored, and thus, as... Figure 21 As shown, some ROIs can share the same row and / or column with other ROIs. Figure 21 The system includes a control circuitry system, which may include a control circuitry system 2102 for TXx, a control circuitry system 2103 for TXy, a control circuitry system 2104 for RSTx, and a control circuitry system 2105 for RSTy. Through the operation of the control circuitry, ROIs 0 to ROI 8 can be reset, exposed, reset, and readout in various timing sequences, including cases where two or more ROIs have different exposure times. Although in Figure 21 The control circuits 2102, 2103, 2104 and / or 2105 are represented as individual function blocks, but one or more control circuits can be combined into one or more combined control circuits as needed.

[0110] Figure 21 It also includes a multiplexer 2106 and several analog-to-digital converters (ADCs) 2107. The multiplexer 2106 allows a pixel of a column to be routed in a ROI to a specific ADC and read. For example, the multiplexer 2106 can direct all columns of ROI 0 to be read by a first set of ADCs, while directing less than all columns of ROI 1 to be read by a second set of ADCs, and the remaining columns to be read by a third set of ADCs. The ability of the multiplexer 2106 to selectively assign one or more columns of an ROI allows for improved interleaving of control over the pixel state in each ROI. An ADC, either alone or in combination with other circuitry including one or more multiplexers, can be understood as an example of a readout circuit.

[0111] Figure 22 It shows the method for using according to Figure 21 The example circuit diagram shows a ROI with six pixels in one implementation, but this disclosure is not limited to such an implementation. ROI 0 2201 is part of a larger CMOS pixel array, where pixels other than ROI 0 2201 are not shown. ROI 0 2201 includes six pixels in two columns (column 0 and column 1) and three rows (row 0, row 1, and row 2). Figure 22 Each pixel in the array includes two transfer selection inputs (TXx and TXy), two reset selection inputs (RSTx and RSTy), one anti-halo input (AB), one pixel selection input (Sel), and one output terminal (Out). Figure 22 It includes a first transfer control circuit 2202 having multiple transfer selection lines corresponding to the number of rows in the pixel array. Figure 22 It also includes a second transfer control circuit 2203 with multiple transfer selection lines corresponding to the number of columns in the pixel array. For simplicity, the first transfer control circuit 2202 and the second transfer control circuit 2203 are shown as having three selection lines and two selection lines, respectively, which correspond to the number of rows and columns associated with ROI 0 2201. Figure 22 It also includes a first reset selection control circuit RSTx 2204 and a second reset selection control circuit RSTy 2205.

[0112] Figure 22 Various control lines connected to sub-control lines are shown to allow pixels to receive relevant selection signals. Figure 22 The arrangement of the control lines is merely an example, and other arrangements can be easily used. For simplicity, the connections to the anti-halo input, selection input, and output terminals for each pixel are not shown.

[0113] Figure 23 A block diagram of an example control circuit system and a CMOS array having ROIs managed by different control circuit systems is shown. The CMOS array 2301 includes four ROIs (e.g., ROI 10, ROI 11, ROI 12, and ROI 13). Figure 21 Compared to a standard CMOS array, the ROI is handled by a different combination of control circuitry. The first transfer selection control circuit TXx 0 2302 supports the first group of rows, while the second transfer selection control circuit TXx 1 2303 supports the second group of rows. The first transfer selection control circuit TXy 0 2304 supports the first group of columns, while the second transfer selection control circuit TXy 1 2305 supports the second group of columns. The first reset selection control circuit RSTx 0 2306 supports the first group of rows, while the second reset selection control circuit RSTx 1 2307 supports the second group of rows. The first reset selection control circuit RSTy 0 2308 supports the first group of columns, while the second reset selection control circuit RSTy1 2309 supports the second group of columns. Multiplexer 2310 allows all pixels in the CMOS array 2301 to be read by any ADC 2311, or it can restrict columns of the CMOS array 2301 to be read by only one set of ADCs 2311.

[0114] For example, ROI 10 receives selection inputs from transfer selection control circuits TXx 0 2302, TXy 0 2304, RSTx 0 2306, and RSTy 0 2308. ROI 11 receives selection inputs from transfer selection control circuits TXx 0 2302, TXy 1 2305, RSTx 0 2306, and RSTy 1 2309. ROI 12 receives selection inputs from transfer selection control circuits TXx 1 2303, TXy 0 2304, RSTx 1 2307, and RSTy 0 2308. ROI 13 receives selection inputs from transfer selection control circuit TXx 1 2303, transfer selection control circuit TXy 1 2305, reset selection control circuit RSTx 1 2307, and reset selection control circuit RSTy 1 2309.

[0115] Figure 23 The method shown can be further extended to 2 N , where N is the total number of individual blocks in the CMOS array.

[0116] Figure 24 A block diagram of one embodiment of the control circuitry system and the CMOS array responsible for sharing each Region of Interest (ROI) among the different control circuitry systems is shown. The CMOS array 2401 includes three ROIs (e.g., ROI 20, ROI 21, and ROI 22). Each ROI is handled by a different combination of control circuitry systems. A first transfer selection control circuit TXx 0 2402 supports a first group of rows, while a second transfer selection control circuit TXx 1 2403 supports a second group of rows. A first transfer selection control circuit TXy 0 2404 supports a first group of columns, while a second transfer selection control circuit TXy 1 2405 supports a second group of columns. A first reset selection control circuit RSTx 0 2406 supports the first group of rows, while a second reset selection control circuit RSTx 1 2407 supports the second group of rows. A first reset selection control circuit RSTx 0 2408 supports the first group of columns, while a second reset selection control circuit RSTx 1 2409 supports the second group of columns. Multiplexer 2410 can enable all pixels in CMOS array 2401 to be read by any ADC 2411, or can restrict columns of CMOS array 2401 to be read by only one set of ADCs 2411.

[0117] For example, the first part of ROI 20 receives selection inputs from transfer selection control circuits TXx 0 2402, TXy 0 2404, RSTx 0 2406, and RSTy 0 2408. The second part of ROI 20 receives selection inputs from transfer selection control circuits TXx 1 2403, TXy 0 2404, RSTx 1 2407, and RSTy 0 2408.

[0118] The first part of ROI 21 receives selection inputs from transfer selection control circuits TXx 0 2402, TXy 1 2405, RSTx 0 2406, and RSTy 1 2409. The second part of ROI 21 receives selection inputs from transfer selection control circuits TXx 1 2403, TXy 1 2405, RSTx 1 2407, and RSTy 1 2409.

[0119] ROI 22 receives four different combinations of selection signals. The first part receives selection inputs from transfer selection control circuits TXx0 2402, TXy 0 2404, and reset selection control circuits RSTx 0 2406 and RSTy 0 2408. The second part of ROI 22 receives selection inputs from transfer selection control circuits TXx1 2403, TXy 0 2404, RSTx1 2407, and RSTy 0 2408. The third part of ROI 22 receives selection inputs from transfer selection control circuits TXx0 2402, TXy1 2405, RSTx 0 2406, and RSTy 1 2409. The fourth part of ROI 22 receives selection inputs from the transfer selection control circuit TXx 1 2403, the transfer selection control circuit TXy 1 2405, the reset selection control circuit RSTx 1 2407, and the reset selection control circuit RSTy 1 2409.

[0120] Although it may increase noise, Figure 24 This method allows for twice the processing speed of an ROI supported by only one set of circuitry systems.

[0121] Figure 25 An example circuit diagram is shown, illustrating six pixels in a region of interest (ROI) controlled by different groups of control circuitry systems. Figure 25 A circuit diagram is shown for a region of interest (ROI) containing six pixels. ROI 0 2501 is part of a larger CMOS pixel array, where pixels other than ROI 0 2501 are not shown. ROI 0 2501 comprises six pixels in two columns (column 0 and column 1) and three rows (row 0, row 1, and row 2). Figure 25 Each pixel in the array includes two transfer selection inputs (TXx and TXy), two reset selection inputs (RSTx and RSTy), one anti-halo input (AB), one pixel selection input (Sel), and one output terminal (Out). Figure 25 It includes a first transfer selection control circuit TXx A2502 having multiple transfer selection lines corresponding to the first portion of rows in the pixel array. Figure 25 It also includes a second transfer selection control circuit TXx B 2503 having multiple transfer selection lines corresponding to the second part of the column in the pixel array. Figure 25 It includes a third transfer selection control circuit TXy 0 2504 having multiple transfer selection lines corresponding to the first portion of the column in the pixel array. Figure 25 It also includes a fourth transfer selection control circuit TXy 1 2505 with multiple transfer selection lines corresponding to the second part of the column in the pixel array.

[0122] Figure 25 Includes a first reset selection control circuit RSTx A 2506 having multiple reset selection lines corresponding to the first portion of rows in the pixel array. Figure 25 It also includes a second reset selection control circuit RSTx B 2507 with multiple reset selection lines corresponding to the second part of the row in the pixel array. Figure 25 It includes a third reset selection control circuit RSTy 0 2508 having multiple reset selection lines corresponding to the first portion of the column in the pixel array. Figure 25 It also includes a fourth reset selection control circuit RSTy 1 2509 with multiple reset selection lines corresponding to the second part of the column in the pixel array.

[0123] Rows and columns can be controlled by corresponding selection circuitry systems, or this can be changed based on the architecture. For example, the number of row transfer selection circuits can be different from or the same as the number of column selection circuits.

[0124] Figure 25 Various control lines connected to sub-control lines are shown to allow pixels to receive relevant selection signals. Figure 25 The arrangement of the control lines shown is merely an example, and other arrangements can be easily used. For simplicity, the connections to the anti-glare input, selection input, and output terminals for each pixel are not shown.

[0125] Figure 26 An example pixel with multiple transfer selection signals, multiple reset selection signals, and multiple output selection transistors is shown. Figure 26 This includes a photodiode 2601 connected between a potential (e.g., ground) and a transfer transistor 2602. The transfer transistor 2602 can be activated by a transfer signal connected to its gate (in...). Figure 26 Functionally represented as an AND logic gate 2603 (but those skilled in the art will understand that such functionality can be implemented in various ways) control. Transfer transistor 2602 connects photodiode 2601 to floating diffusion node 2604. Reset transistor 2605 can connect floating diffusion node 2604 to a constant potential (in... Figure 26 The reset transistor 2605 is connected to the gate of the reset transistor 2605 (represented as VDD 2607). The reset transistor 2605 can be activated by a reset signal connected to its gate (in the...). Figure 26 Functionally represented as AND gate 2606 (though those skilled in the art will understand that such functionality can be implemented in various ways), the AND gate 2603 can receive two or more transfer select signals, represented by TXx 2611 and TXy 2612, as inputs. The AND gate 2606 can receive two or more reset select signals, represented by RSTx 2613 and RSTy 2614, as inputs. The gate of output transistor 2608 can be connected to floating diffusion node 2604, and the terminals of output transistor 2608 (e.g., source / drain) can be connected to the terminals of first select transistor 2609 and second select transistor 2615. Another terminal of output transistor 2608 can be connected to a constant potential (here, VDD 2607). First selection transistor 2609 connects the terminals of output transistor 2608 to one or more output lines leading to read circuit 0 (not shown), and second selection transistor 2615 connects the terminals of output transistor 2608 to one or more output lines leading to the same or different read circuits 1 (not shown). First selection transistor 2609 can be controlled by selection signal 2610 connected to its gate. Second selection transistor 2615 can be controlled by selection signal 2616 connected to its gate. The combination of two or more selection transistors in each unit allows for interleaved control of rows and / or columns of the ROI, where outputs are sent to different groups of read circuits (e.g., read circuit 0 and read circuit 1). Figure 26 It also includes an optional anti-corona transistor 2617 connected between the photodiode 2601 and a potential shown as VDD. An anti-corona select signal 2618AB is connected to the gate of the anti-corona transistor 2617.

[0126] Figure 27 This illustrates one possible depiction of the scheduling when the ROI is to be reset, exposed, reset, and readout. Those skilled in the art will understand that... Figure 27 This is not a linear flowchart, but a depiction of the scheduling as described herein. The process therefore involves defining ROIs 2701 based on the number of rows, columns, readout mode, and exposure time. Here, the number of ROIs is specified as M. Furthermore, the number of frames budgeted for each ROI is N. Additionally or alternatively, a stop time T may also be included. 停止 At 2702, the sorting process when ROIs are activated. At 2703, the start of the loop is shown for ROIs ranging from 1 to M. At 2704, the start of the loop is shown for frames 1 to N. At 2705, the times for reset B, reset F, and reading out ROs are calculated. At 2706, the frame used to control the operation of a specific ROI is placed in the next available time slot. At 2707, Figure 27 The scheduling determines whether time is available to complete the frames for the ROI (e.g., whether the expected total time has been exceeded). If not enough time is available, the process returns to 2703 to process the next ROI. If enough time is available to process all states of the pixels of the ROI, the process proceeds to 2708. At 2708, the process determines whether the expected number of frames has been collected for the ROI. If enough frames have been collected for the ROI, the process returns to 2703 to process the next ROI. If another frame needs to be added, the process determines whether there is a conflict between the output of the transfer selection signal, the reset selection signal, and the column of the newly added frame. If there is no conflict, the process returns to 2704. If there is a conflict, the frame is delayed by time Tro, as shown in 2710, and the process returns to 2705. Time Tro can be defined as the time for reading information from the photodiode by the readout circuitry system. Because readout operations can be stacked in n rows or columns, time Tro can include readouts from n rows or columns. Calculating the total time to read all rows or columns from all ROIs can be the total time to read rows or columns individually, or 1 / n rows or columns read together. Therefore, in some cases, Tro may equal Trow / n, where Trow is the time to read one row.

[0127] Figure 28 The hardware components of a computing device 2800 are shown, which can be used to determine the order of actions of ROIs and, additionally or alternatively, control the associated circuitry of a CMOS sensor. The computing device 2800 may include one or more processors 2801 that can execute instructions of a computer program to perform any of the functions described herein. Instructions may be stored in read-only memory (ROM) 2802, random access memory (RAM) 2803, removable media 2804 (e.g., USB drive, optical disc (CD), digital versatile disc (DVD)), and / or any other type of computer-readable medium or memory. Instructions may also be stored in an attached (or internal) fixed drive 2805 or other types of storage media. The computing device 2800 may include one or more output devices, such as a display device 2806 (e.g., an external display and / or other external or internal display devices) and a speaker 2811, and may include one or more output device controllers 2807, such as a video processor. One or more user input devices 2808 may include a remote control, keyboard, mouse, touchscreen (which may be integrated with display device 2806), microphone, etc. Computing device 2800 may also include one or more network interfaces, such as a network input / output (I / O) interface 2810 (e.g., a network interface card) for communicating with an external network 2809. Network I / O interface 2810 may be a wired interface (e.g., electrical, RF (via coaxial cable), optical (via fiber optic)), wireless interface, or a combination of both. Network I / O interface 2810 may include a modem configured to communicate via external network 2809.

[0128] The computing device may include interface 2812 to control and / or program transfer selection, reset selection, and other circuitry associated with the CMOS sensor. Processor 2801 may include a single processor or multiple processors, each of which may perform fewer operations. For example, one processor may reside within a housing containing the CMOS sensor. Another processor may reside in an external device that interacts with the CMOS sensor.

[0129] although Figure 28 An example hardware configuration is shown, but one or more of the elements of the computing device 2800 can be implemented as software or a combination of hardware and software. Modifications can be made to add, remove, combine, divide, etc., components of the computing device 2800. Additionally, Figure 28 The components shown can be implemented using basic computing devices and components already configured to perform operations such as those described herein. For example, the memory of computing device 2800 may store computer-executable instructions that, when executed by processor 2801 and / or one or more other processors of computing device 2800, cause computing device 2800 to perform one, some, or all of the operations described herein. Such memory and one or more processors may also be implemented, or alternatively, by one or more integrated circuits (ICs). The IC may be, for example, a microprocessor that accesses programming instructions or other data stored in ROM and / or hardwired into the IC. For example, the IC may include an application-specific integrated circuit (ASIC) having gates and / or other logic dedicated to the computations and other operations described herein. The IC may perform some operations based on the execution of programming instructions read from ROM or RAM, while other operations are hardwired into gates or other logic. Furthermore, the IC may be configured to output image data to a display buffer.

[0130] In examples of spectrometer systems that can utilize CMOS sensors, light of a given wavelength can be focused onto a specific portion of the photosensor. By limiting the Region of Interest (ROI) to the specific location where light will be focused, the operation of a CMOS sensor can be more efficient than scanning the entire array. In a spectrometer, the light measured by the photosensor can cover multiple orders of magnitude. Exposing all ROIs within a given time length limits the detectable light, as some ROIs will be correctly exposed while others may be underexposed or overexposed. For example, in inductively coupled plasma emission spectrometry (ICP-OES), a sample is injected into a plasma, and the resulting excitation of the sample in the plasma produces charged ions. As the various molecules in the sample break down into their individual atoms, then lose electrons and repeatedly recombine in the plasma, they emit radiation at characteristic wavelengths of the elements involved. Spectrometers can receive light from a light source (e.g., an ICP-OES plasma or other light sources, including but not limited to telescopes, microscopes, or other light-generating or light-transmitting systems).

[0131] Various techniques can be applied to CMOS sensor arrays to accommodate orders of magnitude of light. A sample can be injected into a plasma, and its light received on a CMOS sensor. Pixels in one or more Regions of Interest (ROIs) can be analyzed to determine whether a pixel is overexposed, underexposed, or properly exposed. The exposure length of the ROI can be adjusted, and the operation of the CMOS sensor can be tuned to accommodate the modified exposure length and any additional reset (B), reset (F), and / or readout (RO) times. The sample can then be passed through the plasma again, and, if necessary, the exposure time can be adjusted to properly expose pixels in the desired ROI (e.g., extending the exposure time of underexposed pixels and / or shortening the exposure time of overexposed pixels).

[0132] To analyze the light measured by the CMOS sensor, the actual concentration of the sample illuminating the ROI can be determined using the intensity of each ROI or each individual pixel.

[0133] Although examples have been described above, the features and / or steps of those examples can be combined, divided, omitted, rearranged, modified, and / or expanded in any desired manner. Various changes, modifications, and improvements will readily occur to those skilled in the art. While not explicitly stated herein, such changes, modifications, and improvements are intended to be part of this description and are intended to fall within the spirit and scope of this disclosure. Therefore, the foregoing description is by way of example only and not as a limitation.< / cols> < / cols> < / cols> < / cols> < / j> < / j> < / cols> < / cols> < / cols> < / cols> < / j> < / cols> < / cols> < / cols> < / cols> < / cols> < / cols> < / j> < / j> < / cols> < / cols> < / cols> < / cols> < / cols> < / cols> < / cols> < / cols> < / j> < / j>

Claims

1. A circuit comprising: A first transfer transistor connects a photodiode to a floating diffusion node, wherein the first transfer transistor can be individually selected by a combination of the following: (i) First transition selection input, and (ii) Second transfer selection input, A reset transistor is connected between one or more potentials and the floating diffusion node, wherein the reset transistor can be individually selected by a combination of the following: (i) First reset selection input; and (ii) Second reset selection input; A first reset select transistor has its gate terminal connected to (i) the first reset select input or (ii) the second reset select input, and the first reset select transistor is also connected between the gate terminal of the reset transistor (1) and the other of (2)(a) the first reset select input or (b) the second reset select input; The output transistor in the source follower configuration has its gate connected to the floating diffusion node; and The selection transistor is connected to the output of the output transistor.

2. The circuit according to claim 1, further comprising: The first transfer selection transistor has its gate terminal connected to (i) The first transfer selection input, or (ii) The second transfer selection input, The first transfer selection transistor is connected between (1) the gate terminal of the first transfer transistor and (2) the other of the following: (a) The first transfer selection input, or (b) The second transfer selection input.

3. The circuit according to claim 2, further comprising: A second transfer selection transistor, wherein the gate terminal of the second transfer selection transistor is connected to the complement of the following: (i) The first transfer selection input, or (ii) The second transfer selection input, The second transfer selection transistor is also connected between (1) the gate terminal of the first transfer transistor and (2) one or more potentials.

4. The circuit according to claim 1, further comprising: A second reset selection transistor, wherein the gate terminal of the second reset selection transistor is connected to a complement of one of the following: (i) The first reset selection input, or (ii) The second reset selection input, The second reset selection transistor is also connected between the gate terminal of the reset transistor (1) and one or more of the potentials (2).

5. The circuit according to claim 2, further comprising: At least one reset selection control circuit is configured to: (i) Address the first reset selection input separately, and (ii) Address the second reset selection input separately.

6. The circuit according to claim 1, further comprising: At least one anti-corona transistor.

7. The circuit according to claim 1, further comprising: At least one transfer selection control circuit is configured to (i) Address the first transfer selection input separately, and (ii) Address the second transfer selection input separately.

8. A spectrometer system comprising: The circuit according to claim 1.

9. A CMOS sensor, comprising: At least one source follower output; At least one transfer selection control circuit is configured to control (i) a first transfer selection input that can be addressed individually and (ii) a second transfer selection input that can be addressed individually; At least one reset selection control circuit is configured to control (i) at least one individually addressable first reset selection input, and (ii) at least one plurality of individually addressable second reset selection inputs; A pixel array, comprising: Photodiode; Floating diffusion nodes; A transfer transistor that connects the photodiode to the floating diffusion node, wherein the transfer transistor can be individually selected via a combination of a first transfer selection input and a second transfer selection input; and A reset transistor connected between one or more potentials and the floating diffusion node, wherein the reset transistor can be individually selected by a combination of at least one first reset select input and at least one second reset select input; and A reset selection transistor, comprising a first reset selection transistor, the gate terminal of the first reset selection transistor being connected to (i) one of the at least one first reset selection input or (ii) one of the at least one second reset selection input, and the first reset selection transistor being further connected between the gate terminal of (1) the reset transistor and (2) (a) the first reset selection input or (b) the other of the second reset selection input; The output transistor in the source follower configuration connects the floating diffusion node to the output node; and A controller configured to control the at least one transfer selection control circuit to: (i) Expose the first pixel of the pixel array for a first time duration, and (ii) Expose the second pixel of the pixel array for a second time length, the second time length being independent of the first time length.

10. The CMOS sensor according to claim 9, The first time length is different from the second time length.

11. The CMOS sensor according to claim 9, The first time length and the second time length start at different times.

12. The CMOS sensor according to claim 9, further comprising: Multiplexer; as well as Multiple readout circuits, including: The first read circuit is connected via the multiplexer during the first read time to read the value on the output of the first source follower, and The second read circuit is connected via the multiplexer during the second read time to read the value on the output of the second source follower.

13. The CMOS sensor according to claim 12, The second read time is independent of the first read time.

14. The CMOS sensor according to claim 9, The two pixels in the pixel array are in the same row. Wherein at least one of the two pixels is exposed for a first exposure time, and The second pixel of at least two pixels is exposed for a second exposure time, which is independent of the first exposure time.

15. The CMOS sensor according to claim 9, Where the two pixels of the pixel array are in the same column, Wherein at least one of the two pixels is exposed for a first exposure time, and The second pixel of at least two pixels is exposed for a second exposure time, which is independent of the first exposure time.

16. The CMOS sensor according to claim 9, The photodiode is arranged between the transfer transistor and the light source.

17. The CMOS sensor according to claim 16, The light source mentioned above is the light source of the spectrometer.

18. A CMOS sensor, comprising: At least one photodiode; At least one floating diffusion node; At least one output node; At least one addressable first transfer selection input; At least one independently addressable second transfer selection input; At least one independently addressable first reset selection input; At least one independently addressable second reset selection input; At least one transfer transistor comprising a first transfer transistor of a first floating diffusion node connected to the first photodiode of the at least one floating diffusion node, wherein the first transfer transistor is individually selectable by a combination of: (i) one of the at least one first transfer selection input, and (ii) one of the at least one second transfer selection input; It is connected between one or more potentials and the floating diffusion node. At least one reset transistor, comprising a reset transistor connected between one or more potentials and the first floating diffusion node, wherein the reset transistor is individually selectable by a combination of (i) one of the at least one first reset selection input and (ii) one of the at least one second reset selection input; At least one reset select transistor, comprising a first reset select transistor, the gate terminal of the first reset select transistor being connected to (i) one of the at least one first reset select input or (ii) one of the at least one second reset select input, and the first reset select transistor being further connected between the gate terminal of (1) the reset transistor and (2) the other of (a) the first reset select input or (b) the second reset select input; and At least one output transistor in a source follower configuration that connects the at least one first floating diffusion node to the at least one output node.

19. The CMOS sensor of claim 18, further comprising: At least a first transfer select transistor, the gate terminal of which is connected to (i) one of the at least one first transfer select input or (ii) one of the at least one second transfer select input, the first transfer select transistor also being connected between: (1) the gate terminal of the first transfer transistor, and (2) the other of: (a) the first transfer select input or (b) the second transfer select input.

20. The CMOS sensor of claim 19, further comprising: A second transfer selection transistor, the gate terminal of which is connected to a complement of (i) one of the at least one first transfer selection inputs or (ii) one of the at least one second transfer selection inputs, the second transfer selection transistor being additionally connected between (i) the gate terminal of the first transfer transistor and (ii) one or more potentials.

21. The CMOS sensor of claim 18, further comprising: A second reset select transistor, wherein the gate terminal of the second reset select transistor is connected to a complement of (i) the first reset select input or (ii) the second reset select input, and the second reset select transistor is also connected between the gate terminal of (i) the reset transistor and (ii) one or more potentials.

22. The CMOS sensor of claim 18, further comprising: At least one anti-corona transistor.

23. The CMOS sensor according to claim 18, further comprising: At least one transfer selection control circuit is configured to (i) individually address the at least one first transfer selection input, and (ii) individually address the at least one second transfer selection input.

24. A spectrometer system comprising: The CMOS sensor according to claim 18.

25. A CMOS sensor, comprising: At least one output; At least one transfer selection control circuit is configured to control (i) a first transfer selection input that can be addressed individually and (ii) a second transfer selection input that can be addressed individually; At least one reset selection control circuit is configured to control (i) at least one individually addressable first reset selection input, and (ii) at least one individually addressable second reset selection input; A pixel array, comprising: Photodiode; Floating diffusion nodes; A transfer transistor that connects the photodiode to the floating diffusion node; wherein the transfer transistor can be individually selected via a combination of a first transfer selection input and a second transfer selection input; A reset transistor connected between one or more potentials and the floating diffusion node, wherein the reset transistor can be individually selected by a combination of the first reset select input and the second reset select input; and A reset selection transistor, comprising a first reset selection transistor, the gate terminal of the first reset selection transistor being connected to (i) one of the at least one first reset selection input or (ii) one of the at least one second reset selection input, and the first reset selection transistor being further connected between the gate terminal of (1) the reset transistor and (2)(a) one of the at least one first reset selection input or (b) one of the at least one second reset selection input; The output transistor in the source follower configuration connects the floating diffusion node to the at least one output; and A controller configured to control the at least one transfer selection control circuit to: (1) Expose the first pixel of the pixel array for a first time duration, and (2) Expose the second pixel of the pixel array for a second time length, the second time length being independent of the first time length.

26. The CMOS sensor according to claim 25, The first time length is different from the second time length.

27. The CMOS sensor according to claim 25, The first time length and the second time length start at different times.

28. The CMOS sensor of claim 25, further comprising: Multiplexer; as well as Multiple readout circuits, including: The first read circuit is connected via the multiplexer during the first read time to read the value on the output of the first source follower, and The second read circuit is connected via the multiplexer during the second read time to read the value on the output of the second source follower.

29. The CMOS sensor according to claim 28, The second read time is independent of the first read time.

30. The CMOS sensor according to claim 25, The first and second pixels are in the first row. Where at least the first pixel is exposed for the first exposure time, and At least the second pixel is exposed for a second exposure time, which is independent of the first exposure time.

31. The CMOS sensor according to claim 25, The first and second pixels are in the first column. Where at least the first pixel is exposed for the first exposure time, and At least the second pixel is exposed for a second exposure time, which is independent of the first exposure time.

32. The CMOS sensor according to claim 25, The photodiode is arranged between the transfer transistor and the light source.

33. The CMOS sensor according to claim 32, The light source mentioned above is the light source of the spectrometer.

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