Data Processing Method and Related Device for Fourier Transform

Abstract

The present application discloses a data processing method and related apparatus for Fourier transform. The processing method includes: writing a first data stream into a memory; reading out the first data stream from the memory in bit-reversed order; writing a second data stream into the memory in a first address order, where the second data stream is the subsequent data stream of the first data stream, and the first address order is the same as the address order used when the first data stream is read out from the memory; reading out the second data stream from the memory in a second address order, where the second address order is the same as the address order used when the first data stream is written into the memory. This method can implement the bit-reversed order processing in the Fourier transform for two consecutive data streams through a single memory, thereby significantly reducing the area overhead brought by the memory.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and particularly to a data processing method for Fourier transform, a data processing method for Fourier transform, and related devices. Background Art

[0002] As an important algorithm in digital signal processing, Fourier transform can be widely applied in the field of communication technologies. For example, Fourier transform can be used for signal modulation and demodulation in a Long Term Evolution (LTE) of a mobile communication system or a 5G New Radio (5GNR).

[0003] In order to meet the requirements of the communication field for data throughput, it is necessary to perform Fourier transform on a continuous data stream (or a pipelined data stream). When performing bit-reversal processing on a continuous data stream in the existing method, the memory area overhead required is very large. Summary of the Invention

[0004] This application provides a data processing method for Fourier transform, a data processing method for Fourier transform, and related devices.

[0005] In a first aspect, a data processing method for Fourier transform is provided, including: writing a first data stream into a memory; reading out the first data stream from the memory in bit-reversed order; writing a second data stream into the memory in a first address order, where the second data stream is the subsequent data stream of the first data stream, and the first address order is the same as the address order when the first data stream is read out from the memory; reading out the second data stream from the memory in a second address order, where the second address order is the same as the address order when the first data stream is written into the memory.

[0006] In a second aspect, a data processing device for Fourier transform is provided, including: a memory for storing data; a processor for performing the following operations: writing a first data stream into the memory; reading out the first data stream from the memory in bit-reversed order; writing a second data stream into the memory in a first address order, where the second data stream is the subsequent data stream of the first data stream, and the first address order is the same as the address order when the first data stream is read out from the memory; reading out the second data stream from the memory in a second address order, where the second address order is the same as the address order when the first data stream is written into the memory.

[0007] In a third aspect, a baseband system is provided, including: a modulator for modulating a bit stream; and a data processing device for Fourier transform as described in the second aspect, for performing Fourier transform on the modulated data.

[0008] In a fourth aspect, a wireless communication device is provided, including: the baseband system as described in the third aspect, for outputting a baseband signal; and a radio frequency system for frequency conversion of the baseband signal output by the baseband system to obtain a radio frequency signal.

[0009] In a fifth aspect, a chip is provided, the chip includes programmable logic circuits and / or program instructions, and when the chip runs, it implements the method as described in the first aspect

[0010] The data processing method for Fourier transform provided by the embodiments of the present application, after writing the first data stream into the memory, reads the first data stream out of the memory in bit-reversed order, and writes the second data stream into the memory in the same address order as the address order when the first data stream is read out of the memory and reads the second data stream out in the same address order as the address order when the first data stream is written into the memory. In this way, the bit-reversed order processing in the Fourier transform can be performed on the continuous first data stream and second data stream based on a single memory, thereby greatly reducing the area overhead brought by the memory. Description of the Drawings

[0011] Figure 1 It is a schematic structural diagram of the baseband system provided by the embodiments of the present application.

[0012] Figure 2 It is a schematic structural diagram of the Fourier transform module provided by the embodiments of the present application.

[0013] Figure 3 It is a schematic flowchart of a data processing method for Fourier transform provided by the embodiments of the present application.

[0014] Figure 4 It is a schematic diagram of a read / write method provided by the embodiments of the present application.

[0015] Figure 5 It is a schematic diagram of another read / write method provided by the embodiments of the present application.

[0016] Figure 6 It is a schematic diagram of a read / write method for a continuous data stream provided by the embodiments of the present application.

[0017] Figure 7 It is a schematic diagram of another read / write method for a continuous data stream provided by the embodiments of the present application.

[0018] Figure 8It is a schematic structural diagram of a data processing device for Fourier transform provided by an embodiment of the present application. Detailed implementation manners

[0019] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0020] For the convenience of understanding, relevant terms involved in the embodiments of the present application will be explained first.

[0021] The Fourier transform is a very important algorithm in the field of digital signal processing, which can represent any continuously measured time series or signal as an infinite superposition of sine wave signals of different frequencies. By using the Fourier transform, a time-domain signal that is difficult to process can be converted into a frequency-domain signal that is easy to analyze, and by using the inverse Fourier transform, the frequency-domain signal can be converted back into a time-domain signal. It should be noted that the Fourier transform mentioned in the embodiments of the present application may refer to either the Fourier transform or the inverse Fourier transform.

[0022] There are various types of Fourier transforms, such as the Discrete Fourier Transform (DFT), the Inverse Discrete Fourier Transform (IDFT), the Fast Fourier Transform (FFT), and the Inverse Fast Fourier Transform (IFFT), etc. The Fourier transform method mentioned in the embodiments of the present application can be applicable to any of the above types of Fourier transforms.

[0023] Bit reversal, which can also be called reordering, is a necessary step in the Fourier transform. It can output the data stream (or a set of data) input to the Fourier transform module in the order of binary bit reversal (i.e., bit reversal). Bit reversal is usually implemented through a memory. For example, each data in the data stream is written into the memory in the corresponding address order according to the sequential order, and then each data is read out from the memory in the address order corresponding to the bit reversal, so as to achieve bit reversal by reading and writing different address orders. It can be understood that bit reversal can be located either at the beginning or at the end of the Fourier transform module. The embodiments of the present application do not limit this and can be set according to requirements.

[0024] In this application, the data for Fourier transform may include the data output by the processor or core that performs the Fourier transform, and may also include the data to be input to the processor or core that performs the Fourier transform. In terms of scenarios, the Fourier transform described herein is applicable to two different scenarios: bit-reversal-first and bit-reversal-last. Bit-reversal-first means that the bit-reversal module is before the processor or core that performs the Fourier transform; bit-reversal-last means that the bit-reversal module is after the processor or core that performs the Fourier transform. Among them, the bit-reversal module can be implemented as the data processing device, or data access module, or memory, etc. described in this application.

[0025] For ease of understanding, the bit-reversal is exemplarily described below with reference to Table 1 and Table 2.

[0026] Suppose the data stream input to the Fourier transform module has a number of points N = 2 n , and its N data are sequentially input into the memory that implements bit-reversal, and the sequential numbers are 0, 1, 2, …, N - 2, N - 1 respectively. This sequential number can be represented by the cumulative count from the low bit to the high bit of n binary counters (m n-1 , m n-2 , …, m1, m0) (or the sequence formed by the respective count values of the n binary counters from low to high). Taking 16 = 2 4 as an example, the sequential numbers 0 - 15 can be represented by 4 binary counters as shown in Table 1.

[0027] Table 1

[0028]

[0029] The so-called bit-reversal is to output the cumulative counter after bit reversal in sequence, that is, the previous counter carries over to the next counter. It can also be understood that when the data stream is written in the sequence formed by the respective count values of multiple counters from low to high, and read out in the sequence formed by the respective count values of these multiple counters from high to low, it is bit-reversal. For example, the output sequence of the cumulative count after bit reversal of the counters in Table 1 can be represented as shown in Table 2.

[0030] Table 2

[0031]

[0032] As can be seen from Table 1 and Table 2, after the data stream is written to each storage address in the memory in the order of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, the data stream will be read from the storage addresses in the memory corresponding to the sequential numbers in the order of 0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15.

[0033] It can be understood that if the input sequential numbers of the data stream are represented by the counting method of each count value of multiple counters from high to low (i.e., Table 2 above), then when the data stream is read from the memory in the order represented by the counting method of each count value of the multiple counters from low to high (i.e., Table 1 above), the bit-reversal order of the above data stream can still be achieved. Thus, it can be seen that using a bit-reversed accumulative counter can easily achieve the output of the bit-reversal order.

[0034] With the development of digital signal processing technology and large-scale integrated circuits, the Fourier transform is widely used in the communication field. For example, it is used in the baseband systems of the uplink and downlink of LTE or 5GNR. Since the baseband systems of LTE or 5GNR both adopt the modulation method of Orthogonal Frequency Division Multiplexing (OFDM), it enables wireless communication devices (such as network devices and / or terminal devices) to modulate using IDFT or IFFT respectively and demodulate using DFT or FFT.

[0035] For ease of understanding, the following will be combined with Figure 1 exemplarily introduce a typical baseband system (such as an OFDM system).

[0036] As Figure 1 shown, the baseband system 10 may include a transmitter 11 and a receiver 12.

[0037] The transmitter 11 can be used to generate a transmitted signal from an input signal and transmit the transmitted signal to the receiver 12. The receiver 12 can be used to receive the above transmitted signal after channel processing and restore the original input signal therefrom.

[0038] The embodiments of the present application do not specifically limit the data processing methods in the transmitter 11 and the receiver 12, as long as the transmitter 11 and the receiver 12 can perform Fourier transform on the input signal.

[0039] As an example, as Figure 1 shown, the transmitter 11 can perform a Fourier transform on the input signal ( Figure 1The following processing is performed on the input signal (expressed as a bit stream in the Chinese text): constellation point modulation, serial-to-parallel conversion, subcarrier mapping, N-point IFFT, parallel-to-serial conversion, adding a cyclic prefix, and upconversion and radio frequency processing. Through these processes, the input signal can be generated into a transmitted signal to be transmitted through the transmitting antenna 111.

[0040] After being transmitted through the channel, the above-mentioned transmitted signal can become a received signal and is received by the receiving antenna 121 of the receiver 12. The receiver 12 can perform the following processing on the received signal: radio frequency and downconversion processing, removing the cyclic prefix, serial-to-parallel conversion, N-point FFT, subcarrier demapping, parallel-to-serial conversion, and constellation point demodulation. Through these processes, the original input signal can be restored from the received signal. The above-mentioned N-point FFT or N-point IFFT can refer to performing FFT or IFFT on N points of data (or data stream, a set of data, etc.) in the signal, and N can be called the number of points of the data stream supported by the Fourier transform.

[0041] With the significant increase in the data throughput of communication systems, the requirements for the number of points supported by the Fourier transform are getting higher and higher. For example, the FFT points supported by the NR system can include 32, 64, 128, 256, 512, 1024, 2048, and even up to 4096. In order to enable the communication system to achieve higher uplink and downlink throughput rates, a higher-speed Fourier transform algorithm needs to be provided.

[0042] In view of this, it is proposed in the related art that a high-speed Fourier transform algorithm can be provided based on a pipeline manner. The Fourier transform scheme based on a pipeline can refer to performing Fourier transform on continuous data streams in the form of a pipeline in sequence, thereby reducing the delay required for performing the Fourier transform.

[0043] As described above, the Fourier transform can include a module that performs a bit-reversal order step on the data stream, and this bit-reversal module can be located at the beginning or the end of the Fourier transform module. The following combines Figure 2 Exemplarily, taking the case where the bit-reversal module is located at the end of the Fourier transform module as an example, the Fourier transform based on a pipeline is described.

[0044] As Figure 2As shown, when multiple data streams enter the Fourier transform module, the Fourier transform module can process the successively input data streams one by one through a Fourier transform kernel (or an FFT transform kernel, a processor or kernel for performing Fourier transform) and a bit-reversal module (or bit-reversal transform). Specifically, the Fourier transform kernel can first perform relevant calculations on the data in the first data stream, such as butterfly calculations, and then output the calculation results of this data stream. Immediately afterwards, the Fourier transform kernel performs relevant calculations on the next data stream (i.e., the second data stream) after the first data stream and outputs its calculation results. Since the calculation results of the Fourier transform kernel are still output in the form of data streams, the first data stream and the second data stream can still be referred to as the first data stream and the second data stream after being output from the Fourier transform kernel.

[0045] When the Fourier transform kernel outputs the first data stream, it can be completely written into the memory in the bit-reversal module in the forward order, and then the first data stream can be completely read out in the bit-reversed order. After that, the bit-reversal module performs corresponding operations on the second data. In some implementation manners, as Figure 2 shown, the bit-reversal module can combine a read-write address controller to perform different read-write address sequences in the memory to achieve bit-reversal.

[0046] Generally speaking, in the pipeline-based Fourier transform, when the first data stream output by the Fourier transform kernel has been completely written into the memory of the bit-reversal module but not yet read out, the Fourier transform kernel has already output the calculated second data stream. The second data stream can also be understood as the subsequent data stream of the first data stream. At this time, in order to store the second data stream and perform bit-reversal on the second data stream, a feasible solution is to adopt a solution of adding a memory of the same size, that is, two memories of the same size are required to support bit-reversal in a pipeline manner. It can be understood that in the pipeline-based Fourier transform, when its bit-reversal module is located at the beginning of the Fourier transform module, there is also a situation where the second data stream has to be input into the memory when the first data stream has not been read out from the memory.

[0047] However, the area overhead brought by the two-memory solution is very large. Especially in the NR system, since the maximum number of points of Fourier transform it needs to support is 4096, the area overhead brought by two memories for storing the output data of 4096-point Fourier transform is very unacceptable.

[0048] To solve the above problems, as Figure 3 shown, the embodiment of the present application proposes a data processing method for Fourier transform. This method can implement bit-reversal processing in the Fourier transform of two consecutive data streams through a single memory, which can greatly reduce the area overhead brought by the memory.

[0049] The following will be combined with Figure 3 to describe in detail the data processing method for Fourier transform in the embodiments of the present application.

[0050] In step S310, write the first data stream into the memory.

[0051] In step S320, read out the first data stream from the memory in bit-reversed order.

[0052] In step S330, write the second data stream into the memory in the first address order.

[0053] In step S340, read out the second data stream from the memory in the second address order.

[0054] In the embodiments of the present application, the address order is the arrangement order of the storage addresses when each data in the data stream is written into the corresponding storage address or read out from the corresponding storage address. In some implementation manners, the address order can be represented by the cumulative counting of the binary counter described above. The first address order in the embodiments of the present application is the same as the address order used when the first data stream is read out from the memory, and the second address order is the same as the address order used when the first data stream is written into the memory.

[0055] In the embodiments of the present application, the first data stream and the second data stream can be data for Fourier transform. The first data stream can be any one of multiple data streams that need to perform Fourier transform, and the second data stream can be a data stream adjacent to and after the first data stream. The number of points of the first data stream or the second data stream can be 2 n , where n can be any integer greater than 0. For example, if the number of points of the first data stream or the second data stream is 32, then n is 5. Or if the number of points of the first data stream or the second data stream is 4096, then n is 12. As described above, the address order can be represented by the cumulative counting of the binary counter, and the number of binary counters is related to the number of points of the data stream. Specifically, when the number of points of the data stream is N = 2 n , the number of its binary counters is n.

[0056] The embodiments of the present application do not make specific limitations on the number of points of the first data stream and the second data stream. As a implementation manner, the number of points of the first data stream and the second data stream can be the same. Since the address order can be represented by the counter and the address order is in one-to-one correspondence with the storage address, when the number of points of the first data stream and the second data stream is the same, the mapping relationship mechanism between the address order represented by the same set of binary counters and the storage address can be used to represent the read / write address order of the first data stream and the read / write address order of the second data stream, which holds for most pipelined Fourier transforms. For specific descriptions, see the following text.

[0057] As another implementation, the number of points of the first data stream and the second data stream can be different. The number of points of the first data stream can be greater than or less than the number of points of the second data stream. To support the bit-reversal order of data streams of different lengths, the size of the memory implementing the bit-reversal order should be configured to the maximum data stream length N supported. max For such two data streams, two different mapping mechanisms between the address order represented by two sets of binary counters and the storage address are required to represent the read / write address order of the first data stream and the read / write address order of the second data stream. The specific description can be found later.

[0058] It can be understood that after the first data stream is written into the memory in the forward order, the addresses of each data in the data stream in the memory are unique, that is, there is a one-to-one mapping relationship between the address order of the data in the first data stream and the storage address. Reading the first data stream in the bit-reversal order requires reading each data arranged in the bit-reversal order of the first data stream from its corresponding storage address in sequence. That is to say, if the address order used when the first data stream is written into the memory is known, the address order used when the first data stream is read out of the memory in the bit-reversal order can be known.

[0059] In the embodiment of the present application, since the address orders when the first data stream is written and read are both known, it is only necessary to keep the address order when the second data stream is written the same as the address order when the first data stream is read, and keep the address order when the second data stream is read the same as the address order when the first data stream is written, so as to achieve the bit-reversal order of the second data stream. This avoids the process of using a second memory to implement the bit-reversal order for the second data stream, thereby reducing the area overhead brought by the memory.

[0060] In addition, since the address order when the second data stream is written is the same as the address order when the first data stream is read, it is possible to write the second data stream at the storage address where the first data stream is read when reading the first data stream, without having to wait until the first data stream is completely read before writing the second data stream, thus ensuring the real-time performance of the Fourier transform. For the specific method of writing the second data stream at the storage address where the first data stream is read when the first data stream is read in the bit-reversal order, see the description later. For the convenience of understanding later, the method of how the address order is represented by a counter and how the address order is mapped to the storage address one by one will be described in detail first.

[0061] To improve the processing speed of the pipelined Fourier transform, multiple pipelines are usually used for parallel input and parallel output. Figure 2For example, the data of the FFT transform kernel needs to be written into the memory in parallel and then read out in bit-reversed order from the memory in parallel. Here, P in the figure is the parallelism of the pipeline. When performing Fourier transform on the data stream in the form of parallelism P, the memory is usually required to support P parallel read and write operations. That is, the memory needs to complete the reading of P parallel data of the first data stream and then complete the writing of P parallel data of the second data stream within an average of one clock cycle.

[0062] As an implementation method, the memory may include P memory banks, and each memory bank has the same depth. At this time, any memory address can be represented as the bank number b and the offset a within the bank. For a memory with P memory banks, it needs to perform read and write operations on each bank in each clock cycle. That is, within one clock cycle, the P memory addresses for reading and writing need to be located in different banks. In addition, considering that the address order has a one-to-one mapping relationship with the memory address, the embodiments of the present application also design a set of feasible address schemes, as specifically described below.

[0063] Taking the size of the Fourier transform data as N = 2 n , and the parallelism P = 2 p as an example. The depth of each bank can be expressed as As described above, the n-bit binary of each input / output serial number of the data stream (i.e., the address order described above) can be expressed as:

[0064] l = (m n-1 , m n-2 , …, m p , m p-1 …, m1, m0)2

[0065] The mapping scheme between the address order and the memory address is:

[0066] b = ((m n-p , …, m n-2 , m n-1 )2 + (m p-1 …, m1, m0)2) % P (1)

[0067]

[0068] Taking the number of points of the data stream as 32 = 2 5 , and the parallelism as 4 = 2 2, taking the case where the maximum number of points of the data stream supported by the memory is 32 as an example. By adopting a set of counters including 5 counters for carry counting from low to high, according to the above formulas (1) and (2), it is possible to write a 32-point data stream output by the FFT transform kernel described above into the memory in 8 cycles according to its counting order. These 8 cycles are: 0, 1, 2, 3; 4, 5, 6, 7; 8, 9, 10, 11; 12, 13, 14, 15; 16, 17, 18, 19; 20, 21, 22, 23; 24, 25, 26, 27; 28, 29, 30, 31. At this time, the storage state of the memory is shown in Table 3:

[0069] Table 3

[0070]

[0071] For the above data stream, by counting the above counters from high to low for carry counting, the data stream can also be read out in 8 cycles in the order of bit-reversal as 0, 16, 8, 24; 4, 20, 12, 28; 2, 18, 10, 26; 6, 22, 14, 30; 1, 17, 9, 25; 5, 21, 13, 29; 3, 19, 11, 27; 7, 23, 15, 31.

[0072] Or, taking the number of points of the data stream as 16 = 2 4 , the parallel number as 4 = 2 2 and the maximum number of points of the data stream supported as 32 as an example. By adopting a set of counters including 4 counters for carry counting from low to high, according to the above formulas (1) and (2), it is possible to write a 16-point data stream output by the FFT transform kernel described above into the memory in 4 cycles according to its counting order. These 4 cycles are: 0, 1, 2, 3; 4, 5, 6, 7; 8, 9, 10, 11; 12, 13, 14, 15. At this time, the storage state of the memory is shown in Table 4.

[0073] Table 4

[0074]

[0075]

[0076] For the above data stream, by counting the above counters from high to low for carry counting, the data stream can also be read out in 4 cycles in the order of bit-reversal as 0, 8, 4, 12; 2, 10, 6, 14; 1, 9, 5, 13; 3, 11, 7, 15.

[0077] As can be seen from Table 3 and Table 4, the 4 data written in each clock cycle of this data stream are in different columns in Table 3 and Table 4, and the 4 data read in each clock cycle of this data stream are also in 4 different columns (the data represented by the same underlined format are read in the same clock cycle). Thus, it can be seen that through the address mapping method described above, it is possible to achieve that the 4 data written or read in each clock cycle are in different banks.

[0078] Based on the expression method of the address order and the mapping relationship between the address order and the storage address described above, in some embodiments, such as Figure 4 as shown, when the first data stream is read out from the memory in reverse bit order, the second data stream can be written into the memory according to the first address order in the following way: in one clock cycle, after reading out P data from the storage addresses in P storage units with the first data stream in reverse bit order, write the second data stream in accordance with the first address order into the storage addresses of P data in P storage units. That is to say, in Figure 4 the embodiment shown, the memory has P read address lines and P write address lines, and this memory can achieve parallel reading first and then parallel writing in one clock cycle, that is Figure 4 the memory in

[0079] Below, taking the number of points of the first data stream and the second data stream both being 32 = 2 5 , and the parallel number being 4 = 2 2 as an example. If the first data stream is written into the memory according to the address order described in Table 3 (the counting order of the counter is represented from low to high), and then read out according to the reverse bit order described above (the counting order of the counter is represented from high to low). Since the output of the memory is also pipelined, when part of the data of the previous data stream is read out from the storage address of the memory, the remaining storage address vacancies can be used to write part of the data of the next data stream in sequence.

[0080] If we write the data of the latter data stream (the second data stream) into the above-mentioned storage address vacancies according to the read address order of the previous data stream (the first data stream) described in the embodiments of the present application (that is, the counting order of the counter is represented from high to low), and finally read the data of the latter data stream from the memory according to the write address order of the previous data stream (that is, the counting order of the counter is represented from low to high), the functions of the reverse bit order of the first data stream and the second data stream can be achieved simultaneously. If the data of the first data stream in Table 3 are completely read out and the data of the second data stream are completely written into the memory, the storage state of the memory should be equivalent to that shown in Table 5.

[0081] Table 5

[0082]

[0083] It should be understood that Table 5 is only for facilitating the understanding of the bit-reversed order implementation of the second data stream, rather than the counter representation corresponding to the true address order of the second data stream. Specifically, when the second data stream is written to the memory, its address order should be the same as the read address order of the first data stream, that is, the natural order of the second data stream (equivalent to 0, 1, 2, 3; 4, 5, 6, 7; 8, 9, 10, 11; 12, 13, 14, 15; 16, 17, 18, 19; 20, 21, 22, 23; 24, 25, 26, 27; 28, 29, 30, 31) of the write address order can be represented as 0, 16, 8, 24; 4, 20, 12, 28; 2, 18, 10, 26; 6, 22, 14, 30; 1, 17, 9, 25; 5, 21, 13, 29; 3, 19, 11, 27; 7, 23, 15, 31 to be written to the storage addresses where the first data stream is read. Taking the second data in the data stream as an example, the natural order of the second data should originally be 1 (00001), but its address order will be represented as 16 (10000), and thus it will be written to the storage address mapped by the address mapping relationship shown in Table 3, which is equivalent to directly writing the second data at this position. By analogy, the same applies to other data, and no further elaboration will be made here.

[0084] As another implementation method, the memory may further include 2P memory banks (banks) to achieve reading P data of the first data stream in bit-reversed order and writing P data of the second data stream within an average of one clock cycle. Specifically, as Figure 5 shown, this process can be that in the first clock cycle, 2P data are read from the storage addresses in 2P memory banks for the first data stream in bit-reversed order, and in the next clock cycle after the first clock cycle, the second data stream is written with 2P data to the storage addresses in 2P memory banks according to the first address order. By reading or writing 2P data in parallel in each clock cycle and performing one read operation and one write operation every two clock cycles, it is thus possible to achieve P parallel read and write operations in each clock cycle.

[0085] Since in this embodiment, the number of banks in the memory is 2P, that is, the number of storage units is expanded by 2 times, the storage depth of each bank can be expressed as Correspondingly, the mapping relationship between its address order and the storage address can be expressed as:

[0086]

[0087] b = ((m n-p ,…,mn-2 , m n-1 )2 + (m p-1 …, m1, m0)2)%P + P * (m p == 1) (4)

[0088] Perform address mapping on the data stream described in Table 3 above according to the above address mapping relationship. Its effect is equivalent to moving the odd rows of the memory to the right half, and the specific memory storage state can be as shown in Table 6.

[0089] Table 6

[0090]

[0091] And if the data stream in Table 6 is the first data stream, after all the data of the first data stream is read out, the data of the second data stream is completely written into the memory, and its memory storage state should be equivalent to that shown in Table 7.

[0092] Table 7

[0093]

[0094] It should be understood that Table 7 is also only for facilitating the understanding of the implementation of the bit-reversed order of the second data stream, rather than the counter representation corresponding to the real address order of the second data stream. The description of its specific address order is similar to that of Table 5, and will not be elaborated here one by one.

[0095] By expanding the storage units of the memory to 2P and implementing its read and write processes according to the above embodiments, there is no need for the memory to support read and write operations simultaneously in one clock cycle, that is, the use of a dual-port memory is avoided. Therefore, the area of this memory is less than that of two memories and also less than the storage area of a dual-port memory, which can effectively ensure the overhead of the memory area.

[0096] As mentioned above, the address order can be represented by the counting order of the counter, and the counting order of the counter can be either counting from high to low or from low to high. Therefore, the bit-reversed order of the two data streams mentioned in the embodiments of the present application can include the following two modes.

[0097] Mode 1: When the address order of the first data stream is written in the counting order of the counter from low to high and read in the counting order of the counter from high to low, then the address order of the second data stream is written in the counting order of the counter from high to low and read in the counting order of the counter from low to high.

[0098] Mode 2: When the address order of the first data stream is written in the counting order of the counter from high to low and read in the counting order of the counter from low to high, the address order of the second data stream is written in the counting order of the counter from low to high and read in the counting order of the counter from high to low.

[0099] Combined with the content described above, the number of points of the first data stream and the second data stream can be the same or different. When the number of points of the first data stream and the second data stream is the same, the mapping relationship between the counting order of the same counter and the storage address can be used to respectively implement the reading and writing described above. When the number of points of the first data stream and the second data stream is different, the mapping relationship between the counting order of the first group of counters and the storage address and the mapping relationship between the counting order of the second group of counters and the storage address need to be used respectively to implement the reading and writing described above.

[0100] Specifically, the address order used when the first data stream is written into the memory is the first counting order of the first group of counters, the address order used when the first data is read from the memory is the second counting order of the first group of counters, the first address order (i.e., the address order used when the second data stream is written into the memory) is the second counting order of the second group of counters, and the second address order (i.e., the address order used when the second data stream is read from the memory) is the first counting order of the second group of counters.

[0101] Among them, the first counting order of the first group of counters or the second group of counters corresponds to a sequence formed by the respective count values of multiple binary counters from low to high, the second counting order of the first group of counters or the second group of counters corresponds to a sequence formed by the respective count values of multiple binary counters from high to low, or the first counting order of the first group of counters or the second group of counters corresponds to a sequence formed by the respective count values of multiple binary counters from high to low, and the second counting order of the first group of counters or the second group of counters corresponds to a sequence formed by the respective count values of multiple binary counters from low to high. That is to say, the second counting order of the first group of counters is the reverse order of the first counting order of the first group of counters, and the second counting order of the second group of counters is the reverse order of the first counting order of the second group of counters, and the counting methods of the first counting order of the first group of counters and the first counting order of the second group of counters are the same, and the counting methods of the second counting order of the second group of counters and the second counting order of the second group of counters are the same.

[0102] When implementing the reverse bit order for the first data stream and the second data stream according to the above counter, the following steps need to be included: After completely reading out the first data stream from the memory in the second counting order of the first group of counters and completely writing the second data stream into the memory in the second counting order of the second group of counters, read the second data stream from the memory in the first counting order of the second group of counters.

[0103] Especially when the number of points of the first data stream is less than that of the second data stream, the above steps are particularly important. Exemplarily, as Figure 6 shown, a continuous plurality of data streams can be respectively represented as FFT0, FFT1, FFT2, and FFT3. The number of points of FFT0 and FFT1 is the same, and the number of points of FFT2 and FFT3 is the same. When the first data stream is FFT1 and the second data stream is FFT2, it can be known through Figure 6 that since the number of points of the first data stream FFT1 is less than that of the second data stream FFT2, when the first data stream FFT1 is completely read out, the second data stream FFT2 has not been completely written yet. At this time, it is necessary to wait for the second data stream FFT2 to be completely written before reading the second data stream FFT2. Otherwise, an address conflict will occur and the reverse bit order processing of the second data stream cannot be achieved.

[0104] Taking the number of points of the first data stream as 16, the number of points of the second data stream as 32, and the storage units of the memory as 2P as an example. In the above cases of Mode 1 and Mode 2: It is equivalent to the first data stream being output in parallel in reverse order at the 0th and 2nd clock cycles by 8, and the order is the data shown by the underline and the data shown by the double underline. At the same time, it is equivalent to writing the data of the second data stream in parallel in order at the 1st, 3rd, 5th, and 7th clock cycles, and the order is equivalent to the data shown by the underline, the data shown by the double underline, the data shown by the dotted line, and the data shown by the dash-dotted line. The difference is that in Mode 1, the first data stream is written into the memory in a counting manner from low to high, and the storage state is shown in Table 8; the second data stream is written into the memory in a counting manner from high to low, and its storage state is equivalent to that shown in Table 9. In Mode 2, the first data stream is written into the memory in a counting manner from high to low, and the storage state is equivalent to that shown in Table 10; the second data stream is written into the memory in a counting manner from low to high, and its storage state is shown in Table 11.

[0105] Table 8

[0106]

[0107] Table 9

[0108]

[0109] Table 10

[0110]

[0111] Table 11

[0112]

[0113] As described above, the number of points in the first data stream can also be greater than the number of points in the second data stream. Therefore, in some implementations, in order to implement the reverse bit order of the first data stream and the second data stream, it is necessary to wait for several clock cycles after the first data stream is written before writing the second data stream, otherwise it will cause an address conflict.

[0114] Taking the memory including 2P memory banks described above as an example, it is necessary to read 2P data from the storage addresses in the 2P memory banks in reverse bit order for the first data stream within the first clock cycle, and write 2P data of the second data stream in the first address order to the storage addresses in the 2P memory banks in the next clock cycle after the first clock cycle. If the number of points in the first data stream and the second data stream is the same or the number of points in the first data stream is less than the number of points in the second data stream, the first clock cycle is the clock cycle when the first data stream starts to be read. For the case where the number of points in the first data stream is greater than the number of points in the second data stream, the first clock cycle is not the first clock cycle when the first data stream starts to be read, but at least one clock cycle needs to be included before the first clock cycle for reading the data in the first data stream. Specifically, after the first data stream is read for multiple clock cycles, as long as the available storage addresses are sufficient for the second data stream to be written without conflicting with the addresses when the second data stream is written.

[0115] As an implementation, as Figure 7 shown, a plurality of consecutive data streams can be respectively represented as FFT0, FFT1, FFT2, and FFT3. The number of points in FFT0 and FFT1 is the same, and the number of points in FFT2 and FFT3 is the same. It should be noted that Figure 7 for illustration only, when the second data stream starts to be written, the read cycle of the first data stream and the write cycle of the second data stream are shown as synchronous, but in reality, the first data stream is read for one clock cycle first and then the second data stream is written for one clock cycle. When the first data stream is FFT1 and the second data stream is FFT2, it can be known through Figure 7 that since the number of points in the first data stream FFT1 is greater than the number of points in the second data stream FFT2, it is necessary to control the pipeline to make the second data stream wait for multiple clock cycles before writing the second data stream FFT2 (that is, at the first clock cycle and the next clock cycle after the first clock cycle). These multiple cycles can be represented as

[0116] Take the case where the number of points of the first data stream is 32, the number of points of the second data stream is 16, and the storage units of the memory are all 2P. In the above cases of Mode 1 and Mode 2: It is equivalent to the first data stream being output in parallel and in reverse order in the 0th, 2nd, 4th, and 6th clock cycles, and the order is the data shown by the underscore, the data shown by the double underscore, the data shown by the dotted line, and the data shown by the wavy line. At the same time, it is equivalent to writing the data of the second data stream in parallel and in order in the 5th and 7th clock cycles, and the order is equivalent to the data shown by the dotted line and the data shown by the wavy line. The difference is that in Mode 1, the first data stream is written into the memory using a counting method from the low bit to the high bit, and the storage state is shown in Table 12; the second data stream is written into the memory using a counting method from the high bit to the low bit, and its storage state is equivalent to that shown in Table 13. In Mode 2, the first data stream is written into the memory using a counting method from the high bit to the low bit, and the storage state is equivalent to that shown in Table 14; the second data stream is written into the memory using a counting method from the low bit to the high bit, and its storage state is shown in Table 15.

[0117] Table 12

[0118]

[0119] Table 13

[0120]

[0121] Table 14

[0122]

[0123] Table 15

[0124]

[0125]

[0126] The method mentioned in the embodiments of the present application can implement a parallel address scheme with reverse bit order: It writes the data of the latter data stream into the memory according to the reading order of the previous data stream, and reads the data of the latter data stream from the memory according to the writing order of the previous data stream. Thus, only one memory can be used to implement parallel reverse bit order in a pipelined manner, which can greatly reduce the required memory area. Taking the data stream with a maximum of 4096 points, the real and imaginary parts of the output data are quantized with 16 bits each, and 4 parallel outputs as an example. At a clock frequency of 1 GHz, when using the method of two memories, the memory area is about 16,800 square micrometers, while the memory area of the method in the embodiments of the present application is 10,400 square micrometers, and the area overhead is reduced by 38%.

[0127] As mentioned above in combination with Figures 1 - 7, which details the method embodiments of this application. Next, the device embodiments of this application will be described. It should be understood that the description of the device embodiments corresponds to that of the method embodiments. Therefore, for parts not described in detail, reference can be made to the previous method embodiments.

[0128] Refer to Figure 8 , embodiments of this application provide a data processing device 800 for Fourier transform.

[0129] As Figure 8 shown, the processing device 800 includes a memory 810 and a processor 820.

[0130] The memory 810 is used to store data.

[0131] The processor 820 is used to perform the following operations: write a first data stream into the memory; read out the first data stream from the memory in bit-reversed order; write a second data stream into the memory in a first address order, where the second data stream is the subsequent data stream of the first data stream, and the first address order is the same as the address order when the first data stream is read out from the memory; read out the second data stream from the memory in a second address order, where the second address order is the same as the address order when the first data stream is written into the memory.

[0132] Optionally, the first data stream and / or the second data stream perform Fourier transform in a form with a parallel number of P. The memory includes P storage units. Specifically, the processor 820 is used to: within one clock cycle, after reading out P data from the storage addresses in the P storage units in bit-reversed order for the first data stream, write the second data stream into the storage addresses of the P storage units in the first address order with P data.

[0133] Optionally, the first data stream and / or the second data stream perform Fourier transform in a form with a parallel number of P. The memory includes 2P storage units. Specifically, the processor 820 is used to: within the first clock cycle, read out 2P data from the storage addresses in the 2P storage units in bit-reversed order for the first data stream; within the next clock cycle after the first clock cycle, write 2P data into the storage addresses of the 2P storage units in the first address order for the second data stream.

[0134] Optionally, when the first data stream is written into the memory, the address order used is the first counting order of the first group of counters, and when the first data is read from the memory, the address order used is the second counting order of the first group of counters. The first address order is the second counting order of the second group of counters, and the second address order is the first counting order of the second group of counters. Specifically, the processor 820 is configured to: after completely reading the first data stream from the memory in accordance with the second counting order of the first group of counters and completely writing the second data stream into the memory in accordance with the second counting order of the second group of counters, read the second data stream from the memory in accordance with the first counting order of the second group of counters.

[0135] Optionally, when the number of points of the first data stream is greater than the number of points of the second data stream, at least one clock cycle is included before the first clock cycle for reading the data in the first data stream.

[0136] Optionally, the first counting order of the first group of counters or the second group of counters corresponds to a sequence formed by the respective count values of multiple binary counters from low to high, and the second counting order of the first group of counters or the second group of counters corresponds to a sequence formed by the respective count values of multiple binary counters from high to low. Or the first counting order of the first group of counters or the second group of counters corresponds to a sequence formed by the respective count values of multiple binary counters from high to low, and the second counting order of the first group of counters or the second group of counters corresponds to a sequence formed by the respective count values of multiple binary counters from low to high.

[0137] An embodiment of the present application provides a baseband system, which includes: a modulator for modulating a bit stream; and the data processing device 800 for Fourier transform described above, which is used for performing Fourier transform on the modulated data.

[0138] An embodiment of the present application provides a wireless communication device, which includes: the baseband system described above for outputting a baseband signal; and a radio frequency system for frequency-converting the baseband signal output by the baseband system to obtain a radio frequency signal. It should be noted that the wireless communication device can be either the terminal device described above or the network device described above for implementing wireless communication.

[0139] The terminal device in the embodiments of this application may be a receiving end in a communication system. For example, it may be a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station (MS), a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, or a user device, etc.

[0140] The network device in the embodiments of this application may be a transmitting end in a communication system, and may also be referred to as an access network device or a radio access network device. For example, the network device may be a base station. The base station may generally cover various names as follows, such as: Node B, evolved Node B (eNB), next generation Node B (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station MeNB, secondary station SeNB, multi-mode radio (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), positioning node, etc.

[0141] The embodiments of this application also provide a chip, which includes programmable logic circuits and / or program instructions. When the chip runs, it implements the steps of the various methods described above.

[0142] The embodiments of this application also provide a computer-readable storage medium, on which a program is stored. When the program is executed by a processor, it implements the steps of the various methods described above.

[0143] It should be understood that in the embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0144] It should be understood that the term "and / or" in this text is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " in this text generally represents an "or" relationship between the associated objects before and after.

[0145] It should be understood that in various embodiments of the present application, the magnitude of the sequence numbers of the above processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0146] In several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and apparatuses can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be in electrical, mechanical, or other forms.

[0147] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0148] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0149] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a Digital Video Disc (DVD)), or a semiconductor medium (such as a Solid State Disk (SSD)), etc.

[0150] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments of the present application can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0151] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data processing method for Fourier transform, characterized in that, Including: Writing a first data stream into a memory; Reading out the first data stream from the memory in a reverse bit order; Writing a second data stream into the memory in a first address order, where the second data stream is a subsequent data stream of the first data stream, and the first address order is the same as the address order used when the first data stream is read out from the memory; Reading out the second data stream from the memory in a second address order, where the second address order is the same as the address order used when the first data stream is written into the memory; The first data stream and the second data stream are data for Fourier transform; The address order used when the first data stream is written into the memory is the first counting order of a first group of counters, the address order used when the first data stream is read out from the memory is the second counting order of the first group of counters, the first address order is the second counting order of a second group of counters, the second address order is the first counting order of the second group of counters, and the reading out the second data stream from the memory in the second address order includes: After completely reading out the first data stream from the memory in the second counting order of the first group of counters and completely writing the second data stream into the memory in the second counting order of the second group of counters, reading out the second data stream from the memory in the first counting order of the second group of counters.

2. The method according to claim 1, characterized in that, The first data stream and / or the second data stream perform Fourier transform in a form with a parallel number of P, the memory includes P storage units, and the reading out the first data stream from the memory in a reverse bit order and writing the second data stream into the memory in the first address order include: Within one clock cycle, after reading out P data from the storage addresses in the P storage units in a reverse bit order for the first data stream, writing P data for the second data stream into the storage addresses in the P storage units in the first address order.

3. The method according to claim 1, wherein The first data stream and / or the second data stream perform Fourier transform in a form with a parallel number of P, the memory includes 2P storage units, and the reading out the first data stream from the memory in a reverse bit order and writing the second data stream into the memory in the first address order include: Within a first clock cycle, reading out 2P data from the storage addresses in the 2P storage units in a reverse bit order for the first data stream; Within the next clock cycle after the first clock cycle, writing 2P data for the second data stream into the storage addresses in the 2P storage units in the first address order.

4. The method according to claim 3, wherein When the number of points of the first data stream is greater than the number of points of the second data stream, at least one clock cycle before the first clock cycle is used to read out the data in the first data stream.

5. The method according to claim 1, characterized in that, The first counting order of the first set of counters or the second set of counters corresponds to a sequence formed by the respective count values of multiple binary counters from low to high. The second counting order of the first set of counters or the second set of counters corresponds to a sequence formed by the respective count values of multiple binary counters from high to low. Or the first counting order of the first set of counters or the second set of counters corresponds to a sequence formed by the respective count values of multiple binary counters from high to low, and the second counting order of the first set of counters or the second set of counters corresponds to a sequence formed by the respective count values of multiple binary counters from low to high.

6. A data processing device for Fourier transform, characterized in that, Comprising: A memory for storing data; A processor for performing the following operations: Writing a first data stream to the memory; Reading out the first data stream from the memory in a reverse bit order; Writing a second data stream to the memory in a first address order, where the second data stream is the subsequent data stream of the first data stream, and the first address order is the same as the address order used when the first data stream is read out from the memory; Reading out the second data stream from the memory in a second address order, where the second address order is the same as the address order used when the first data stream is written to the memory; The first data stream and the second data stream are data for Fourier transform; The address order used when the first data stream is written to the memory is the first counting order of the first set of counters. The address order used when the first data stream is read out from the memory is the second counting order of the first set of counters. The first address order is the second counting order of the second set of counters. The second address order is the first counting order of the second set of counters. The reading out the second data stream from the memory in the second address order includes: After completely reading out the first data stream from the memory in the second counting order of the first set of counters and completely writing the second data stream to the memory in the second counting order of the second set of counters, reading out the second data stream from the memory in the first counting order of the second set of counters.

7. The device according to claim 6, characterized in that, The first data stream and / or the second data stream are subjected to Fourier transform in a form with a parallel number of P. The memory includes P storage units. Specifically, the processor is configured to: Within one clock cycle, after reading out P data from the storage addresses in the P storage units in a reverse bit order for the first data stream, writing the second data stream to the storage addresses in the P storage units in the first address order for P data.

8. The device according to claim 6, characterized in that, The first data stream and / or the second data stream are subjected to Fourier transform in a form with a parallel number of P. The memory includes 2P storage units. Specifically, the processor is configured to: Within the first clock cycle, reading out 2P data from the storage addresses in the 2P storage units in a reverse bit order for the first data stream; In the next clock cycle after the first clock cycle, write 2P data of the second data stream to the storage addresses in the 2P storage units according to the first address order.

9. The device according to claim 8, wherein When the number of points of the first data stream is greater than the number of points of the second data stream, at least one clock cycle is included before the first clock cycle for reading the data in the first data stream.

10. The device according to claim 6, characterized in that, The first counting order of the first set of counters or the second set of counters corresponds to a sequence formed by the respective count values of a plurality of binary counters from low to high, and the second counting order of the first set of counters or the second set of counters corresponds to a sequence formed by the respective count values of a plurality of binary counters from high to low, or the first counting order of the first set of counters or the second set of counters corresponds to a sequence formed by a plurality of binary counters from high to low, and the second counting order of the first set of counters or the second set of counters corresponds to a sequence formed by a plurality of binary counters from low to high.

11. A baseband system, characterized in that, Comprising: A modulator for modulating a bit stream; And The data processing device for Fourier transform according to any one of claims 6-10, for performing Fourier transform on the modulated data.

12. A wireless communication device, characterized in that, Comprising: The baseband system according to claim 11, for outputting a baseband signal; And A radio frequency system for frequency-converting the baseband signal output by the baseband system to obtain a radio frequency signal.

13. A chip, characterized in that The chip includes programmable logic circuits and / or program instructions, and when the chip runs, it implements the method according to any one of claims 1-5.

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