Semiconductor structure and method for forming the same

Abstract

The present application provides a semiconductor structure and a method for forming the same, the structure comprising: a substrate, the substrate comprising a stacked first wafer and a second wafer and a silicon through hole that penetrates the second wafer and electrically connects a first rewiring layer in the first wafer, a second metal wiring layer being formed in the second wafer; a barrier layer located on the surface of the second wafer; a dielectric layer located on the surface of the barrier layer; a second rewiring layer located in the barrier layer and the dielectric layer, a first portion of the second rewiring layer electrically connected to the silicon through hole, a second portion of the second rewiring layer located above the second metal wiring layer; a second through hole located below the second portion of the second rewiring layer and electrically connecting the second portion of the second rewiring layer and the second metal wiring layer. The semiconductor structure and the method for forming the same described in the present application use an auxiliary layer to improve the photolithography effect, and can produce high aspect ratio through holes of better quality.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Through Silicon Via (TSV) can be used to connect wafers in 3D integrated packaging. In some 3D integrated packaging processes, TSV is not directly connected to the device layer on the stacked wafer, but requires redistribution layers (RDLs) and through holes to connect TSV and the devices on the stacked wafer to achieve electrical connection.

[0003] In some semiconductor structure formation methods, since the thickness of the stacked wafer is relatively thick (usually tens of microns), the height of the TSV is also relatively high, which results in a thicker film thickness between the metal wiring layer and the RDLs in the stacked wafer, and thus the through hole connecting the metal wiring layer and the RDLs has a higher aspect ratio (usually greater than 6, while only about 1-2 is required in conventional logic processes), which is difficult for current photolithography processes. Therefore, it is necessary to provide a more effective and reliable technical solution to make such a high aspect ratio through hole. Summary of the invention

[0004] The present application provides a semiconductor structure and a method for forming the same, which can produce high aspect ratio through holes with better quality.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a stacked first wafer and a second wafer and a silicon through hole that penetrates the second wafer and electrically connects a first rewiring layer in the first wafer, and a second metal wiring layer is formed in the second wafer; forming a barrier layer and a dielectric layer on the surface of the silicon through hole and the surface of the second wafer in sequence; forming at least one auxiliary layer on the surface of the dielectric layer; forming a first groove penetrating the auxiliary layer, the first groove being located above the second metal wiring layer; etching along the first groove until the second metal wiring layer is exposed; removing the at least one auxiliary layer; forming a second groove in the dielectric layer and the barrier layer, a first portion of the second groove exposing the silicon through hole, and a second portion of the second groove connecting to the first groove; forming a second rewiring layer in the second groove and a second through hole in the first groove.

[0006] In some embodiments of the present application, the method for forming the first groove includes: forming a photoresist layer on the surface of the at least one auxiliary layer; exposing and developing the photoresist layer to form a patterned photoresist layer, wherein the patterned photoresist layer defines the position of the first groove; and etching the at least one auxiliary layer using the patterned photoresist layer as a mask to form the first groove.

[0007] In some embodiments of the present application, the method of forming the second redistribution layer and the second through hole includes: filling the first trench and the second trench with a conductive material; and removing the conductive material above the surface of the second trench by grinding.

[0008] In some embodiments of the present application, a method for forming the at least one auxiliary layer includes a chemical vapor deposition process.

[0009] In some embodiments of the present application, the auxiliary layer includes a stacked amorphous carbon layer and a capping layer.

[0010] In some embodiments of the present application, the thickness of the amorphous carbon layer is 1000 angstroms to 9000 angstroms, and the thickness of the capping layer is 1000 angstroms to 9000 angstroms.

[0011] In some embodiments of the present application, the at least one auxiliary layer has one to three layers.

[0012] In some embodiments of the present application, the material of the barrier layer includes silicon nitride.

[0013] In some embodiments of the present application, the first wafer further includes a first metal wiring layer, and the first metal wiring layer is electrically connected to the first redistribution layer through a first through hole.

[0014] In some embodiments of the present application, the semiconductor structure further includes an intermediate dielectric layer located between the first wafer and the second wafer.

[0015] Another aspect of the present application also provides a semiconductor structure, including: a substrate, the substrate including a stacked first wafer and a second wafer and a silicon-through via that penetrates the second wafer and is electrically connected to a first rewiring layer in the first wafer, a second metal wiring layer being formed in the second wafer; a barrier layer, located on the surface of the second wafer; a dielectric layer, located on the surface of the barrier layer; a second rewiring layer, located between the barrier layer and the dielectric layer, a first portion of the second rewiring layer is electrically connected to the silicon-through via, and a second portion of the second rewiring layer is located above the second metal wiring layer; a second through hole, located below the second portion of the second rewiring layer and electrically connecting the second portion of the second rewiring layer and the second metal wiring layer.

[0016] In some embodiments of the present application, the first wafer includes a first substrate and a first interlayer dielectric layer and a first metal wiring layer located in the first interlayer dielectric layer, and the first redistribution layer is located in the first interlayer dielectric layer and is electrically connected to the first metal wiring layer.

[0017] In some embodiments of the present application, the second wafer includes a second substrate and a second interlayer dielectric layer, and the second metal wiring layer is located in the second interlayer dielectric layer and is electrically connected to the second redistribution layer.

[0018] In some embodiments of the present application, the material of the barrier layer includes silicon nitride.

[0019] In some embodiments of the present application, the first wafer further includes a first metal wiring layer, and the first metal wiring layer is electrically connected to the first redistribution layer through a first through hole.

[0020] In some embodiments of the present application, the semiconductor structure further includes an intermediate dielectric layer located between the first wafer and the second wafer.

[0021] The present application provides a semiconductor structure and a method for forming the same, which uses an auxiliary layer to improve the photolithography effect and can produce a high aspect ratio through hole with better quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only used for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0023] Figures 1 to 10 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0025] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0026] Figures 1 to 10 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application.

[0027] An embodiment of the present application provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a stacked first wafer and a second wafer and a silicon-through via that penetrates the second wafer and electrically connects a first rewiring layer in the first wafer, a second metal wiring layer being formed in the second wafer; forming a barrier layer and a dielectric layer on the surface of the silicon-through via and the surface of the second wafer in sequence; forming at least one auxiliary layer on the surface of the dielectric layer; forming a first groove penetrating the auxiliary layer, the first groove being located above the second metal wiring layer; etching along the first groove until the second metal wiring layer is exposed; removing the at least one auxiliary layer; forming a second groove in the dielectric layer and the barrier layer, a first portion of the second groove exposing the silicon-through via and a second portion of the second groove connecting to the first groove; forming a second rewiring layer in the second groove and a second through hole in the first groove.

[0028] refer to Figure 1 As shown, a substrate 100 is provided, which includes a stacked first wafer 110 and a second wafer 120 and a through silicon via 140 that penetrates the second wafer 120 and electrically connects the first redistribution layer 115 in the first wafer 110, and a second metal wiring layer 123 is formed in the second wafer 120.

[0029] Continue to refer Figure 1 As shown, the first wafer 110 includes a first substrate 111 and a first interlayer dielectric layer 112. The material of the first substrate 111 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or indium gallium phosphide, etc.; or (iv) a combination of the above. The material of the first interlayer dielectric layer 112 includes silicon oxide or silicon nitride, etc.

[0030] In some embodiments of the present application, the first wafer 110 further includes a first metal wiring layer 113, which is located in the first interlayer dielectric layer 112 and is used to electrically connect active devices (not shown in the figure) in the first substrate 111. The first metal wiring layer 113 is also electrically connected to the first redistribution layer 115 through a first through hole 114. The material of the first metal wiring layer 113 includes copper or aluminum. The material of the first through hole 114 includes tungsten or copper. The material of the first redistribution layer 115 includes copper or aluminum.

[0031] The second wafer 120 includes a second substrate 121 and a second interlayer dielectric layer 122. The material of the second substrate 121 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or indium gallium phosphide; or (iv) a combination of the above. The material of the second interlayer dielectric layer 122 includes silicon oxide or silicon nitride. The second metal wiring layer 123 is located in the second interlayer dielectric layer 122 and is used to electrically connect the active devices (not shown in the figure) in the second substrate 121. The material of the second metal wiring layer 123 includes copper or aluminum.

[0032] In some embodiments of the present application, the material of the through silicon via 140 includes copper or tungsten.

[0033] In some embodiments of the present application, the semiconductor structure further includes an intermediate dielectric layer 130 located between the first wafer 110 and the second wafer 120 for bonding the first wafer 110 and the second wafer 120. The through silicon via 140 also penetrates the intermediate dielectric layer 130.

[0034] In the 3D packaging process of the semiconductor structure, the stacked first wafer 110 and the second wafer 120 need to be electrically connected, so the second metal wiring layer 123 also needs to be electrically connected to the through silicon via 140. It should be noted that the embodiment of the present application only takes two wafers as an example, and the process of the present application can also be applied to the stacking process of more than two wafers.

[0035] refer to Figure 2 As shown, a barrier layer 150 and a dielectric layer 160 are sequentially formed on the surface of the through silicon via 140 and the surface of the second wafer 120. The barrier layer 150 is mainly used to block the diffusion of metal ions in the through silicon via 140, for example, diffusing into the dielectric layer 160 to affect device performance. The dielectric layer 160 is used to form a second rewiring layer.

[0036] In some embodiments of the present application, the material of the barrier layer 150 includes silicon nitride. The thickness of the barrier layer 150 is, for example, 1 micron to 8 microns, such as 2 microns, 4 microns, 5 microns or 6 microns. The method of forming the barrier layer 150 includes a chemical vapor deposition process or a physical vapor deposition process.

[0037] In some embodiments of the present application, the material of the dielectric layer 160 includes silicon oxide. The method of forming the dielectric layer 160 includes a chemical vapor deposition process or a physical vapor deposition process.

[0038] refer to Figure 3As shown, at least one auxiliary layer 170 is formed on the surface of the dielectric layer 160. The auxiliary layer 170 is used to improve the effect of subsequent photolithography to form the second through hole. Specifically, on the one hand, it can improve the clarity of the photolithography pattern, and on the other hand, it can serve as an etching stop layer for photolithography.

[0039] In some embodiments of the present application, the method for forming the at least one auxiliary layer 170 includes a chemical vapor deposition process. The process for forming the auxiliary layer 170 can be compatible with conventional processes and will not cause additional burden.

[0040] In some embodiments of the present application, the auxiliary layer 170 includes a stacked amorphous carbon layer 171 and a capping layer 172. The auxiliary layer 170 is used to assist the photolithography process, so it is necessary to select a suitable material to improve the pattern clarity and precision of the photoresist after exposure and development, such as amorphous carbon. The amorphous carbon layer can also be replaced with other suitable materials, such as anti-reflective materials. The capping layer 172 can also be used as an etching stop layer for photolithography, and its material is, for example, oxide.

[0041] In some embodiments of the present application, the thickness of the amorphous carbon layer is 1000 angstroms to 9000 angstroms, such as 2000 angstroms, 4000 angstroms, 6000 angstroms or 8000 angstroms, etc., and the thickness of the capping layer is 1000 angstroms to 9000 angstroms, such as 2000 angstroms, 4000 angstroms, 6000 angstroms or 8000 angstroms, etc. The thickness of the amorphous carbon layer 171 and the capping layer 172 can be set according to process conditions and photolithography requirements.

[0042] In some embodiments of the present application, the at least one auxiliary layer 170 has one to three layers. In actual processes, when the required auxiliary layer thickness is thicker, it may not be possible to form an auxiliary layer of sufficient thickness at one time due to process limitations, so multiple auxiliary layers may be formed to achieve the required thickness.

[0043] refer to Figures 4 to 6 As shown, a first trench 180 penetrating the auxiliary layer 170 is formed, and the first trench 180 is located above the second metal wiring layer 123 .

[0044] refer to Figure 4 As shown, a photoresist layer 1810 is formed on the surface of the at least one auxiliary layer 170. In order to control the cost, the material of the photoresist layer 181 can be selected from common materials in the process. When the photoresist layer is used alone, the current photolithography accuracy may not meet the requirements for etching a high aspect ratio groove, so it needs to be used together with the auxiliary layer 170.

[0045] refer to Figure 5As shown, the photoresist layer 181 is exposed and developed to form a patterned photoresist layer 181, and the patterned photoresist layer 181 defines the position of the first groove 180. Due to the role of the auxiliary layer 170, specifically the role of the amorphous carbon layer 171, the clarity and precision of the patterned photoresist layer 181 are better than when the auxiliary layer 170 is not used, thereby improving the photolithography effect.

[0046] refer to Figure 6 As shown, the at least one auxiliary layer 170 is etched using the patterned photoresist layer 181 as a mask to form the first groove 180. The etching includes wet etching or dry etching.

[0047] refer to Figure 7 As shown, etching is performed along the first groove 180 until the second metal wiring layer 123 is exposed. Since the etching thickness is relatively thick, the entire photoresist layer 181 and even part of the auxiliary layer 170 can be consumed. Of course, the photoresist layer 181 can also be removed separately before etching.

[0048] In some embodiments of the present application, the first groove 180 can also be formed by one etching, that is, Figure 6 and Figure 7 The step can be one step.

[0049] In some embodiments of the present application, the aspect ratio of the first trench 180 is greater than or equal to 6. The aspect ratio refers to the ratio of the trench diameter to the trench depth. The number of the first trench 180 can be multiple.

[0050] refer to Figure 8 As shown, the at least one auxiliary layer 170 is removed. The method of removing the auxiliary layer 170 includes wet etching or ashing.

[0051] refer to Fig. 9 As shown, a second trench 190 is formed in the dielectric layer 160 and the barrier layer 150, a first portion of the second trench 190 exposes the through silicon via 140, and a second portion of the second trench 190 is connected to the first trench 180. The second trench 190 is used to form a second rewiring layer.

[0052] In some embodiments of the present application, a method of forming the second trench 190 includes wet etching or dry etching.

[0053] In the embodiment of the present application, a first trench for making a second through hole is first formed, and then a second trench for making a second redistribution layer is formed, which can further improve the ability to make a through hole with a high aspect ratio.

[0054] refer to Fig.10As shown, a second redistribution layer 125 is formed in the second trench and a second through hole 124 is formed in the first trench.

[0055] In some embodiments of the present application, the aspect ratio of the second through hole 124 is greater than 6. The aspect ratio refers to the ratio of the through hole diameter to the through hole depth. The number of the second through hole 124 can be multiple.

[0056] In some embodiments of the present application, the method of forming the second redistribution layer 125 and the second through hole 124 includes: filling the first trench 180 and the second trench 190 with conductive material; and grinding away the conductive material above the surface of the second trench 190 .

[0057] In the method for forming a semiconductor structure described in an embodiment of the present application, a photolithography process is used to form a second through hole with a high aspect ratio, wherein an auxiliary layer is used to improve the photolithography effect, so that a through hole with a high aspect ratio of better quality can be produced. In addition, the selected photoresist layer material and auxiliary layer material and the corresponding formation process can be compatible with conventional processes to reduce costs.

[0058] An embodiment of the present application also provides a semiconductor structure, comprising: a substrate, the substrate comprising a stacked first wafer and a second wafer and a silicon-through via that penetrates the second wafer and is electrically connected to a first rewiring layer in the first wafer, a second metal wiring layer being formed in the second wafer; a barrier layer, located on the surface of the second wafer; a dielectric layer, located on the surface of the barrier layer; a second rewiring layer, located between the barrier layer and the dielectric layer, a first portion of the second rewiring layer is electrically connected to the silicon-through via, and a second portion of the second rewiring layer is located above the second metal wiring layer; a second through hole, located below the second portion of the second rewiring layer and electrically connecting the second portion of the second rewiring layer and the second metal wiring layer.

[0059] refer to Fig.10 As shown, the substrate 100 includes a stacked first wafer 110 and a second wafer 120 and a through silicon via 140 penetrating the second wafer 120 and electrically connecting the first redistribution layer 115 in the first wafer 110 , and a second metal wiring layer 123 is formed in the second wafer 120 .

[0060] Continue to refer Fig.10As shown, the first wafer 110 includes a first substrate 111 and a first interlayer dielectric layer 112. The material of the first substrate 111 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or indium gallium phosphide; or (iv) a combination of the above. The material of the first interlayer dielectric layer 112 includes SiO 2 ,SiOCHSiC,Si 3 N 4 , BN, AIN, Al 2 O 3 wait.

[0061] In some embodiments of the present application, the first wafer 110 further includes a first metal wiring layer 113, which is located in the first interlayer dielectric layer 112 and is used to electrically connect active devices (not shown in the figure) in the first substrate 111. The first metal wiring layer 113 is also electrically connected to the first redistribution layer 115 through a first through hole 114. The material of the first metal wiring layer 113 includes copper or aluminum. The material of the first through hole 114 includes tungsten or copper. The material of the first redistribution layer 115 includes copper or aluminum.

[0062] The second wafer 120 includes a second substrate 121 and a second interlayer dielectric layer 122. The material of the second substrate 121 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. The material of the second interlayer dielectric layer 122 includes SiO 2 ,SiOCHSiC,Si 3 N 4 , BN, AIN, Al 2 O 3 The material of the second interlayer dielectric layer 122 may be the same as or different from that of the first interlayer dielectric layer 112. The second metal wiring layer 123 is located in the second interlayer dielectric layer 122 and is used to electrically connect active devices (not shown) in the second substrate 121. The material of the second metal wiring layer 123 includes copper or aluminum.

[0063] In some embodiments of the present application, the material of the through silicon via 140 includes copper or tungsten.

[0064] In some embodiments of the present application, the semiconductor structure further includes an intermediate dielectric layer 130 located between the first wafer 110 and the second wafer 120, for bonding the first wafer 110 and the second wafer 120. The through silicon via 140 also penetrates the intermediate dielectric layer 130. The material of the intermediate dielectric layer 130 includes SiO 2 ,SiOCHSiC,Si 3 N 4 , BN, AIN, Al 2 O 3 The material of the intermediate dielectric layer 130 may be the same as or different from the material of the second interlayer dielectric layer 122 and the material of the first interlayer dielectric layer 112 .

[0065] It should be noted that the embodiments of the present application only take two wafers as an example, and the process of the present application can also be applied to the stacking process of more than two wafers.

[0066] Continue to refer Fig.10 As shown, a barrier layer 150 and a dielectric layer 160 are sequentially formed on the surface of the second wafer 120. The barrier layer 150 is mainly used to block the diffusion of metal ions in the through silicon via 140, for example, diffusing into the dielectric layer 160 to affect device performance. The dielectric layer 160 is used to form a second rewiring layer.

[0067] In some embodiments of the present application, the material of the barrier layer 150 includes silicon nitride. The thickness of the barrier layer 150 is, for example, 1 micrometer to 8 micrometers, such as 2 micrometers, 4 micrometers, 5 micrometers or 6 micrometers.

[0068] In some embodiments of the present application, the material of the dielectric layer 160 includes silicon oxide.

[0069] Continue to refer Fig.10 As shown, a second rewiring layer 125 is formed in the dielectric layer 160 and the barrier layer 150 , a portion of the second rewiring layer 125 is electrically connected to the through silicon via 140 , and another portion of the second rewiring layer 125 is electrically connected to the second metal wiring layer 123 through a second through hole 124 .

[0070] In some embodiments of the present application, the aspect ratio of the second through hole 124 is greater than 6. The aspect ratio refers to the ratio of the through hole diameter to the through hole depth. The number of the second through hole 124 can be multiple.

[0071] The present application provides a semiconductor structure and a method for forming the same, which uses an auxiliary layer to improve the photolithography effect and can produce a high aspect ratio through hole with better quality.

[0072] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0073] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may also be present.

[0074] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0075] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0076] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, the substrate comprising a stacked first wafer and a second wafer and a through silicon via penetrating the second wafer and electrically connected to a first rewiring layer in the first wafer, a second metal wiring layer formed in the second wafer, the second wafer comprising a second substrate and a second interlayer dielectric layer, the second metal wiring layer being located in the second interlayer dielectric layer and electrically connected to active devices in the second substrate; Sequentially forming a barrier layer and a dielectric layer on the surface of the through silicon via and the surface of the second wafer; forming at least one auxiliary layer on the surface of the dielectric layer, wherein the auxiliary layer comprises a stacked amorphous carbon layer and a covering layer; forming a first trench penetrating the auxiliary layer, wherein the first trench is located above the second metal wiring layer; Etching along the first groove until the second metal wiring layer is exposed; removing the at least one auxiliary layer; forming a second trench in the dielectric layer and the barrier layer, wherein a first portion of the second trench exposes the through silicon via, and a second portion of the second trench is connected to the first trench; A second rewiring layer is formed in the second trench and a second via is formed in the first trench.

2. The method for forming a semiconductor structure according to claim 1, It is characterized in that The method of forming the first groove includes: forming a photoresist layer on the surface of the at least one auxiliary layer; exposing and developing the photoresist layer to form a patterned photoresist layer, wherein the patterned photoresist layer defines a position of the first groove; The at least one auxiliary layer is etched using the patterned photoresist layer as a mask to form the first groove.

3. The method for forming a semiconductor structure according to claim 1, It is characterized in that The method of forming the second redistribution layer and the second through hole includes: Filling a conductive material in the first trench and the second trench; The conductive material above the surface of the second trench is removed by grinding.

4. The method for forming a semiconductor structure according to claim 1, It is characterized in that The method of forming the at least one auxiliary layer includes a chemical vapor deposition process.

5. The method for forming a semiconductor structure according to claim 1, It is characterized in that The thickness of the amorphous carbon layer is 1000 angstroms to 9000 angstroms. The thickness of the capping layer is 1000 angstroms to 9000 angstroms.

6. The method for forming a semiconductor structure according to claim 1, It is characterized in that The at least one auxiliary layer has one to three layers.

7. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the barrier layer includes silicon nitride.

8. The method for forming a semiconductor structure according to claim 1, It is characterized in that The first wafer further includes a first metal wiring layer, and the first metal wiring layer is electrically connected to the first redistribution layer through a first through hole.

9. The method for forming a semiconductor structure according to claim 1, It is characterized in that Also included is an intermediate dielectric layer located between the first wafer and the second wafer.

10. A semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 1 to 9, It is characterized in that include: A substrate, the substrate comprising a stacked first wafer and a second wafer and a through silicon via penetrating the second wafer and electrically connected to a first redistribution layer in the first wafer, wherein a second metal wiring layer is formed in the second wafer; A barrier layer, located on the surface of the second wafer; A dielectric layer, located on the surface of the barrier layer; A second rewiring layer is located between the barrier layer and the dielectric layer, a first portion of the second rewiring layer is electrically connected to the through silicon via, and a second portion of the second rewiring layer is located above the second metal wiring layer; The second through hole is located below the second portion of the second re-wiring layer and electrically connects the second portion of the second re-wiring layer and the second metal wiring layer.

11. The semiconductor structure according to claim 10, It is characterized in that The first wafer includes a first substrate, a first interlayer dielectric layer, and a first metal wiring layer located in the first interlayer dielectric layer. The first redistribution layer is located in the first interlayer dielectric layer and is electrically connected to the first metal wiring layer.

12. The semiconductor structure according to claim 10, It is characterized in that The second wafer includes a second substrate and a second interlayer dielectric layer. The second metal wiring layer is located in the second interlayer dielectric layer and is electrically connected to the second redistribution layer.

13. The semiconductor structure according to claim 10, It is characterized in that The material of the barrier layer includes silicon nitride.

14. The semiconductor structure according to claim 10, It is characterized in that The first wafer further includes a first metal wiring layer, and the first metal wiring layer is electrically connected to the first redistribution layer through a first through hole.

15. The semiconductor structure according to claim 10, It is characterized in that Also included is an intermediate dielectric layer located between the first wafer and the second wafer.

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