A power structure and method of manufacture and apparatus

Abstract

The embodiment of the present application discloses a power structure, a preparation method and equipment, which are used for providing a high-integration power structure and meeting the demand of a high-frequency and high-power field. The embodiment of the present application provides a power structure, which comprises a first substrate, a second substrate, a driving chip, a power chip and a conductive component. The first surface of the first substrate and the second surface of the second substrate are oppositely arranged. The first end of the conductive component is connected with the first surface, and the second end of the conductive component is connected with the second surface. The driving chip is arranged on the first substrate. The power chip is arranged on the second substrate.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a power structure, its fabrication method, and apparatus. Background Technology

[0002] Power management constantly addresses various user needs, such as requiring more functionality and higher performance, or reducing the geometric dimensions of power supply products to achieve smaller sizes. Sometimes, these user needs are conflicting, necessitating superior power solutions that optimize conversion efficiency, transient response, and noise power density to meet stringent performance requirements and the final product's form factor.

[0003] Power supply products can be used in a variety of fields, such as data center power supplies, adapter power supplies, and inverter power supplies. For example, power supply products can be power supplies in a package (PSIP). PSIPs can provide superior performance without compromising on conversion efficiency, transient response, or noise power density.

[0004] The increasing demands on power and operating frequency of power supply products are driving their continuous evolution towards higher power, higher frequency, and higher power density. For example, power supply integrated circuits (PSIPs) are constantly evolving towards higher power, higher frequency, and higher power density.

[0005] Current power supply products cannot achieve the integration required by the industry, making it difficult to adapt to the trend of product miniaturization. In addition, current power supply products have large parasitic parameters, which cannot meet the needs of high-frequency, high-power applications above megahertz. Summary of the Invention

[0006] This application provides a power structure, a fabrication method, and an apparatus for providing a highly integrated power structure to meet the needs of high-frequency, high-power applications.

[0007] To address the aforementioned technical problems, this application provides the following technical solutions:

[0008] In a first aspect, embodiments of this application provide a power structure, including: a first substrate, a second substrate, a driver chip, a power chip, and a conductive component, wherein a first surface of the first substrate and a second surface of the second substrate are disposed opposite to each other; a first end of the conductive component is connected to the first surface, and a second end of the conductive component is connected to the second surface; the driver chip is disposed on the first substrate; and the power chip is disposed on the second substrate.

[0009] In the above scheme, the first substrate has a first surface, and the second substrate has a second surface. The first and second surfaces are arranged opposite to each other. The power chip is disposed on the second substrate, thus the power chip is located between the first and second substrates. Additionally, the driver chip is disposed on the first substrate. Therefore, the power chip and driver chip are disposed on two substrates, forming a stacked structure based on the two substrates, which improves the integration of the power structure. The conductive component has a first end and a second end. The first end is connected to the first surface, and the second end is connected to the second surface. This conductive component can connect the first and second substrates, conducting electricity between them. This enables electrical transmission between the first and second substrates, reducing parasitic parameters of the power structure and meeting the needs of high-frequency, high-power applications.

[0010] In one possible implementation, the power structure further includes a package, wherein the package covers a first surface of the first substrate, the second substrate, the driver chip, the power chip, and the conductive components. In the above embodiment, the package serves to encapsulate the internal structure of the power structure. The driver chip, the power chip, and the conductive components are all encapsulated within the package, thereby obtaining a sealed power structure. For example, the power structure could be a three-dimensional, highly hermetically sealed package structure with two substrates interconnected by conductive components.

[0011] In one possible implementation, the driver chip is disposed on a first surface of the first substrate, or embedded within the first substrate; the power chip is disposed on a second surface of the second substrate. For example, the driver chip is located on the first surface and faces the second surface. In the above scheme, the driver chip and the power chip are disposed between the first and second substrates, and the driver chip and the power chip are disposed on different planes, resulting in a three-dimensional power structure. This allows for device miniaturization and high integration of the power structure.

[0012] In one possible implementation, the driver chip is disposed on the second surface of the second substrate; the power chip is disposed on the second surface of the second substrate. In the above scheme, the power structure includes multiple driver chips, some disposed on the first substrate and some on the second substrate, with the driver chips and power chips disposed between the first and second substrates. The driver chips and power chips are disposed on different planes, and the power structure is a three-dimensional structure. This allows for the miniaturization and high integration of the power structure.

[0013] In one possible implementation, the conductive component is located between the first and second surfaces. In the above embodiment, the conductive component can be a conductive pillar located between the first and second surfaces. In addition to conducting electricity, the conductive component in this application embodiment also serves a supporting function, allowing the power chip and the driver chip to be disposed in the space between the first and second substrates. Furthermore, the power structure also includes electronic components, which can also be disposed in the space between the first and second substrates.

[0014] In one possible implementation, the first end is soldered to the first surface, and the second end is soldered to the second surface. For example, the first end is connected to the first surface via a first solder, and the second end is connected to the second surface via a second solder. In the above solution, the conductive component can be connected to the first substrate and the second substrate via solder. By using solder, the conductive component can be fixed together with the first substrate and the second substrate, thereby forming a space between the first substrate and the second substrate.

[0015] In one possible implementation, the power structure further includes an electronic component, wherein the electronic component is disposed on a first surface of the first substrate and / or a second surface of the second substrate. For example, the electronic component is specifically a first electronic component, wherein it is disposed on the first surface and faces the second surface. In the above solution, the first electronic component can be disposed side-by-side with the driver chip on the first surface of the first substrate, the first electronic component can be disposed in the space between the first and second substrates, and the first electronic component and the power chip can be distributed on different planes. Therefore, the power structure is a three-dimensional structure, which is beneficial for miniaturization design. For example, the electronic component is specifically a second electronic component, disposed on the second surface and facing the first surface. In the above solution, the second electronic component can be disposed side-by-side with the power chip on the second surface of the second substrate, the second electronic component can be disposed in the space between the first and second substrates, and the second electronic component and the driver chip can be distributed on different planes. Therefore, the power structure is a three-dimensional structure, which is beneficial for miniaturization design. For example, there can be multiple electronic components, some disposed on the first surface and some disposed on the second surface. In the above scheme, electronic components can be placed in the space between the first substrate and the second substrate. The electronic components and the driving chip can be distributed on different planes. Therefore, the power structure is a three-dimensional structure, which is beneficial for the miniaturization design of the power structure.

[0016] In one possible implementation, the power structure further includes a heat dissipation module disposed on the back side of the second substrate. For example, the second substrate includes a third surface, and the second and third surfaces of the second substrate are opposite surfaces. The third surface of the second substrate is the reverse side of the second substrate, and for example, the third surface is used to house the heat dissipation module. The power chip and the heat dissipation module are disposed on different surfaces of the second substrate. The power chip is encapsulated by a package, but the heat dissipation module is not encapsulated by a package. Therefore, the heat dissipation module can be used to dissipate heat from the power structure. For example, the power structure can be a three-dimensional high-density, high-thermal-conductivity package structure in which two substrates are interconnected by conductive components.

[0017] In one possible implementation, the power structure further includes a pad located on a fourth surface of the first substrate, which is the back surface of the first surface. In this embodiment, the fourth surface and the first surface of the first substrate are opposite surfaces; the fourth surface is the reverse side of the first substrate, for example, it is used to mount the pad. The driver chip and the pad are respectively mounted on different surfaces of the first substrate. The driver chip is encapsulated by a package, but the pad is not encapsulated by the package. This pad can be used for electrical connection between the power structure and other external devices.

[0018] In one possible implementation, the first substrate is a first embedded substrate, wherein a driver chip is disposed within the first embedded substrate. In the above scheme, the driver chip is embedded in the first embedded substrate, so only the power chip and conductive components need to be disposed between the first embedded substrate and the second substrate, which can further reduce the size of the power structure and is beneficial to the miniaturization design of the power structure.

[0019] In one possible implementation, to distinguish the multiple power chips in the embodiments of this application, the power chip in "power chip disposed on the second substrate" is referred to as the first power chip. The power structure further includes a second power chip, and the first substrate is a second embedded substrate, wherein the second power chip is disposed within the second embedded substrate. In the above solution, the driver chip can be disposed on the first surface of the second embedded substrate, and the second power chip is disposed within the second embedded substrate. Therefore, only the power chip, conductive components, and driver chip need to be disposed between the second embedded substrate and the second substrate, which can further reduce the volume of the power structure and is beneficial to the miniaturization design of the power structure.

[0020] In one possible implementation, the power structure further includes a third electronic component, wherein the first substrate is a third embedded substrate, and the third electronic component is disposed within the third embedded substrate. In the above solution, the driver chip can be disposed on the first surface of the third embedded substrate, and the third electronic component is disposed within the third embedded substrate. Therefore, only the power chip, conductive component, and driver chip need to be disposed between the third embedded substrate and the second substrate, which can further reduce the size of the power structure and facilitate the miniaturization design of the power structure.

[0021] In one possible implementation, the power structure further includes a third power chip, which is located on the first surface and faces the second surface. In the above scheme, the power structure may include multiple power chips; for example, the power structure may include a power chip and a third power chip, with the power chip disposed on the second substrate and the third power chip disposed on the first substrate. The third power chip can be disposed side-by-side with the driver chip on the first surface of the first substrate, or it can be disposed in the space between the first and second substrates. The third power chip and the power chip can be distributed on different planes, thus the power structure is a three-dimensional structure, which is beneficial for miniaturization design.

[0022] In one possible implementation, the second substrate is a ceramic copper-clad laminate.

[0023] Secondly, embodiments of this application also provide a power structure, including: a first substrate, a second substrate, a driver chip, a power chip, a conductive line, a first package, and an adhesive mold, wherein the power chip is located on a second surface of the second substrate; the first package covers the second surface of the second substrate and the power chip; the first substrate is attached to the first package by the adhesive mold; the driver chip is disposed on the first substrate; one end of the conductive line is connected to the first substrate, and the other end of the conductive line is connected to the second substrate.

[0024] In the above scheme, the second substrate has a second surface, and the power chip is located on the second surface. The first substrate is adhered to the first package body by an adhesive mold, so that the power chip is located between the first and second substrates. Additionally, the driver chip is disposed on the first substrate. Therefore, the power chip and the driver chip are disposed on two substrates, forming a stacked structure based on the two substrates, which improves the integration of the power structure. The two ends of the conductive lines are connected to the first substrate and the second substrate respectively, enabling electrical transmission between the first and second substrates, reducing parasitic parameters of the power structure, and meeting the needs of high-frequency, high-power applications.

[0025] In one possible implementation, the power structure further includes a conductive component, wherein a first end of the conductive component is connected to a second surface of the second substrate. The connection between the first end of the conductive component and the second surface of the second substrate allows the second substrate to output electrical signals via the conductive component.

[0026] In one possible implementation, the power structure further includes a second package, wherein the second package covers the first substrate, a second surface of the second substrate, the driver chip, the power chip, and the conductive component, wherein a second end of the conductive component protrudes from the second package. In this embodiment, the second package encapsulates the internal structure of the power structure. For example, the second package encapsulates the first substrate, the second surface, the driver chip, the power chip, and the conductive wires, thereby obtaining a packaged power structure. Alternatively, the package can encapsulate the space between the first and second substrates. The power chip and the conductive wires are both encapsulated within the package, resulting in a sealed power structure. After encapsulation by the second package, the end of the conductive component protrudes from the second package, thus allowing the conductive component to be used for electrical connection between the power structure and external devices.

[0027] In one possible implementation, the driver chip is disposed on a first surface of the first substrate, or embedded within the first substrate; the power chip is disposed on a second surface of the second substrate. For example, the driver chip is located on the first surface and faces the second surface. The first surface is the surface of the first substrate away from the first package. In the above solution, the driver chip and the power chip are disposed between the first and second substrates, and the driver chip and the power chip are disposed on different planes, resulting in a three-dimensional power structure. This allows for device miniaturization and high integration of the power structure.

[0028] In one possible implementation, the driver chip is disposed on the second surface of the second substrate; the power chip is disposed on the second surface of the second substrate. In the above scheme, the power structure includes multiple driver chips, some disposed on the first substrate and some on the second substrate, with the driver chips and power chips disposed between the first and second substrates. The driver chips and power chips are disposed on different planes, and the power structure is a three-dimensional structure. This allows for the miniaturization and high integration of the power structure.

[0029] In one possible implementation, the power structure further includes an electronic component, wherein the electronic component is disposed on a first surface of the first substrate and / or a second surface of the second substrate, wherein the first surface is the surface of the first substrate away from the first package. For example, the first electronic component is disposed on the first surface and faces the second surface. In the above solution, the first electronic component can be disposed side-by-side with the driver chip on the first surface of the first substrate, and the first electronic component can be disposed in the space between the first substrate and the second substrate. The first electronic component and the power chip can be distributed on different planes, thus the power structure is a three-dimensional structure, which is beneficial for the miniaturization design of the power structure. For example, the electronic component is specifically a second electronic component, which is disposed on the second surface and faces the first surface. In the above solution, the second electronic component can be disposed side-by-side with the power chip on the second surface of the second substrate, and the second electronic component can be disposed in the space between the first substrate and the second substrate. The second electronic component and the driver chip can be distributed on different planes, thus the power structure is a three-dimensional structure, which is beneficial for the miniaturization design of the power structure. For example, the electronic component is disposed on the first surface of the first substrate and the second surface of the second substrate. For example, there are multiple electronic components, some of which are disposed on the first surface and others on the second surface. In the above scheme, the electronic components can be disposed in the space between the first substrate and the second substrate, and the electronic components and the driver chip can be distributed on different planes. Therefore, the power structure is a three-dimensional structure, which is beneficial for the miniaturization design of the power structure.

[0030] In one possible implementation, the power structure further includes a heat dissipation module disposed on the back side of a second surface of the second substrate. For example, the second substrate may have a third surface, and the second and third surfaces are opposite to each other, with the third surface being the reverse side of the second substrate. The third surface may be used to house the heat dissipation module. The power chip and the heat dissipation module are disposed on different surfaces of the second substrate. The power chip is encapsulated by a package, but the heat dissipation module is not encapsulated. Therefore, the heat dissipation module can be used to dissipate heat from the power structure. For example, the power structure may be a three-dimensional high-density, high-thermal-conductivity package structure in which two substrates are interconnected by conductive components.

[0031] In one possible implementation, the first substrate is a first embedded substrate, wherein a driver chip is disposed within the first embedded substrate. In the above scheme, the driver chip is embedded in the first embedded substrate, so only the power chip and conductive components need to be disposed between the first embedded substrate and the second substrate, which can further reduce the size of the power structure and is beneficial to the miniaturization design of the power structure.

[0032] In one possible implementation, to distinguish the multiple power chips in the embodiments of this application, the power chip in "power chip disposed on the second substrate" is referred to as the first power chip. The power structure further includes a second power chip, and the first substrate is a second embedded substrate, wherein the second power chip is disposed within the second embedded substrate. In the above solution, the driving chip can be disposed on the first surface of the second embedded substrate, and the second power chip is disposed within the second embedded substrate. Therefore, only the power chip and conductive components need to be disposed between the second embedded substrate and the second substrate, which can further reduce the volume of the power structure and is beneficial to the miniaturization design of the power structure.

[0033] In one possible implementation, the power structure further includes a third electronic component, wherein the first substrate is a third embedded substrate, and the third electronic component is disposed within the third embedded substrate. In the above solution, the driver chip can be disposed on the first surface of the third embedded substrate, and the third electronic component is disposed within the third embedded substrate. Therefore, only the power chip and conductive components need to be disposed between the third embedded substrate and the second substrate, which can further reduce the size of the power structure and facilitate the miniaturization design of the power structure.

[0034] In one possible implementation, the power structure further includes a fourth electronic component, which is disposed on a first surface of the first substrate. In this embodiment, the fourth surface and the first surface of the first substrate are opposite surfaces; the first surface is the reverse side of the first substrate, and for example, the fourth surface is used to dispose of the fourth electronic component. The fourth electronic component can be disposed on the first surface of the first substrate, and since the fourth electronic component and the power chip are distributed on different planes, the power structure is a three-dimensional structure, which is beneficial for miniaturization design.

[0035] In one possible implementation, the driver chip is located on the first surface of the first substrate. In the above scheme, the fourth surface and the first surface of the first substrate are two opposing surfaces. The driver chip can be disposed on the first surface of the first substrate. The driver chip and the power chip are distributed on different planes. Therefore, the power structure is a three-dimensional structure, which is beneficial for the miniaturization design of the power structure.

[0036] In one possible implementation, the power structure further includes a third power chip, which is located on the fourth surface and faces the second surface. In the above scheme, the power structure can include multiple power chips; for example, the power structure includes a power chip and a third power chip, with the power chip disposed on the second substrate and the third power chip disposed on the first substrate. The third power chip is disposed on the fourth surface of the first substrate, and can be disposed in the space between the first and second substrates. The third power chip can be distributed on different planes from the power chip, thus the power structure is a three-dimensional structure, which is beneficial for miniaturization design.

[0037] In one possible implementation, the second substrate is a ceramic copper-clad laminate.

[0038] Thirdly, embodiments of this application also provide a method for preparing a power structure, comprising: placing a power chip on a second surface of a second substrate; covering the second surface of the second substrate and the power chip with a first package; attaching the first substrate to the first package using an adhesive mold; placing a driver chip on the first substrate; and connecting one end of a conductive wire to the first substrate and the other end of the conductive wire to the second substrate.

[0039] In one possible implementation, the method further includes connecting a first end of the conductive component to a second surface of the second substrate.

[0040] In one possible implementation, the method further includes: covering the first substrate, the second surface of the second substrate, the driver chip, the power chip, and the conductive component with a second end of the conductive component exposed in the second package.

[0041] In one possible implementation, placing the driver chip on the first substrate includes: disposing the driver chip on a first surface of the first substrate, or embedding it within the first substrate;

[0042] Placing the power chip on the second surface of the second substrate includes: setting the power chip on the second surface of the second substrate.

[0043] In one possible implementation, the method further includes: placing an electronic component on a first surface of the first substrate, and / or disposing the electronic component on a second surface of the second substrate, wherein the first surface is the surface of the first substrate away from the first package.

[0044] In one possible implementation, the method further includes placing the heat dissipation module on the back side of the second surface of the second substrate.

[0045] In the third aspect of this application, the power structure prepared in the method of preparing the power structure includes the steps described in the second aspect and various possible implementations above, as detailed in the foregoing description of the second aspect and various possible implementations.

[0046] Fourthly, embodiments of this application also provide an alternating current (AC) module, including: a power structure as described in the first or second aspect.

[0047] Fifthly, embodiments of this application also provide an energy device, including: a power structure as described in the first or second aspect above; or,

[0048] The energy equipment includes: the alternating current module as described in the fourth aspect.

[0049] For example, energy equipment can include: site energy, network energy, data center energy, onboard charger (OBC) energy, inverter energy (i.e., photovoltaic energy), adapter energy, etc.

[0050] In a sixth aspect, embodiments of this application also provide a remote radio unit (RRU), including: an alternating current module as described in the fourth aspect.

[0051] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:

[0052] In this embodiment, the power structure includes a first substrate, a second substrate, a driver chip, a power chip, and a conductive component. The first substrate has a first surface, and the second substrate has a second surface, which are disposed opposite to each other. The power chip is disposed on the second substrate, thus positioned between the first and second substrates. The driver chip is disposed on the first substrate. Therefore, the power chip and driver chip are disposed on two substrates, forming a stacked structure based on the two substrates, which improves the integration of the power structure. The conductive component has a first end and a second end, with the first end connected to the first surface and the second end connected to the second surface. This conductive component connects the first and second substrates, conducting electricity between them, thereby reducing parasitic parameters of the power structure and meeting the needs of high-frequency, high-power applications.

[0053] In this embodiment, the second substrate has a second surface, and the power chip is located on the second surface. The first substrate is adhered to the first package via an adhesive mold, thereby placing the power chip between the first and second substrates. Additionally, a driver chip is disposed on the first substrate. Therefore, the power chip and driver chip are disposed on two substrates, forming a stacked structure based on the two substrates, which improves the integration of the power structure. The two ends of a conductive line are respectively connected to the first and second substrates, enabling electrical transmission between the first and second substrates, reducing parasitic parameters of the power structure, and meeting the needs of high-frequency, high-power applications. Attached Figure Description

[0054] Figure 1 This is a schematic diagram of a power structure provided in an embodiment of this application;

[0055] Figure 2 A schematic diagram of a power structure including two conductive components provided for an embodiment of this application;

[0056] Figure 3 This is a schematic diagram of the power structure including the package provided in the embodiments of this application;

[0057] Figure 4 A schematic diagram of a power structure including solder provided for an embodiment of this application;

[0058] Figure 5 A schematic diagram of a power structure including a first electronic component, provided for an embodiment of this application;

[0059] Figure 6 A schematic diagram of a power structure including multiple first electronic components provided for embodiments of this application;

[0060] Figure 7 A schematic diagram of a power structure including a second electronic component, provided for an embodiment of this application;

[0061] Figure 8 A schematic diagram of a power structure including multiple second electronic components provided for embodiments of this application;

[0062] Figure 9 A schematic diagram of a power structure including a ceramic layer and a copper layer is provided for an embodiment of this application;

[0063] Figure 10 A schematic diagram of a power structure including a heat dissipation module provided for an embodiment of this application;

[0064] Figure 11 A schematic diagram of a power structure including pads provided for an embodiment of this application;

[0065] Figure 12 A schematic diagram of a power structure including a first embedded substrate provided in an embodiment of this application;

[0066] Figure 13 A schematic diagram of a power structure including a second power chip, provided for an embodiment of this application;

[0067] Figure 14 A schematic diagram of a power structure including a third electronic component provided for an embodiment of this application;

[0068] Figure 15 A schematic diagram of a power structure including a second power chip, provided for an embodiment of this application;

[0069] Figure 16 This is a schematic diagram of the structure of assembling a first power chip on a second substrate provided in an embodiment of this application;

[0070] Figure 17 This is a schematic diagram of the structure of assembling a driver chip and conductive components on a first substrate provided in an embodiment of this application;

[0071] Figure 18 A schematic diagram of another power structure provided for an embodiment of this application;

[0072] Figure 19 A schematic diagram of a power structure including a second package and a first package provided in this application embodiment;

[0073] Figure 20 A schematic diagram of a power structure including conductive components provided in an embodiment of this application;

[0074] Figure 21 A schematic diagram of a power structure including a first electronic component, provided for an embodiment of this application;

[0075] Figure 22 A schematic diagram of a power structure including a second electronic component provided for an embodiment of this application;

[0076] Figure 23 A schematic diagram of a power structure including a heat dissipation module provided for an embodiment of this application;

[0077] Figure 24 A schematic diagram of a power structure including a first embedded substrate provided for an embodiment of this application;

[0078] Figure 25 A schematic diagram of a power structure including a second power chip, provided for an embodiment of this application;

[0079] Figure 26 A schematic diagram of a power structure including a third electronic component provided for an embodiment of this application;

[0080] Figure 27 A schematic diagram of a power structure including a fourth electronic component provided for an embodiment of this application;

[0081] Figure 28 A schematic diagram of a power structure including a third power chip, provided for an embodiment of this application;

[0082] Figure 29 A schematic diagram illustrating the fabrication method of the power structure provided in the embodiments of this application;

[0083] Figure 30 This is a schematic diagram of the structure of assembling a first power chip on a second substrate provided in an embodiment of this application;

[0084] Figure 31 This is a schematic diagram of the structure of a first package being packaged on a second substrate according to an embodiment of this application.

[0085] In addition, the reference numerals in the accompanying drawings of this application are as follows, and the reference numerals for each device component will not be referenced again in the subsequent detailed embodiments.

[0086] First substrate 101,

[0087] The first surface 1011 of the first substrate

[0088] Second substrate 102,

[0089] The second surface 1021 of the second substrate,

[0090] Driver chip 103,

[0091] The first power chip is 104.

[0092] Conductive component 105,

[0093] The first end 1051 of the conductive component

[0094] The second end 1052 of the conductive component

[0095] Package 106,

[0096] First solder 1071,

[0097] Second solder 1072,

[0098] First electronic component 108,

[0099] Second electronic component 109,

[0100] Heat dissipation module 110,

[0101] The ceramic layer 1022 of the second substrate,

[0102] The copper layer 1023 of the second substrate

[0103] The third surface 1024 of the second substrate,

[0104] The fourth surface 1012 of the first substrate,

[0105] Pad 111,

[0106] Second power chip 112,

[0107] Third electronic component 113,

[0108] The third power chip is 114.

[0109] Conductive wire 115,

[0110] Second package 116,

[0111] First package 117,

[0112] Adhesive mold 118,

[0113] Fourth electronic component 119. Detailed Implementation

[0114] This application provides a power structure, a fabrication method, and an apparatus for providing a highly integrated power structure to meet the needs of high-frequency, high-power applications.

[0115] The embodiments of this application will now be described with reference to the accompanying drawings.

[0116] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate; this is merely a way of distinguishing objects with the same properties in the embodiments of this application. For example, "first substrate" and "second substrate" refer to two different substrates that are not interdependent. In embodiments where "first" is not mentioned, "second" may be mentioned; similarly, in embodiments where "first" is mentioned, "second" may not be mentioned. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion so that a process, method, system, product, or apparatus that comprises a series of units is not necessarily limited to those units but may include other units not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0117] This application provides a power structure, which refers to a structural unit comprising a power chip. For example, a power structure can be a power module, power component, or power structural unit. In this application, the power structure can also be defined as a structural unit with other names, such as a module, device, equipment, terminal, or component. The specific implementation is not limited. The power structure provided in this application includes a power chip, which can also be called a "power semiconductor chip." A power chip is a chip that can generate power when energized. The specific implementation of the power chip is related to the application scenario of the power structure. For different power structures, the type of power chip included, the number of power chips, the arrangement of the power chips within the power structure, and the connection method between the power chips and other electronic components and chips within the power structure all need to be determined in conjunction with the specific application scenario of the power structure. For example, a power structure can be a power supply in a package (PSIP), and the power chip can be a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0118] The following is a description of the terminology used to describe the components of the power structure involved in the embodiments of this application:

[0119] The power structure provided in this application includes a dual-substrate architecture, a driver chip, a power chip, and conductive components. The substrate in this application can be a printed circuit board (PCB). A dual-substrate architecture refers to two substrates, defined as a first substrate and a second substrate. The first and second substrates can be two substrates arranged opposite each other, with a certain space between them (i.e., a certain distance between them, the value of which is not limited here). The first and second substrates are substrates with circuit functions and are also used to fix the chip. Based on the spatial distribution of the first and second substrates, one of the first and second substrates can be called the upper substrate, and the other substrate can be called the lower substrate. For ease of description, in subsequent embodiments, the first substrate can be the lower substrate, and the second substrate can be the upper substrate. The upper and lower substrates are defined based on the spatial distribution of the substrates and are not intended to limit the embodiments of this application.

[0120] In some embodiments of this application, the second substrate can be a substrate with heat dissipation function. For example, the second substrate can be a direct-bonded copper (DBC) ceramic substrate, which includes a ceramic layer and a copper layer. A DBC is a substrate made by directly sintering copper foil onto a ceramic surface. DBCs can be used in high-power semiconductor modules, power control circuits, power hybrid circuits, smart power components, high-frequency switching power supplies, solid-state relays, solar panel assemblies, etc.

[0121] In some embodiments of this application, a driver chip may be disposed on the first substrate, for example, the driver chip may be disposed on the surface of the first substrate. Alternatively, the first substrate may be an embedded substrate, which employs embedded component packaging (ECP) to embed electronic components and chips (e.g., driver chips, power chips) inside the substrate.

[0122] In this embodiment, the power structure includes a driver chip, which is a chip component used to drive the power chip. The driver chip stores a driver program. After the driver chip is powered on, it can run the driver program to drive the operation of the power chip.

[0123] The power structure in this application embodiment includes one or more power chips, the specific number of which needs to be determined based on the application scenario. For example, the power structure includes a first power chip. The first power chip and the driver chip are respectively disposed on different substrates in the power structure. The power structure includes a dual substrate, with the first power chip and the driver chip respectively disposed on one substrate. As can be seen from the foregoing description of the dual substrate, the two substrates in the dual substrate are arranged opposite each other, and the first power chip and the driver chip are disposed on different substrates. Therefore, the first power chip and the driver chip are not distributed on the same plane, but on different planes. Therefore, the power structure provided in this application embodiment is a three-dimensional structure. This distribution method of the first power chip and the driver chip can improve the integration of the power structure, reduce the spatial volume of the power structure, and adapt to the development trend of device miniaturization.

[0124] In some embodiments of this application, the power structure includes a first power chip and a second power chip, and the substrates on which the first power chip and the second power chip are located are different.

[0125] In this embodiment, the power structure includes a conductive component that can conduct electricity between the first substrate and the second substrate, i.e., the conductive component can interconnect the two substrates, enabling electrical transmission between the chips mounted on the two substrates. For example, signal transmission between the chips mounted on the two substrates can be achieved through the conductive component.

[0126] In some embodiments of this application, the conductive component may be made of copper or other conductive metal materials, and this is not limited thereto. Furthermore, the conductive component provided in the embodiments of this application may have various shapes, as long as it can achieve the function of interconnecting two substrates. For example, the conductive component may be one of the following shapes: columnar, plate-shaped, sheet-shaped, etc. For example, the cross-section of the conductive component may have various shapes, such as L-shaped, U-shaped, circular, rhomboid, etc.

[0127] In some embodiments of this application, the conductive component may have a supporting function in addition to its conductive function. For example, the conductive component may be supported between two substrates, thereby forming a space of a certain size between the two substrates, in which the components of the power structure can be accommodated.

[0128] In some embodiments of this application, the power structure may include one or more packages. When the power structure includes multiple packages, such as two packages, these two packages are defined as the second package and the first package, respectively. The chip in the power structure needs to be packaged to obtain a package. This package can encapsulate the surface of the substrate, the power chip, the driver chip, and conductive components. The package refers to the outer shell used to mount the semiconductor integrated circuit chip, serving to place, fix, seal, protect the chip, and enhance thermal conductivity. For example, the package can be a plastic encapsulation obtained by molding the surface of the substrate, the power chip, the driver chip, and conductive components. Alternatively, the package can be an encapsulation layer.

[0129] In some embodiments of this application, the power structure may include electronic components, which are necessary components within the power structure. For example, the power structure may contain one or more electronic components. For instance, an electronic component may be at least one of the following components: resistor, capacitor, and inductor. The implementation of electronic components is not limited in the embodiments of this application. When the power structure includes multiple electronic components, such as two electronic components, these two electronic components are defined as the first electronic component and the second electronic component, respectively. The deployment positions and functions of the first electronic component and the second electronic component within the power structure differ, as detailed in the examples provided in subsequent embodiments.

[0130] In some embodiments of this application, the second substrate is a substrate with heat dissipation function, such as a heat dissipation module disposed on the second substrate, which can be used to dissipate heat from the power chip. For example, the heat dissipation module can provide heat dissipation channels for the chip assembled on the upper substrate. In the embodiments of this application, the heat dissipation module includes, but is not limited to, the heat dissipation module being a heat dissipation material, or the heat dissipation module having heat dissipation channels, etc.

[0131] The foregoing has described the components of the power structure in the embodiments of this application. The power structure provided in the embodiments of this application will now be described in conjunction with the accompanying drawings.

[0132] Please see Figure 1 This application provides a power structure comprising: a first substrate, a second substrate, a driver chip, a power chip, and conductive components, wherein...

[0133] The first surface of the first substrate and the second surface of the second substrate are disposed opposite to each other.

[0134] The first end of the conductive component is connected to the first surface, and the second end of the conductive component is connected to the second surface;

[0135] The driver chip is disposed on the first substrate;

[0136] The power chip is mounted on the second substrate.

[0137] In some embodiments of this application, to distinguish the multiple power chips in the embodiments of this application, the power chip in the "power chip disposed on the second substrate" is referred to as the first power chip. For example, the first power chip is located on the second surface and faces the first surface.

[0138] in, Figure 1 There is a certain space between the first substrate and the second substrate shown. The conductive component plays the role of conducting electricity and providing support. The first surface of the first substrate is the main surface on which the chip is placed, for example, the first surface of the first substrate faces upward.

[0139] In some embodiments of this application, such as Figure 1 As shown, a driver chip is disposed on a first substrate, for example, the driver chip is located on the first surface and faces the second surface. The second surface of the second substrate is the main surface on which the chip is disposed, for example, the second surface of the second substrate faces downwards. There is a space between the first surface and the second surface, and the driver chip and the first power chip are disposed between the first substrate and the second substrate. For example, the first power chip can be connected to the second substrate via solder. The conductive component has a first end and a second end, which are the upper and lower ends of the conductive component. The first end is connected to the first surface, and the second end is connected to the second surface, so that the conductive component can conduct electricity between the first substrate and the second substrate. Figure 1In the power structure shown, the driver chip and the first power chip are disposed on different planes, and the power structure is a three-dimensional structure. Conductive components can connect the first substrate and the second substrate, thereby reducing the transmission path between the first substrate and the second substrate and reducing the parasitic parameters of the power structure. Based on Figure 1 The power structure shown can achieve miniaturization and high integration of power structure devices.

[0140] In some embodiments of this application, the driver chip is disposed on a first surface of the first substrate or embedded within the first substrate; the power chip is disposed on a second surface of the second substrate. For example, the driver chip is located on the first surface and faces the second surface. Alternatively, the driver chip can be embedded in the first substrate, as detailed in the following embodiments. In the above scheme, the driver chip and the power chip are disposed between the first and second substrates, and the driver chip and the power chip are disposed on different planes, resulting in a three-dimensional power structure. This allows for device miniaturization and high integration of the power structure.

[0141] It should be noted that the embodiments of this application do not limit the number and distribution of conductive components in the power structure, the number and distribution of driving chips in the power structure, or the number and distribution of the first power chip in the power structure. The specific details can be determined in conjunction with the application scenario. This is only an example for illustration. Figure 1 The power structure includes two conductive components, each of which serves to conduct electricity and support the first and second substrates. For example, the two conductive components may be symmetrically arranged.

[0142] like Figure 2 As shown, the power structure includes one conductive component, which serves to conduct electricity and provide support to the first and second substrates. It is not limited to this; the power structure in this embodiment may include other numbers of conductive components.

[0143] In some embodiments of this application, such as Figure 3 As shown, the power structure also includes: a package, wherein,

[0144] The package covers the first surface of the first substrate, the second substrate, the driver chip, the power chip, and the conductive components.

[0145] The package serves to encapsulate the internal structure of the power structure. For example, the package encapsulates the first surface of the first substrate, the second substrate, the driver chip, the power chip, and conductive components, thereby obtaining the encapsulated power structure. The package can cover one or more surfaces of the second substrate; for example, the package can cover the first surface of the first substrate, the second surface of the second substrate, the driver chip, the power chip, and the conductive components. Alternatively, the package can cover the second surface and side surfaces of the second substrate. Or, the package can encapsulate the space between the first and second substrates. The driver chip, the first power chip, and the conductive components are all encapsulated within the package, resulting in a sealed power structure. For example, this power structure can be a three-dimensional, highly sealed package structure with two substrates interconnected by conductive components.

[0146] In some embodiments of this application, the conductive component connects the first substrate and the second substrate. Additionally, the conductive component also provides support for the substrate, and is located between the first surface and the second surface. The conductive component can be a conductive pillar located between the first surface and the second surface. In these embodiments, the conductive component not only conducts electricity but also provides support, allowing the power chip and the driver chip to be disposed in the space between the first substrate and the second substrate. Furthermore, the power structure also includes electronic components, which can also be disposed in the space between the first substrate and the second substrate.

[0147] In some embodiments of this application, the power structure further includes solder, wherein a first end is soldered to a first surface, and a second end is soldered to a second surface. For ease of description and illustration, depending on the location of the solder application, they are referred to as the first solder and the second solder, respectively. Figure 4 As shown, the first end is connected to the first surface via a first solder, and the second end is connected to the second surface via a second solder. Therefore, the conductive component can be connected to the first substrate and the second substrate via solder. By using solder, the conductive component can be fixed together with the first substrate and the second substrate, thereby forming a space between the first substrate and the second substrate.

[0148] In some embodiments of this application, the power structure further includes electronic components, wherein the electronic components are disposed on a first surface of a first substrate and / or a second surface of a second substrate. For ease of description and illustration, depending on the distribution and connection relationship of the electronic components, they are referred to as a first electronic component, a second electronic component, and a third electronic component, etc. For example, the electronic component is specifically a first electronic component, such as... Figure 5 As shown, the power structure also includes: a first electronic component, wherein,

[0149] The first electronic component is disposed on the first surface and faces the second surface.

[0150] In this embodiment, the first electronic component can be disposed side-by-side with the driver chip on the first surface of the first substrate. The first electronic component can also be disposed in the space between the first and second substrates. Furthermore, the first electronic component and the first power chip can be distributed on different planes, thus the power structure is a three-dimensional structure, which is beneficial for miniaturization design. The number of first electronic components is not limited in this embodiment.

[0151] It should be noted that when the power structure also includes a first electronic component, the package covers the first surface of the first substrate, the second substrate, the driver chip, the first power chip, the conductive component, and the first electronic component.

[0152] In some embodiments of this application, such as Figure 6 As shown, the power structure includes four first electronic components as an example. The four first electronic components can be arranged side by side with the driver chip. There is no limitation on the distribution of the four first electronic components on the first surface of the first substrate. In addition, there is no limitation on the type of the four first electronic components.

[0153] It should be noted that when the power structure also includes four first electronic components, the package covers the first surface of the first substrate, the second substrate, the driver chip, the first power chip, the conductive component, and the four first electronic components.

[0154] In some embodiments of this application, such as Figure 7 As shown, the power structure also includes: a second electronic component, wherein,

[0155] The second electronic component is disposed on the second surface and faces the first surface.

[0156] In this embodiment, the second electronic component can be disposed side-by-side with the first power chip on the second surface of the second substrate. The second electronic component can be located in the space between the first and second substrates, and it can be distributed on different planes from the driving chip. Therefore, the power structure is a three-dimensional structure, which is beneficial for miniaturization design. The number of second electronic components is not limited in this embodiment.

[0157] It should be noted that when the power structure also includes a second electronic component, the package covers the first surface of the first substrate, the second substrate, the driver chip, the first power chip, the conductive component, and the second electronic component.

[0158] It should be noted that, Figure 7 and Figure 5 The difference lies in the different locations of the electronic components. For example, the first electronic component is located on the first substrate, while the second electronic component is located in the second substrate.

[0159] In some embodiments of this application, such as Figure 8 As shown, the power structure includes four second electronic components as an example. The four second electronic components can be arranged side by side with the driver chip. There is no limitation on the distribution of the four second electronic components on the second surface of the second substrate. In addition, there is no limitation on the type of the four second electronic components.

[0160] It should be noted that when the power structure also includes four second electronic components, the package covers the first surface of the first substrate, the second substrate, the driver chip, the first power chip, the conductive component, and the four second electronic components.

[0161] In some embodiments of this application, such as Figure 9 As shown, the second substrate can be a substrate with heat dissipation function, such as a DBC (Digital Curve Block), which includes a ceramic layer and a copper layer. The ceramic layer can be encapsulated by a package, while the surface of the copper layer is not encapsulated by a package; therefore, the DBC can achieve heat dissipation.

[0162] In some embodiments of this application, such as Figure 10 As shown, the power structure also includes a heat dissipation module, wherein,

[0163] The heat dissipation module is located on the back side of the second surface of the second substrate.

[0164] For example, the second substrate has a third surface. The second and third surfaces of the second substrate are opposite surfaces, and the third surface is the reverse side of the second substrate. For example, the third surface is used to mount a heat dissipation module. The first power chip and the heat dissipation module are respectively mounted on different surfaces of the second substrate. The first power chip is encapsulated by a package, but the heat dissipation module is not encapsulated by a package. Therefore, the heat dissipation module can be used to dissipate heat from the power structure. For example, the power structure can be a three-dimensional high-density, high-thermal-conductivity package structure in which two substrates are interconnected by conductive components.

[0165] In some embodiments of this application, such as Figure 11 As shown, the power structure also includes: pads, wherein,

[0166] The pads are located on the fourth surface of the first substrate.

[0167] The fourth surface is the back side of the first surface.

[0168] In this embodiment, the fourth surface of the first substrate and the first surface are opposite to each other; the fourth surface is the reverse side of the first substrate, and for example, it is used to set pads. The driver chip and the pads are respectively disposed on different surfaces of the first substrate. The driver chip is encapsulated by a package, but the pads are not encapsulated by a package. These pads can be used for electrical connection between the power structure and other external devices. In this embodiment, the distribution position and number of pads on the fourth surface are not limited.

[0169] In some embodiments of this application, the driver chip may be embedded within the first substrate. For example, as... Figure 12 As shown, the first substrate is a first embedded substrate, wherein,

[0170] A driver chip is disposed within the first embedded substrate.

[0171] Among them, such as Figure 12 As shown, the driver chip is embedded in the first embedded substrate. Therefore, only the first power chip and conductive components need to be set between the first embedded substrate and the second substrate, which can further reduce the volume of the power structure and is conducive to the miniaturization design of the power structure.

[0172] In some embodiments of this application, the power chip may be embedded within the first substrate. For example, as... Figure 13 As shown, the power structure also includes: a second power chip.

[0173] The first substrate is a second embedded substrate, wherein...

[0174] A second power chip is disposed within the second embedded substrate.

[0175] Among them, such as Figure 13 As shown, the driver chip can be disposed on the first surface of the second embedded substrate, and the second power chip is disposed inside the second embedded substrate. Therefore, only the first power chip, conductive components and driver chip need to be disposed between the second embedded substrate and the second substrate, which can further reduce the volume of the power structure and is conducive to the miniaturization design of the power structure.

[0176] It should be noted that, Figure 12 and Figure 13 The difference lies in the type of units embedded in the embedded substrate. For example... Figure 12 A driver chip is disposed within the first embedded substrate. Figure 13 A second power chip is disposed within the second embedded substrate. It is not limited to this; a driver chip and a second power chip may also be embedded simultaneously within the embedded substrate of the power structure. This is not a limitation here.

[0177] In some embodiments of this application, electronic components may be embedded within a first substrate. For example, such as... Figure 14 As shown, the power structure also includes: a third electronic component,

[0178] The first substrate is a third embedded substrate, wherein...

[0179] A third electronic component is disposed within the third embedded substrate.

[0180] Among them, such as Figure 14 As shown, the driver chip can be disposed on the first surface of the third embedded substrate, and a third electronic component is disposed within the third embedded substrate. Therefore, only the first power chip, conductive component and driver chip need to be disposed between the third embedded substrate and the second substrate, which can further reduce the volume of the power structure and is conducive to the miniaturization design of the power structure.

[0181] It should be noted that, Figure 13 and Figure 14 The difference lies in the type of units embedded in the embedded substrate. For example... Figure 13 A second power chip is disposed within the second embedded substrate. Figure 14 A third electronic component is disposed within the third embedded substrate. It is not limited to this; a second power chip and a third electronic component may also be embedded simultaneously within the embedded substrate of the power structure. This is not a limitation here.

[0182] In some embodiments of this application, such as Figure 15 As shown, the power architecture also includes a third power chip, wherein,

[0183] The third power chip is located on the first surface and faces the second surface.

[0184] The power structure may include multiple power chips, such as a first power chip and a third power chip. The first power chip is disposed on a second substrate, and the third power chip is disposed on a first substrate. The third power chip may be disposed side by side with the driver chip on a first surface of the first substrate. The third power chip may be disposed in the space between the first and second substrates. The third power chip and the first power chip may be distributed on different planes. Therefore, the power structure is a three-dimensional structure, which is beneficial for the miniaturization design of the power structure.

[0185] The foregoing embodiments described the power structure. Next, this application describes an alternating current module provided in its embodiments, which includes: based on... Figures 1 to 15 The power structure shown is illustrated. This alternating current module has the advantages of small size, high integration, and small parasitic parameters.

[0186] The following describes an energy device provided by an embodiment of this application, which includes: based on... Figures 1 to 15 The power structure shown;

[0187] or,

[0188] The energy device includes the aforementioned alternating current module.

[0189] This energy device has the advantages of small size, high integration, and low parasitic parameters.

[0190] The following describes a radio frequency (RF) remote unit provided in an embodiment of this application. This RF remote unit includes the aforementioned alternating current module. This RF remote unit has the advantages of small size, high integration, and low parasitic parameters.

[0191] As illustrated by the foregoing embodiments, the first substrate has a first surface, and the second substrate has a second surface. The first and second surfaces are disposed opposite to each other. The power chip is disposed on the second substrate, thus positioned between the first and second substrates. Additionally, the driver chip is disposed on the first substrate. Therefore, the power chip and driver chip are disposed on two substrates, forming a stacked structure based on the two substrates, which improves the integration of the power structure. The conductive component has a first end and a second end. The first end is connected to the first surface, and the second end is connected to the second surface. This conductive component can connect the first and second substrates, conducting electricity between them. This enables electrical transmission between the first and second substrates, reducing parasitic parameters of the power structure and meeting the needs of high-frequency, high-power applications.

[0192] The power structure described above will be illustrated with examples from actual application scenarios.

[0193] The power structure provided in this application embodiment can be applied to wireless 5G enhanced mass multiple-input multiple-output (MMO) products, improving the packaging integration of the power structure while solving the problems of heat dissipation and large parasitic parameters of high-frequency high-power devices.

[0194] The power structure provided in this application is a three-dimensional high-density, high-thermal-conductivity packaging structure that interconnects two substrates using conductive components. It stacks and encapsulates multiple chips, improving the packaging integration. The interconnected structure reduces the signal transmission path. The upper substrate of the stacked structure is designed with a heat dissipation structure, making it suitable for high-frequency, high-power applications.

[0195] like Figure 16 and Figure 17As shown, the power structure in this embodiment includes: a lower substrate with circuitry, an upper substrate with heat dissipation, a driver chip (or a driver function chip), a power chip, and conductive pillars. Optionally, the power structure may also include other necessary electronic components and a package.

[0196] Specifically, such as Figure 16 As shown, multiple chips are assembled on the upper substrate. Figure 17 As shown, a driver chip is mounted on one side of the lower substrate, as follows. Figure 11 As shown, the other side of the lower substrate has solder pads to enable electrical connections between the power structure and other components, allowing other components to be assembled on the upper and lower substrates as needed. Figure 1 As shown, conductive pillars are used to interconnect the upper and lower substrates, which have heat dissipation functions. Electrical transmission of the chips on the upper substrate is achieved through the conductive pillars, and after molding, a three-dimensional multi-chip stacking and encapsulation is completed.

[0197] The upper substrate has a heat dissipation function, providing a heat dissipation channel for the power chips assembled on it. The interconnection of the upper and lower substrates using conductive pillars shortens the transmission path of each signal, reduces parasitic parameters in high-frequency applications, and the stacked power structure also improves the integration of the package.

[0198] The upper and lower substrates are assembled using conductive pillars via an inverted design. The manufacturing process for this packaging method includes three main parts: the individual assembly of the upper and lower substrates and the assembly of the two substrates. The assembly of the upper and lower substrates is completed using interconnection processes such as die attach, wire bonding, and surface mount technology (SMT) to assemble the chips, components, and substrates. The assembly of the two substrates achieves electrical connection between the upper and lower substrates through conductive pillars (such as copper pillars) and interconnection structures (such as solder). Finally, a molding process is performed to form a power structure.

[0199] like Figure 10 As shown, a heat dissipation module can be assembled on the upper substrate to improve heat dissipation.

[0200] like Figure 12 and Figure 13 As shown, to further improve the packaging integration, the lower substrate can be a substrate with embedded chips or other electronic components.

[0201] In this embodiment, the power structure is a multi-chip stacked dual-substrate three-dimensional packaging structure, which improves packaging density and reduces packaging size. The upper substrate with heat dissipation function provides a good heat dissipation channel, solving the difficulty of heat dissipation in three-dimensional packaging; the stacked packaging structure reduces parasitic parameters, expands its application in the high-frequency field, and the upper substrate has no direct signal transmission with the outside world, thus providing electrical isolation.

[0202] This application also provides a power structure, which includes: a first substrate, a second substrate, a driver chip, a power chip, and conductive components, wherein...

[0203] The first surface of the first substrate and the second surface of the second substrate are disposed opposite to each other;

[0204] The first end of the conductive component is connected to the first surface, and the second end of the conductive component is connected to the second surface;

[0205] The power chip is disposed on the second substrate;

[0206] The driver chip is disposed on the second substrate.

[0207] The driver chip can be disposed on the second substrate, for example, the driver chip is located on the second surface and faces the first surface.

[0208] As illustrated by the foregoing embodiments, the power structure includes: a first substrate, a second substrate, a driver chip, a power chip, and conductive components. The second substrate has a second surface, and the power chip is located on the second surface, facing the first surface, thus positioning the power chip between the first and second substrates. The driver chip is also disposed on the second substrate, improving the integration of the power structure. The conductive component has a first end and a second end, with the first end connected to the first surface and the second end connected to the second surface. This conductive component connects the first and second substrates, conducting electricity between them, thereby enabling electrical transmission between the first and second substrates, reducing parasitic parameters of the power structure, and meeting the needs of high-frequency, high-power applications.

[0209] The foregoing embodiments described one power structure provided by the present application. The following describes another power structure provided by the present application, such as... Figure 18 As shown, the power structure includes: a first substrate, a second substrate, a driver chip, a power chip, conductive lines, a first package, and an adhesive mold, wherein...

[0210] The power chip is located on the second surface of the second substrate;

[0211] The second surface and the first power chip are packaged using a first package;

[0212] The first substrate is adhered to the first package body using an adhesive mold;

[0213] Conductive lines are used to connect the first substrate and the second substrate;

[0214] The driver chip is mounted on the first substrate.

[0215] In some embodiments of this application, the power structure further includes a conductive component, wherein a first end of the conductive component is connected to a second surface of the second substrate. The connection between the first end of the conductive component and the second surface of the second substrate allows the second substrate to output electrical signals via the conductive component.

[0216] In some embodiments of this application, in order to distinguish the multiple power chips in the embodiments of this application, the power chip in "the power chip is located on the second surface of the second substrate" is referred to as the first power chip. For example, the first power chip is located on the second surface.

[0217] in, Figure 18 A certain space exists between the first substrate and the second substrate. The conductive component provides conductivity. The first surface is the surface of the first substrate furthest from the first package, for example, the first surface of the first substrate faces downwards. The fourth surface is the surface of the first substrate closest to the first package, for example, the fourth surface of the fourth substrate faces upwards. The second surface of the second substrate is the main surface for mounting the chip, for example, the second surface of the second substrate faces downwards. A space exists between the fourth surface and the second surface. The first power chip is disposed between the first substrate and the second substrate, and the first substrate and the first power chip are fixed together. There are various ways to fix the first substrate and the first power chip, such as directly fixing them together, or packaging the first power chip first and then fixing it to the first substrate. For example, the first power chip can be connected to the second substrate using solder. The conductive component allows for conductivity between the first substrate and the second substrate. Figure 18 In the power structure shown, the driver chip and the first power chip are disposed on different planes, and the power structure is a three-dimensional structure. Conductive components can connect the first substrate and the second substrate, thereby reducing the transmission path between the first substrate and the second substrate and reducing the parasitic parameters of the power structure. Based on Figure 18 The power structure shown can achieve miniaturization and high integration of power structure devices.

[0218] In this embodiment, a first package covers the second surface of the second substrate and the first power chip. The packaging process of the first package can be the same as or different from that of the aforementioned second package. After the first power chip on the second surface of the second substrate is packaged, the first package is obtained. The first substrate is adhered to the first package by an adhesive mold. Therefore, the first substrate can be fixed together with the first power chip by the first package and the adhesive mold. The material and thickness of the adhesive mold are not limited.

[0219] It should be noted that the embodiments of this application do not limit the number and distribution of conductive components in the power structure, the number and distribution of driving chips in the power structure, or the number and distribution of the first power chip in the power structure. The specific details can be determined in conjunction with the application scenario. This is only an example for illustration.

[0220] In some embodiments of this application, such as Figure 19 As shown, the power structure further includes: a second package, wherein the second package covers the first substrate, the second surface of the second substrate, the driver chip, and the power chip.

[0221] In some embodiments of this application, such as Figure 20 As shown, the power structure further includes a conductive component, wherein a first end of the conductive component is connected to a second surface of the second substrate.

[0222] A second package covers the first substrate, the second surface of the second substrate, the driver chip, the power chip, and the conductive component. The second end of the conductive component is exposed within the second package.

[0223] The second package encapsulates the internal structure of the power structure. For example, the second package encapsulates the first substrate, the second surface of the second substrate, the driver chip, the first power chip, and the conductive lines, thus obtaining the encapsulated power structure. Alternatively, the second package can encapsulate the space between the first and second substrates. The first power chip and the conductive lines are both encapsulated within the second package, resulting in a sealed power structure. For instance, the power structure can be a three-dimensional, highly sealed package structure with conductive components interconnecting the two substrates. After encapsulation by the second package, the ends of the conductive components are exposed within the second package, allowing them to be used for electrical connections between the power structure and external devices.

[0224] Figure 20 Taking the power structure including two conductive components as an example, it is not limited to the number of conductive components, which can be one or more.

[0225] In some embodiments of this application, the power structure further includes electronic components, wherein the electronic components are disposed on a first surface of a first substrate and / or a second surface of a second substrate. For ease of description and illustration, depending on the distribution and connection relationship of the electronic components, they are referred to as a first electronic component, a second electronic component, and a third electronic component, etc. For example, the electronic component is specifically a first electronic component, such as... Figure 21 As shown, the power structure also includes: a first electronic component, wherein,

[0226] The first electronic component is disposed on the fourth surface and faces the second surface.

[0227] In this embodiment, a first electronic component is disposed on the fourth surface of the first substrate, and a driving chip is disposed on the first surface of the first substrate. The first electronic component can be disposed in the space between the first substrate and the second substrate. The first electronic component and the first power chip can be distributed on different planes, thus the power structure is a three-dimensional structure, which is beneficial for the miniaturization design of the power structure. The number of first electronic components is not limited in this embodiment.

[0228] It should be noted that when the power structure also includes the first electronic component, the second package covers the first substrate, the second surface, the driver chip, the first power chip, the conductive line, the conductive component, and the first electronic component.

[0229] In some embodiments of this application, the driver chip is disposed on a first surface of the first substrate or embedded within the first substrate; the power chip is disposed on a second surface of the second substrate. For example, the driver chip is located on the first surface and faces the second surface. The first surface is the surface of the first substrate away from the first package. In the above scheme, the driver chip and the power chip are disposed between the first substrate and the second substrate, and the driver chip and the power chip are disposed on different planes, and the power structure is a three-dimensional structure. This allows for the miniaturization and high integration of the power structure.

[0230] In one possible implementation, the driver chip is disposed on the second surface of the second substrate; the power chip is disposed on the second surface of the second substrate. In the above scheme, the power structure includes multiple driver chips, some disposed on the first substrate and some on the second substrate, with the driver chips and power chips disposed between the first and second substrates. The driver chips and power chips are disposed on different planes, and the power structure is a three-dimensional structure. This allows for the miniaturization and high integration of the power structure.

[0231] like Figure 22 As shown, the power structure also includes: a second electronic component, wherein,

[0232] The second electronic component is disposed on the second surface and faces the fourth surface.

[0233] In this embodiment, the second electronic component can be disposed side-by-side with the first power chip on the second surface of the second substrate. The second electronic component can be located in the space between the first and second substrates, and it can be distributed on different planes from the driving chip. Therefore, the power structure is a three-dimensional structure, which is beneficial for miniaturization design. The number of second electronic components is not limited in this embodiment.

[0234] It should be noted that when the power structure also includes a second electronic component, the second package covers the first substrate, the second surface, the driver chip, the first power chip, the conductive component, and the second electronic component.

[0235] In some embodiments of this application, such as Figure 23 As shown, the power structure also includes a heat dissipation module, wherein,

[0236] The heat dissipation module is located on the back side of the second surface of the second substrate.

[0237] For example, the second substrate has a third surface. The second and third surfaces of the second substrate are opposite surfaces, and the third surface is the reverse side of the second substrate. For example, the third surface is used to mount a heat dissipation module. The first power chip and the heat dissipation module are respectively mounted on different surfaces of the second substrate. The first power chip is encapsulated by a package, but the heat dissipation module is not encapsulated by a package. Therefore, the heat dissipation module can be used to dissipate heat from the power structure. For example, the power structure can be a three-dimensional high-density, high-thermal-conductivity package structure in which two substrates are interconnected by conductive components.

[0238] In some embodiments of this application, the driver chip may be embedded within the first substrate. For example, as... Figure 24 As shown, the first substrate is a first embedded substrate, wherein,

[0239] A driver chip is disposed within the first embedded substrate.

[0240] Among them, such as Figure 24 As shown, the driver chip is embedded in the first embedded substrate. Therefore, only the first power chip and conductive components need to be set between the first embedded substrate and the second substrate, which can further reduce the volume of the power structure and is conducive to the miniaturization design of the power structure.

[0241] In some embodiments of this application, the power chip may be embedded within the first substrate. For example, as... Figure 25 As shown, the power structure also includes: a second power chip.

[0242] The first substrate is a second embedded substrate, wherein...

[0243] A second power chip is disposed within the second embedded substrate.

[0244] Among them, such as Figure 25 As shown, the driver chip can be disposed on the first surface of the second embedded substrate, and the second power chip is disposed inside the second embedded substrate. Therefore, only the first power chip and conductive components need to be disposed between the second embedded substrate and the second substrate, which can further reduce the volume of the power structure and is beneficial to the miniaturization design of the power structure.

[0245] It should be noted that, Figure 25 and Figure 24 The difference lies in the type of units embedded in the embedded substrate. For example... Figure 24 A driver chip is disposed within the first embedded substrate. Figure 25 A second power chip is disposed within the second embedded substrate. It is not limited to this; a driver chip and a second power chip may also be embedded simultaneously within the embedded substrate of the power structure. This is not a limitation here.

[0246] In some embodiments of this application, electronic components may be embedded within a first substrate. For example, such as... Figure 26 As shown, the power structure also includes: a third electronic component,

[0247] The first substrate is a third embedded substrate, wherein...

[0248] A third electronic component is disposed within the third embedded substrate.

[0249] Among them, such as Figure 26 As shown, the driver chip can be disposed on the first surface of the third embedded substrate, and a third electronic component is disposed within the third embedded substrate. Therefore, only the first power chip and conductive components need to be disposed between the third embedded substrate and the second substrate, which can further reduce the volume of the power structure and is beneficial to the miniaturization design of the power structure.

[0250] It should be noted that, Figure 25 and Figure 26 The difference lies in the type of units embedded in the embedded substrate. For example... Figure 25 A second power chip is disposed within the second embedded substrate. Figure 26 A third electronic component is disposed within the third embedded substrate. It is not limited to this; a second power chip and a third electronic component may also be embedded simultaneously within the embedded substrate of the power structure. This is not a limitation here.

[0251] In some embodiments of this application, such as Figure 27 As shown, the power structure also includes: a fourth electronic component, wherein,

[0252] The fourth electronic component is disposed on the first surface of the first substrate.

[0253] In this design, the fourth surface of the first substrate and the first surface are opposite to each other, with the first surface being the reverse side of the first substrate. For example, the fourth surface is used to mount the fourth electronic component. The fourth electronic component can be mounted on the first surface of the first substrate. Since the fourth electronic component and the first power chip are distributed on different planes, the power structure is a three-dimensional structure, which is beneficial for the miniaturization design of the power structure.

[0254] In some embodiments of this application, such as Figure 27 As shown, the driver chip is located on the first surface of the first substrate.

[0255] In this design, the fourth surface and the first surface of the first substrate are two opposing surfaces. The driving chip can be disposed on the first surface of the first substrate. The driving chip and the first power chip are distributed on different planes. Therefore, the power structure is a three-dimensional structure, which is beneficial for the miniaturization design of the power structure.

[0256] In some embodiments of this application, such as Figure 28 As shown, the power architecture also includes a third power chip, wherein,

[0257] The third power chip is located on the fourth surface and faces the second surface.

[0258] The power structure may include multiple power chips. For example, the power structure may include a first power chip and a third power chip. The first power chip is disposed on a second substrate, and the third power chip is disposed on a first substrate. The third power chip is disposed on a fourth surface of the first substrate. The third power chip may be disposed in the space between the first substrate and the second substrate. The third power chip and the first power chip may be distributed on different planes. Therefore, the power structure is a three-dimensional structure, which is beneficial for the miniaturization design of the power structure.

[0259] The foregoing embodiments described the power structure. Next, this application describes an alternating current module provided in its embodiments, which includes: based on... Figures 18 to 28 The power structure shown is illustrated. This alternating current module has the advantages of small size, high integration, and small parasitic parameters.

[0260] The following describes an energy device provided by an embodiment of this application, which includes: based on... Figures 18 to 28 The power structure shown;

[0261] Alternatively, the energy device may include the aforementioned alternating current module.

[0262] This energy device has the advantages of small size, high integration, and low parasitic parameters.

[0263] The following describes a radio frequency (RF) remote unit provided in an embodiment of this application. This RF remote unit includes the aforementioned alternating current module. This RF remote unit has the advantages of small size, high integration, and low parasitic parameters.

[0264] As illustrated by the foregoing embodiments, the second substrate has a second surface, on which the power chip is located. The first substrate is adhered to the first package via an adhesive mold, thus placing the power chip between the first and second substrates. Additionally, the driver chip is disposed on the first substrate. Therefore, the power chip and driver chip are mounted on two substrates, forming a stacked structure based on the two substrates, which improves the integration of the power structure. The two ends of the conductive lines are connected to the first and second substrates respectively, enabling electrical transmission between them, reducing parasitic parameters of the power structure, and meeting the requirements of high-frequency, high-power applications.

[0265] The preparation process will be described next. Figures 18 to 28 The method of the power structure shown, such as Figure 29 As shown, this method mainly includes the following steps:

[0266] S01. Place the power chip on the second surface of the second substrate;

[0267] S02. The first package is wrapped around the second surface of the second substrate and the power chip;

[0268] S03. The first substrate is attached to the first package body using an adhesive mold;

[0269] S04. Place the driver chip on the first substrate;

[0270] S05. Connect one end of the conductive wire to the first substrate and the other end of the conductive wire to the second substrate.

[0271] In some embodiments of this application, the method further includes:

[0272] The first end of the conductive component is connected to the second surface of the second substrate.

[0273] In some embodiments of this application, the method further includes:

[0274] The second package is wrapped around the first substrate, the second surface of the second substrate, the driver chip, the power chip, and the conductive components.

[0275] The second end of the conductive component is exposed in the second package.

[0276] In some embodiments of this application, the driver chip is placed on the first substrate, including:

[0277] The driver chip is disposed on the first surface of the first substrate, or embedded within the first substrate;

[0278] Placing the power chip on the second surface of the second substrate includes:

[0279] The power chip is disposed on the second surface of the second substrate.

[0280] In some embodiments of this application, the method further includes:

[0281] Electronic components are placed on the first surface of the first substrate and / or the second surface of the second substrate.

[0282] Wherein, the first surface is the surface of the first substrate that is away from the first package.

[0283] In some embodiments of this application, the heat dissipation module is placed on the back side of the second surface of the second substrate.

[0284] Understandable Figure 29 The method shown can be used to prepare Figures 18 to 28 The power structure shown in the embodiments of this application is described in detail in the foregoing embodiments, and will not be repeated in the method embodiments here.

[0285] As illustrated by the foregoing embodiments, the second substrate has a second surface, on which the power chip is located. The first substrate is adhered to the first package via an adhesive mold, thus placing the power chip between the first and second substrates. Additionally, the driver chip is disposed on the first substrate. Therefore, the power chip and driver chip are mounted on two substrates, forming a stacked structure based on the two substrates, which improves the integration of the power structure. The two ends of the conductive lines are connected to the first and second substrates respectively, enabling electrical transmission between them, reducing parasitic parameters of the power structure, and meeting the requirements of high-frequency, high-power applications.

[0286] The power structure described above will be illustrated with examples from actual application scenarios.

[0287] The power structure provided in this application embodiment can be applied to wireless 5G enhanced mass multiple-input multiple-output (MMO) products, improving the packaging integration of the power structure while solving the problems of heat dissipation and large parasitic parameters of high-frequency high-power devices.

[0288] The power structure provided in this application is a three-dimensional high-density, high-thermal-conductivity packaging structure that interconnects two substrates using conductive components. It stacks and encapsulates multiple chips, improving the packaging integration. The interconnected structure reduces the signal transmission path. The upper substrate of the stacked structure is designed with a heat dissipation structure, making it suitable for high-frequency, high-power applications.

[0289] like Figure 30 and Figure 31As shown, the power structure in this embodiment includes: a lower substrate with circuitry, an upper substrate with heat dissipation, a driver chip (or a driver function chip), a power chip, and conductive lines. Optionally, the power structure may further include: other necessary electronic components, a second package, a first package, and conductive parts.

[0290] As mentioned above Figure 16 , Figure 17 Compared to the embodiments, such as Figure 30 As shown, this embodiment changes the dual-substrate inverted packaging mode, stacking and assembling the substrates, with the power chip mounted on the upper substrate that has a heat dissipation function. Then, the power chip portion is molded to obtain the first package, as shown... Figure 31 As shown. An adhesive film is then adhered to the surface of the first package, and the lower substrate with the driver chip mounted on it is assembled onto the first package. Electrical interconnection processes are completed as needed, and finally, a second package is used for encapsulation to obtain... Figure 18 The power structure shown. The conductive components assembled on the upper substrate are used for signal transmission of the power chip, and the conductive components exposed after molding are used for electrical interconnection between the power structure and the outside.

[0291] In the embodiments of the application, the power structure is a multi-chip stacked dual-substrate three-dimensional packaging structure, which improves packaging density and reduces packaging size. The upper substrate with heat dissipation function provides a good heat dissipation channel, solving the difficulty of heat dissipation in three-dimensional packaging; the stacked packaging structure reduces parasitic parameters, expands its application in the high-frequency field, and the upper substrate has no direct signal transmission with the outside world, thus providing electrical isolation.

[0292] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0293] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0294] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0295] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

Claims

1. A power structure, characterized by, The power structure comprises a first substrate, a second substrate, a driving chip, a power chip and a conductive component, wherein a first surface of the first substrate and a second surface of the second substrate are oppositely arranged; a first end of the conductive component is connected with the first surface, and a second end of the conductive component is connected with the second surface; the driving chip is arranged on the first substrate; the power chip is arranged on the second substrate; the second substrate is a substrate with a heat dissipation function; wherein the heat dissipation function comprises that the second substrate is a ceramic copper clad plate; or the heat dissipation function comprises a heat dissipation module arranged on the second substrate.

2. The power structure of claim 1, wherein, The power structure further comprises a packaging body, the packaging body being wrapped on the first surface of the first substrate, the second substrate, the driving chip, the power chip and the conductive component.

3. The power structure according to claim 1 or 2, wherein the driving chip is arranged on the first surface of the first substrate or embedded in the first substrate; the power chip is arranged on the second surface of the second substrate.

4. The power structure of any one of claims 1 to 2, wherein, the first end is welded with the first surface, and the second end is welded with the second surface.

5. The power structure of any one of claims 1 to 2, wherein, The power structure further comprises an electronic element, wherein the electronic element is arranged on the first surface of the first substrate and / or the second surface of the second substrate.

6. The power structure of any one of claims 1 to 2, wherein, the heat dissipation module is arranged on the back surface of the second surface of the second substrate.

7. A power structure body, characterized by, The power structure comprises a first substrate, a second substrate, a driving chip, a power chip, a conductive wire, a first packaging body and an adhesive module, wherein the power chip is located on the second surface of the second substrate; the first packaging body is wrapped on the second surface of the second substrate and the power chip; the first substrate is pasted on the first packaging body through the adhesive module; the driving chip is arranged on the first substrate; one end of the conductive wire is connected with the first substrate, and the other end of the conductive wire is connected with the second substrate; the second substrate is a substrate with a heat dissipation function; wherein the heat dissipation function comprises that the second substrate is a ceramic copper clad plate; or the heat dissipation function comprises a heat dissipation module arranged on the second substrate.

8. The power structure of claim 7, wherein, The power structure further comprises a conductive component, wherein a first end of the conductive component is connected with the second surface of the second substrate.

9. The power structure of claim 8, wherein, The power structure further comprises a second packaging body, wherein the second packaging body is wrapped on the first substrate, the second surface of the second substrate, the driving chip, the power chip and the conductive component, wherein a second end of the conductive component is exposed from the second packaging body.

10. The power structure according to any one of claims 7 to 9, wherein the driving chip is arranged on the first surface of the first substrate or embedded in the first substrate; the power chip is arranged on the second surface of the second substrate.

11. The power structure of any one of claims 7 to 9, wherein, The power structure further comprises an electronic element, wherein the electronic element is arranged on the first surface of the first substrate and / or the second surface of the second substrate, The first surface is a surface of the first substrate away from the first package.

12. The power structure of any one of claims 7 to 9, wherein, The heat dissipation module is disposed on a back surface of the second surface of the second substrate.

13. A method for producing a power structure body, characterized by The method comprises: placing the power chip on the second surface of the second substrate; encapsulating the first package on the second surface of the second substrate and the power chip; adhering the first substrate to the first package by the adhesive module; placing the driving chip on the first substrate; connecting one end of the conductive wire to the first substrate, and connecting the other end of the conductive wire to the second substrate; The second substrate is a substrate with a heat dissipation function; wherein, The heat dissipation function comprises that the second substrate is a ceramic copper-clad plate; or, The heat dissipation function comprises a heat dissipation module disposed on the second substrate.

14. The method of claim 13, wherein, The method further comprises: connecting the first end of the conductive component to the second surface of the second substrate.

15. The method of claim 14, wherein, The method further comprises: encapsulating the second package on the first substrate, the second surface of the second substrate, the driving chip, the power chip and the conductive component, wherein the second end of the conductive component is exposed from the second package.

16. The method according to any one of claims 13 to 15, characterized in that, The method further comprises: placing the driving chip on the first substrate, comprising: disposing the driving chip on the first surface of the first substrate, or embedding the driving chip in the first substrate; The method further comprises:

17. The method according to any one of claims 13 to 15, characterized in that, placing the power chip on the second surface of the second substrate, comprising: disposing the power chip on the second surface of the second substrate. The method further comprises:

18. The method of any one of claims 13-15, wherein, placing electronic components on the first surface of the first substrate and / or the second surface of the second substrate, wherein the first surface is a surface of the first substrate away from the first package.

19. An alternating current module, comprising: The method further comprises:

20. An energy device, comprising: placing the heat dissipation module on the back surface of the second surface of the second substrate. The alternating current module comprises: the power structure body according to any one of claims 1 to 6, or the power structure body according to any one of claims 7 to 12. The energy device comprises: the power structure body according to any one of claims 1 to 6, or the power structure body according to any one of claims 7 to 12.

21. A radio remote unit, characterized by: Alternatively, The energy device comprises the alternating current module according to claim 19. The radio frequency remote unit comprises the alternating current module according to claim 19.

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