Memory system and method of operating the same

Abstract

An operating method of a memory system including a non-volatile memory device, the non-volatile memory device including a plurality of blocks, the operating method including: randomly storing valid data in the plurality of blocks; entering a useless data collection mode; reducing the update frequency of the plurality of mapping tables during the useless data collection operation by simultaneously copying valid data randomly stored in two or more source blocks selected from the plurality of blocks and mapped to a single mapping table in the plurality of mapping tables to a target block in the useless data collection operation; updating the changed mapping information in the single mapping table in a meta area of ​​the non-volatile memory device according to the copying result; and generating a free block by erasing the two or more source blocks.

Description

[0001] This application is a divisional application of the following application: Application number: 201610842112.0, Application date: September 22, 2016, Invention name: Memory controller, non-volatile memory system and operating method thereof. Technical Field

[0002] The inventive concept relates to a nonvolatile memory system, and more particularly, to a memory system capable of performing a garbage collection operation and an operating method thereof. Background Art

[0003] Memory systems, for example, flash memory systems are widely used as non-volatile memory devices in Universal Serial Bus (USB) drives, digital cameras, mobile phones, smart phones, tablet personal computers (PC) memory cards, and solid-state drives (SSDs). In flash memory devices, write / read units and erase units may be different from each other, and thus memory operations may be managed by a flash translation layer (FTL), which may include firmware.

[0004] In a flash memory system, data may be written to an erased block (e.g., a free block), and a garbage collection operation may be performed to ensure one or more free blocks. Since data may be transferred according to the execution of the garbage collection operation, the address mapping information of the data may be changed, and a specific area of ​​the memory system may be frequently updated or the amount of metadata written may be increased during the process of updating its mapping information. This may increase the waiting period required to complete the garbage collection, and may also shorten the effective life of the memory system. Summary of the invention

[0005] According to one aspect of the present invention, there is provided an operating method of a memory system including a non-volatile memory device, the non-volatile memory device including a plurality of blocks, the operating method comprising: randomly storing valid data in the plurality of blocks; entering a useless data collection mode; in the useless data collection mode, by simultaneously copying valid data of a single mapping table randomly stored in two or more source blocks selected from the plurality of blocks and mapped to a plurality of mapping tables to a target block in the useless data collection operation, thereby reducing the update frequency of the plurality of mapping tables during the useless data collection operation; updating the changed mapping information in the single mapping table in a meta area of ​​the non-volatile memory device according to the copying result; and generating a free block by erasing the two or more source blocks.

[0006] According to one aspect of the present invention, there is provided an operating method for a memory system including a memory controller and a non-volatile memory device, the operating method comprising: randomly storing valid data in a source block of the non-volatile memory device; selecting the source block of the non-volatile memory device for useless data collection by the memory controller in a simultaneous useless data collection operation; reducing the update frequency of multiple mapping tables during the useless data collection operation by simultaneously copying valid data of a single mapping table randomly stored in the source block and mapped to multiple mapping tables to a target block in the simultaneous useless data collection operation; storing changed mapping information in an update cache of the memory controller in response to valid data being copied from the source block to the target block in the simultaneous useless data collection operation; and updating the single mapping table with the changed mapping information stored in the update cache.

[0007] According to one aspect of the present invention, a memory system is provided, comprising: a memory device including a meta area and a storage area, wherein the storage area includes a plurality of blocks and the meta area stores mapping information related to valid data randomly stored in the plurality of blocks, and in a simultaneous useless data collection mode of the memory system, the memory device selects together valid data randomly stored in two or more source blocks selected from the plurality of blocks and mapped to a single mapping table in a plurality of mapping tables, reduces the update frequency of the plurality of mapping tables during a useless data collection operation by simultaneously copying the selected valid data to a target block, and updates the changed mapping information in the single mapping table for the selected valid data in the meta area of ​​the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present invention will be more easily understood according to the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is an overall block diagram illustrating a memory system according to an embodiment of the inventive concept;

[0010] Figure 2 It further shows Figure 1 A block diagram of one embodiment of a memory controller;

[0011] Figure 3 It further shows Figure 1 A block diagram of an embodiment of a memory device;

[0012] Figure 4 is a flowchart summarizing an exemplary operation of a memory controller according to an embodiment of the inventive concept;

[0013] Figure 5 It is shown Figure 3A conceptual diagram of a possible structure of a memory cell array;

[0014] Fig. 6A and Figure 6B are conceptual diagrams showing examples of mapping information stored in a mapping table, respectively;

[0015] Figure 7 , Figure 8 and Fig. 9 Each is a conceptual diagram illustrating an example of performing a garbage collection operation, an example of updating a mapping table of a memory device using information stored in an update cache, and an example of performing an update operation multiple times for a mapping table during a garbage collection operation according to some embodiments of the inventive concept;

[0016] Fig.10 , Fig.11 and Fig.12 Each is a flow chart summarizing various memory controller operations for an embodiment of the inventive concept;

[0017] Fig.13 is a graph showing an example of the number (count) of valid data included in a block when data is written in a random pattern;

[0018] Fig.14A and Fig. 14B Each is a block diagram illustrating an example of selecting a source block and a target block and an example of mapping information stored in an update cache;

[0019] Fig.15 is a block diagram illustrating an example of updating a mapping table according to an embodiment of the inventive concept;

[0020] Fig.16 is a flowchart summarizing the operation of a memory controller according to an embodiment of the inventive concept;

[0021] Fig.17 is a graph showing an example of the frequency (count) of update operations according to the number of selected source blocks;

[0022] Fig.18 is a block diagram illustrating a configuration of a memory controller according to an embodiment of the inventive concept;

[0023] Fig.19 is a perspective view showing one possible implementation variant of a memory cell array for a memory device;

[0024] Fig. 20 is a block diagram illustrating an example of applying a memory system to a memory card system according to an embodiment of the inventive concept; and

[0025] Fig.21 is a block diagram illustrating an example of applying a memory device to a solid state drive (SSD) system according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0026] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When phrases such as "at least one of" appear after a list of elements, it modifies the entire list of elements rather than the individual elements of the list.

[0027] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. These embodiments are provided so that the present disclosure will be thorough and complete, and fully convey the inventive concept to those of ordinary skill in the art. The inventive concept may include various embodiments and modifications, and its embodiments are shown in the accompanying drawings and will be described in detail herein. However, it should be understood that the inventive concept is not limited to these embodiments, and includes all modifications, equivalents and substitutions that fall within the scope of the inventive concept. In the specification and the accompanying drawings, the same reference numerals and marks always refer to the same or similar elements. In the accompanying drawings, the dimensions of the structure may be exaggerated for ease of description and clarity.

[0028] The terms used herein are only used to describe specific embodiments and are not intended to limit the inventive concept. As used herein, the singular forms "a", "an", and "the" are also intended to include plural forms unless the context clearly indicates otherwise. It should be understood that when terms such as "comprises", "includes", and "having" are used herein, they specify the presence of stated features, integers, steps, operations, elements, parts, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, or combinations thereof.

[0029] Although terms such as "first" and "second" are used herein to describe various elements or components, the elements or components should not be limited by the terms. These terms can be used to distinguish one element or component from another element or component. For example, a first element or component may also be referred to as a second element or component, and vice versa.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein may have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and should not be interpreted in an idealized or overly formal manner, unless explicitly defined herein.

[0031] Figure 1is a block diagram showing a memory system according to an embodiment. Figure 1 , the memory system 100 generally includes a memory controller 110 and a memory device 120. The memory device 120 may be a non-volatile memory device, such as a flash memory device (e.g., NAND type or NOR type), or a memory device including a resistive memory cell (e.g., ReRAM, MRAM, or PRAM). Regardless of the type of memory cell used in the memory device 120, a large number of constituent memory cells may be arranged in a memory cell array 121, which generally includes a meta region 121_1 and a storage region 121_2.

[0032] The memory controller 110 may be used to control the memory device 120 during the execution of various memory system operations, such as read, write (or program), read / write and erase operations, as well as certain housekeeping functions or memory system management operations. One or more memory system operations are typically performed in response to one or more requests from a host (hereinafter individually or collectively referred to as "data access requests"), wherein various data access requests are associated with one or more commands (CMD), (multiple) control signal indications (CTRL), data transfer (DATA), etc.

[0033] exist Figure 1 In the example shown, the memory controller 110 is assumed to include a flash translation layer (FTL) 111 and an update cache 112. The FTL 111 can be implemented using system software (or firmware) that manages the execution of certain memory system operations of the memory device 120. One or more components of the FTL 111 can be loaded into a working memory (not shown) of the memory controller 110. The firmware included in the FTL 111 can be driven by a processing unit (not shown) provided in the memory controller 110. The update cache 112 can include any type of memory capable of storing data. However, in many embodiments of the inventive concept, the update cache 112 will be implemented using a volatile memory such as a DRAM or SRAM that provides relatively fast data access operations.

[0034] When a data access request including at least one logical address is received from the host, the FTL 111 converts the logical address into a corresponding physical address and provides the physical address to the memory device 120. The FTL 111 may also be used during certain memory system management operations, wherein such management operations are performed on a defined cell area basis (e.g., on a chip unit basis, on a block unit basis, or on a page unit basis) with respect to the memory cell array 121. Many different types of management operations, including so-called garbage collection operations, bad block management operations, etc., will be understood by those skilled in the art.

[0035] As a result of the management operation, the mapping information that relates (multiple) physical addresses to corresponding (multiple) logical addresses will often be changed. The resulting changed mapping information will eventually be updated in the meta region 121_1 of the memory cell array 121. That is, the changed mapping information can be provided to the memory device 120 by the memory controller 110 periodically or non-periodically. In this regard, the update cache 112 can be used to temporarily store the changed mapping information.

[0036] In the memory cell array 121, the meta region 121_1 can be used to store one or more types of non-normal (or "metadata") data, such as overhead data, storage system management data, reference data, etc., while the storage region 121_2 can be used to store normal data, such as user-defined data, user-indicated data, payload data, etc. Of course, the exact boundary between normal data and metadata will vary between memory system designs and applications, but those skilled in the art will generally understand these conventional distinctions. For example, the meta region 121_1 is typically used to store metadata (associated with various information types) that is useful in defining, arranging, allocating / deallocating, characterizing, and managing normal data stored in the storage region 121_2. As a specific example of metadata that can be used in this manner, certain logical-physical mapping information (or "L2P information") can be stored in the meta region 121_1 in a non-volatile manner. Here, the L2P information is data that identifies or allows correlation between (multiple) logical addresses and corresponding (multiple) physical addresses. Hereinafter, L2P information will be used as an example of a more general “mapping information” that may be generated and / or used by the FTL 111 and the memory device 120 to enable communication of normal data between the memory controller 110 and the memory device 120 .

[0037] In this regard, a currently requested read operation or write operation is arbitrarily selected as a time reference point, and metadata including an initial (or first) version of the mapping information L2P information is stored in the meta area 121_1. The first mapping information L2P information stored in the meta area 121_1 is provided to the memory controller 110 at a certain point. When received by the memory controller 110, the first mapping information may be stored in the update cache 112 or a memory associated with the update cache 112. In this way, the memory controller 110 can manage the execution of data access operations to the memory device 120 by referring to the mapping information L2P information stored in the update cache 112. And when each data access operation is performed, the memory controller 110 can change the mapping information L2P information stored in the update cache 112 or the associated memory as necessary. At some point in time after the first mapping information is transferred from the memory device 120 to the memory controller 110 and also after the stored first mapping information is changed at least once by the memory controller 110 as a result of (multiple) data access operations, the changed (or second, or updated) version of the mapping information will be transferred to and stored in a non-volatile manner in the memory device 120 (e.g., in the meta area 121_1). In certain embodiments of the inventive concept, this storage of the "updated mapping information" may result from the execution of a garbage collection operation or some other management operation.

[0038] For example, the meta region 121_1 may include a plurality of mapping tables, which are used to store mapping information in different ways. It should be appreciated that the memory cell array 121 may be divided into a plurality of regions, each of which has a certain size, and the meta region 121_1 may include mapping tables corresponding to the plurality of regions. Therefore, assuming that the storage region 121_2 of the memory cell array 121 is implemented using a plurality of regions of size X, where "X" is a natural number representing GB, a corresponding mapping table may be maintained for each region of size X. That is, each mapping table may be used to store mapping information associated with a corresponding cell of size X. Therefore, in some embodiments, the meta region 121_1 may include hundreds or thousands of mapping tables, which are used together to manage the logical-physical address conversion of the region of size X of the storage region 121_2. Here, the value of "X" may be determined by the block size, the grouping of blocks, the grouping of pages, and the like.

[0039] Those skilled in the art will appreciate that the garbage collection operation can be performed per one or more source units and target units. (Hereinafter, it is assumed that the source / target units are blocks, but this need not always be the case). Therefore, assuming that the requested garbage collection operation specifies a source block and a target block, at least one mapping table stored in the meta area 121_1 will be updated as a result of the garbage collection operation. That is, during the garbage collection operation, data designated as "valid data" in the source block will be moved (i.e., copied) to the target block, and the corresponding mapping information associated with the valid data will be updated or changed. For example, the resulting updated mapping information will be written to one or more mapping tables stored in the meta area 121_1 after being temporarily stored in the update cache 112. Assuming that in a specific example that the update cache 112 has a relatively small size (e.g., 4KB) - because it has a relatively low integration of constituent memory cells - the update of the (multiple) mapping tables in the meta area 121_1 using the update cache 112 during the garbage collection operation can be an iterative process requiring multiple data copy / write operations and associated memory cell erase operations.

[0040] However, as the number of data copy / write operations (or iterative copy / write steps constituting the garbage collection operation) required to update the mapping table(s) increases, the waiting period of the garbage collection operation tends to increase, and the number (or count) of erase operations applied to the memory cells used to store metadata in the meta area 121_1 also increases. This increased number of applied erase operations causes accelerated fatigue of the non-volatile memory cells and may reduce the actual working life of the memory device 120.

[0041] Recognizing these potential adverse effects, embodiments of the present invention contemplate attempting to reduce the frequency of updates to mapping tables resulting from execution of useless data collection operations, to reduce the waiting period required for execution of useless data collection operations, and to extend the actual life of non-volatile memory devices provided in memory systems consistent with embodiments of the present invention contemplated herein.

[0042] As an example of reducing the update frequency of the mapping table of the meta area 121_1, the information stored in the update cache 112 may be managed in a manner that provides high locality with respect to the mapping table. As an embodiment thereof, during a garbage collection operation, two or more source blocks may be selected together, and the garbage collection operation may be performed simultaneously on the selected source blocks.

[0043] For example, assuming that mapping information is stored in the update cache 112, the more mapping information to be updated in the same mapping table stored in the update cache 112, the mapping information stored in the update cache 112 can be updated in a smaller number of mapping tables. That is, when the mapping information of the update cache 112 has high locality relative to the mapping table, the update operation can be performed on a relatively small number of mapping tables during the mapping information update process. On the contrary, when the mapping information of the update cache 112 has low locality relative to the mapping table, the update operation can be performed on a relatively large number of mapping tables in the update process. That is, when the locality relative to the mapping table increases, because the number of mapping tables to be updated is reduced, the delay time required to perform the mapping information update process can be reduced.

[0044] In addition, during the useless data collection operation, the update operation based on the update cache 112 can be repeatedly performed. That is, since the number of copy / write steps for valid data transferred during the useless data collection operation may be relatively large, but the size (i.e., data storage capacity) of the update cache 112 is relatively small, the associated mapping table must be repeatedly updated during the execution of the useless data collection operation. Therefore, when the locality relative to the mapping table increases, since the update operation for any given mapping table can be avoided (or reduced in frequency), the update frequency of each mapping table can be reduced. In addition, since the memory cells located at the same position of the meta region 121_1 can be prevented from being frequently erased, the life of the memory device 120 can be prevented from being shortened.

[0045] According to some embodiments of the present invention, in order to increase locality with respect to a mapping table, a garbage collection operation can be performed on multiple source blocks simultaneously. That is, instead of performing the garbage collection operation sequentially by block (i.e., one source block after another), the garbage collection operation can be performed on multiple source blocks simultaneously. This method allows a larger pool to be used to select valid data that is potentially related to the same mapping table (multiple).

[0046] For example, when the garbage collection operation is sequentially performed in source block units, mapping information corresponding to 600 different mapping tables may be stored in the update cache 112 having a size of 4 KB (or capable of storing 1000 mapping information elements). On the other hand, according to some embodiments of the inventive concept, when garbage collection is performed simultaneously for three (3) source blocks, only mapping information corresponding to 200 different mapping tables may be stored in the update cache 112. Therefore, the update frequency for the relevant mapping tables in the meta area 121_1 may be reduced to 1 / 3 of the frequency required by a similar conventional method.

[0047] The aforementioned method for performing a garbage collection operation, in which "garbage collection" is performed simultaneously for two or more source blocks, can be facilitated by using a source block to determine the operation. For example, when data is written to the memory device 120 according to a sequential pattern rather than a random pattern, the data can be physically written to the memory cell array 121 or invalidated in the memory cell array 121 according to the position of the sequence. In this case, even when the garbage collection operation is performed in a block-sequential manner, the mapping information stored in the update cache 112 will still have high locality relative to the mapping table. Therefore, recognizing this result, some embodiments of the present invention will determine the data type (e.g., random data vs. patterned data) of the data written to one or more blocks included in the memory cell array 121, and in the case where the data is determined to have a random pattern, the garbage collection operation for the block will be performed simultaneously on multiple source blocks. In this way, the amount of metadata that must be updated during the garbage collection operation can be reduced. For example, assuming that the size of each mapping table is 16KB, the mapping table can be updated in units of 16KB. However, since the update frequency for the mapping table(s) may be reduced in an update process that may be performed multiple times, the total amount of metadata updated during the garbage collection operation may be reduced.

[0048] Reference Figure 1 , the memory controller 110 and the memory device 120 may be integrated into a single semiconductor device. As an example, the memory controller 110 and the memory device 120 may be integrated into a single semiconductor device to constitute a memory card such as a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM / SMC), a memory stick, a multimedia card (MMC, RS-MMC or MMCmicro), an SD card (SD, miniSD card or microSD), or a universal flash memory (UFS). As another example, the memory controller 110 and the memory device 120 may be integrated into a single semiconductor device to constitute a solid state disk / drive (SSD).

[0049] In the context of the aforementioned example, the term "garbage collection operation" covers the scope of operations of copying valid data from at least one source block to at least one target block to generate one or more free blocks. The term "simultaneous garbage collection operation" used hereinafter refers to a garbage collection operation of copying valid data from at least two source blocks to at least one target block to generate one or more free blocks. In this regard, the simultaneous garbage collection operation may include the following steps: (1) selecting two or more source blocks; (2) copying valid data from the selected source blocks to at least one target block; (3) storing updated mapping information in an update cache associated with a memory controller based on the execution of the copying step; (4) updating mapping information stored in one or more mapping tables in consideration of the updated mapping information stored in the update cache; and (5) erasing the selected source block from which the valid data was copied.

[0050] The block-sequential junk data collection operation performed in units of one source block can ensure free blocks by copying valid data from one source block and then copying valid data from another source block. In contrast, the simultaneous junk data collection operation for two or more selected source blocks performed according to an embodiment of the present invention can ensure free blocks by copying valid data from multiple source blocks, regardless of the order of the selected source blocks. In this case, the valid data of two or more different source blocks can be referred to as "copied together" to one or more target blocks.

[0051] Figure 2 It further shows Figure 1 A block diagram of an embodiment 200 of the memory controller 110 is shown. Figure 2 , the memory controller 200 includes a processing unit 210, a working memory 220, a host interface 230, a memory interface 240, an update cache 250, and a read-only memory (ROM) 260. The FTL may be loaded into the working memory 220 and may include firmware. According to the functions implemented by the firmware, the FTL may variously include one or more of a wear leveling module 221, a bad block management module 222, a useless data collection module 223, and an address mapping table 224.

[0052] Although Figure 2 Not shown, the memory controller 200 may also include other conventionally understood components, such as a buffer memory for temporarily storing data during the execution of a read / write operation, a buffer control module for controlling the use of the buffer memory, and a command generation module for generating (multiple) commands (CMD) for controlling the execution of different data access operations in response to (multiple) requests from a host.

[0053] The processing unit 210 may include, for example, a central processing unit (CPU) or a microprocessor, and may control the overall operation of the memory controller 200. In order to control the memory controller 200, the processing unit 210 may drive the firmware loaded into the working memory 220. The memory controller 200 may communicate with an external host through various standard interfaces, and the host interface 230 may provide an interface between the host and the memory controller 200. The standard interface may include various interface schemes such as ATA (Advanced Technology Attachment), SATA (Serial ATA), E-SATA (External SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnect), PCI-E (PCI Express), IEEE 1394, USB (Universal Serial Bus), SD (Secure Digital) card, MMC (Multimedia Card), eMMC (Embedded Multimedia Card), Universal Flash (UFS), and CF (CF Flash) card.

[0054] The memory interface 240 may provide an interface for the memory device. For example, write data and read data may be communicated with the memory device through the memory interface 240. In addition, the memory interface 240 may provide commands (CMD) and addresses (ADD) to the memory device, and may also receive various information from the memory device and provide it to the memory controller 200.

[0055] The working memory 220 may include various memories, and may include, for example, at least one of a cache memory, a DRAM, an SRAM, a PRAM, and a flash memory. The wear leveling module 221 may be used to manage the wear leveling of memory cells in the memory device. Memory cells "age" due to the execution of write and erase operations, and eventually highly aged or "worn" memory cells may cause data errors when storing data, or cause defects in the operation of the memory system. By managing the number of program / erase cycles applied to each memory cell in the memory cell array 121, the wear leveling module 221 may prevent memory cells in a specific memory cell array area from wearing out faster than memory cells in other areas. As an example, the wear leveling module 221 may manage the address mapping table 224 so that the program / erase count (the number of erase and write operations for the same memory cell) is evenly distributed over a defined area (e.g., in blocks or pages) of the memory cell array.

[0056] Bad block management module 222 may be used to manage identification and non-use or avoidance of blocks considered defective ("bad blocks") among a plurality of blocks provided by memory device 120. For example, bad block management module 222 may manage address mapping table 224 so that data is not written to bad blocks.

[0057] The garbage collection module 223 can be used to manage the execution of various types of garbage collection operations, including simultaneous garbage collection operations according to embodiments of the inventive concept. As described above, the garbage collection operation is performed to generate one or more additional free blocks by copying valid data from at least one source block to at least one target block and thereafter erasing at least one source block to create or reallocate one or more free blocks.

[0058] The address mapping table 224 can be used to manage the storage of mapping information (e.g., information that correlates logical address(es) provided from the host with corresponding physical address(es) that represent the physical location of the data actually being addressed). By referring to the mapping information, the logical addresses provided from the host can be converted into corresponding physical addresses. The address mapping table 224 can include mapping information received from the meta-area of ​​the memory device, and updated versions (partial or complete) of the mapping information received from the meta-area of ​​the memory device. Thus, mapping information can be passed back and forth between an update cache associated with the memory controller and the meta-area of ​​the memory device based on the address mapping table 224.

[0059] ROM 260 may be used to store code and / or data required for initially booting memory controller 200 and / or memory device 120 of memory system 100. When mapping information of address mapping table 224 is updated, update cache 250 may be used to temporarily store the resulting updated mapping information so that the updated mapping information can be subsequently provided to the memory device. Since update cache 250 has a relatively small size, it may only store some mapping information of address mapping table 224. Although Figure 2 It is shown that the update cache 250 is provided separately in the memory controller 200, but other arrangements or combinations of the update cache 250 and the address mapping table 224 may also be provided in different embodiments of the inventive concept. For example, the update cache 250 including a volatile memory such as DRAM or SRAM may be provided in the processing unit 210, or may be provided in the working memory 220.

[0060] Figure 3 It further shows Figure 1 1 is a block diagram of one embodiment 300 of a memory device 120.

[0061] Reference Figure 3 , the memory device 300 includes a memory cell array 310, a control logic 320, a voltage generator 330, a row decoder 340, and a page buffer 350. Figure 3Not shown, but the memory device 300 may further include a data input / output circuit or an input / output interface.

[0062] The memory cell array 310 includes a meta region 311 for storing metadata and a storage region 312 for storing normal data. Each of the meta region 311 and the storage region 312 may include a plurality of memory cells. Assuming that for some embodiments in which the memory cell array 310 includes flash memory cells, the memory cell array 310 may be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and bit lines BL. For example, the memory cell array 310 may be connected to the row decoder 340 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL, and may be connected to the page buffer 350 through the bit lines BL.

[0063] Based on the command CMD, address ADD, and control signal CTRL received from the memory controller, the control logic 320 may output various internal control signals for writing data to the memory cell array 310 , reading data from the memory cell array 310 , and erasing data stored in the memory cell array 310 .

[0064] Various control signals output from the control logic 320 may be provided to the voltage generator 330, the row decoder 340, and the page buffer 350. For example, the control logic 320 may provide the voltage control signal CTRL_vol to the voltage generator 330, the row address X-ADD to the row decoder 340, and the column address Y-ADD to the page buffer 350. However, the inventive concept is not limited thereto, and the control logic 320 may also provide other control signals to the voltage generator 330, the row decoder 340, and the page buffer 350.

[0065] According to one embodiment, the meta area 311 may include a plurality of mapping tables. Under the control of the memory controller, during a garbage collection operation, the memory device 300 copies valid data from at least one source block of the storage area 312 to at least one target block. In addition, under the control of the memory controller, the mapping table stored in the meta area 311 will be updated according to the result of performing the garbage collection process. The update operation for the meta area 311 may be repeatedly performed during the execution of the garbage collection operation, and one or more mapping tables may be updated during each iteration of the update operation. However, the number of required mapping table updates previously described may be significantly reduced by embodiments of the inventive concept.

[0066] Figure 4 is a flowchart illustrating the operation of a memory controller according to an embodiment.

[0067] Reference Figure 1 , Figure 2 , Figure 3 and Figure 4 , the memory controller 110 (200) determines a requirement to perform a garbage collection operation. This requirement may be triggered, for example, by an indication that the number of free blocks has fallen below a minimum threshold, or by the elapse of a predetermined period of time. However, the determination of the requirement to perform a garbage collection operation will result in the generation of at least one additional free block, and the memory system 100 enters a corresponding garbage collection mode (S11). In some embodiments, an ongoing memory system data access operation (e.g., (multiple) read / write operations) may be interrupted when entering the garbage collection mode, wherein the memory controller may provide a corresponding interrupt to the host.

[0068] When entering the useless data collection mode, the memory controller selects multiple source blocks (S12) and at least one target block (S13). More source blocks than target blocks can be selected to ensure one or more free blocks. For example, three source blocks and two target blocks can be selected, and the valid data stored in the three source blocks can be copied to the two target blocks. When all valid data in the three selected source blocks are copied to the (multiple) target blocks, the three selected source blocks can be erased, whereby the three selected source blocks are reallocated as three free blocks.

[0069] When valid data has been copied to at least one target block and at least one free block is generated (S14), the corresponding mapping information is updated (or changed) accordingly. For example, the obtained updated (or changed) mapping information may be temporarily stored in an update cache (S15). Thereafter, the memory controller may use the mapping information stored in the update cache to update the mapping table in the memory device (S16).

[0070] According to the above-described embodiment, multiple source blocks are selected during the useless data collection operation, and the selected source blocks are simultaneously subjected to useless data collection. Therefore, the pool of valid data potentially corresponding to the same mapping table (multiple) can be increased, and the mapping information stored in the update cache is likely to have a relatively high locality relative to the multiple mapping tables of the memory device. Therefore, since the number of mapping tables actually updated as a result of the useless data collection operation can be reduced, the corresponding amount of metadata that needs to be updated can also be reduced, and the frequency with which updates must be performed on the same mapping table can be reduced.

[0071] Figure 5 It further shows Figure 1 The memory cell array 121 and Figure 3 A conceptual diagram of an example of a structure of a memory cell array 310. Figure 5, the memory cell array 310 includes a meta region 311 and a storage region 312 .

[0072] The meta area 311 may be used to store a plurality of mapping tables (L2P tables) containing mapping information associated with normal data stored in the storage area 312. Here, the storage area 312 may be physically or logically divided into various units. For example, the storage area 312 may include a plurality of segments, and each segment may include a plurality of blocks, wherein each block is an erasable unit within a memory device.

[0073] Each block may include multiple pages, and multiple memory cells included in each page may be connected to the same word line. The read / write unit of the memory device may correspond in size to the size of the page. Alternatively, the read / write unit of the memory device may correspond in size to the size of a portion of the page. As an example, the size of each page may be 16KB, and the read / write unit may be 4KB. Alternatively, the size of each page and the size of each read / write unit may be 4KB. The address may be mapped in a 4KB data unit corresponding to the read / write unit.

[0074] Fig. 6A and Figure 6B Each is a conceptual diagram showing an example of storing mapping information in a mapping table.

[0075] Reference Figure 5 , Fig. 6A and Figure 6B , each mapping table (L2P table) is assumed to have the same size and will store mapping information for normal data stored in an area of ​​a certain size of the storage area 312. As an example, the size of each mapping table may be 16KB, where the mapping table is used to store mapping information for a 16MB area of ​​the storage area. The above sizes are exemplary only, and the size of the mapping table in the memory system and the size of the storage area of ​​the storage area 312 corresponding to the mapping table may be modified in various ways.

[0076] When data is written randomly, any one mapping table can store mapping information for data stored in multiple blocks (BLK). For example, random data can be written in units of 4KB, and in a 16KB mapping table, 4B is used to store mapping information for 4KB data. Assuming a 16KB mapping table size, each mapping table can store mapping information associated with approximately 4000 units of 4KB normal data. Assuming that the number of blocks included in the storage area 312 is M, each mapping table can store mapping information for approximately N data blocks, where "N" can be less than or equal to "M". If the stored data is random data, the value of N can be increased.

[0077] Reference Fig. 6A In the first mapping table (L2P table 1) shown in FIG, mapping information for data stored in a plurality of blocks is stored in the first mapping table (L2P table 1). When data is written in a sequential mode, the first mapping table (L2P table 1) may store mapping information for data located in a relatively small number of blocks. On the other hand, when data is written randomly, the first mapping table (L2P table 1) may store mapping information for data located in a relatively large number of blocks.

[0078] Reference Figure 6B , assuming that the first mapping table (L2P table 1) includes table information for a logical address (ADD_L) and a corresponding physical address (ADD_P). The physical address (ADD_P) may include a block address (A_BLK) and a page address (A_Page). When the read / write unit is smaller than the size of a page, in addition to information indicating a page in a block, the page address (A_Page) may also include information representing the location of data in the page (e.g., a column address).

[0079] like Figure 6B As shown, when data is randomly written, the first mapping table (L2P table 1) may store mapping information for data located in each block.

[0080] Figure 7 is a conceptual diagram further illustrating one example of performing simultaneous garbage collection operations according to some embodiments of the inventive concept.

[0081] like Figure 7 As shown, multiple source blocks are selected and useless data is collected simultaneously with respect to at least one target block. For example, three source blocks (source BLK 1, source BLK 2, and source BLK 3) and two target blocks (target BLK 1 and target BLK 2) are selected.

[0082] Each source block currently stores some valid data, but also stores other invalid data. Mapping information related to valid data may be stored effectively, where valid data is data that can be usefully accessed by an external host. On the other hand, mapping information related to invalid data may not be stored effectively, where invalid data is data that cannot be usefully accessed by an external host.

[0083] exist Figure 7 In the simple example of , it is assumed that valid data is collected into a continuous area of ​​each block. However, in particular, in the case where data is written randomly, the storage locations of valid data may be randomly (non-continuously) distributed on the block.

[0084] like Figure 7As conceptually shown in , instead of sequentially copying valid data from a selected source block to a specific target block, some valid data stored in each of three selected source blocks can be copied together to one or more target blocks. As an example, in these three source blocks, valid data associated with a common mapping table (i.e., mapping information stored in the same mapping table) can be selected together and preferentially copied to the same target block. Under these conditions, within the update cache, the proportion of updated mapping information corresponding to the same mapping table can be increased, and thus locality relative to the mapping table can be improved.

[0085] Figure 8 is another conceptual diagram illustrating one example of updating a mapping table of a memory device using updated mapping information stored in an update cache.

[0086] Reference Figure 8 , the update cache is assumed to be 4KB in size. The mapping information 4B is stored in 4KB write units. Under these assumptions, the update cache can temporarily store about 1000 mapping information elements (e.g., updated (or changed) mapping information elements I1, I2, I3, ...).

[0087] Valid data can be copied to the target block during the useless data collection operation, and the updated mapping information will be stored in the update cache accordingly. Then, the mapping table can be updated according to the mapping information stored in the update cache. For example, the update operation for each mapping table can be performed as a metadata write operation of 16KB size. Figure 8 This example is shown in which an update cache is used to store updated mapping information related to a plurality of mapping tables, and some of the mapping tables are thereafter selectively updated using the updated mapping information stored in the update cache.

[0088] Fig. 9 is yet another conceptual diagram illustrating an exemplary iterative update operation for a mapping table during a garbage collection operation.

[0089] Here, it is assumed that a plurality of source blocks (e.g., source BLK 1, source BLK 2, and source BLK 3) each contain some valid data (e.g., 6KB of valid data). It is also assumed that the composed update cache can store up to 1KB of data. Under these assumptions, during the conventional useless data collection operation sequentially performed with respect to a plurality of source blocks, a total of 18KB of valid data will be copied to the target block. Therefore, the mapping information associated with the 18KB of copied data will be updated. In this case, the update operation based on the update cache can be performed up to 18 times.

[0090] Therefore, in the aforementioned example, each 1KB of valid data present in the source block must be copied and the corresponding mapping information updated by updating the cache. This method inherently reduces the possibility that the "update data" contained in the updated mapping information will be related to the same mapping table. In other words, as a result of the useless data collection operation, the aforementioned method tends to increase the number of mapping tables that need to be updated. As a result, during the update operation, many different mapping tables are updated, and the waiting period required to perform the update operation increases.

[0091] It can also be appreciated from the foregoing examples that during the update operation, the same mapping table may be frequently updated, up to 18 times. Such high-frequency repeated write / erase operations for the memory cells storing the same mapping table will reduce the service life of the memory device.

[0092] However, compared with the aforementioned examples, some embodiments of the present invention's concept select multiple source blocks, and the collective valid data of the selected source blocks are simultaneously performed useless data collection operations. Using the method of the present invention, the probability that the valid data from multiple source blocks is relevant to the same mapping table (L2P table) is much higher than the conventional method. That is, the extended pool of valid data is more likely to be relevant to the same mapping table (L2P table), and therefore, the mapping information corresponding to the mapping table of relatively small number can be stored in the update cache. As a result, during the subsequent update operation for any given mapping table, it is likely that the mapping table will need less update cycles, thereby avoiding unnecessary memory cell loss.

[0093] Fig.10 , Fig.11 and Fig.12 Each is a flowchart illustrating various exemplary operations performed by a memory controller in a memory system according to an embodiment of the inventive concept.

[0094] Reference Fig.10 , a threshold determination can be made as to whether a simultaneous garbage collection operation should be performed. For example, a determination can be made as to the data type (e.g., random or patterned) of one or more blocks selected (or potentially selected) for garbage collection. Therefore, a threshold determination of the type of garbage collection operation to be performed can be made by considering the data type (e.g., block sequentially or block simultaneously). In the event that the data type is random or substantially random (S20=Yes), the memory controller may determine to perform a simultaneous garbage collection operation according to an embodiment of the present inventive concept. Otherwise, if the data is determined to be patterned data (S20=No), the memory controller may determine to perform a sequential garbage collection operation (S21).

[0095] The sequential garbage collection operation may be performed substantially along conventional lines, but ultimately results in storing corresponding updated mapping information in an update cache (S25), and storing at least one mapping table in a non-volatile memory (S26).

[0096] The simultaneous garbage collection operation may be performed as described above. That is, if no selection has been made in the data type determination step (S20), a plurality of source blocks (i.e., at least two) are selected (S22), and at least one target block is also selected (S23). Following these selections, the simultaneous garbage collection operation is performed on the plurality of source blocks (24). Again, this again results in storing the corresponding updated mapping information in an update cache (S25), and storing at least one mapping table in a non-volatile memory (S26).

[0097] The determination of whether to perform sequential garbage collection operations or simultaneous garbage collection operations may be made using one or more different considerations. In one example, the memory system may be pre-configured to randomly write data in response to write request(s) received from the host. In another example, the randomly written data will exhibit a relatively high ratio of valid data to total written data for the selected source block(s).

[0098] Fig.11 A second alternative for determining the type of garbage collection operation is shown. Here, instead of considering the type of data stored ( Fig.10 In step S20 of the embodiment, a valid data ratio of data stored in the selected block(s) is determined (S31). In the case where the determined valid data ratio is greater than the established threshold value (S32=Yes), a simultaneous garbage collection operation is performed. However, in the case where the determined ratio is not greater than the established threshold value (S32=No), a sequential garbage collection operation is performed.

[0099] Here, the sequential garbage collection operation includes a step of copying valid data in units of one (1) source block (S33). Ultimately, this sequential garbage collection operation results in updated mapping information being written to the update cache (S36). Subsequently, the mapping table stored in the non-volatile memory is updated using the updated mapping information stored in the update cache (S37). In contrast, if no selection has been made in the valid data ratio determination step (S31), the simultaneous garbage collection operation includes a step of selecting multiple source blocks (S34), and copying valid data in units of more than one resource block (S35). Ultimately, this sequential garbage collection operation results in updated mapping information being written to the update cache (S36). Subsequently, the mapping table stored in the non-volatile memory is updated using the updated mapping information stored in the update cache (S37).

[0100] Reference Fig.12 , an example is shown in which multiple considerations or factors are used to determine whether sequential garbage collection operations should be performed or simultaneous garbage collection operations should be performed. For example, a first determination is made regarding a minimum value of a valid data ratio of data stored in at least one selected source block (S41). After comparing the ratio of valid data to a threshold, it can be further determined whether the data is written randomly (S42). These two determinations can be made independently or conditionally for each of a plurality of source blocks. Thereafter, some of the considered source blocks that are determined to store substantially random data and / or meet an established threshold for a valid data ratio can be selected for simultaneous garbage collection (S43), and thereafter simultaneous garbage collection operations can be performed (S44). Although in Fig.12 Not shown, but it will be appreciated, that other possible source blocks considered in steps (S41) and (S42) (i.e., source blocks determined to store substantially patterned data and / or not satisfying established thresholds for valid data ratios) may be designated for sequential junk data collection.

[0101] Fig.13 is a graph showing an example of valid data count for data stored in a selected block when data is randomly written.

[0102] When random data is written to a plurality of blocks contained in a memory device, the distribution of valid data counts for each block may be as follows: Fig.13 Here, the effective data ratio for each block can be calculated based on Fig.13 It is calculated based on the valid data count in .

[0103] Blocks that do not have a (0) valid data count are free blocks. Blocks that have a valid data count less than an established threshold (i.e., have a relatively low valid data count) are active blocks to be additionally written. However, as described above, the continuous writing and rewriting of data stored in the blocks increasingly leads to the accumulation of invalid data in the blocks. Therefore, the rising count of invalid data reduces the valid data ratio in the block until it is below a given valid data ratio threshold.

[0104] exist Fig.13 In the example shown, the exemplary source block has random data written therein and has a relatively low effective data ratio, corresponding to about 53KB, which represents that the effective data ratio of the block is about 64%. The designed memory system can establish multiple thresholds by which it is determined whether a sequential garbage collection operation or a simultaneous garbage collection operation should be performed. In addition, these multiple thresholds can be used to "select" one or more source blocks related to the sequential garbage collection operation or the simultaneous garbage collection operation to be performed.

[0105] Fig.14A and Fig. 14B Each is a conceptual diagram showing an example of selecting a source block and a target block and an example of mapping information stored in an update cache.

[0106] Fig.14A An example is shown in which, for a simultaneous useless data collection operation, a plurality of (e.g., M) source blocks are selected and a plurality of (e.g., N) target blocks are selected. The number of source blocks (source BLK 1 to source BLK M) may be greater than the number of target blocks (target BLK 1 to target BLK N). Valid data of each of the source blocks (source BLK 1 to source BLK M) may be copied to the target blocks (target BLK 1 to target BLK N).

[0107] When multiple source blocks (source BLK 1 to source BLK M) are selected, the mapping information stored in the update cache can have a higher locality relative to the mapping table. On the other hand, when multiple source blocks (source BLK 1 to source BLK M) are selected, the processing throughput that needs to be managed, such as the selection of related valid data across multiple source blocks, increases. According to certain embodiments of the present invention, in view of memory system resources, (multiple) appropriate restrictions can be set for the selection of source blocks (source BLK 1 to source BLK M).

[0108] like Fig. 14BAs shown, in the source blocks (source BLK 1 to source BLK M), valid data related to the same mapping table can be defined as valid data of the same group. For example, valid data having mapping information associated with the first mapping table (L2P table 1) can be distributed (or in a distributed manner) stored in the source blocks (source BLK 1 to source BLK M), and valid data corresponding thereto can be defined as valid data of the first group. Multiple groups of valid data can be stored in the source blocks (source BLK 1 to source BLK M).

[0109] In consideration of the above, the valid data copy operation can be performed in groups, and its mapping information can be stored in the update cache based on the copy operation performed in groups. Therefore, the mapping information associated with the valid data belonging to the same group can be stored in the update cache, and therefore, the mapping information stored in the update cache can have high locality.

[0110] Fig.15 is a conceptual diagram illustrating an example of updating a mapping table according to an embodiment of the inventive concept. Fig.15 An example is shown in which three source blocks (source BLK 1 to source BLK 3 ) are selected together.

[0111] Each of the source blocks (source BLK 1 to source BLK M) may include a plurality of valid data related to a plurality of mapping tables. As an example, the first source block (source BLK 1) may store valid data (Data_T1, Data_T2, Data_T3, Data_T12, Data_T21, ...) related to various mapping tables.

[0112] Valid data belonging to the same group can be selected from the source block (source BLK 1 to source BLK M) and copied to the target block, and the changed mapping information can be stored in the update cache according to the copy result. For example, the valid data (Data_T1) of the first group can be selected from the source block (source BLK 1 to source BLK M), and the changed mapping information can be stored in some areas of the update cache related to the valid data (Data_T1) of the first group. Similarly, the valid data (Data_T12 and Data_21) in the 12th and 21st groups can be selected from the source block (source BLK 1 to source BLK M), and the changed mapping information can be stored in some other areas of the update cache related thereto.

[0113] The amount of mapping information corresponding to the same mapping table in the update cache can be increased, and therefore, the number of mapping tables updated in each update process can be minimized. For example, when the mapping information stored in the update cache includes only information related to the first, 12th, and 21st mapping tables (L2P tables 1, 12, and 21), only the first, 12th, and 21st mapping tables (L2P tables 1, 12, and 21) among the plurality of mapping tables can be updated during the update process.

[0114] Fig.16 is a flowchart illustrating the operation of a memory controller according to an embodiment of the inventive concept. Fig.16 An example of selecting valid data from a plurality of source blocks, and corresponding mapping information to be stored together in an update cache is shown.

[0115] Reference Fig.16 , a plurality of source blocks for useless data collection may be selected, and the selection operation may be performed by determining the valid data ratio in the source blocks according to the above-described embodiment. The mapping information may be stored as metadata in the memory system, and thus the mapping information of the valid data in the plurality of source blocks may be determined (S51).

[0116] According to the determination result, the location of the mapping table related to the valid data stored in each of the plurality of source blocks can be determined. According to the determination result, valid data whose mapping information is to be stored together in the update cache can be selected from the plurality of source blocks. For example, valid data related to the same mapping table (or valid data having mapping information stored in the same mapping table) can be selected (S52).

[0117] The selected valid data may be copied to one or more target blocks (S53), and the mapping information about the selected valid data may be stored together in the update cache (S54). By repeating the above operations, the mapping information corresponding to a relatively small number of mapping tables may be stored in the update cache. From another perspective, a large number of mapping information elements corresponding to any one mapping table may be stored together in the update cache.

[0118] Thereafter, it may be determined whether the update timing has been reached (S55). When the update timing has not been reached, the above process of selecting valid data and the above process of storing the changed mapping information in the update cache may be repeated. Thereafter, when the update timing has been reached, the mapping information stored in the update cache may be updated in one or more mapping tables (S56).

[0119] Fig.17 is a graph showing an example of the frequency (count) of update operations according to the number of selected source blocks.

[0120] like Fig.17 As shown, when the number of source blocks selected for garbage collection increases, the update count for the mapping table can be reduced. As an example, when one source block is selected, up to about 74% of the mapping table of the number of mapping information elements stored in the update cache can be updated. However, according to one embodiment, when four source blocks are selected, only about 38% of the mapping table of the number of mapping information elements stored in the update cache can be updated. This can indicate that the update count is reduced to about 51%.

[0121] Fig.18 is a block diagram illustrating a configuration of a memory controller according to an embodiment of the inventive concept.

[0122] like Fig.18 As shown, the memory controller 400 may include a source block characteristic determination unit 410, a source block selection unit 420, a useless data collection execution unit 430, and an update cache 440. The update cache 440 may include a volatile memory, such as an SRAM or a DRAM. In addition, the source block characteristic determination unit 410, the source block selection unit 420, and the useless data collection execution unit 430 may be implemented as hardware or software. As an example, the functions of the source block characteristic determination unit 410, the source block selection unit 420, and the useless data collection execution unit 430 may be implemented as software through the firmware of the above-mentioned FTL.

[0123] By referring to the mapping information (L2P information), the source block characteristic determination unit 410 can determine the characteristics of the valid data included in each source block. For example, the location of the mapping table storing the mapping information related to each valid data included in the source block can be determined. In addition, the valid data related to the same group (or the mapping information managed by the same mapping table) can be stored in some source blocks in a centralized manner (or in a centralized manner), and the source block characteristic determination unit 410 can determine the relationship between the source blocks by referring to the mapping information (L2P information) about the valid data of multiple source blocks.

[0124] With reference to the above-mentioned determination result, the source block selection unit 420 can select the source block to be collected with useless data at the same time. The source block that can improve its locality can be selected according to the above-mentioned determination result. For example, when the storage ratio of the valid data related to a specific mapping table is high in any one source block and the storage ratio of the valid data related to the same mapping table is also high in another source block, these source blocks can be selected as the source blocks to be collected with useless data at the same time. That is to say, according to the present embodiment, the storage characteristics of the valid data can be considered to select the source block.

[0125] According to the above selection result (Info_sel), the useless data collection execution unit 430 can generate a useless data collection control signal (Ctrl_GC) to perform the operation of copying valid data from the selected source block, the operation of storing the mapping information in the update cache, and the operation of updating the mapping table by using the update cache, as in the above embodiment.

[0126] Fig.19 is a perspective view illustrating a memory cell array of a memory device that may be incorporated in some embodiments of the inventive concept.

[0127] The memory cell array may include a plurality of blocks, and each block may have a three-dimensional (3D) structure (or a vertical structure). For example, each block may include a structure extending from a first to a third direction. For example, in the case of a flash memory device, each cell block may include a plurality of NAND strings extending along a third direction. In this case, the plurality of NAND strings may be spaced a certain distance from each other along the first and second directions. Fig.19 A schematic diagram corresponding to one block BLK1 may be shown. In addition, the block BLK1 may be a block included in the meta region, or may be a block included in the storage area.

[0128] Reference Fig.19 , the unit block BLK1 may be formed in a vertical direction relative to the substrate SUB. Fig.19 It is shown that the cell block BLK1 includes two selection lines GSL and SSL, eight word lines WL1 to WL8 , and three bit lines BL1 to BL3 , but the number of lines may be variously modified.

[0129] The substrate SUB may have a first conductivity type (e.g., p-type), and a common source line CSL may be provided on the substrate SUB, which extends in a first direction (e.g., Y direction) and is doped with impurities of a second conductivity type (e.g., n-type). On a region between two adjacent common source lines CSL of the substrate SUB, a plurality of insulating layers IL extending in the first direction may be sequentially provided in a third direction (e.g., Z direction). The plurality of insulating layers IL may be spaced a certain distance from each other in the third direction. For example, the plurality of insulating layers IL may include an insulating material such as silicon oxide.

[0130] In the region between two adjacent common source lines CSL of the substrate SUB, a plurality of pillars P may be provided to be sequentially arranged along a first direction and to penetrate the insulating layer IL along a third direction. For example, the pillars P may penetrate the insulating layer IL to contact the substrate SUB. For example, the surface layer S of each pillar P may include a silicon material having a first type and may be used as a channel region. The inner layer I of each pillar P may include an insulating material, such as silicon oxide, or an air gap.

[0131] In the region between two adjacent common source lines CSL, the charge storage layer CS may be provided along the exposed surfaces of the insulating layer IL, the pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (or a tunneling insulating layer), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, in the region between two adjacent common source lines CSL, a gate electrode GE including select lines GSL and SSL and word lines WL1 to WL8 may be provided on the exposed surface of the charge storage layer CS.

[0132] Drains or drain contacts DR may be provided on the pillars P, respectively. For example, the drains or drain contacts DR may include a silicon material doped with impurities having a second conductivity type. On the drains or drain contacts DR, bit lines BL1 to BL3 may be provided to extend in a second direction (e.g., X direction) and be spaced apart from each other by a certain distance in the first direction.

[0133] U.S. Patent Publication Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application No. 2011 / 0233648 describe various configurations of 3D memory arrays that include multiple levels and share word lines and / or bit lines between the levels, and the contents of these disclosures are incorporated herein by reference.

[0134] Fig. 20 is a block diagram illustrating an example of applying a memory system to a memory card system according to an embodiment of the inventive concept. As an example, it is assumed that the memory system is a flash memory system.

[0135] Reference Fig. 20 , the memory card system 500 may include a host 510 and a memory card 520. The host 510 may include a host controller 511 and a host connector 512. The memory card 520 may include a card connector 521, a card controller 522, and a memory system 523. The memory system 523 may be connected to a host computer 510 by using Figures 1 to 19 Therefore, the memory system 523 can perform the garbage collection operation according to the above embodiment, and can reduce the update frequency of the mapping table by selecting multiple source blocks and performing the garbage collection operation on them simultaneously.

[0136] The host 510 can write / read data to / from the memory card 520. The host controller 511 can transmit a command (CMD), data (DATA), and a clock signal (CLK) generated by a clock generator (not shown) in the host 510 to the memory card 520 through the host connector 512.

[0137] In response to a request received through the card connector 521, the card controller 522 may provide data to the memory system 523 in synchronization with a clock signal generated by a clock generator (not shown) in the card controller 522. The memory system 523 may store data received from the host 510.

[0138] The memory card 520 may be implemented to include, for example, a compact flash card (CFC), a micro drive, a smart media card (SMC), a multimedia card (MMC), a secure digital card (SDC), a universal flash memory (UFS), a memory stick, and a USB flash drive.

[0139] Fig.21 is a block diagram illustrating an example of applying a memory device to an SSD system according to an embodiment of the inventive concept.

[0140] Reference Fig.21 , the SSD system 600 may include a host 610 and an SSD 620. The SSD 620 may exchange signals with the host 610 through a signal connector, and receive input of power through a power connector. The SSD 620 may include an SSD controller 621, an auxiliary power supply 622, and a plurality of non-volatile memory systems 623, 624, and 625. Each of the non-volatile memory systems 623, 624, and 625 may include a memory device according to an embodiment. According to an embodiment, each of the non-volatile memory systems 623, 624, and 625 may perform a useless data collection operation according to the above-described embodiment, and may reduce the update frequency of the mapping table by selecting a plurality of source blocks and performing a useless data collection operation thereon simultaneously.

[0141] The above illustrates embodiments of the inventive concept and should not be construed as limiting the inventive concept. In addition, it will be readily appreciated by those skilled in the art that various modifications may be made to these embodiments without substantially departing from the scope of the inventive concept.

[0142] Although embodiments have been shown and described with reference to particular embodiments, various changes in form and details may be made without departing from the spirit and scope of the following claims.

Claims

1. A method for operating a memory system including a non-volatile memory device, the non-volatile memory device including a plurality of blocks, the method comprising: Storing valid data randomly in multiple blocks; Enter useless data collection mode; reducing the update frequency of the plurality of mapping tables during a garbage collection operation by simultaneously copying valid data of a single mapping table randomly stored in two or more source blocks selected from the plurality of blocks and mapped to the plurality of mapping tables to a target block in the garbage collection operation in a garbage collection mode; updating the changed mapping information in the single mapping table in a meta area of ​​the non-volatile memory device according to the result of the copying; as well as A free block is generated by erasing the two or more source blocks.

2. The operating method according to claim 1, wherein: The replication includes: The valid data of the two or more source blocks are copied together to a single target block.

3. The operating method according to claim 1, wherein: The replication includes: concurrently reading valid data from the two or more source blocks; and Valid data read from the two or more source blocks are written to the target block.

4. The operating method according to claim 1, wherein: The memory system also includes a memory controller including an update cache; and The changed mapping information in the single mapping table is stored in the update cache, and the changed mapping information in the update cache is provided to the meta area of ​​the nonvolatile memory device.

5. The operating method according to claim 4, wherein: The plurality of mapping tables are included in a meta region, and Mapping information in the plurality of mapping tables is updated according to the changed mapping information provided to the meta area.

6. The operating method according to claim 4, wherein: Mapping information about changes in valid data of the two or more source blocks is stored together in an update buffer.

7. The operating method according to claim 4, in, The meta area includes the plurality of mapping tables, and mapping information about valid data of the plurality of blocks is stored in the plurality of mapping tables, Therein, mapping information about changes to valid data located in different source blocks and associated with a single mapping table are stored together in an update cache.

8. The operating method according to claim 7, wherein: Generating the free block includes erasing the two or more source blocks after all valid data of the two or more source blocks are copied to the target block.

9. A method for operating a memory system including a memory controller and a non-volatile memory device, the method comprising: Randomly storing valid data in a source block of a non-volatile memory device; selecting, by the memory controller, a source block of the nonvolatile memory device for garbage collection in a simultaneous garbage collection operation; Reducing the update frequency of the plurality of mapping tables during the simultaneous garbage collection operation by simultaneously copying valid data of a single mapping table randomly stored in the source block and mapped to the plurality of mapping tables to the target block in the simultaneous garbage collection operation; storing the changed mapping information in an update cache of a memory controller in response to valid data being copied from the source block to the target block in a simultaneous garbage collection operation; as well as The single mapping table is updated with the changed mapping information stored in the update cache.

10. The operating method according to claim 9, further comprising: determining whether the data written to each of the source blocks has a random pattern, The number of source blocks selected for garbage collection varies according to a result of determining whether data written to each of the source blocks has a random pattern.

11. The operating method according to claim 9, further comprising: After valid data from the source block is copied to the target block, the source block is erased.

12. The operating method according to claim 9, wherein: The non-volatile memory device stores the plurality of mapping tables including mapping information associated with data stored in the memory system, and The updating of the mapping table includes selectively updating a single mapping table of the plurality of mapping tables using the changed mapping information stored in the update cache.

13. A memory system comprising: A memory device comprising a meta area and a storage area, wherein the storage area comprises a plurality of blocks and the meta area stores mapping information associated with valid data randomly stored in the plurality of blocks, and In the simultaneous garbage collection mode of the memory system, The memory device selects together valid data randomly stored in two or more source blocks selected from the plurality of blocks and mapped to a single mapping table in the plurality of mapping tables, reduces an update frequency of the plurality of mapping tables during a useless data collection operation by simultaneously copying the selected valid data to a target block, and updates changed mapping information in the single mapping table in a meta area of ​​the memory device for the selected valid data.

14. The memory system according to claim 13, wherein: After all valid data of the two or more source blocks are copied to the target block, the memory device erases the two or more source blocks together.

15. The memory system according to claim 13, wherein: The meta area includes the plurality of mapping tables, and each of the mapping tables stores mapping information about valid data of the plurality of blocks, and In a garbage collection mode of the memory system, Valid data associated with a single mapping table is selected from the two or more source blocks and copied to the target block.

16. The memory system of claim 15, wherein: Valid data associated with the single mapping table is read from the two or more source blocks together.

17. The memory system of claim 13, further comprising: Memory controller including flash translation layer and update cache, The flash translation layer includes a garbage collection module that controls garbage collection based on the selected two or more source blocks.

18. The memory system of claim 17, wherein: The changed mapping information is stored in the update cache, and the changed mapping information in the update cache is provided to a meta area of ​​the memory device.

19. The memory system of claim 18, wherein: Mapping information about changes to valid data located in different source blocks is stored together in the update cache.

20. The memory system of claim 18, wherein: In the garbage collection mode, valid data is read from the two or more source blocks and provided to the memory controller, and the memory controller provides the read valid data to the target block, and The update operation using the update cache is performed a plurality of times, and valid data of the two or more source blocks are read together during one update operation.

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