Asynchronous Forward Caching Memory System and Method

Abstract

This application relates to an asynchronous forward cache memory system and method. A memory system (14) can be communicatively coupled to a processor (12) via one or more data buses (20). Additionally, the memory system (14) can include one or more memory devices (18) that store data to be used by processing circuitry (16) implemented in the processor (12) to perform operations. Further, the memory system (14) can include a memory controller (26) that receives a memory access request requesting the return of the data via the one or more data buses (20), and in response, determines the storage location of the data in the one or more memory devices (18) at least in part based on the memory access request, and instructs the memory system (14) to store the data directly into a processor-side cache (22) integrated with the processing circuitry (16) such that the processing circuitry (16) implemented in the processor (12) performs the operations based on the data.

Description

[0001] Relevant information of divisional application

[0002] This is a divisional application. The parent case of this divisional application is a Chinese patent application for invention with the title "Asynchronous Forward Caching Memory System and Method", application date of July 29, 2019, and application number of 201980056134.6. Technical Field

[0003] The present disclosure generally relates to memory devices, and more particularly, to address management techniques implemented in a memory subsystem. Background Art

[0004] Typically, a computing system includes a processing subsystem and a memory subsystem that can store data accessible by the processing circuitry of the processing subsystem. For example, for operation, the processing circuitry may execute corresponding instructions retrieved from a memory device of the memory subsystem. In some instances, operational data inputs may also be retrieved from the memory device. Additionally or alternatively, operational (e.g., generated by it) data outputs may be stored in the memory device, e.g., to enable subsequent retrieval. However, at least in some instances, the operational efficiency of a computing system may be limited by its architecture, e.g., the architecture that controls the order of operations performed in the computing system. Summary of the Invention

[0005] In one aspect, the present invention provides an apparatus, comprising: a processing system including a processor and a cache; a system bus coupled to the processing system; and a memory system coupled to the processing system via the system bus, wherein the memory system includes: a main memory array configured to store a plurality of data records, each data record of the plurality of data records including at least a first data field; and a memory controller configured to: store the first portion of each data record of the plurality of data records in the first data field of the corresponding data record based on determining a correlation among values of the first portion of each data record of the plurality of data records; receive, from the processor, a first memory access request for first targeted data targeted to be stored in the first data field of a first data record of the plurality of data records; in response to receiving the first memory access request, provide the first targeted data to the processing system; predict, based on the correlation determined among the values of the first portion of each data record and the received first memory access request targeting the first targeted data, a first subsequent memory access request from the processor for second targeted data targeted to be stored in the first data field of a second data record of the plurality of data records; and based on predicting the first subsequent memory access request, provide an instruction to store the second targeted data in the cache of the processing system.

[0006] In another aspect, the present invention provides a method, comprising: receiving, by a memory system, a plurality of data records; determining, by a memory controller of the memory system, a correlation among values of a first portion of each data record of the plurality of data records; storing, by the memory controller based on determining the correlation among the values of the first portion of each data record, the first portion of each data record of the plurality of data records in a first data field of the corresponding data record; receiving, by the memory controller, a first memory access request from a processor system, the first memory access request targeting first targeted data targeted to be stored in the first data field of a first data record of the plurality of data records; providing, by the memory controller in response to receiving the memory access request, the first targeted data to the processing system; predicting, by the memory controller based on the correlation determined among the values of the first portion of each data record and the received first memory access request targeting the first targeted data, a first subsequent memory access request from the processor system, the first subsequent memory access request targeting second targeted data targeted to be stored in the first data field of a second data record of the plurality of data records; and based on predicting the subsequent memory access request, providing, by the memory controller, an instruction to store the second targeted data in the cache of the processing system.

[0007] In another aspect, the present invention provides a memory device configured to couple to a processing system, the memory device including: one or more memory arrays; a memory controller configured to perform operations in response to receiving data and instructions from the processing system when the memory device is coupled to the processing system, wherein the operations include: receiving a plurality of data records from the processing system; determining a mutual relationship among values of a first portion of each of the plurality of data records; based on the determined mutual relationship among the values of the first portion of each of the plurality of data records, storing the first portion of each of the plurality of data records in a first data field of a corresponding data record; receiving a first memory access request from the processor system, the first memory access request targeting first target data stored in the first data field of the first data record of the plurality of data records; in response to receiving the memory access request, providing the first target data to the processing system; predicting a first subsequent memory access request from the processor system based on the determined mutual relationship among the values of the first portion of each data record and the received first memory access request targeting the first target data, the first subsequent memory access request targeting second target data stored in the first data field of a second data record of the plurality of data records; and based on predicting the subsequent memory access request, providing an instruction to store the second target data in a cache of the processing system. Description of the Drawings

[0008] Aspects of the present disclosure can be better understood by reading the following detailed description and referring to the drawings, in which:

[0009] Figure 1 is a block diagram of a computing system including a processing subsystem and a memory subsystem according to one embodiment of the present disclosure;

[0010] Figure 2 is according to one embodiment of the present disclosure Figure 1 a block diagram of an example of a processing subsystem of

[0011] Figure 3 is a flowchart of an exemplary process for operating Figure 2 a processing subsystem according to one embodiment of the present disclosure;

[0012] Figure 4 is a block diagram of an example of a memory subsystem of Figure 1 utilizing one or more index tables according to one embodiment of the present disclosure;

[0013] Figure 5is a block diagram of an exemplary volatile memory array that may be implemented in a memory subsystem of Figure 4 ;

[0014] Figure 6 is an illustration of an index table that may be used by a memory subsystem of Figure 4 ;

[0015] Figure 7 is a block diagram of a portion of an index table memory array that stores an index table of Figure 6 and a memory controller coupled to the index table memory array;

[0016] Figure 8 is a flowchart of an exemplary process for generating index entries to be included in an index table;

[0017] Figure 9 is a flowchart of an exemplary process for generating and / or updating an index table;

[0018] Figure 10 is a flowchart of an exemplary process for storing data records in a memory subsystem of Figure 4 ;

[0019] Figure 11 is a flowchart of an exemplary process for operating a memory subsystem of Figure 4 ; and

[0020] Figure 12 is a flowchart of an exemplary process for predictively identifying data expected to be targeted subsequently. DETAILED DESCRIPTION

[0021] The present disclosure provides techniques for promoting improved operational efficiency of a computing system, such as by alleviating architectural features that may limit operational efficiency. Generally, a processing subsystem of a computing system includes processing circuitry implemented using, for example, one or more processors and / or one or more processor cores. Additionally, a memory subsystem of a computing system may include one or more memory devices (e.g., chips or integrated circuits) implemented in, for example, one or more memory modules (e.g., dual in-line memory modules (DIMMs)).

[0022] Typically, memory cells implemented in a memory device can be organized into one or more main memory arrays, e.g., each main memory array corresponds to one memory channel. To implement a memory array, the memory cells can be coupled to word lines formed in a first (e.g., horizontal) direction and bit lines formed in a second (e.g., vertical) direction. For example, a row of a memory array can include memory cells coupled to one word line. Additionally, in some embodiments, a column of a memory array can include memory cells coupled to multiple bit lines.

[0023] In other words, a memory cell (e.g., storage location) connected at the pairing of a row address and a column address can store a data block having a bit depth (e.g., size) that depends on the number of bit lines included in the column identified by the column address. For example, when each column includes 1024 bit lines, the memory cells implemented at each row address and column address pairing can store a 64-byte (e.g., 1024-bit) data block. Additionally, when the memory array includes sixteen columns, each row of the memory array can store up to sixteen data blocks.

[0024] In any case, during operation of a computing system, processing circuitry can perform various operations by executing corresponding instructions, e.g., by operating on input data to determine output data. At least in some instances, data accessible to the processing circuitry can be stored in a memory subsystem. For example, the memory subsystem can store data inputs for an operation, data outputs of the operation (e.g., produced thereby), data indicating executable instructions, or any combination thereof.

[0025] Thus, the processing subsystem and the memory subsystem can be communicatively coupled via a system (e.g., data) bus. Typically, the system bus can be implemented to provide limited communication bandwidth. In fact, at least in some instances, the system bus can be shared with other subsystems of the computing system, such as a radio frequency (RF) subsystem. In other words, data communication between the processing subsystem and the memory subsystem via the system bus may limit the amount of communication bandwidth available for other computing subsystems and / or other operations, which may limit the operating efficiency of the computing system at least in some instances.

[0026] In any case, via the system bus, the processing subsystem can output data to be stored in the memory subsystem. Additionally or alternatively, via the system bus, the memory subsystem can output (e.g., return) data to the processing subsystem, e.g., for processing and / or execution by processing circuitry implemented in the processing subsystem. In other words, the memory subsystem can store data (e.g., in a main memory array) for subsequent access by the processing subsystem.

[0027] To access data stored in a memory subsystem, a processing subsystem may output a memory access request to the memory subsystem via a system bus, where the memory access request identifies data, for example, via a virtual memory address. Typically, each memory access request may include overhead (e.g., header data and / or metadata). For example, since the system bus may be shared with other computing subsystems, a memory access request may include overhead indicating that the memory access request is intended for the memory subsystem.

[0028] At least in part based on the memory access request, the memory subsystem may determine a storage location of the data in the memory subsystem, for example, by mapping the virtual memory address to a physical memory address (e.g., a row address and a column address pair). At least in part based on its storage location, the memory subsystem may retrieve the data from, for example, a main (e.g., volatile) memory array and / or a non-volatile memory device implemented in the memory subsystem. In this way, the memory subsystem may output (e.g., return) the target data to the processing subsystem via the system bus, for example, for processing and / or execution by processing circuitry implemented in the processing subsystem.

[0029] In at least some instances, the processing circuitry may operate at least in part based on data from multiple data blocks, for example, to execute an application or algorithm. Thus, in some instances, the processing subsystem may sequentially output memory access requests, each of which identifies one of the multiple data blocks. For example, the processing subsystem may output a first memory access request identifying a first data block to the memory subsystem via the system bus and subsequently output a second memory access request identifying a second data block.

[0030] However, as noted above, data communication via the system bus typically utilizes (e.g., consumes) at least a portion of the limited communication bandwidth provided by the system bus. Moreover, data communication via the system bus typically consumes power. In fact, the resulting power consumption and / or bandwidth usage typically depends on the size (e.g., amount) of the data being communicated. For example, the power consumption for communicating data via the system bus may increase as the data size increases. Additionally or alternatively, the amount of the limited communication bandwidth provided by the system bus for communicating data may increase as the data size increases. In other words, due to communication via the system bus, memory access requests may set a lower bound on the operational (e.g., communication and / or power) efficiency of the computing system—particularly when communicating sequentially, for example, because each memory access request includes overhead (e.g., header data and / or metadata).

[0031] Accordingly, to facilitate improved operational (e.g., communication and / or power) efficiency, the present disclosure provides techniques for implementing and / or operating a computing system to provide an address management function (e.g., operation or process) via its memory subsystem. To facilitate providing the address management function, the memory subsystem may include a memory controller. Additionally, to facilitate providing the address management function, the memory subsystem may store data blocks as data records that utilize a data structure that allocates specific bit positions for indicating one or more specific data fields.

[0032] As just one illustrative example, a first data record data structure may allocate bits [0,X] for indicating a name (e.g., first) field, bits [X+1,Y] for indicating a street address (e.g., second) field, and bits [Y+1,Z] for indicating a postal code (e.g., third) field. In other words, a first data record utilizing the first data structure may indicate the name of a first entity in its name field, the street address of the first entity in its street address field, and the postal code of the first entity in its postal code field. Additionally, a second data record utilizing the first data structure may indicate the name of a second entity in its name field, the street address of the second entity in its street address field, and the postal code of the second entity in its postal code field.

[0033] In some embodiments, different data records may utilize different data structures that include, for example, one or more different data fields. As an illustrative example, a second data record data structure may allocate bits [0,Z–(Y+1)+1] for indicating a postal code field. Accordingly, a third data record utilizing the second data structure may indicate the postal code of a third entity in its postal code field.

[0034] By storing data using data record data structures, the memory subsystem (e.g., memory controller) may group data records each including a specific data field via a corresponding index table, where the data records are stored, for example, in separate storage (e.g., memory) devices and / or in an index table memory array that is different (e.g., separate) from one or more main memory arrays. To facilitate grouping the data records, the memory subsystem may generate an index entry corresponding to each data record that includes a specific data field. For example, the memory subsystem may generate a first postal code index entry corresponding to the first data record and a second postal code index entry corresponding to the second data record. Additionally or alternatively, the memory subsystem may generate a third postal code index entry corresponding to the third data record.

[0035] In some embodiments, an index entry corresponding to a data record may indicate the storage location of the data record in the memory subsystem, for example, via a pointer pointing to the storage location of the data record in the main memory array or the non-volatile memory device. In other words, continuing with the above example, the memory subsystem may generate a first postal code index entry to indicate the storage location of the first data record in the memory subsystem, and generate a second postal code index entry to indicate the storage location of the second data record in the memory subsystem. Additionally or alternatively, the memory subsystem may generate a third postal code index entry corresponding to the third data record to indicate the storage location of the third data record in the memory subsystem.

[0036] To group data records each containing specific data fields, the memory subsystem (e.g., the memory controller) may store the corresponding index entries in the index entry positions of the corresponding index table. For example, in the postal code index table, the memory subsystem may store the first postal code index entry at the first index entry position and the second postal code index entry at the second index entry position. Additionally or alternatively, the memory subsystem may store the third postal code index entry at the third index entry position in the postal code index table.

[0037] As described above, in some embodiments, the index table may be stored in an index table memory array (e.g., different from (e.g., separate from) one or more main memory arrays implemented in the memory subsystem). In fact, in some embodiments, the index table memory array may be implemented using a memory type different from the main memory array. For example, the index table memory array may be implemented using a relatively fast memory type (e.g., static random access memory (SRAM)), while the main memory array is implemented using a relatively slow memory type (e.g., dynamic random access memory (DRAM)).

[0038] Furthermore, in some embodiments, the index table memory array may be implemented such that each index table is stored in a corresponding row of memory cells. For example, the postal code index table may be stored in the first row of memory cells of the index table memory array, while the street address index table is stored in the second row of memory cells of the index table memory array. Additionally, in some embodiments, the index table memory array may be implemented such that each index table entry is stored in a corresponding column of memory cells. In other words, the memory cell at each row address and column address pair in the index table memory array may be implemented as an index table entry position. For example, the first index entry position of the postal code index table may be implemented at the first column of the first row of memory cells, and the second index entry position of the postal code index table may be implemented at the second column of the first row of memory cells.

[0039] In any case, by traversing the index entries included in the index table, a memory subsystem (e.g., a memory controller) can identify data records each of which includes a corresponding data field. For example, the memory subsystem can read the first index entry position in the zip code index table to determine the first zip code index entry, read the second index entry position in the zip code index table to determine the second zip code index entry, and so on. Additionally, the memory subsystem can read the first pointer included in the first zip code index entry that indicates the storage location of the first data record to identify the first data record and thus identify that the first data record includes a zip code field. Similarly, the memory subsystem can read the second pointer included in the second zip code index entry that indicates the storage location of the second data record to identify the second data record and thus identify that the second data record includes a zip code field. Additionally or alternatively, the memory subsystem can read the third pointer included in the third zip code index entry that indicates the storage location of the third data record to identify the third data record and thus identify that the third data record includes a zip code field.

[0040] To facilitate access (e.g., read and / or write) to index table entries, in some embodiments, the memory subsystem can include entry cells each of which is coupled to a respective memory cell column of the index table memory array via a corresponding column amplifier. In other words, the first entry cell can be coupled to the first memory cell column of the index table memory array, the second entry cell can be coupled to the second memory cell column of the index table memory array, and so on. Additionally, in some embodiments, each entry cell can be implemented with a register (e.g., 64 bytes) such that the entry cell reads (e.g., retrieves) an index entry from the index table memory array and / or writes (e.g., stores) an index entry to the index table memory array.

[0041] In some embodiments, in addition to the storage location of the corresponding data record, the index entry can indicate the value of one or more data fields included in the data record. For example, the first zip code index entry can include the first zip code value indicated by the zip code field of the first data record, and the second zip code index entry can include the second zip code value indicated by the zip code field of the second data record. Additionally or alternatively, the third zip code index entry can include the third zip code value indicated by the zip code field of the third data record.

[0042] In some embodiments, including data field values in index entries can enable a memory subsystem (e.g., a memory controller) to adaptively (e.g., dynamically) adjust the interrelationship between data records by merely adjusting the order of the index entries (e.g., the index entry positions) in an index table (e.g., without adjusting the corresponding data records). In particular, the memory subsystem can sort the index entries such that the data field values indicated by the index entries are in ascending order, descending order, or any other suitable order. For example, when sorted in descending order, the memory subsystem can indicate that an index entry contains the largest data field value in the first index entry position of the corresponding index table, and so on, where the index entry contains the smallest data field value in the last index entry position.

[0043] On the other hand, when sorted in ascending order, the memory subsystem can indicate that an index entry contains the smallest data field value in the first index entry position of the corresponding index table, and so on, where the index entry contains the largest data field value in the last index entry position. For example, when sorted in ascending order, when the value of the first postal code field is "83704" and the value of the second postal code field is "83707", the first postal code index entry can be indicated at the first index entry position, and the second postal code index entry can be indicated at the second (e.g., last) index entry position. Additionally or alternatively, when sorted in ascending order, when the value of the third postal code field is "83713", the third postal code index entry can be indicated at the third index entry position.

[0044] To facilitate the generation of index entries, in some embodiments, the memory subsystem can provide an application programming interface (API) that includes an allocation function. In some embodiments, the input parameters (e.g., operators) of the allocation function can include pointers to the storage locations of one or more blocks of data records in the memory subsystem, the number of data records included in the blocks, the size of each data record, the number of data fields to be indexed, and / or the specific data fields to be indexed. In other words, the input parameters of the allocation function (e.g., the size of the data records, the number of data fields to be indexed, and / or the number of specific data fields to be indexed) can be determined at least in part based on the parameters of the data structure implemented by the data records.

[0045] In some embodiments, the data structure of the data record can be predefined, such that an indication of the data structure is pre-stored in the memory subsystem. Additionally or alternatively, the data structure of the data record can be explicitly indicated, for example, via metadata (e.g., header data) included with the data record and / or a separate control signal (e.g., a command or request) received with the data record. In any case, by executing an allocation function, the memory subsystem can allocate a storage location (e.g., the starting storage location of a block + (the number of data records in the block * the size of each data record)) indicated by the input parameters to store one or more data records utilizing the data structure.

[0046] Furthermore, to facilitate inclusion of an index entry in the index table, the memory subsystem can process (e.g., analyze, evaluate, and / or adjust) the index entry, for example, by comparing the index entry with another index entry already included in the index table. Thus, in some embodiments, the memory subsystem is implemented with processing circuitry, such as in a memory controller and / or other processing circuitry different (e.g., separate) from the processing subsystem. However, to enable more complex data processing operations, the processing circuitry is typically more highly doped (compared to the memory circuitry). Additionally, a higher degree of doping generally increases the likelihood of generating leakage current, which in at least some instances can affect the operational reliability of the memory subsystem, for example, by causing corruption of the data stored in the memory subsystem.

[0047] Thus, in some embodiments, the memory subsystem can be implemented with limited processing capabilities, for example, compared to a processing subsystem and / or a processor-in-memory (PIM). In some embodiments, the processing performed by the memory subsystem can be implemented with comparison logic circuitry. For example, an entry unit coupled to an index table memory array can include comparison logic circuitry implemented to compare a data field value stored in its register with an input data field value (e.g., included in a different index entry). In some embodiments, the comparison logic circuitry can indicate whether the data field value stored in the register of the entry unit is greater than the input data field value. Additionally or alternatively, the comparison logic circuitry can indicate whether the data field value stored in the register of the entry unit is less than the input data field value.

[0048] To facilitate sorting, adjacent item units can be communicatively coupled, for example such that a first item unit shifts an index item stored in its register to a second item unit. As described above, the index items included in the index table can be sorted such that the data field values indicated by the index items are in ascending order, descending order, or any other suitable order. For example, when sorting in ascending order and a new (e.g., input) postal code index item indicates that the new postal code field value is "83706", the first item unit can compare the postal code field value indicated by the new postal code index item with the first postal code index item stored at the first index item position of the postal code index table. When the first postal code index item indicates that the first postal code field value is "83704", the first item unit can determine that the new postal code field value indicated by the new postal code index item is greater than the first postal code field value indicated by the first postal code index item.

[0049] Additionally, for example, after the first item unit determines that the new postal code field value is greater than the first postal code field value, the second item unit can compare the postal code field value indicated by the new postal code index item with the second postal code index item stored at the second index item position of the postal code index table. When the new postal code index item indicates that the new postal code field value is "83706" and the second postal code index item indicates that the second postal code field value is "83707", the second item unit can determine that the new postal code field value is not greater than the second postal code field value. Thus, the second item unit can shift the second postal code index item to a third item unit coupled to the third index item position in the postal code index table, thereby shifting the second postal code index item from the second index item position to the third index item position.

[0050] In a similar manner, downstream item units can compare and / or shift index items. For example, a third index item unit can compare the postal code field value indicated by a second (e.g., input) postal code index item with the third postal code index item stored at the third index item position of the postal code index table. When the second postal code index item indicates that the value of the second postal code is "83707" and the third postal code index item indicates that the third postal code field value is "83713", the third item unit can determine that the second postal code password field value is not greater than the third postal code field value. Thus, the third item unit can shift the third postal code index item to a fourth item unit coupled to the fourth index item position in the postal code index table, thereby shifting the third postal code index item from the third index item position to the fourth index item position.

[0051] However, in some embodiments, storing an index entry in an entry unit may overwrite an index entry previously stored in the entry unit, e.g., due to the size of its buffer relative to the size of the index entry. Thus, in some embodiments, the entry unit may store the index entry in its register after the index entry previously stored in its register has been output to, e.g., another entry unit and / or an index table memory array. In other words, continuing with the above example, after the second postal code index entry has been shifted to the third entry unit, the second entry unit may store the new postal code index entry in its register; after the third postal code index entry has been shifted to the fourth entry unit, the third entry unit may store the second postal code index entry in its register; and so on.

[0052] To reduce the likelihood that the address management function impacts data retrieval latency, in some embodiments, a memory subsystem (e.g., a memory controller) may index data records without the processing subsystem targeting the data records. For example, the memory subsystem may index data records in response to the data records being written to the main memory array (e.g., a memory channel) of the memory subsystem. In other words, the memory subsystem may perform the indexing operation in a timely manner to reduce the likelihood that the indexing operation latency will return targeted data to the processing subsystem, which, at least in some instances, may facilitate improving the operational efficiency of the computing system.

[0053] In addition, implementing the address management function in this manner may facilitate reducing the amount of data communicated between the processing subsystem and the memory subsystem, e.g., to request data from multiple data records and / or return targeted data. In particular, in some embodiments, implementing the address management function in this manner may cause the memory subsystem to return only the targeted portions (e.g., one or more data fields) of one or more data records, which, at least in some instances, may facilitate reducing data communication from the memory subsystem to the processing system via the system bus. Additionally or alternatively, implementing the address management function in this manner may cause the processing subsystem to use fewer memory access requests to request data from multiple data records, which, at least in some instances, may facilitate reducing data communication from the processing subsystem to the memory subsystem via the system bus.

[0054] For example, instead of requesting data from multiple data records individually (e.g., sequentially), the processing subsystem may output a single memory access request that identifies the target data. In some embodiments, to access multiple data records in sorted order, the processing subsystem may output a memory access request that identifies a target access index and one or more target index entry positions included in a target index table. For example, the processing subsystem may output a memory access request that identifies the postal code field as the target access index and a vector [N,M] that identifies the target index entry positions.

[0055] Based on the target access index, a memory subsystem (e.g., a memory controller) can identify a corresponding index table. For example, when the target access index is a zip code field, the memory controller can identify a zip code index table. Additionally or alternatively, when the target access index is a name field, the memory controller can identify a name index table.

[0056] To facilitate identifying the target index table, in some embodiments, the memory subsystem can provide an application programming interface (API) that includes a sorted access function. In some embodiments, the input parameters (e.g., operators) of the sorted access function can include pointers to the storage locations of one or more blocks of data records in the memory subsystem and the specific data fields to be indexed. Additionally, by executing the sorted access function, the memory subsystem can determine, for example, a sorted access pointer that indicates the storage location of the corresponding index table in the index table memory array. In other words, to facilitate identifying the target index table, the memory subsystem can determine a sorted access pointer corresponding to the target access index indicated by the memory access request.

[0057] Additionally, at least in part based on the memory access request, the memory subsystem (e.g., the memory controller) can identify which index entry positions in the target index table are to be read. For example, when the memory access request includes a vector [M, N], the memory subsystem can determine that the index entries are to be read from the (M + 1)-th index entry position to the (N + 1)-th index entry position in the target index table. As an illustrative example, when the memory access request includes a vector [0, 1], the memory subsystem can determine that the indices are to be read from the first index entry position and the second index entry position of the identified index table.

[0058] Furthermore, at least in part based on the index entries stored at the identified index entry positions, the memory subsystem (e.g., the memory controller) can identify (e.g., retrieve) the corresponding data records. For example, at least in part based on a first zip code index entry, the memory subsystem can identify a first data record. Similarly, at least in part based on a second zip code index entry, the memory subsystem can identify a second data record. In this way, the processing subsystem can request access to multiple data records in sorted order using fewer memory access requests, which, at least in some instances, can facilitate reducing data communication from the processing subsystem to the memory subsystem via the system bus.

[0059] In addition, in some embodiments, the processing subsystem may target specific portions or subsets (e.g., one or more data fields) from a plurality of data records stored, for example, as contiguous blocks in a main memory array. To access a specific portion of the plurality of data records, in some embodiments, the processing subsystem may output a memory access request that identifies the storage location of the block of data records and the targeted portion of each data record. For example, the processing subsystem may output a memory access request that identifies a block of memory addresses in the main memory array and identifies a targeted zip code field.

[0060] To facilitate access to the targeted portions of the plurality of data records, in some embodiments, the memory subsystem may provide an application programming interface (API) that includes a strided access function. In some embodiments, the input parameters (e.g., operators) of the strided access function may include pointers to the storage locations of blocks of one or more data records in the memory subsystem, the starting bit position of the target data field within the data record, the size of the target data field, and the stride length between consecutive data records. Thus, in some embodiments, the input parameters of the strided access function (e.g., the starting bit position of the target data field within the data record, the size of the target data field, and / or the stride length between consecutive data records) are determined at least in part based on the data structure of the data records.

[0061] Additionally, by executing the strided access function, the memory subsystem may determine a strided access pointer that indicates, for example, the storage locations of the targeted portions of the plurality of data records. In other words, using the strided access pointer, the memory subsystem may identify (e.g., retrieve) the targeted portions of the plurality of data records. In this way, the processing subsystem may request access to specific portions of the plurality of data records (e.g., in address order) using fewer memory access requests, which in at least some instances may facilitate reducing data communication from the processing subsystem to the memory subsystem via the system bus.

[0062] As described above, after identifying the targeted data, the memory subsystem may output (e.g., return) the targeted data to the processing subsystem via the system bus, for example, for processing and / or execution by processing circuitry implemented in the processing subsystem. In fact, in some embodiments, providing strided access to the stored data may also facilitate reducing data communication from the memory subsystem to the processing subsystem via the system bus. For example, by providing strided access, the memory subsystem may output only the targeted portions of the data records rather than outputting the entire data records (which include data other than the targeted portions).

[0063] In any case, data communication between different computing subsystems is generally slower than data communication within a computing subsystem, for example due to the timing of different computing subsystems, the system bus being shared with other computing subsystems, and / or the communication distance between different subsystems. In other words, data communication within a processing subsystem (e.g., its interior) can be faster than data communication between a processing subsystem and a memory subsystem. Thus, to facilitate improved operational efficiency, one or more caches can be implemented in the processing subsystem. For example, the processing subsystem can be implemented with one or more processor-side caches (e.g., L1 cache, L2 cache, and / or L3 cache integrated with the processing circuitry).

[0064] To facilitate utilization of the faster data communication provided by the cache, in some embodiments, the memory subsystem can store targeted data directly into the processor-side cache. In fact, in some embodiments, the memory subsystem can automatically store targeted data directly into a higher-level (e.g., shared) processor-side cache (e.g., L3 cache). In other words, in these embodiments, the memory subsystem can store the data targeted by a memory access request directly into the processor-side cache in response to the memory access request (e.g., without additional instructions from the processing subsystem).

[0065] In fact, in some embodiments, the memory subsystem can return the targeted data indeterminately, for example, in an out-of-order manner. Thus, when implemented to store targeted data directly into the processor-side cache, the memory subsystem can output a control signal to the processing subsystem that indicates when the targeted data is stored into the processor-side cache. In some embodiments, the memory subsystem can output a control signal whenever the target data from a data record is successfully stored in the processor-side cache. Additionally or alternatively, the memory subsystem can output a control signal after all of the target data identified by a memory access request has been successfully stored in the processor-side cache.

[0066] To facilitate further utilization of the faster data communication provided by the cache, in some embodiments, a memory subsystem (e.g., a memory controller) may predictively identify data (e.g., data records or data fields) expected to be subsequently targeted by a processing subsystem. In other words, the memory subsystem may predict the data access patterns expected to occur subsequently and thus preemptively identify the data, which in some embodiments may enable the memory subsystem to directly store the target data into the processor-side cache even before the processing subsystem targets the data. Thus, when the processing circuitry actually targets the data (e.g., for processing and / or execution), the processing subsystem may determine that the target data is already stored in the processor-side cache and thus provide the target data to the processing circuitry, e.g., via the processor-side cache, rather than requesting the target data from the memory subsystem and waiting for the return of the target data.

[0067] In some embodiments, the memory subsystem (e.g., a memory controller) may predict what data will be subsequently targeted at least in part based on what data the processing subsystem is currently targeting and / or in what order the data is being targeted. As described above, the processing subsystem may target data from multiple data records, e.g., via a single memory access request. Thus, in some embodiments, the memory subsystem may determine the data access pattern that results in data from multiple data records being targeted and extrapolate the data access pattern to predict what data the processing subsystem will subsequently target.

[0068] For example, when a memory access request targets the vector [0,1] of index entry positions, the memory subsystem may predict that the processing subsystem will subsequently target the index entries at the third and fourth index entry positions. In other words, in this way, the memory subsystem may identify the target index entries and the corresponding data records before the processing subsystem actually requests the data. Indeed, in some embodiments, the memory subsystem may preemptively store directly into the processor-side cache the data records expected to be subsequently targeted by the processing subsystem, which in at least some instances may facilitate reducing data retrieval latency.

[0069] In addition, in some embodiments, a memory subsystem (e.g., a memory controller) may predict what data will be targeted subsequently based at least in part on a data structure of data records stored in the memory subsystem. As described in the above illustrative example, the first data record data structure may allocate bits [0,X] for indicating a name field, bits [X+1,Y] for indicating a street address field, and bits [Y+1,Z] for indicating a postal code (e.g., third) field. Thus, when a memory access request targets the street address field, for example, since the first data record data structure directly allocates bit positions after the street address field for indicating the postal code, the memory subsystem may predict that the processing subsystem will subsequently target the postal code field. In this way, the memory subsystem may identify the target portion of the data record before the processing subsystem actually requests it. In fact, in some embodiments, the memory subsystem may preemptively store directly into the processor-side cache the portion of the data record expected to be targeted by the processing subsystem subsequently.

[0070] In other words, as will be described in more detail below, the present disclosure describes techniques for implementing and / or operating a memory subsystem such that data records may be stored in a main memory array while index entries (e.g., metadata) associated with the data records are stored in a particular portion of the memory subsystem, such as an index table memory array that manages the metadata using advanced lookup techniques. In some embodiments, this may enable the memory subsystem to perform important (e.g., advanced) memory addressing operations on behalf of the processing subsystem. For example, the memory subsystem may implement a forward caching technique by which the memory subsystem anticipates (e.g., predicts) upcoming memory access requests from the processing subsystem and prepares the data expected to be requested prior to the memory access request. Thus, at least in some instances, implementing and operating the memory subsystem in this way may facilitate improved operation (e.g., power and / or communication) efficiency, for example, by alleviating the burden on the processing subsystem in address calculation and / or reducing the effective data retrieval latency experienced by the processing subsystem.

[0071] Additionally or alternatively, the memory subsystem may implement a fast (e.g., improved) forward caching technique by which the memory subsystem asynchronously transfers the requested data to the processing subsystem. In some embodiments, based on the forward caching technique, the memory subsystem may preemptively transfer the data expected to be targeted by an anticipated memory access request to the processing subsystem, thereby delivering the data expected to be requested by the processing subsystem prior to the memory access request. Thus, at least in some instances, implementing and operating the memory subsystem in this way may further facilitate improved operation (e.g., power and / or communication) efficiency, for example, by further reducing the effective data retrieval latency experienced by the processing subsystem (e.g., reducing it to zero in an ideal case).

[0072] In addition, as will be described in more detail below, an application programming interface (API) can provide tools (e.g., functions) to facilitate support for advanced memory addressing techniques such as forward caching techniques and / or fast forward caching techniques. In some embodiments, programming techniques can cover different memory access patterns abstracted under the concept of an access axis. For example, the access axis can provide sufficient information (e.g., metadata) to enable the memory subsystem to access the stored data in a direct (e.g., address) order, a stride order, and / or a sorted order. In any case, at least in some instances, implementing and operating the computing system in this manner can facilitate improved operation (e.g., power and / or communication) efficiency, such as by reducing data retrieval latency, reducing data communication via the system bus, and / or increasing the communication bandwidth available to other computing subsystems.

[0073] For purposes of illustration, an example of a computing system 10 (e.g., a device) that includes a processing subsystem 12 and a memory subsystem 14 is shown in Figure 1 . It should be understood that the depicted embodiments are intended to be illustrative only and not restrictive. In particular, the computing system 10 can additionally or alternatively include other computing subsystems. For example, the computing system 10 can additionally include a networking subsystem, a radio frequency subsystem, a user input subsystem, and / or a display subsystem.

[0074] In addition, in some embodiments, the computing system 10 can be implemented in a single electronic device, such as a desktop computer, a workstation computer, a laptop computer, a server, a mobile phone, a virtual reality headset, etc. In other embodiments, the computing system 10 can be distributed among multiple electronic devices. For example, the processing subsystem 12 and the memory subsystem 14 can be implemented in a host device, while other computing subsystems (e.g., a user input subsystem and / or a display subsystem) can be implemented in a client (e.g., remote) device. In fact, in some embodiments, the computing subsystems can be distributed among multiple electronic devices. For example, a first portion of the processing subsystem 12 and / or a first portion of the memory subsystem 14 can be implemented in a host device, while a second portion of the processing subsystem 12 and / or a second portion of the memory subsystem 14 can be implemented in a client device.

[0075] In any case, the processing subsystem 12 generally performs various operations during the operation of the computing system 10, such as determining output data by performing corresponding operations on input data by executing instructions. Thus, as in the depicted example, the processing subsystem 12 can include processing circuitry 16. In some embodiments, the processing circuitry 16 can include one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more processor cores, or any combination thereof.

[0076] In addition, as described above, the memory subsystem 14 generally stores data accessible by the processing subsystem 12, such as data including output data, input data, and / or data indicating executable instructions. Thus, as in the depicted example, the memory subsystem 14 can include one or more memory devices 18 (e.g., chips or integrated circuits). As will be described in more detail below, in some embodiments, the memory device 18 can include memory cells (e.g., circuitry) organized into one or more memory arrays and can thus include one or more tangible non-transitory computer-readable media. For example, the memory subsystem 14 can include one or more volatile memory devices (e.g., dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices) and / or one or more non-volatile memory devices (e.g., flash (e.g., NAND) memory devices, phase change memory (e.g., 3D XPoint TM ) memory devices, ferroelectric random access memory (FeRAM) devices, or any combination thereof).

[0077] In addition, in some embodiments, multiple memory devices 18 can be implemented on a memory module (e.g., a dual in-line memory module (DIMM) or a single in-line memory module (SIMM)). For example, the memory module can include a printed circuit board (PCB) and multiple memory devices, each memory device disposed on a flat or planar (e.g., front or back) surface of the printed circuit board. Additionally, the memory device 18 can be coupled to external pins formed along an edge (e.g., bottom) of the printed circuit board via conductive traces formed on the printed circuit board.

[0078] It should be understood that other packaging techniques can be used to implement one or more memory devices 18. For example, the memory device 18 can be coupled to a semiconductor (e.g., silicon) interposer to implement a 2.5D configuration. Additionally or alternatively, the memory devices 18 can be stacked to implement a 3D configuration. Further, in some embodiments, organic packaging techniques can be used to implement the memory device 18. In other words, the techniques described in this disclosure can be implemented as an on-package solution.

[0079] In any case, as described above, the memory subsystem 14 generally stores data accessible to the processing subsystem 12. To facilitate data communication, the memory subsystem 14 and the processing subsystem 12 can communicate via a system bus 20 (e.g., including one or more data buses). In some embodiments, the system bus 20 can include one or more cables, one or more wires, one or more conductive traces, one or more communication networks, or any combination thereof, and can thus be implemented to provide limited communication bandwidth. In any case, via the system bus 20, the processing subsystem 12 can communicate (e.g., output) data to be stored in the memory subsystem 14. Additionally or alternatively, via the system bus 20, the memory subsystem 14 can communicate (e.g., output) data for processing and / or execution by the processing subsystem 12, e.g., in response to a request for data targeted by the processing circuitry 16 of the processing subsystem 12.

[0080] However, as described above, data communication between different computing subsystems is generally slower than data communication within a computing subsystem. In other words, data communication within the processing subsystem 12 (e.g., internally) can be faster compared to data communication between the processing subsystem 12 and the memory subsystem 14, and thus helps reduce data retrieval latency, which is due, for example, to the system bus 20 being shared with other computing subsystems, timing differences between the processing subsystem 12 and the memory subsystem 14, and / or the communication distance between the processing subsystem 12 and the memory subsystem 14. Therefore, to facilitate improved operational efficiency, a cache can be implemented between the processing circuitry 16 of the processing subsystem 12 and the memory device 18 of the memory subsystem 14, e.g., to store instances (e.g., copies) of data that is also stored in the memory device 18.

[0081] As in the depicted example, the cache can include one or more processor - side caches 22 implemented in the processing subsystem 12. In some embodiments, one or more processor - side caches 22 can be integrated with the processing circuitry 16. For example, the processor - side cache 22 can include an L1 cache, an L2 cache, and / or an L3 cache. To facilitate reducing data retrieval latency, in some embodiments, different memories can be used to implement the processor - side cache 22 compared to the memory device 18 implemented in the memory subsystem 14. For example, the processor - side cache 22 can be implemented with static random - access memory (SRAM), while the memory device 18 is implemented with dynamic random - access memory (DRAM) and / or non - volatile memory.

[0082] To facilitate control of data storage in cache and / or memory device 18, computing system 10 may include one or more memory controllers 26 (e.g., which are communicatively coupled to cache and / or memory device 18 via instruction bus 20A). In some embodiments, one or more memory controllers 26 may be implemented in memory subsystem 14, such as as a memory-side memory controller 26. Additionally or alternatively, one or more memory controllers 26 may be implemented in processing subsystem 12, such as as a processor-side memory controller 26.

[0083] For purposes of illustration, an example of processing subsystem 12A that includes processor-side memory controller 26A is shown in Figure 2 . As described above, processing circuitry 16 may be implemented using one or more processor cores 28. For example, as in the depicted embodiment, processing circuitry 16A of processing subsystem 12A may include first processor core 28A and Nth processor core 28N.

[0084] Additionally, as in the depicted embodiment, the cache may be hierarchically organized into different cache levels 30. For example, processor-side cache 22A may be organized as a first (e.g., lower) cache level 30A and a Kth (e.g., higher) cache level 30K, which may be communicatively coupled to the memory system via system bus 20. In some embodiments, processor-side cache 22A may be implemented using volatile memory (e.g., static random access memory (SRAM) and / or dynamic random access memory (DRAM)).

[0085] Additionally, in some embodiments, processor-side cache 22A implemented at first cache level 30A may be dedicated to a corresponding processor core 28. In other words, in these embodiments, the first-level cache 30A may be implemented using one or more dedicated processor-side caches 32. For example, first processor-side cache 32A implemented at first cache level 30A may be dedicated to first processor core 28A, and Nth dedicated processor-side cache 32N implemented at first cache level 30A may be dedicated to Nth processor core 28N. In other words, in some embodiments, dedicated processor-side cache 32 implemented at first cache level 30A may include one or more L1 caches.

[0086] In some embodiments, higher cache levels may also be implemented using one or more dedicated processor-side caches 32. For example, a second cache level 30 may be implemented using another dedicated processor-side cache 32 dedicated to first processor core 28A and another dedicated processor-side cache 32 dedicated to Nth processor core 28N. In other words, in some embodiments, dedicated processor-side cache 32 implemented at second cache level 30 may include one or more L2 caches.

[0087] Additionally or alternatively, a processor-side cache 22 implemented at a higher cache level can be shared among multiple processor cores 28. For example, in the depicted embodiment, the Kth cache level 30K can be implemented with a shared processor-side cache 34 shared by the first processor core 28A and the Nth processor core 28N. In other words, in some embodiments, the shared processor-side cache 34 implemented at the Kth cache level 30K can include an L3 cache.

[0088] In any case, as described above, caches generally provide faster data access (e.g., read and / or write) speeds compared to the main memory array implemented in the memory devices 18 of the memory subsystem 14. However, the storage capacity of a cache is typically smaller than the storage capacity of the main memory array. In fact, in some embodiments, the total storage capacity of the processor-side cache 22A can be smaller than the storage capacity of one or more main memory arrays.

[0089] Accordingly, to facilitate improved data access speed and thus improved operational efficiency of the computing system 10, the processor-side memory controller 26A can control data storage in the processor-side cache 22A at least in part based on when data is expected to be targeted (e.g., requested) by the processing circuitry 16A. For example, the processor-side memory controller 26A can control data storage such that an instance (e.g., copy) of data expected to be targeted by the processing circuitry 16A is stored in one or more of the processor-side caches 22A before the processing circuitry 16A actually targets the data. On the other hand, to facilitate conserving (e.g., optimizing) the storage capacity of the processor-side cache 22A, the processor-side memory controller 26A can control data storage such that instances of data blocks 29 not expected to be targeted by the processing circuitry 16A during an upcoming control time domain (e.g., duration) are not stored in the processor-side cache 22A.

[0090] In addition, in some embodiments, data storage in the processor-side cache 22A can be controlled at least in part based on hierarchical cache levels. For example, the processor-side memory controller 26A can be implemented to exclusively control data storage for a lower cache level 30 (e.g., the first cache level 30A). On the other hand, in some embodiments, the processor-side memory controller 26A can share control of data storage for a higher cache level 30 (e.g., the Kth cache level 30K) with, for example, the memory-side memory controller 26. As will be described in more detail below, sharing control of data storage for the cache levels 30 can facilitate improved operational efficiency of the computing system 10, at least in some instances, such as by causing the memory subsystem 14 to directly and / or predictively store data into the processor-side cache 22.

[0091] In Figure 3An example of a process 46 for operating a memory controller 26 (e.g., a processor-side memory controller 26A) is described. Generally, process 46 includes determining data targeted by processing circuitry (process block 48), determining whether the target data results in a processor-side cache miss (decision block 50), and providing the target data to the processing circuitry (process block 52). Additionally, when the target data results in a processor-side cache miss, process 46 includes requesting the target data from the memory subsystem (process block 56) and determining whether the target data has been received from the memory subsystem (decision block 58).

[0092] Although described in a particular order representing a particular embodiment, it should be noted that process 46 can be performed in any suitable order. Additionally, embodiments of process 46 can omit process blocks and / or include additional process blocks. Further, in some embodiments, process 46 can be implemented at least in part by executing instructions stored in a tangible non-transitory computer-readable medium (e.g., a memory implemented in the memory controller 26) using processing circuitry (e.g., a processor implemented in the memory controller 26).

[0093] Thus, in some embodiments, the memory controller 26 (e.g., the processor-side memory controller 26A) can determine data targeted by the processing circuitry 16 of the computing system 10 (e.g., a data record or one or more data fields) (process block 48). In some embodiments, the processing circuitry 16 can identify the target data using, for example, a corresponding (e.g., target) virtual memory address included in a memory access request. At least partially based on the target virtual memory address, the memory controller 26 can determine the corresponding (e.g., target) physical memory address, which indicates the storage location of the target data in the computing system 10.

[0094] Additionally, the memory controller 26 can determine whether the target data results in a processor-side cache miss (decision block 50). In some embodiments, the memory controller 26 can determine whether the data is stored in the cache at least partially based on the virtual memory address and / or physical memory address associated with the data. For example, at least partially based on its virtual memory address and physical memory address, the memory controller 26 can determine a target value expected to be the tag metadata associated with the target data.

[0095] By searching the processor-side cache 22 based on the target tag metadata value, the memory controller 26 can determine whether the target data causes a processor-side cache miss. For example, when the target tag metadata value does not match the tag metadata 33 included in any of the processor-side caches 22, the memory controller 26 can determine that the target data causes a processor-side cache miss. On the other hand, when the tag metadata 33 is included in one or more of the processor-side caches 22, the memory controller 26 can determine that the target data causes a processor-side cache hit and thus does not cause a processor-side cache miss.

[0096] When the target data does not cause a processor-side cache miss, the memory controller 26 can instruct the processor-side cache 22 to supply the target data to the processing circuitry 16 to facilitate improving the data retrieval speed and thus the operating efficiency of the computing system 10 (process block 52). In some embodiments, the processor-side cache 22 can output a cache line with tag metadata that matches the target tag metadata value expected to be associated with the target data. In some embodiments, when stored at a higher (e.g., the Kth) cache level 30, the target data can pass through one or more lower (e.g., the first) cache levels before reaching the processing circuitry 16.

[0097] On the other hand, when it causes a processor-side cache miss, the memory controller 26 can request the target data from the memory subsystem 14 of the computing system 10 (process block 56). In some embodiments, the memory controller 26 can instruct the memory subsystem 14 to retrieve the target data by outputting a memory access request identifying the target data. To facilitate improving the operating efficiency of the computing system 10, in some embodiments, the memory controller 26 can instruct the memory subsystem 14 to retrieve the target data from multiple data records stored in the memory subsystem 14 via a single memory access request.

[0098] For example, to access multiple data records in sorted order, the memory controller 26 can output a memory access request for a vector [N, M] identifying the target access index and the target index item position (process block 60). Additionally or alternatively, to access a specific portion (e.g., one or more data fields) of a data record block (e.g., in address order), the memory controller 26 can output a memory access request identifying the storage location of the data record block and the targeted portion of each data record (process block 62). In any case, based at least in part on the memory access request, the memory subsystem 14 can identify the target data, for example, via the memory-side memory controller 26 implemented in the memory subsystem 14.

[0099] For purposes of illustration, in Figure 4An example of a memory subsystem 14A that includes a memory - side memory controller 26B is shown. As described above, in some embodiments, the memory devices 18 implemented in the memory subsystem 14 may include volatile memory and / or non - volatile memory 64. For example, the non - volatile memory 64 may include one or more flash (e.g., NAND) memory devices 18A, one or more phase - change memory (e.g., 3D XPoint TM ) memory devices 18A, one or more ferroelectric random - access memory (FeRAM) devices 18A, or any combination thereof. Additionally or alternatively, the volatile memory may include one or more dynamic random - access memory (DRAM) devices 18A and / or one or more static random - access memory (SRAM) devices 18A.

[0100] Furthermore, as described above, the volatile memory implemented in the memory subsystem 14 may be organized into one or more memory arrays. For example, as will be described in more detail below, the memory subsystem 14 may utilize an index - table memory array. Additionally, as in the depicted embodiment, the memory subsystem 14A may include one or more main memory arrays 66, e.g., separate (e.g., different) from the index - table memory array.

[0101] Moreover, as in the depicted embodiment, the main memory array 66 may be implemented in each memory channel 68 in the memory subsystem 14A. For example, a first main memory array 66 may be implemented in a first memory channel 68A, and an Mth main memory array 66 may be implemented in an Mth memory channel 68M. To facilitate access to its main memory array 66 (e.g., read from and / or write to it), as in the depicted embodiment, the memory channel 68 may include, for example, a row - selection (e.g., decoder) circuit system 70 and a column - selection circuit system 72 that are respectively coupled to the rows and columns of the main memory array 66.

[0102] For purposes of illustration, an example of a memory array 66A that can be used to implement the main memory array 66 in the memory channel 68 is shown in Figure 5 . As in the depicted example, the memory array 66A may include memory cells 74 coupled to word lines 76 formed in a first (e.g., horizontal) direction. In other words, a row of memory cells 78 may include each memory cell 74 coupled to a corresponding word line 76. For example, a first row of memory cells 78A may include each memory cell 74 coupled to a first word line 76A, a second row of memory cells 78B may include each memory cell 74 coupled to a second word line 76B, and so on, where an Hth row of memory cells 78H includes each memory cell 74 coupled to an Hth word line 76H.

[0103] Additionally, as in the depicted example, memory cell 74 may be coupled to column amplifier 80 via bit lines 82 formed in a second (e.g., vertical) direction. In other words, memory cell column 84 may include each memory cell 74 coupled to a corresponding column amplifier 80. For example, first memory cell column 84A may include each memory cell 74 coupled to first column amplifier 80A via first bit line 82A, second memory cell column 84B may include each memory cell 74 coupled to second column amplifier 80B via second bit line 82B, and so on, with the Wth memory cell column 84W including each memory cell 74 coupled to the Wth column amplifier via the Wth bit line 82W.

[0104] In any case, memory cell 74 generally includes a switching component (e.g., a metal-oxide semiconductor field-effect transistor (MOSFET)) and a storage component (e.g., a capacitor). For example, memory cell 74 may be implemented such that its MOSFET is coupled between bit line 82 and its storage capacitor, and the gate of its MOSFET is coupled to word line 76. Thus, in some embodiments, each memory cell 74 may be used to store one bit of data. For example, when the charge stored in memory cell 74 results in a voltage greater than the threshold voltage, memory cell 74 may indicate a 1 bit, and when the charge stored in memory cell 74 results in a voltage less than the threshold voltage, the memory cell may indicate a 0 bit. In other embodiments, memory cell 74 may be implemented to store multiple bits of data. For example, memory cell 74 in a quad-level cell (QLC) NAND memory may be implemented to store two bits of data.

[0105] In any case, as in the depicted embodiment, memory cells 74 in memory array 66A may be grouped into storage locations for storing data records (e.g., blocks) 86. For example, first data record 86A may be stored at a storage location including memory cells 74 in first memory cell row 78A and first memory cell column 84A, second data record 86B may be stored at a second storage location including memory cells 74 in second memory cell row 78B and first memory cell column 84A, and so on. In other words, in some embodiments, multiple data records 86 may be stored in memory array 66A as (e.g., consecutive) blocks (e.g., at consecutive memory addresses).

[0106] Additionally or alternatively, one or more data records 86 may be stored at discontinuous memory addresses (e.g., in a sparse array). For example, the R-th data record 86R may be stored at the R-th storage location of the memory cells 74 included in the first memory cell row 78A and the second memory cell column 84B, and / or the W-th data record 86W may be stored at the W-th storage location of the memory cells included in the H-th memory cell row 78H and the W-th memory cell column 84W. To facilitate access to the storage locations in the memory array 66A, the memory cell rows 78 may each be identified via a corresponding row address (e.g., a physical memory address), and the memory cell columns 84 may each be identified via a column address (e.g., a physical memory address).

[0107] Additionally, to facilitate access to the storage locations in the memory array 66A, as described above, the row selection circuitry 70 may be connected to the rows of the memory array 66A. In other words, the row selection circuitry 70 may be coupled to the first memory cell row 78A via the first word line 76A, to the second memory cell row 78B via the second word line 76B, and so on, and the row selection circuitry 70 is coupled to the H-th memory cell row 78H via the H-th word line 76H. Thus, to effect a read and / or write to the memory cell 74, the row selection circuitry 70 may activate the memory cell 74, for example, by outputting an activation (e.g., logic high) signal via the corresponding word line 76, which causes the switching component of the memory cell 74 to electrically couple the storage component of the memory cell 74 to the corresponding bit line 82.

[0108] Furthermore, as described above, the column selection circuitry 72 may be coupled to the columns of the memory array 66A. In other words, the column selection circuitry 72 may be coupled to the first memory cell column 84A via the first bit line 82A and the first column amplifier 80A, to the second memory cell column 84B via the second bit line 82B and the second column amplifier 80B, and so on, and the column selection circuitry 72 is coupled to the W-th memory cell column 84W via the W-th bit line 82W and the W-th column amplifier. In some embodiments, the column amplifier 80 may include a driver to facilitate storing (e.g., writing) data into the memory cell 74, and / or may include a sense amplifier to facilitate outputting (e.g., reading) data from the memory cell 74.

[0109] In some embodiments, the column selection circuitry 72 may selectively effect reading from and / or writing to the memory cell columns 84, e.g., by outputting a column selection to the corresponding column amplifiers 80. In other words, to read data (e.g., the first data record 86A and / or the second data record 86B) from the first memory cell column 84A and / or to write the data record 86A to the first memory cell column 84A, the column selection circuitry 72 may output a column selection (e.g., a logic high) signal to the first column amplifier 80A. Additionally, to read data (e.g., the Rth data record 86R) from the second memory cell column 84B and / or to write data to the second memory cell column 84B, the column selection circuitry 72 may output a column selection signal to the second column amplifier 80B. Further, to read data (e.g., the Wth data record 86W) from the Wth memory cell column 84W and / or to write data to the Wth memory cell column 84W, the column selection circuitry 72 may output a column selection signal to the Wth column amplifier 80W.

[0110] In any case, as described above, the data record 86 may include one or more data fields 88. For example, as in the depicted embodiment, one or more data records 86 may include a first data field 88A and an Fth data field 88F. As described above, in some embodiments, the data record 86 may utilize a data structure that allocates specific bit positions for indicating specific data fields 88. For example, the data structure may allocate bits [0,X] in the data record 86 for indicating a name field 88, bits [X+1,Y] in the data record 86 for indicating a street address field 88, and bits [Y+1,Z] in the data record 86 for indicating a zip code field 88. As described above, in some embodiments, one or more of the data fields 88 may be indexed, e.g., to facilitate accessing the corresponding data records 86 in sorted order.

[0111] Return Figure 6 of the memory subsystem 14A, to facilitate accessing data in sorted order, the memory-side memory controller 26B may utilize one or more index tables 90. In some embodiments, each index table 90 may correspond to a different data field 88 included in one or more data records 86 stored in the memory subsystem 14A. For example, when one or more data records 86 include a name field 88, the index table 90 may include a name index table; when one or more data records 86 include a street address field 88, the index table may include a street address index table; and / or when one or more data records 86 include a zip code field 88, the index table may include a zip code index table.

[0112] In addition, in some embodiments, the index table 90 may include one or more index entries, each corresponding to a data record 86 that includes a corresponding data field 88. For example, when the first data record 86A includes a name field, the name index table 90 may include a first name index entry corresponding to the first data record 86A; when the second data record 86B includes a name field, the name index table may include a second name index entry corresponding to the second data record 86B; and so on. Additionally, when the first data record 86A includes a street address field 88, the street address index table 90 may include a first street address index entry corresponding to the first data record 86A; when the second data record 86B includes a street address field 88, the street address index table may include a second street address index entry corresponding to the second data record 86B; and so on. Furthermore, when the first data record 86A includes a postal code field 88, the postal code index table 90 may include a first postal code index entry corresponding to the first data record 86A; when the second data record 86B includes a postal code field 88, the postal code index table may include a second postal code index entry corresponding to the second data record 86B; and so on.

[0113] To facilitate identifying the corresponding data record 86, in some embodiments, an index entry may identify the storage location of the corresponding data record 86, for example, via a pointer that points to a memory address in the memory subsystem 14. In other words, the first index entry corresponding to the first data record 86A may indicate the storage location of the first data record 86A in the memory subsystem 14, the second index entry corresponding to the second data record 86B may indicate the storage location of the second data record 86B in the memory subsystem 14, and so on. Additionally, to facilitate sorting, in some embodiments, an index entry may indicate the value of the corresponding data field 88. For example, the first postal code index entry may indicate the value of the postal code field 88 in the first data record 86A, the second postal code index entry may indicate the value of the postal code field 88 in the second data record 86B, and so on.

[0114] To help further illustrate, a diagram of an exemplary index table 90 is shown in Figure 6 As depicted, the index table 90 may include an index data field column 94 and one or more index entry location columns 96, each corresponding to an index entry location. Additionally, as in the depicted example, the index table 90 may include index table rows 92, each corresponding to a different index table 90.

[0115] In other words, an index table row 92 can indicate a corresponding index data field in the index data field column 94 (e.g., an access index). For example, the index data field column 94 in the first index table row 92A can indicate that the first index table row 92A corresponds to the first data field 88A. Additionally, the index data field column 94 in the F-th index table row 92F can indicate that the F-th index table row 92F corresponds to the F-th data field 88F.

[0116] Furthermore, an index table row 92 can indicate an index entry, and each index entry corresponds to a data record 85 that contains the index data field in the index entry position column 96. For example, when the first data record 86A contains the first data field 88A, the index entry position column 96 in the first index table row 92A can contain an index entry corresponding to the first data record 86A; when the W-th data record 86W contains the first data field 88A, the index entry position column in the first index table row can contain an index entry corresponding to the W-th data record 86W; and so on. Additionally, when the R-th data record 86R contains the F-th data field 88F, the index entry position column 96 in the F-th index table row 92F can contain an index entry corresponding to the R-th data record 86R; when the first data record 86A contains the first data field 88A, the index entry position column in the F-th index table row can contain an index entry corresponding to the first data record 86A; and so on.

[0117] Moreover, as described above, the index entries in the index table 90 can indicate the storage location of the corresponding data record 86 in the memory subsystem 14 and the value of the corresponding index data field 88 in the data record 86. The index entry corresponding to the first data record 86A in the first index table row 92A can identify the storage location of the first data record 86A and the value of the first data field 88A indicated in the first data record 86. The index entry corresponding to the W-th data record 86W in the first index table row 92A can identify the storage location of the W-th data record 86W and the value of the first data field 88A indicated in the W-th data record 86W, and so on. Additionally, the index entry corresponding to the R-th data record 86R in the F-th index table row 92F can identify the storage location of the R-th data record 86R and the value of the F-th data field 88F indicated in the R-th data record 86R. The index entry corresponding to the first data record 86A in the F-th index table row 92F can identify the storage location of the first data record 86A and the value of the F-th data field 88F indicated in the first data record 86A.

[0118] As described above, in some embodiments, indicating the value of the index data field 88 in the corresponding index entry can facilitate improved sorted access to the corresponding data record 86A. In particular, in some embodiments, indicating the value of the index data field 88 in the corresponding index entry can enable the memory-side memory controller 26B, for example, to sort the corresponding data records 86 in ascending order, descending order, or any other suitable order by adjusting only the index entry position of the index entry without adjusting the actual data record 86. For example, in the depicted instance, the index entries can be sorted in ascending order by indicating the index entry containing the lowest (e.g., smallest) value of the index data field in the first index entry position in the first index entry position column 106A and the index entry containing the highest (e.g., largest) value of the index data field in the Vth (e.g., last) index entry position in the Vth (e.g., last) index entry position column 106V.

[0119] In other words, by reading (e.g., traversing) the index entry position columns 96 included in the index table rows 92, the memory controller 26 (e.g., the memory-side memory controller 26B) can determine the storage location of the data record 86 containing the corresponding index data field in the memory subsystem 14. For example, by reading the index entry position column 96 in the first index table row 92A, the memory controller 26 can determine the storage location of the first data record 86A and the storage location of the Wth data record 86W, and thus determine that both of them contain the first data field 88A. Additionally, by reading the index entry position column 96 in the Fth index table row 92F, the memory controller 26 can determine the storage location of the Rth data record 86R and the storage location of the first data record 86A, and thus determine that they both contain the Fth data field 88F. In any case, as described above, in some embodiments, the index table 90 is stored more in a dedicated memory implemented in a separate storage (e.g., memory) device, for example, and / or in an index table memory array that is different (e.g., separate) from one or more main memory arrays 66.

[0120] For purposes of illustration, an example of a portion 108 of the memory subsystem 14 that includes the index table memory array 100 is shown in Figure 7 As in the depicted embodiment, the index tables 90 can each be stored in the memory cell rows 78 of the index table memory array 100. For example, the first index table 90A can be stored in the first memory cell row 78A of the index table memory array 100, and the Fth index table 90F can be stored in the Fth memory cell row 78F of the index table memory array 100. In other words, the first index table 90A can correspond to the first index table row 92A, and the Fth index table 90F can correspond to the Fth index table row 92F.

[0121] Additionally, as in the depicted embodiment, the index entries 102 may each be stored in a column 84 of memory cells of the index table memory array 100. For example, the first index entry 102A may be stored in the first column 84A of memory cells of the index table memory array 100, the second index entry 102B may be stored in the second column 84B of memory cells of the index table memory array 100, and so on, with the Vth index entry 102V being stored in the Vth column 84V of memory cells of the index table memory array 100. In other words, in some embodiments, the columns 84 of memory cells in the index table memory array 100 may each correspond to a column 96 of index entry positions and thus to the corresponding index entry positions. For example, since it is stored in the first column 84A of the first row 78A of memory cells, the memory controller 26 (e.g., the memory-side memory controller 26B) may determine that the first index entry 102A is included at the first (e.g., smallest or lowest) index entry position in the first index table 90A. Additionally, since it is stored in the Vth column 84V of the first row 78A of memory cells, the memory controller 26 may determine that the Vth index entry 102V is included at the Vth (e.g., largest or highest) index entry position in the first index table 90A.

[0122] To facilitate access to the index entry positions, as in the depicted embodiment, the entry cells 104 may be coupled, for example, via corresponding column amplifiers 80 to each column 84 of memory cells in the index table memory array 100. In other words, the first entry cell 104A may be coupled to the first column 84A of memory cells in the index table memory array 100, the second entry cell 104B may be coupled to the second column 84B of memory cells in the index table memory array 100, and so on, with the Vth entry cell 104V being coupled to the Vth column 84V of memory cells in the index table memory array 100. Additionally, as in the depicted embodiment, the different entry cells 104 may be communicatively coupled, for example, to effect shifting of data therebetween.

[0123] In some embodiments, entry units 104 corresponding to a memory cell column 84 may be communicatively coupled to entry units 104 corresponding to an adjacent memory cell column 84. For example, a first entry unit 104A may be communicatively coupled only to a second entry unit 104B, and / or a fifth entry unit 104V may be communicatively coupled only to a (V-1)th entry unit 104, where the (V-1)th entry unit corresponds to the (V-1)th memory cell column 84 in the index table memory array 100. On the other hand, the second entry unit 104B may be communicatively coupled to the first entry unit 104A and a third entry unit 104, where the third entry unit corresponds to the third memory cell column 84 in the index table memory array 100. Additionally, in some embodiments, the entry units 104 may be included in a memory controller 26 (e.g., a memory-side memory controller 26B implemented in the memory subsystem 14).

[0124] In any case, as will be described in more detail below, the entry unit 104 (e.g., the memory controller 26) may perform data processing operations (e.g., functions), such as to facilitate updating the index table 90 by adding a new index entry 102N to the index table 90. However, as described above, processing circuitry implemented to perform more complex data processing operations is typically more highly doped (compared to memory circuitry). Additionally, a higher degree of doping typically increases the likelihood of generating leakage current, which in at least some instances may affect the operational reliability of the memory subsystem 14, such as by causing corruption of data stored in the memory subsystem 14.

[0125] Thus, as in the depicted embodiment, the entry unit 104 may include a register 106 and comparison logic circuitry 108, which in at least some instances may be implemented with less doped processing circuitry (e.g., compared to the processing subsystem 12 and / or a fully fledged processor-in-memory (PIM)). Using its register 106, the entry unit 104 may store, for example, an index entry 102 read from the index table memory array 100. In some embodiments, one or more of the registers 106 may be sixty-four byte registers.

[0126] Additionally, using its comparison logic circuitry 108, item unit 104 can compare the index item 102 currently stored in its register 106 with the received (e.g., input) index item 102 (e.g., shifted from another item unit 104) and / or a new index item 102N to be added to the corresponding index table 90. In some embodiments, the comparison logic circuitry 108 implemented in item unit 104 can compare the value of the data field 88 indicated by the index item 102 stored in its register 106 with the value of the data field 88 indicated by the received index item 102. For example, the comparison logic circuitry 108 can indicate whether the value of the data field 88 indicated by the received index item 102 is greater than the value of the data field 88 stored in the register 106 of item unit 104. At least partially based on the comparison, the corresponding index table 90 can be updated, e.g., to include the new index item 102N.

[0127] An instance of the process 110 for generating index items is described in Figure 8 . Generally, process 110 includes determining the storage location of a data record (process block 112), identifying a data field in the data record (process block 114), and generating an index item corresponding to the data record (process block 116). Although described in a particular order representing a particular embodiment, it should be noted that process 110 can be performed in any suitable order. Additionally, embodiments of process 110 can omit process blocks and / or include additional process blocks. Furthermore, in some embodiments, process 110 can be implemented at least partially by executing instructions stored in a tangible non-transitory computer-readable medium (e.g., the memory implemented in memory controller 26) using processing circuitry (e.g., the processor implemented in memory controller 26).

[0128] Thus, in some embodiments, the memory controller 26 (e.g., the memory-side memory controller 26B) can determine the storage location of the data record 86 in the memory subsystem 14 (process block 112). As described above, in some embodiments, the storage location of data can be indicated via a (e.g., virtual and / or physical) memory address at which the data is stored in, for example, the main memory array 66 and / or the non-volatile memory 64 implemented in the memory subsystem 14. As an illustrative example, with respect to Figure 5 , the memory controller 26 can determine that the first data record 86A is stored at a first row address and column address pair that identifies the first row 78A of memory cells and the first column 84A of memory cells in the memory array 66A.

[0129] Returning to Figure 6In process 110, memory controller 26 may additionally identify data fields 88 included in data record 86 and determine the values of data fields 88 (process block 114). As described above, in some embodiments, data record 86 may include one or more data fields 88. Additionally, as described above, in some embodiments, data record 86 may utilize a data structure that allocates specific bit positions for indicating specific data fields 88.

[0130] Accordingly, to facilitate determining the values of data fields 88, memory controller 26 may determine the data structure used by data record 86. In some embodiments, the data structure of data record 86 may be predefined, such that an indication of the data structure is pre-stored in memory subsystem 14. Additionally or alternatively, the data structure of data record 86 may be explicitly indicated, for example, via metadata (e.g., header data) included with data record 86 and / or a separate control signal (e.g., a command or request) received with data record 86.

[0131] At least in part based on the data structure, memory controller 26 may read bit positions in data record 86 to determine the values indicated by data fields 88 in data record 86. For example, when the data structure allocates bits [0,X] for indicating a name field 88 (e.g., first data field 88A), memory controller 26 may determine the value of the name field 88 by reading bits [0,X] in data record 86. Additionally, when the data structure allocates bits [X+1,Y] for indicating a street address field 88, memory controller 26 may determine the value of the address field 88 by reading bits [X+1,Y] in data record 86. Further, when the data structure allocates bits [Y+1,Z] for indicating a zip code field (e.g., the Fth data field 88F), memory controller 26 may determine the value of the zip code field 88 by reading bits [Y+1,Z] in data record 86.

[0132] Based at least in part on its storage location and the value indicated by its data field 88, the memory controller 26 may generate an (e.g., new) index entry 102 corresponding to the data record 86 (process block 116). As described above, in some embodiments, the index entry 102 may indicate the storage location of the corresponding data record 86 and the value of the corresponding data field 88 included in the data record 86. For example, the memory controller 26 may generate a name index entry 102 to indicate the storage location of the data record 86 and the value of its name field 88. Additionally, the memory controller 26 may generate a street address index entry to indicate the storage location of the data record 86 and the value of its street address field 88. Further, the memory controller 26 may generate a postal code index entry to indicate the storage location of the data record 86 and the value of its postal code field 88. In any case, as described above, to facilitate providing sorted access, the index table 90 may be updated, e.g., to add one or more new index entries 102N.

[0133] For purposes of illustration, an instance of a process 120 for generating and / or updating an index table 90 sorted in ascending order is described in Figure 9 . Generally, the process 120 includes receiving a current index entry (process block 122); receiving another index entry (process block 124); determining whether the other data field value is greater than the current data field value (decision block 126); and, when the other data field value is greater than the current data field value, maintaining the current index entry at the current index entry position (process block 128). Additionally, when the other data field value is not greater than the current data field value, the process 120 includes shifting the current index entry to the next index entry position (process block 130) and storing the other index entry at the current index entry position (process block 132).

[0134] Although described in a particular order representative of a particular embodiment, it should be noted that the process 120 may be performed in any suitable order. Additionally, embodiments of the process 120 may omit process blocks and / or include additional process blocks. Further, in some embodiments, the process 120 may be implemented at least in part by executing instructions stored in a tangible non-transitory computer-readable medium (e.g., the memory implemented in the memory controller 26) using processing circuitry (e.g., a processor implemented in the memory controller 26).

[0135] Thus, in some embodiments, the memory controller 26 (e.g., the memory-side memory controller 26B) may receive, e.g., via the corresponding entry unit 104, the index entry 102 currently stored at each index entry position in the index table memory array 100 from the index table 90 (process block 122). For purposes of illustration, with respect to Figure 7, the first item unit 104A can receive the first index item 102A currently stored at the first index item position in the first index table 90A from the first memory cell column 84A, and store the first index item 102A in its register 106. Additionally, the second item unit 104B can receive the second index item 102B currently stored at the second index item position in the first index table 90A from the second memory cell column 84B, and store the second index item 102B in its register 106.

[0136] Return Figure 9 In the process 120 of , in addition to the current index item 102, the memory controller 26 can also receive another index item 102 (process block 135). In some embodiments, the another index item 102 can be a new index item 102N to be added to the corresponding index table 90. Additionally or alternatively, the another index item 102 can be an index item 102 received (e.g., shifted) from another item unit 104. For the sake of illustration, regarding Figure 7 , for example, when the first item unit 104A determines that the data field 88 indicated in the new index item 102N is not greater than the value of the data field 88 indicated in the first index item 102A, the second item unit 104B can receive the first index item 102A from the first item unit 104A.

[0137] Return Figure 9 In the process 120 of , the memory controller 26 can then determine whether the value of the data field 88 indicated in the another index item 102 is greater than the value of the data field 88 indicated in the current index item 102 (decision block 126). For example, regarding Figure 7 , the first item unit 104A can compare the value of the data field 88 indicated in the first index item 102A with the value of the data field 88 indicated in the new index item 102N via its comparison logic circuitry 108. Additionally, when the first index item 102A is shifted to the second item unit 104B, the second item unit 104B can compare the value of the data field 88 indicated in the first index item 102A with the value of the data field 88 indicated in the second index item 102B via its comparison logic circuitry 108. On the other hand, when the first index item 102A is not shifted to the second item unit 104B, the second item unit 104B can compare the value of the data field 88 indicated in the new index item 102N with the value of the data field 88 indicated in the second index item 102B via its comparison logic circuitry 108.

[0138] In any case, returning to Figure 9In process 120, when the value of another data field indicated in another index entry 102 is greater than the value of the current data field indicated in the current index entry 102, the memory controller 26 may keep the current index entry 102 at its current index entry position (process block 128). On the other hand, when the value of the other data field is not greater than the value of the current data field, the memory controller 26 may shift the current index entry 102 to the next index entry position (process block 130) and store the other index entry at the current index entry position (process block 132). For example, with respect to Figure 7 , when the value of the data field indicated in the new index entry 102N is not greater than the value of the data field indicated in the first index entry 102A, the first item unit 104A may output the first index entry 102A to the second item unit 104B, thereby shifting the first index entry 102A from the first index entry position in the first index table 90A to the second (e.g., next) index entry position. Additionally, when the value of the data field indicated in the new index entry 102N is not greater than the value of the data field indicated in the first index entry 102A, the first item unit 104A may overwrite its register 106 with the new index entry 102N, thereby storing the new index entry 102N in the first index entry position of the first index table 90A. In this way, the memory subsystem 14 may generate and / or update the index table 90, e.g., to facilitate providing sorted access to the data stored in the memory subsystem 14.

[0139] However, as described above, to facilitate generating and / or updating the index table 90, the memory subsystem 14 may perform data processing operations. Although the computational complexity of the data processing operations may be limited (e.g., to reduce the likelihood of generating leakage current), at least in some instances, the performance of the data processing operations is non-instantaneous. To reduce the likelihood that such data processing operations will affect data retrieval latency, in some embodiments, the memory subsystem 14 (e.g., the memory-side memory controller 26B) generates and / or updates the index table 90 without the processing subsystem targeting the corresponding data record 86. For example, the memory subsystem 14 may generate and / or update the index table 90 in response to one or more data records 86 being written to the main memory array 66.

[0140] To help illustrate, an example of a process 134 for operating the memory subsystem 14 to store and provide access to the data record 86 is described in Figure 10 . Generally, process 134 includes receiving a data record (process block 135), storing the data record as a block in the memory subsystem (process block 136), determining whether strided access is desired (decision block 138), and determining a sorted access pointer (process block 142). Additionally, when strided access is desired, process 134 includes determining a strided access pointer (process block 140).

[0141] Although described in a particular order representing a particular embodiment, it should be noted that process 134 can be performed in any suitable order. Additionally, embodiments of process 134 can omit process blocks and / or include additional process blocks. Further, in some embodiments, process 134 can be implemented at least in part by executing instructions stored in a tangible non-transitory computer-readable medium (e.g., the memory implemented in memory controller 26) using processing circuitry (e.g., a processor implemented in memory controller 26).

[0142] In any case, memory subsystem 14 can receive data record 86 from processing subsystem 12, for example, to store in its memory device 18 (process block 135). To facilitate storing data record 86 in its memory device 18, in some embodiments, memory subsystem 14 can provide an application programming interface (API) that includes an allocation function. An example of an allocation function is as follows:

[0143] Alloc(Ptr,RcdCount,RcdSize,IndexCount,[IndexField]*) (1)

[0144] Where Alloc() is the allocation function, Ptr is a pointer to the starting storage location in memory subsystem 14, RcdCount is the number of data records 86 to be included in the block, RcdSize is the size of each data record 86, IndexCount is the number of data fields 88 to be indexed, and [IndexField]* indicates one or more specific data fields 88 to be indexed.

[0145] In other words, in some embodiments, memory subsystem 14 (e.g., memory-side memory controller 26B) can perform the allocation function (process block 142) at least in part based on the data structure used by the received data record 86. As described above, in some embodiments, the data structure of data record 86 can be predefined, such that an indication of the data structure is pre-stored in memory subsystem 14. Additionally or alternatively, the data structure of data record 86 can be explicitly indicated, for example, via metadata (e.g., header data) included with data record 86 and / or a separate control signal (e.g., a command or request) received with data record 86. In any case, by performing the allocation function, memory subsystem 14 can allocate a contiguous block of memory addresses (e.g., &Ptr+(RcdCount*RcdSize)) for storing data record 86 in, for example, main memory 66. Thus, in some embodiments, memory subsystem 14 can automatically perform the allocation function in response to the receipt of data record 86.

[0146] Then, the memory subsystem 14 can store the data record 86 in the allocated memory address, e.g., automatically in response to the execution of the allocation function (process block 136). In some embodiments, the memory subsystem 14 can store the data record 86 as a contiguous block. In other words, in such embodiments, the memory subsystem 14 can store the data record at contiguous storage locations (e.g., memory addresses). Additionally, in some embodiments, the memory subsystem 14 can automatically generate one or more index entries 102, e.g., in response to the corresponding data record 86 being stored in the memory subsystem 14 (e.g., the main memory array 66).

[0147] In some embodiments, the number of index entries 102 generated for the data record 86 can be equal to the value input for the IndexCount parameter of the allocation function. Additionally, in some embodiments, the index entries 102 generated for the data record 86 can each correspond to different data fields in the specific data fields 88 indicated by the [IndexField]* parameter input of the allocation function. Further, in some embodiments, the memory subsystem 14 can automatically generate and / or update one or more index tables 90, e.g., in response to generating the corresponding index entries 102.

[0148] To facilitate providing strided access to the stored data, in some embodiments, the memory subsystem 14 can determine a strided access pointer (process block 140). As described above, the memory subsystem 14 can provide strided access by identifying specific portions (e.g., one or more data fields 88) of one or more data records 86. In some embodiments, the strided access pointer can identify the storage location of the corresponding portion of the data record 86 in the memory subsystem 14. For example, a name strided access pointer can identify the storage location of the name field 88 in the first data record 86A, the second data record 86B, etc. Additionally or alternatively, a zip code strided access pointer can identify the storage location of the zip code field 88 in the first data record 86A, the second data record 86B, etc.

[0149] To facilitate determining the strided access pointer, in some embodiments, the memory subsystem 14 can provide an application programming interface (API) that includes a striding function. An example of a striding function is as follows:

[0150] StPtr = Striding(Ptr,FieldOffset,FieldLength,StrideLength) (2)

[0151] Where StPtr is a striding access pointer, Striding() is a striding access function, Ptr is a pointer to the starting storage location in the memory subsystem 14, FieldOffset is the starting bit location of the target data field 88 in the data record 86, FieldLength is the size of the target data field 88, and StrideLength is the stride length between consecutive data records 86. In other words, in some embodiments, the memory subsystem 14 (e.g., the memory-side memory controller 26B) can perform the striding access function at least in part based on the data structure used by the received data records 86 to determine one or more striding access pointers, e.g., each striding access pointer corresponding to a data field 88 included in each data record 86 (process block 144). To facilitate reducing the likelihood that the determination of the striding access pointers will affect the data retrieval latency, in some embodiments, the memory subsystem 14 can automatically perform the striding access function, e.g., in response to storing one or more data records 86 in the memory subsystem 14 (e.g., the main memory array 66).

[0152] Additionally or alternatively, to facilitate providing sorted access to the stored data, the memory subsystem 14 can determine sorted access pointers (process block 142). As described above, the memory subsystem 14 can provide sorted access by identifying the data records 86 in a sorted order, e.g., different from the address order. In some embodiments, the sorted access pointers can identify the storage locations of the data records 86 in the memory subsystem 14 in the sorted order. For example, a name sorted access pointer can identify the storage locations of the data records 86 in an order sorted based on the values of the name fields 88 included in each data record 86. Additionally or alternatively, a zip code sorted access pointer can identify the storage locations of the data records 86 in an order sorted based on the values of the zip code fields 88 included in each data record 86. In other words, in some embodiments, the sorted access pointers can identify the storage locations of the corresponding index table 90 in, e.g., the index table memory array 100.

[0153] To facilitate determining the sorted access pointers, in some embodiments, the memory subsystem 14 can provide an application programming interface (API) that includes a sorted access function. An example of a sorted access function is as follows:

[0154] SoPtr = Sorted(Ptr, IndexField) (3)

[0155] Where SoPtr is a sorted access pointer, Sorted() is a sorted access function, Ptr is a pointer to a starting storage location in the memory subsystem 14, and IndexField indicates the specific data field 88 to be indexed. Thus, in some embodiments, the memory subsystem 14 (e.g., the memory-side memory controller 26B) may execute a sorted access function to determine one or more sorted access pointers, such as each sorted access pointer corresponding to a data field 88 included in the index table 90 and / or one or more data records 86 (process block 146). To facilitate reducing the likelihood that the determination of sorted access pointers will affect data retrieval latency, in some embodiments, the memory subsystem 14 may automatically execute the sorted access function, e.g., in response to generating and / or updating one or more index tables 90.

[0156] In this way, e.g., by automatically performing data processing operations in response to data being stored in the memory subsystem 14 (e.g., the main memory array 66), the memory subsystem 14 may perform data processing operations with reduced likelihood that the data processing operations will affect (e.g., increase) data retrieval latency. In fact, in some embodiments, implementing data processing operations in this way may facilitate improving (e.g., reducing) subsequent data retrieval latency, e.g., by having the memory subsystem 14 identify target data using stride access pointers and / or sorted access pointers. Additionally, as described above, providing an address management function in the memory subsystem 14 may facilitate improving the operational efficiency of the computing system 10, e.g., by reducing data communication between the memory subsystem 14 and the processing subsystem 12 in the computing system 10.

[0157] For purposes of illustration, an example of a process 148 for operating a memory controller 26 (e.g., the memory-side memory controller 26B) is described in Figure 11 . Generally, process 148 includes receiving a memory access request (process block 150), determining target data (process block 152), determining whether the target data results in a main memory array miss (decision block 154), and outputting the target data to the processing subsystem (process block 158). Additionally, when the target data results in a main memory array miss, process 148 includes retrieving the target data from non-volatile memory (process block 156).

[0158] Although described in a particular order representing a particular embodiment, it should be noted that process 148 can be performed in any suitable order. Additionally, embodiments of process 148 can omit process blocks and / or include additional process blocks. Further, in some embodiments, process 148 can be implemented at least in part by executing instructions stored in a tangible non-transitory computer-readable medium (e.g., the memory implemented in memory controller 26) using processing circuitry (e.g., the processor implemented in memory controller 26).

[0159] Thus, in some embodiments, memory controller 26 (e.g., memory-side memory controller 26B) can receive a memory access request (process block 150) identifying data that processing circuitry 16 of computing system 10 is currently targeting, for example, from processing circuitry 16 or processor-side memory controller 26A. In some embodiments, the memory access request can identify the target data via its virtual memory address. Additionally or alternatively, the memory access request can identify the target data via its physical memory address, which indicates the storage location of the target data in memory subsystem 14. For example, the physical memory address can include a row address and column address pair that identify a row 78 of memory cells and a column 84 of memory cells in main memory array 66 where the target data is stored.

[0160] Thus, based at least in part on the memory access request, memory controller 26 can determine the data that processing circuitry 16 is currently targeting (process block 160). In some embodiments, memory controller 26 can additionally or alternatively predict what data processing circuitry will target subsequently (process block 162). As described above, at least in some instances, predictively identifying data expected to be targeted subsequently can facilitate improving the operational efficiency of computing system 10, for example, by avoiding subsequent memory access requests and / or reducing the retrieval time when actually targeting data.

[0161] For purposes of illustration, one example of process 166 for predictively identifying data expected to be targeted subsequently is described in Figure 12 . Generally, process 166 includes determining a data access pattern based on the currently targeted data (process block 168), extrapolating the data access pattern outside of a control time domain (process block 170), and predicting the subsequently targeted data based on the extrapolated data access pattern (process block 172).

[0162] Although described in a particular order representing a particular embodiment, it should be noted that process 166 can be performed in any suitable order. Additionally, embodiments of process 166 can omit process blocks and / or include additional process blocks. Further, in some embodiments, process 166 can be implemented at least in part by executing instructions stored in a tangible non-transitory computer-readable medium (e.g., the memory implemented in memory controller 26) using processing circuitry (e.g., the processor implemented in memory controller 26).

[0163] Thus, in some embodiments, memory controller 26 (e.g., memory-side memory controller 26B) can determine a data access mode (process block 168) at least in part based on what data is currently targeted. As described above, a memory access request can identify, for example, the data currently targeted by processing circuitry 16 implemented in processing subsystem 12. In other words, in some embodiments, memory controller 26 can determine a data access mode at least in part based on one or more corresponding memory access requests.

[0164] Additionally, as described above, in some embodiments, processing subsystem 12 can identify data from multiple data records 86 using a single memory access request. For example, a first memory access request can indicate a vector [N,M] of a target access index and a target index item location. Thus, memory controller 26 can determine that the first memory access request results in a first data access mode that targets data records 86 corresponding to index items 102 at the N+1 index item location to the M+1 index item location in index table 90, the index table corresponding to the target access index. Additionally or alternatively, a second memory access request can indicate a storage location of a block of data records 86 and a targeted data field 88 in each data record 86. Thus, memory controller 26 can determine that the second memory access request results in a second data access mode that targets a specific data field 88 in each data record 86 stored in the block.

[0165] In any case, the memory controller 26 can then extrapolate the data access pattern within the upcoming control time domain (process block 170). In some embodiments, the control time domain can be a certain time period (e.g., one or more clock cycles) from the current time to a future time when it is expected to receive another memory access request. In other words, by extrapolating the data access pattern, the memory controller 26 can predict what data will be targeted subsequently (process block 172). For example, by extrapolating a first data access pattern resulting from a first memory access request, the memory controller 26 can predict that the processing circuitry 16 will subsequently target a data record 86 corresponding to a vector [M+1, 2M–N+1] at an index entry position in the index table 90, where the index table corresponds to the target access index.

[0166] In addition to extrapolating the data access pattern, in some embodiments, the memory controller 26 can predict what data will be targeted subsequently based at least in part on the data structure used by the data records 86 stored in the memory subsystem 14. For example, by extrapolating a second data access pattern resulting from a second memory access request, the memory controller 26 can predict that the processing circuitry 16 will subsequently target another data field 88 in each of the data records 86 stored in the block. Additionally, based at least in part on the data structure used by the data records 86, the memory controller 26 can predict that another data field 88 is a data field 88 adjacent to the data field 88 targeted by the second memory access request. In this way, the memory subsystem 14 can predictively identify the data that is expected to be targeted subsequently, for example, by the processing circuitry 16 implemented in the processing subsystem 12.

[0167] Return Figure 11 In the process 148 of, the memory controller 26 can determine (e.g., currently and / or predictively) whether the target data results in a main memory array miss (decision block 154). As described above, in some embodiments, the memory controller 26 can determine the storage location of the data in the memory subsystem 14 based at least in part on the (e.g., virtual and / or physical) memory address associated with the data. For example, when the corresponding memory address is implemented in the main memory array 66, the memory controller 26 can determine that the target data does not result in a main memory array miss and thus instruct the memory subsystem 14 to retrieve (e.g., read) the target data from the main memory array 66. On the other hand, when the corresponding memory address is not implemented in any of the main memory arrays 66, the memory controller 26 can determine that the target data results in a main memory array miss and thus instruct the memory subsystem 14 to retrieve (e.g., read) the targeted data from the non-volatile memory 64 (process block 156).

[0168] In any case, after retrieving from the memory device 18, the memory controller 26 may direct the memory subsystem 14 to output the target data to the processing subsystem 12 via the system bus 20 (process block 158). To facilitate further improving the operation efficiency, in some embodiments, the memory subsystem 14 may, for example, automatically respond to a memory access request and / or store the target data directly into the processor side cache 22 without a separate (e.g., additional) instruction from the processing subsystem 12 (process block 164). In other words, in some embodiments, the memory subsystem 14 may preemptively store data expected to be subsequently targeted directly into the processor side cache 22, which, at least in some instances, may facilitate further improving the operation efficiency by causing the data to be provided from the processor side cache 22 when the data is actually targeted.

[0169] However, as described above, the processing subsystem 12 may also control data storage in its processor side cache 22, for example, via the processor side memory controller 26A. Thus, in some embodiments, after the target data is stored in the processor side cache 22, the memory controller 26 may output a control signal to the processing subsystem 12 that indicates that the targeted data has been successfully stored in the processor side cache 22 and is thus ready for processing and / or execution. Moreover, at least in some instances, storing the target data directly into the processor side cache 22 may conflict with the data storage control implemented in the processing subsystem 12. For example, predictively storing data expected to be subsequently targeted directly into the processor side cache 22 may inadvertently overwrite other data that the processing subsystem 12 is still using and may thus result in a processor side cache miss when targeting other data. To facilitate reducing the likelihood that such conflicts will affect the data retrieval latency, in some embodiments, the memory subsystem 14 may store the targeted data directly into the processor side cache 22 implemented at a higher cache level 30 (e.g., the L3 processor side cache 22 implemented at the Kth cache level 30K and / or the shared processor side cache 34). In this way, the memory subsystem 14 may operate to provide the target data to the processing subsystem 12.

[0170] Return Figure 3In process 46, after the processing subsystem 12 requests the target data, the memory controller 26 (e.g., the processor-side memory controller 26A) can determine whether the target data has been received from the memory subsystem 14 (decision block 58). To facilitate improved operational efficiency, in some embodiments, while the processing subsystem 12 is waiting for the return of the target data, the processing circuitry 16 can continue with other operations. Additionally, in some embodiments, when a control signal indicating that the target data has been successfully stored in the processor-side cache 22 is received from the memory subsystem 14, the memory controller 26 can determine that the target data has been received.

[0171] In any case, after receiving the target data, the memory controller 26 can instruct the processing subsystem 12 to supply the target data, e.g., from the processor-side cache 22, to the processing circuitry 16 (process block 52). In some embodiments, the processor-side cache 22 can output a cache line with tag metadata that matches the target tag metadata value expected to be associated with the target data. In some embodiments, when stored in a higher-level cache (e.g., the shared processor-side cache 34), the target data can pass through one or more lower-level caches (e.g., the private processor-side cache 32) before reaching the processing circuitry 16.

[0172] One or more specific embodiments of the present disclosure are described herein and depicted in the corresponding drawings. These described embodiments are merely examples of the technology of the present disclosure. Additionally, to provide a brief description of these embodiments, not all features of the actual implementation may be described in the specification. It should be understood that in the development of any such actual implementation, such as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as meeting system-related and business-related constraints, which may vary between implementations. Furthermore, it should be understood that such development work may be complex and time-consuming, but may still be routine work in design, fabrication, and manufacturing for those of ordinary skill in the art who benefit from the present disclosure.

[0173] When introducing elements of the various embodiments of the present disclosure, the articles "a" and "the" are intended to mean that there is one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements in addition to the listed elements. Additionally, it should be understood that a reference to "one embodiment" of the present disclosure is not intended to be construed as excluding the existence of additional embodiments that also incorporate the recited features.

[0174] The above specific embodiments have been shown by way of examples, and it should be understood that these embodiments may be readily subject to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the specific forms disclosed, but rather cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure.

Claims

1. A device, comprising: A processing system including a processor and a cache; A system bus coupled to the processing system; And A memory system coupled to the processing system via the system bus, wherein the memory system includes: A main memory array configured to store a plurality of data records, wherein each of the plurality of data records includes a plurality of data bits other than header data and includes at least a first data field having a plurality of allocated bit positions; and A memory controller configured to: Based on determining a mutual relationship among values of a first portion of the plurality of data bits in each of the plurality of data records, store the first portion of the data bits of each of the plurality of data records in the first data field of the corresponding data record; Receive a first memory access request from the processor targeting a first targeted data bit stored in the first data field of a first data record of the plurality of data records; In response to receiving the first memory access request, provide the first targeted data bit to the processing system; Based on the mutual relationship determined among the values of the first portion of the data bits of each data record and the received first memory access request targeting the first targeted data bit, predict a first subsequent memory access request from the processor targeting a second targeted data bit stored in the first data field of a second data record of the plurality of data records; and Based on predicting the first subsequent memory access request, provide an instruction to store the second targeted data bit in the cache of the processing system.

2. The device according to claim 1, wherein the memory controller is configured to store the first portion of the data bits of each of the plurality of data records in the first data field of the corresponding data record based on receiving each corresponding data record of the plurality of data records.

3. The device according to claim 1, wherein the memory controller is configured to predict the first subsequent memory access request by determining a data access pattern based on the mutual relationship determined among the values of the first portion of the data bits of each data record and the received first memory access request targeting the first targeted data bit.

4. The device according to claim 1, wherein the memory controller is configured to determine a stride access pointer based on the mutual relationship determined among the values of the first portion of the data bits of each data record of the plurality of data records to identify the first data field of the plurality of data records.

5. The device according to claim 4, wherein the memory controller is configured to predict the first subsequent memory access request targeting the second targeted data bit based on the processor using the stride access pointer to identify the first data field of the second data record in response to receiving the first memory access request.

6. The apparatus according to claim 1, wherein the memory controller is configured to sort the first data field of each data record of the plurality of data records in ascending or descending order based on the value of the first partial data bits of each corresponding data record stored in the corresponding first data field, so as to determine the mutual relationship among the values of the first partial data bits of each data record of the plurality of data records.

7. The apparatus according to claim 1, wherein the memory controller is configured to allocate bit positions in the main memory array for storing each data record of the plurality of data records.

8. The apparatus according to claim 1, wherein the main memory array is configured to: receive the first memory access request from the processor, the first memory access request targeting a first targeted data bit stored in the first data field of the first data record to perform a first operation; in response to receiving the first memory access request, provide the first targeted data bit to the processing system to perform the first operation; in response to receiving the first memory access request, predict, based on the mutual relationship determined among the values of the first partial data bits of each data record, one or more second subsequent memory access requests from the processor, the one or more second subsequent memory access requests targeting a second targeted data bit stored in the first data field of the second data record, a third targeted data bit stored in the first data field of a third data record of the plurality of data records, and a fourth targeted data bit stored in the first data field of a fourth data record of the plurality of data records; and based on predicting the one or more second subsequent memory access requests, provide an instruction to store the second targeted data bit, the third targeted data bit, and the fourth targeted data bit in the cache of the processing system.

9. A method, comprising: receiving, by a memory system, a plurality of data records, wherein each data record of the plurality of data records includes a plurality of data bits other than header data and includes at least a first data field having a plurality of allocated bit positions; determining, by a memory controller of the memory system, the mutual relationship among the values of the first partial data bits among the plurality of data bits in each data record of the plurality of data records; storing, by the memory controller, based on the mutual relationship among the values of the first partial data bits of each data record of the plurality of data records, the first partial data bits of each data record of the plurality of data records in the first data field of the corresponding data record; receiving, by the memory controller, a first memory access request from a processing system, the first memory access request targeting a first targeted data bit stored in the first data field of the first data record of the plurality of data records; providing, by the memory controller, in response to receiving the memory access request, the first targeted data bit to the processing system; Based on the mutual relationship determined from the values of the first partial data bits of each data record and the received memory access request targeting the first targeted data bit, the memory controller predicts a subsequent memory access request from the processing system, the subsequent memory access request targeting a second targeted data bit stored in a first data field of a second data record among the plurality of data records; and Based on predicting the subsequent memory access request, the memory controller provides an instruction to store the second targeted data bit in a cache of the processing system.

10. The method according to claim 9, comprising predicting the subsequent memory access request by the memory controller by determining a data access pattern based on the mutual relationship determined from the values of the first partial data bits of each data record and the received memory access request targeting the first targeted data bit.

11. The method according to claim 9, comprising determining a stride access pointer by the memory controller to identify the first data field of the plurality of data records based on the mutual relationship in the values of the first partial data bits of each data record of the plurality of data records.

12. The method according to claim 11, wherein predicting the subsequent memory access request includes using the stride access pointer to identify the first data field of the second data record in response to receiving the first memory access request.

13. The method according to claim 9, wherein determining the mutual relationship in the values of the first partial data bits of each data record of the plurality of data records includes sorting the first data field of each data record of the plurality of data records in ascending or descending order based on the values of the first partial data bits of each data record stored in the corresponding first data field.

14. The method according to claim 9, comprising allocating bit positions in the memory system by the memory controller to store each data record among the plurality of data records.

15. The method according to claim 9, comprising: Based on the mutual relationship determined from the values of the first partial data bits of each data record and the received memory access request targeting the first targeted data bit, the memory controller predicts an additional subsequent memory access request from the processing system, the additional subsequent memory access request targeting a third targeted data bit stored in a first data field of a third data record among the plurality of data records; and Based on predicting the additional subsequent memory access request, the memory controller provides an instruction to store the third targeted data bit in a cache of the processing system.

16. The method according to claim 9, comprising: Receiving, by the memory system, the first data record and the second data record for storage in the memory system; and Through the memory control system, before storing the first data record and the second data record in the memory system, in response to receiving the first data record and the second data record, bit positions for storing the first data record and the second data record are allocated in the memory system.

17. A memory device configured to be coupled to a processing system, the memory device comprising: One or more memory arrays; A memory controller configured to perform operations in response to receiving data and instructions from the processing system when the memory device is coupled to the processing system, wherein the operations include: Receiving a plurality of data records from the processing system, wherein each data record of the plurality of data records includes a plurality of data bits other than header data and includes at least a first data field having a plurality of allocated bit positions; Determining a mutual relationship among values of a first portion of the plurality of data bits in each data record of the plurality of data records; Based on the mutual relationship among the values of the first portion of the plurality of data bits in each data record of the plurality of data records, storing the first portion of the plurality of data bits in the first data field of the corresponding data record; Receiving a first memory access request from the processing system, the first memory access request targeting a first targeted data bit stored in the first data field of the first data record of the plurality of data records; In response to receiving the memory access request, providing the first targeted data bit to the processing system; Predicting a first subsequent memory access request from the processing system based on the mutual relationship determined among the values of the first portion of the plurality of data bits in each data record and the received memory access request targeting the first targeted data bit, the first subsequent memory access request targeting a second targeted data bit stored in the first data field of the second data record of the plurality of data records; and Based on predicting the subsequent memory access request, providing an instruction to store the second targeted data bit in a cache of the processing system.

18. The memory device according to claim 17, wherein the operations of the memory controller include predicting the subsequent memory access request by determining a data access pattern based on the mutual relationship determined among the values of the first portion of the plurality of data bits in each data record and the received memory access request targeting the first targeted data bit.

19. The memory device according to claim 17, wherein the operations of the memory controller include determining a stride access pointer based on the mutual relationship among the values of the first portion of the plurality of data bits in each data record of the plurality of data records to identify the first data field of the plurality of data records, wherein predicting the subsequent memory access request includes using the stride access pointer to identify the first data field of the second data record corresponding to receiving the first memory access request.

20. The memory device according to claim 17, wherein determining the mutual relationship among the values of the first partial data bits of each of the plurality of data records includes sorting the first data fields of each of the plurality of data records in ascending or descending order based on the values of the first partial data bits of each of the corresponding data records stored in the corresponding first data fields.

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