A method for optimizing power consumption of multi-level MPRM logic circuits

Abstract

The present invention discloses a method for optimizing the power consumption of a multi-level MPRM logic circuit. By changing the layout of the logic network and the node order through the list method and the onset method, the power consumption of the highly optimized multi-level MPRM logic circuit can be effectively reduced while ensuring that the function of the logic network remains unchanged. Due to the combination of advanced cutting algorithms, the method of the present invention also has good optimization efficiency for large-area circuits. The experimental results of the EPFL and MCNC test sets show that the average power consumption optimization rate of the algorithm in this paper reaches 27.87% and 32.44% compared with the original circuit. Compared with the two-level MPRM power consumption optimization algorithm, the average area optimization rate is 4.04%, and the average power consumption optimization rate reaches 2.74%. The present invention provides a new research idea for the power consumption optimization of multi-level MPRM logic circuits: it not only provides a new method for reducing the power consumption of multi-level MPRM, but also effectively reduces the cost of integrated circuit design, which has strong theoretical and practical significance for electronic design automation.

Description

Technical Field

[0001] The invention relates to a method for simplifying a digital logic circuit, in particular to a method for optimizing power consumption of a multi-level MPRM logic circuit. Background Art

[0002] As the integration of integrated circuits increases, power consumption has become the second largest issue after performance in the field of high-end chip design, and has become the primary issue in the field of portable devices. At the logic level, integrated circuits can be represented as Reed-Muller logic circuits (RM logic circuits) with AND / XOR structures. Unlike Boolean logic circuits with AND / OR structures, the optimization technology of RM logic circuits is not yet mature. At the same time, studies have shown that in arithmetic circuits, parity check circuits, and communication circuits, RM logic circuits have more advantages than Boolean logic circuits in power consumption, area, speed, and testable lines. Therefore, research on RM logic circuits can effectively improve and develop electronic design automation.

[0003] RM logic circuits can be divided into fixed polarity RM (fixed polarity Reed-Muller, FPRM) and mixed polarity RM (mixed polarity Reed-Muller, MPRM) according to their polarity. FPRM requires that variables exist in logical expressions as positive variables or negative variables, while in MPRM, variables can exist in any form. The diversity of forms makes MPRM have better performance than FPRM, but it also brings complexity to the optimization method. Current research on MPRM mainly focuses on the two-level MPRM, in which the maximum number of gates connected in series between the input and output is two. Multi-level MPRM has no limit on the number of gates connected in series between the input and output gates, allowing the number of logic gates of the two-level MPRM to be further simplified.

[0004] Studies have shown that the power consumption of Reed-Muller is proportional to the sum of the jump probabilities of each logic node. The advantage of multi-level MPRM in the number of logic gates may be accompanied by an advantage in power consumption. Therefore, in order to improve the MPRM power consumption optimization method and meet the growing demand for low-power integrated circuit design, the present invention proposes a multi-level MPRM logic circuit power consumption optimization method, which changes the logic network layout and node order through the list method and the onset method, and effectively optimizes the power consumption of the multi-level MPRM logic circuit while ensuring that the logic network function remains unchanged. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a method for optimizing the power consumption of a multi-level MPRM logic circuit in response to the gaps in the prior art. The method obtains the two-level and multi-level MPRM expressions after power consumption optimization based on the list method and the onset method, respectively, and simultaneously selects the expression of the optimal power consumption to replace the original expression, thereby providing a new research idea for the power consumption optimization of the multi-level MPRM logic circuit; the method also has good optimization efficiency for large-area circuits.

[0006] The technical solution adopted by the present invention to solve the above technical problems is: a multi-level MPRM logic circuit power consumption optimization method, comprising the following steps:

[0007] Step 1: Take the multi-level MPRM logic circuit to be optimized as the input circuit and use the dynamic logic power consumption relationship Estimated total power consumption E of the input circuit, where pr(v a ) is the transition probability of node a in the input circuit, N is the total number of nodes in the input circuit, N≥1, k is a fixed coefficient, let k=1;

[0008] For the AND logic node v in the input circuit a1 , the jump probability calculation formula is pr(v a1 )=pr(x a1 )pr(y a1 ), where pr(x a1 ),pr(y a1 ) are respectively logical nodes v a1 Input;

[0009] For the XOR logic node v in the input circuit a2 , the jump probability calculation formula is pr(v a2 )=pr(x a2 )+pr(y a2 )-2pr(x a2 )pr(y a2 ), where pr(x a2 ),pr(y a2 ) are respectively logical nodes v a2 Input;

[0010] Step 2: Define a subcircuit as a cut set, which satisfies the following two conditions at the same time: (1) Any path from the input node of the circuit to the output node of the cut set must pass through at least one node of the cut set; (2) Except for the input node of the cut set, the outputs of other nodes are in the cut set; Search for a cut set in the input circuit that meets the above two conditions, which is recorded as cut set C; Evaluate the power consumption of cut set C based on the dynamic logic power consumption relationship in step 1, and record it as E1;

[0011] Step 3: Optimize the power consumption of cut set C. The specific steps are as follows:

[0012] Step 3-1, for the continuous AND logic gates in the cut set C:

[0013] Step 3-1-1, arrange the input nodes in the continuous AND logic gates in ascending order of transition probability to obtain node sequence A1;

[0014] Step 3-1-2: For the two nodes with the smallest jump probability in the node sequence A1, calculate their jump probability according to the AND logic node jump probability calculation formula in step 1 and obtain new nodes, delete these two nodes from the node sequence A1, and arrange the new nodes into the node sequence A1 according to the calculated jump probability;

[0015] Step 3-1-3, repeat step 3-1-2 until only one node remains in node sequence A1;

[0016] Step 3-2, for the continuous XOR logic gates in the cut set C:

[0017] Step 3-2-1, arrange the input nodes in the continuous XOR logic gates in ascending order of transition probability to obtain node sequence A2;

[0018] Step 3-2-2: For the two nodes with the largest and smallest jump probabilities among the nodes with jump probabilities greater than 0.5 in the node sequence A2, calculate their jump probabilities according to the XOR logic node jump probability calculation formula in step 1 and obtain new nodes, delete these two nodes from the node sequence A2, and arrange the new nodes into the node sequence A2 according to the calculated jump probabilities;

[0019] Step 3-2-3, repeat step 3-2-2 until the number of nodes in node sequence A2 with a jump probability greater than 0.5 is less than or equal to 1;

[0020] Step 3-2-4: For the two nodes with the smallest jump probability in the node sequence A2, calculate their jump probabilities according to the XOR logic node jump probability calculation formula in step 1 and obtain new nodes, delete these two nodes from the node sequence A2, and arrange the new nodes into the node sequence A2 according to the calculated jump probability;

[0021] Step 3-2-5, repeat step 3-2-4 until only one node remains in node sequence A2;

[0022] Step 4: For an MPRM with n input variables, there is an n-bit ternary polarity P. The polarity of the kth bit in the n-bit ternary polarity P is denoted as P k , where 0≤k <n,n≥1,P k Determines the input variables x in MPRMk The manifestation of: When P k =0, the variable x is allowed to be input k Appears or does not appear in the form of a positive variable; when P k =1, variable x is allowed to be input k Appears or does not appear in the form of an inverse variable; when P k =2, the variable x is allowed to be input k Appearing as a positive or negative variable;

[0023] Since the MPRM logic circuits of different polarities are different in complexity, based on the list method, all polarities of the sub-circuits corresponding to the cut set C are traversed to find the secondary MPRM with the optimal power consumption. The specific steps are as follows:

[0024] Step 4-1, read the truth table of the cut set C with n input variables and expand it into polarity P = 3 n -1, and transform it into the initial list L0, where the column of the initial list L0 is polarity P, and the list content i is represented by {0,1}; when the polarity P of the kth column in the initial list L0 k =0, the list content i is 0, indicating that the input variable x k Does not appear, the list content i is 1, indicating the input variable x k Appears in the form of a positive variable; when the polarity P of the kth column in the initial list L0 k =1, the list content i is 0, indicating the input variable x k Does not appear, the list content i is 1, indicating the input variable x k Appears in the form of an inverse variable; when the polarity P of the kth column in the initial list L0 k =2, the list content i is 0, indicating the input variable x k Appears in the form of an inverse variable, and the list content i is 1, indicating the input variable x k Appears as a positive variable;

[0025] Initialize target polarity P=0;

[0026] Step 4-2, initialize k=n-1, at this time the initial list L0 is the current list L;

[0027] Step 4-3, if P k =2, go to step 4-5; if P k = 0, extract the row with i = 0 in the kth column of the current list L to generate a temporary list L′, and make i = 1 in the kth column of the temporary list L′, and go to step 4-4; if P k =1, extract the row with i=1 in the kth column of the current list L to generate a temporary list L′, and make i=0 in the kth column of the temporary list L′, and go to step 4-4;

[0028] Step 4-4, delete the rows in the current list L with the same content as in the temporary list L′, and add the rows in the temporary list L′ with different content from the current list L to the current list L. If the polarity P of the kth column in the current list L is k =1, then invert the content i of the kth column and go to step 4-5;

[0029] Step 4-5, let k = k-1, if k ≥ 0, go to step 4-3, otherwise go to step 4-6;

[0030] Step 4-6: Optimize the power consumption of the secondary MPRM corresponding to the current list L through step 3 and record the power consumption; let P = P + 1, if P < n 3 , then go to step 4-2, otherwise go to step 4-7;

[0031] Step 4-7, compare the power consumption of the sub-circuits corresponding to the cut sets C of all polarities, record the minimum power consumption as E2, and the secondary MPRM expression corresponding to E2 is the secondary MPRM with optimal power consumption;

[0032] Step 5: Use the onset method to convert the two-level MPRM with polarity 0 into a multi-level MPRM and optimize its power consumption. The specific steps are as follows:

[0033] Step 5-1, convert the secondary MPRM with polarity 0 into onset list T. The column of onset list T is the variable number. The content of each line of the list is the AND terms of the secondary MPRM expression with polarity 0, represented by j=0,1. The content of each line of the list is 0, which means the input variable x k Appears, and the content of each line of the list is 1, indicating the input variable x k It does not appear, the rows are in an XOR relationship, and the columns are in an AND relationship; since AND logic and XOR logic satisfy the commutative law, the row-column exchange of the onset method does not affect its essence; since AND logic and XOR logic satisfy the associative law, the row-column extraction of the onset method does not affect its essence;

[0034] Step 5-2: If the contents of a column in the onset list T are all the same, extract the column, which can be viewed as follows:

[0035]

[0036] The remaining list after record extraction is the current onset list T′;

[0037] Step 5-3, continuously adjust the rows and columns of the current onset list T', find the rectangular sub-table ST1 with the largest area and all contents 1, and decompose the current onset list T' into: the rectangular sub-table ST1, the remaining sub-tables ST corresponding to the rows of the rectangular sub-table ST1 12 , the remaining rows form the subtable ST2, and ST 12 Replace the current onset list T′ and store ST2 in the register;

[0038] Step 5-4: If there is only one j=1 in each row of the current onset list T′, or there is only one row left in the current onset list T′, the remaining sub-table in the register replaces the current onset list T′, and go to step 5-2; if there is no sub-table in the register, the onset list optimization is completed, and go to step 5-5;

[0039] Step 5-5, convert the optimized onset list into a multi-level MPRM expression, and use step 3 to optimize the power consumption of the multi-level MPRM, record the power consumption as E3 and the multi-level MPRM expression corresponding to E3;

[0040] Step 6, compare the power consumption E1, E2, and E3, and replace the cut set C with the MPRM expression corresponding to the minimum value among the three and incorporate it into the input circuit; if the power consumption values ​​of two of the three are relatively small and the same, then select the MPRM expression with the least number of gate circuits corresponding to the two to replace the cut set C and incorporate it into the input circuit; if the power consumption values ​​of the three are the same, then select the MPRM expression with the least number of gate circuits corresponding to the three to replace the cut set C and incorporate it into the input circuit; if the power consumption values ​​and the corresponding number of gate circuits of the three are the same, then select the MPRM expression with the least number of gate circuits corresponding to any one to replace the cut set C and incorporate it into the input circuit;

[0041] Step 7: Repeat steps 2 to 6 until no cut sets are found in the input circuit, thus completing the power consumption optimization of the multi-level MPRM logic circuit.

[0042] Compared with the prior art, the present invention has the following advantages:

[0043] (1) The method of the present invention changes the layout of the logic network and the order of nodes through the list method and the onset method. Under the premise of ensuring that the function of the logic network remains unchanged, it can effectively reduce the power consumption of the highly optimized multi-level MPRM logic circuit. Compared with the conventional two-level MPRM power consumption optimization method, the method of the present invention can effectively reduce the area of ​​the circuit while effectively reducing the power consumption of the MPRM logic circuit. Experiments on the MCNC test set show that compared with the original circuit, the average power consumption optimization rate of the method of the present invention is 32.44%; compared with the existing two-level MPRM power consumption optimization method, the average area optimization rate of the method of the present invention reaches 4.04%, and the power consumption optimization rate reaches 2.74%.

[0044] (2) Due to the combination of advanced cutting algorithms, the method of the present invention also has good optimization efficiency for large-area circuits. Experiments in the EPFL circuit collection show that the average power consumption optimization rate of the method of the present invention reaches 27.87%. The present invention provides a new research idea for the power consumption optimization of multi-level MPRM logic circuits: it not only provides a new method for reducing the power consumption of multi-level MPRM, but also effectively reduces the cost of integrated circuit design, which has strong theoretical and practical significance for electronic design automation. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a cut-set circuit of router.aig, where the dotted line represents the inverter and the numbers represent the node transition probability;

[0046] Figure 2 is the secondary MPRM expression obtained by optimizing the cut set by the method of the present invention;

[0047] Figure 3 It is the solution step of onset method;

[0048] Figure 4 The multi-level MPRM expression solved for onset. DETAILED DESCRIPTION

[0049] The present invention is further described in detail below with reference to the accompanying drawings.

[0050] Figure 1 is a cut set of the router.aig circuit in the EPFL test set, which is a multi-level MPRM function, and its expression is: [(!((((ab)c)d)f)e)! e], where () represents AND logic, [] represents XOR logic, and ! represents negation. The power consumption is optimized by the method of the present invention. The jump probabilities of the initial input nodes of the cut set are 0.5, 0.5, 0.5, 0.5, 1, and 0, respectively. The power consumption of the cut set obtained by the dynamic logic power consumption relationship in step 1 of the present invention is 5.44. Figure 2 The secondary MPRM expression obtained by optimizing the cut set by the method of the present invention is: [(((((f!e)d)c)b)a)!e], and its total power consumption is reduced to 3. Compared with the original cut set expression, the power consumption optimization rate is 12.94%. Figure 3 is the onset optimization process of the cut set, which uses the onset table to Figure 2 The two-level MPRM expression is converted into a multi-level MPRM expression. Figure 4 For the multi-level MPRM logic circuit, its expression is: (!e!((((ab)c)d)f)), its power consumption is 3, and the power consumption optimization rate is 12.94% compared with the original cut set expression.

[0051] For the power consumption optimization of the above router.aig circuit, the specific optimization method adopted includes the following steps:

[0052] Step 1: Use the router.aig circuit as the input circuit and based on the dynamic logic power consumption relationship The total power consumption of the input circuit is evaluated to be E=89.1077;

[0053] Step 2: Define a subcircuit as a cut set. Optimize the overall circuit by optimizing each cut set. To avoid changing the logical structure of the circuit due to the optimization of the cut set, the cut set should satisfy the following two conditions: (1) Any path from the input node of the circuit to the output node of the cut set must pass through at least one node of the cut set; (2) Except for the input node of the cut set, the outputs of other nodes are in the cut set. Search for the cut set that meets the above two conditions in the input circuit, which is recorded as cut set C.

[0054] Based on the dynamic logic power consumption relation in step 1, the power consumption of cut set C is evaluated and recorded as E1=5.44;

[0055] Step 3: Optimize the power consumption of cut set C. The specific steps are as follows:

[0056] Step 3-1, for the continuous AND logic gates in the cut set C:

[0057] Step 3-1-1, arrange the input nodes in the continuous AND logic gates in ascending order of transition probability to obtain node sequence A1;

[0058] Step 3-1-2: For the two nodes with the smallest jump probability in the node sequence A1, calculate their jump probability according to the AND logic node jump probability calculation formula in step 1 and obtain new nodes, delete these two nodes from the node sequence A1, and arrange the new nodes into the node sequence A1 according to the calculated jump probability;

[0059] Step 3-1-3, repeat step 3-1-2 until only one node remains in node sequence A1;

[0060] Step 3-2, for the continuous XOR logic gates in the cut set C:

[0061] Step 3-2-1, arrange the input nodes in the continuous XOR logic gates in ascending order of transition probability to obtain node sequence A2;

[0062] Step 3-2-2: For the two nodes with the largest and smallest jump probabilities among the nodes with jump probabilities greater than 0.5 in the node sequence A2, calculate their jump probabilities according to the XOR logic node jump probability calculation formula in step 1 and obtain new nodes, delete these two nodes from the node sequence A2, and arrange the new nodes into the node sequence A2 according to the calculated jump probabilities;

[0063] Step 3-2-3, repeat step 3-2-2 until the number of nodes in node sequence A2 with a jump probability greater than 0.5 is less than or equal to 1;

[0064] Step 3-2-4: For the two nodes with the smallest jump probability in the node sequence A2, calculate their jump probabilities according to the XOR logic node jump probability calculation formula in step 1 and obtain new nodes, delete these two nodes from the node sequence A2, and arrange the new nodes into the node sequence A2 according to the calculated jump probability;

[0065] Step 3-2-5, repeat step 3-2-4 until only one node remains in node sequence A2;

[0066] Step 4: For an MPRM with n input variables, there is an n-bit ternary polarity P. The polarity of the kth bit in the n-bit ternary polarity P is denoted as P k , where 0≤k <n,n≥1,P k Determines the input variables x in MPRM k The manifestation of: When P k =0, the variable x is allowed to be input k Appears or does not appear in the form of a positive variable; when P k =1, variable x is allowed to be input k Appears or does not appear in the form of an inverse variable; when P k =2, the variable x is allowed to be input k Appearing as a positive or negative variable;

[0067] Since the MPRM logic circuits of different polarities are different in complexity, based on the list method, all polarities of the sub-circuits corresponding to the cut set C are traversed to find the secondary MPRM with the optimal power consumption. The specific steps are as follows:

[0068] Step 4-1, read the truth table of the cut set C with n input variables and expand it into polarity P = 3 n -1 (which is equivalent to the minimum term in polarity), and transforms it into an initial list L0, where the column of the initial list L0 is polarity P, and the list content i is represented by {0,1}; when the polarity P of the kth column in the initial list L0 k =0, the list content i is 0, indicating that the input variable x kDoes not appear, the list content i is 1, indicating the input variable x k Appears in the form of a positive variable; when the polarity P of the kth column in the initial list L0 k =1, the list content i is 0, indicating the input variable x k Does not appear, the list content i is 1, indicating the input variable x k Appears in the form of an inverse variable; when the polarity P of the kth column in the initial list L0 k =2, the list content i is 0, indicating the input variable x k Appears in the form of an inverse variable, and the list content i is 1, indicating the input variable x k Appears as a positive variable;

[0069] Initialize target polarity P=0;

[0070] Step 4-2, initialize k=5, at this time the initial list L0 is the current list L;

[0071] Step 4-3, if P k =2, go to step 4-5; if P k = 0, extract the row with i = 0 in the kth column of the current list L to generate a temporary list L′, and make i = 1 in the kth column of the temporary list L′, and go to step 4-4; if P k =1, extract the row with i=1 in the kth column of the current list L to generate a temporary list L′, and make i=0 in the kth column of the temporary list L′, and go to step 4-4;

[0072] Step 4-4, delete the rows in the current list L with the same content as in the temporary list L′, and add the rows in the temporary list L′ with different content from the current list L to the current list L. If the polarity P of the kth column in the current list L is k =1, then invert the content i of the kth column and go to step 4-5;

[0073] Step 4-5, let k = k-1, if k ≥ 0, go to step 4-3, otherwise go to step 4-6;

[0074] Step 4-6: Optimize the power consumption of the secondary MPRM corresponding to the current list L through step 3 and record the power consumption; let P = P + 1, if P < n 3 , then go to step 4-2, otherwise go to step 4-7;

[0075] Step 4-7: Compare the power consumption of the subcircuits corresponding to the cut sets C of all polarities, record the minimum power consumption as E2=3, and the secondary MPRM expression corresponding to E2 is the secondary MPRM with the optimal power consumption, as shown in Figure 2 As shown;

[0076] Step 5: Use the onset method to convert the two-level MPRM with polarity 0 into a multi-level MPRM and optimize its power consumption. The specific steps are as follows:

[0077] Step 5-1: Figure 3 As shown, the secondary MPRM with polarity 0 is converted into an onset list T. The column of the onset list T is the variable number. The content of each line of the list is the AND terms of the secondary MPRM expression with polarity 0, represented by j=0,1. The content of each line of the list is 0, which means the input variable x k Appears, and the content of each line of the list is 1, indicating the input variable x k It does not appear, the rows are in an XOR relationship, and the columns are in an AND relationship; since AND logic and XOR logic satisfy the commutative law, the row-column exchange of the onset method does not affect its essence; since AND logic and XOR logic satisfy the associative law, the row-column extraction of the onset method does not affect its essence;

[0078] Step 5-2: If the contents of a column in the onset list T are all the same, extract the column, which can be viewed as follows:

[0079]

[0080] The remaining list after record extraction is the current onset list T′;

[0081] Step 5-3, continuously adjust the rows and columns of the current onset list T', find the rectangular sub-table ST1 with the largest area and all contents 1, and decompose the current onset list T' into: the rectangular sub-table ST1, the remaining sub-tables ST corresponding to the rows of the rectangular sub-table ST1 12 , the remaining rows form the subtable ST2, and ST 12 Replace the current onset list T′ and store ST2 in the register;

[0082] Step 5-4: If there is only one j=1 in each row of the current onset list T′, or there is only one row left in the current onset list T′, the remaining sub-table in the register replaces the current onset list T′, and go to step 5-2; if there is no sub-table in the register, the onset list optimization is completed, and go to step 5-5;

[0083] Step 5-5, such as Figure 4 As shown, the optimized onset list is converted into a multi-level MPRM expression, and the multi-level MPRM is optimized for power consumption using step 3, and the power consumption is recorded as E3=3 and the multi-level MPRM expression corresponding to E3;

[0084] Step 6: Compare the power consumption E1, E2, and E3. Since E2 and E3 are both 3 and less than E1, the number of gate circuits (i.e., area) corresponding to E2 and E3 are 6 and 5 respectively. Select the MPRM expression corresponding to E3 to replace the cut set C and incorporate it into the input circuit.

[0085] Step 7: Repeat steps 2 to 6 until no cut sets are found in the input circuit, thus completing the power consumption optimization of the router.aig circuit.

[0086] The proposed multi-level MPRM logic circuit power optimization method is implemented in the open source EDA software also, tested on the EPFL and MCNC test sets, and compared with the two-level MPRM power optimization method mentioned in the literature (Li Hui, "Power and Area Optimization of Mixed Polarity Reed-Muller Logic Circuits," Master, Ningbo University, 2011.). The results are shown in Tables 1 and 2.

[0087] Table 1 Test results of EPFL test set

[0088]

[0089] Table 2 Test results of MCNC test set

[0090]

[0091] The experimental results of the EPFL test set show that the method of the present invention can effectively reduce the power consumption of the circuit, and has good optimization efficiency for large-area circuits. The average power consumption optimization rate of the method of the present invention reaches 27.87%. The test results of the MCNC test set show that compared with the two-level MPRM power consumption optimization method, the method of the present invention can effectively reduce the power consumption of the circuit while also reducing the area of ​​the circuit. Compared with the original circuit, the average power consumption optimization rate of the method of the present invention is 32.44%. Compared with the existing two-level MPRM power consumption optimization method, the average area optimization rate of the method of the present invention reaches 4.04%, and the power consumption optimization rate reaches 2.74%.

[0092] The present invention provides a new research idea for the power consumption optimization of multi-level MPRM logic circuits: it not only provides a new algorithm for reducing the power consumption of logic circuits, but also effectively reduces the cost of logic circuit design, and has strong theoretical and practical significance for electronic design automation.

Claims

1. A method for optimizing power consumption of a multi-level MPRM logic circuit, characterized in that: The following steps are involved: Step 1: Take the multi-level MPRM logic circuit to be optimized as the input circuit and use the dynamic logic power consumption relationship Estimated total power consumption E of the input circuit, where pr(v a ) is the node v in the input circuit a The jump probability, N is the total number of nodes in the input circuit, N ≥ 1, k is a fixed coefficient, let k = 1; For the AND logic node v in the input circuit a1 , the jump probability calculation formula is pr(v a1 )=pr(x a1 )pr(y a1 ), where pr(x a1 ),pr(y a1 ) are respectively logical nodes v a1 Input; For the XOR logic node v in the input circuit a2 , the jump probability calculation formula is pr(v a2 )=pr(x a2 )+pr(y a2 )-2pr(x a2 )pr(y a2 ), where pr(x a2 ),pr(y a2 ) are respectively logical nodes v a2 Input; Step 2: Define a subcircuit as a cut set, which satisfies the following two conditions at the same time: (1) Any path from the input node of the circuit to the output node of the cut set must pass through at least one node of the cut set; (2) Except for the input node of the cut set, the outputs of other nodes are in the cut set; Search for a cut set in the input circuit that meets the above two conditions, which is recorded as cut set C; Evaluate the power consumption of cut set C based on the dynamic logic power consumption relationship in step 1, and record it as E1; Step 3: Optimize the power consumption of cut set C. The specific steps are as follows: Step 3-1, for the continuous AND logic gates in the cut set C: Step 3-1-1, arrange the input nodes in the continuous AND logic gates in ascending order of transition probability to obtain node sequence A1; Step 3-1-2: For the two nodes with the smallest jump probability in the node sequence A1, calculate their jump probability according to the AND logic node jump probability calculation formula in step 1 and obtain new nodes, delete these two nodes from the node sequence A1, and arrange the new nodes into the node sequence A1 according to the calculated jump probability; Step 3-1-3, repeat step 3-1-2 until only one node remains in node sequence A1; Step 3-2, for the continuous XOR logic gates in the cut set C: Step 3-2-1, arrange the input nodes in the continuous XOR logic gates in ascending order of transition probability to obtain node sequence A2; Step 3-2-2: For the two nodes with the largest and smallest jump probabilities among the nodes with jump probabilities greater than 0.5 in the node sequence A2, calculate their jump probabilities according to the XOR logic node jump probability calculation formula in step 1 and obtain new nodes, delete these two nodes from the node sequence A2, and arrange the new nodes into the node sequence A2 according to the calculated jump probabilities; Step 3-2-3, repeat step 3-2-2 until the number of nodes in node sequence A2 with a jump probability greater than 0.5 is less than or equal to 1; Step 3-2-4: For the two nodes with the smallest jump probability in the node sequence A2, calculate their jump probabilities according to the XOR logic node jump probability calculation formula in step 1 and obtain new nodes, delete these two nodes from the node sequence A2, and arrange the new nodes into the node sequence A2 according to the calculated jump probability; Step 3-2-5, repeat step 3-2-4 until only one node remains in node sequence A2; Step 4: For an MPRM with n input variables, there is an n-bit ternary polarity P. The polarity of the kth bit in the n-bit ternary polarity P is denoted as P k , where 0≤k<n, n≥1, P k Determines the input variables x in MPRM k The manifestation of: When P k =0, the variable x is allowed to be input k Appears or does not appear in the form of a positive variable; when P k =1, variable x is allowed to be input k Appears or does not appear in the form of an inverse variable; when P k =2, the variable x is allowed to be input k Appears as a positive or negative variable; Since the MPRM logic circuits of different polarities are different in complexity, based on the list method, all polarities of the sub-circuits corresponding to the cut set C are traversed to find the secondary MPRM with the optimal power consumption. The specific steps are as follows: Step 4-1, read the truth table of the cut set C with n input variables and expand it into polarity P = 3 n -1, and transform it into the initial list L0, where the column of the initial list L0 is polarity P, and the list content i is represented by {0,1}; when the polarity P of the kth column in the initial list L0 k =0, the list content i is 0, indicating that the input variable x k Does not appear, the list content i is 1, indicating the input variable x k Appears in the form of a positive variable; when the polarity P of the kth column in the initial list L0 k =1, the list content i is 0, indicating the input variable x k Does not appear, the list content i is 1, indicating the input variable x k Appears in the form of an inverse variable; when the polarity P of the kth column in the initial list L0 k =2, the list content i is 0, indicating the input variable x k Appears in the form of an inverse variable, and the list content i is 1, indicating the input variable x k Appears as a positive variable; Initialize target polarity P=0; Step 4-2, initialize k=n-1, at this time the initial list L0 is the current list L; Step 4-3, if P k =2, go to step 4-5; if P k = 0, extract the row with i = 0 in the kth column of the current list L to generate a temporary list L′, and make i = 1 in the kth column of the temporary list L′, and go to step 4-4; if P k =1, extract the row with i=1 in the kth column of the current list L to generate a temporary list L′, and make i=0 in the kth column of the temporary list L′, and go to step 4-4; Step 4-4, delete the rows in the current list L with the same content as in the temporary list L′, and add the rows in the temporary list L′ with different content from the current list L to the current list L. If the polarity P of the kth column in the current list L is k =1, then invert the content i of the kth column and go to step 4-5; Step 4-5, let k = k-1, if k ≥ 0, go to step 4-3, otherwise go to step 4-6; Step 4-6: Optimize the power consumption of the secondary MPRM corresponding to the current list L through step 3 and record the power consumption; let P = P + 1, if P < n 3 , then go to step 4-2, otherwise go to step 4-7; Step 4-7, compare the power consumption of the sub-circuits corresponding to the cut sets C of all polarities, record the minimum power consumption as E2, and the secondary MPRM expression corresponding to E2 is the secondary MPRM with optimal power consumption; Step 5: Use the onset method to convert the two-level MPRM with polarity 0 into a multi-level MPRM and optimize its power consumption. The specific steps are as follows: Step 5-1, convert the secondary MPRM with polarity 0 into onset list T. The column of onset list T is the variable number. The content of each line of the list is the AND terms of the secondary MPRM expression with polarity 0, represented by j=0,1. The content of each line of the list is 0, which means the input variable x k Appears, and the content of each line of the list is 1, indicating the input variable x k It does not appear, the rows are in an XOR relationship, and the columns are in an AND relationship; since AND logic and XOR logic satisfy the commutative law, the row-column exchange of the onset method does not affect its essence; since AND logic and XOR logic satisfy the associative law, the row-column extraction of the onset method does not affect its essence; Step 5-2: If the contents of a column in the onset list T are all the same, extract the column, which is essentially: The remaining list after record extraction is the current onset list T′; Step 5-3, continuously adjust the rows and columns of the current onset list T', find the rectangular sub-table ST1 with the largest area and all contents 1, and decompose the current onset list T' into: the rectangular sub-table ST1, the remaining sub-tables ST corresponding to the rows of the rectangular sub-table ST1 12 , the remaining rows form the subtable ST2, and ST 12 Replace the current onset list T′ and store ST2 in the register; Step 5-4: If there is only one j=1 in each row of the current onset list T′, or there is only one row left in the current onset list T′, the remaining sub-table in the register replaces the current onset list T′, and go to step 5-2; if there is no sub-table in the register, the onset list optimization is completed, and go to step 5-5; Step 5-5, convert the optimized onset list into a multi-level MPRM expression, and use step 3 to optimize the power consumption of the multi-level MPRM, record the power consumption as E3 and the multi-level MPRM expression corresponding to E3; Step 6, compare the power consumption E1, E2, and E3, and replace the cut set C with the MPRM expression corresponding to the minimum value among the three and incorporate it into the input circuit; if the power consumption values ​​of two of the three are relatively small and the same, then select the MPRM expression with the least number of gate circuits corresponding to the two to replace the cut set C and incorporate it into the input circuit; if the power consumption values ​​of the three are the same, then select the MPRM expression with the least number of gate circuits corresponding to the three to replace the cut set C and incorporate it into the input circuit; if the power consumption values ​​and the corresponding number of gate circuits of the three are the same, then select the MPRM expression with the least number of gate circuits corresponding to any one to replace the cut set C and incorporate it into the input circuit; Step 7: Repeat steps 2 to 6 until no cut sets are found in the input circuit, thus completing the power consumption optimization of the multi-level MPRM logic circuit.

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