Packaged devices and methods of forming the same

Abstract

The packaged device includes a first device die and a second device die bonded thereto. When the area of the second device die is less than half the area of the first device die, one or more non-active structures having a semiconductor substrate are also bonded to the first device die such that the combined area of the second device die and the one or more non-active structures is greater than half the area of the first device die. Embodiments of the present application also relate to methods of forming a packaged device.

Description

Technical Field

[0001] Embodiments of this application relate to packaged devices and methods of forming the same. Background Technology

[0002] Integrated circuit packages are becoming increasingly complex, with more device dies packed into a single package to achieve more functions. For example, System-on-Chip (SoIC) has been developed to include multiple device dies, such as processors and memory datasets, in a single package. SoIC can include device dies formed using different technologies and have different functions bonded to the same device die, thus forming a system. This can save manufacturing costs and optimize device performance. Summary of the Invention

[0003] Embodiments of this application provide a method for forming a packaged device, comprising: providing a first device die, the first device die including an active device disposed therein, the first device die having a first surface area; bonding a second device die to the first device die, the second device die having a second surface area less than half of the first surface area; bonding one or more non-active structures to the first device die, the one or more non-active structures having a cumulative third surface area, the second surface area and the cumulative third surface area together being greater than half of the first surface area; and filling a gap laterally surrounding the second device die and the one or more non-active structures with a gap-filling material.

[0004] Other embodiments of this application provide a packaged device comprising: a first device die having a first coverage area; a second device die bonded to the first device die having a second coverage area less than half the first coverage area, the second device die including a semiconductor substrate; one or more non-active structures bonded to the first device die adjacent to the second device die, the one or more non-active structures including a semiconductor substrate without any active devices; a gap filler material laterally surrounding the second device die and the one or more non-active structures; and a connector structure disposed above the gap filler material, the connector structure being electrically coupled to the second device die.

[0005] Some embodiments of this application provide a packaged device, including: a first device die; a second device die bonded to the first device die; one or more non-active structures bonded to the first device die, wherein the cumulative area of ​​the second device die and the one or more non-active structures is greater than 50% of the area of ​​the first device die; a dielectric layer laterally surrounding the second device die and the one or more non-active structures; and a connector structure disposed above the dielectric layer, the connector structure being electrically coupled to the second device die. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1 A perspective view of a packaged device in an intermediate step according to some embodiments is shown.

[0008] Figure 2 A top view of a package assembly having multiple device dies defined therein is shown.

[0009] Figures 3 to 6 A cross-sectional view of an intermediate stage in forming a packaged device is shown according to some embodiments of the present invention.

[0010] Figure 7 This is a top view of a device die disposed on another device die according to some embodiments.

[0011] Figure 8 A top view of an active packaged component with multiple non-active structures defined therein is shown.

[0012] Figures 9 to 22 Intermediate stages for various non-active structures according to some embodiments are shown, as well as their relationship to the device die.

[0013] Figures 23 to 28 Intermediate steps for forming a packaged device, according to some embodiments, including a first device die, one or more second device dies attached thereto, and one or more non-active structures also attached thereto.

[0014] Figures 29 to 37 A packaged device having a first device die, one or more device dies attached thereto, and one or more non-active structures also attached thereto, according to various embodiments, is shown. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] According to various embodiments, integrated system-on-a-chip (SoIC) packages and methods of forming them are provided. Intermediate stages of forming the SoIC package are shown according to some embodiments. Variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. It should be understood that while the formation of the SoIC package is used as an example to explain the concept of embodiments of the invention, embodiments of the invention are readily applicable to other bonding methods and structures where metal pads and vias are joined together.

[0018] Figure 1 A perspective view of a SoIC packaged device at an intermediate step according to some embodiments is shown. While some examples of the types of device dies 105 and 205 are listed below, device dies 105 and 205 can be any die. Device die 105 can be a logic die, such as a central processing unit (CPU) die, a microcontroller unit (MCU) die, an input / output (I / O) die, a baseband (BB) die, an application processor (AP) die, etc. Device die 105 can also be a memory die, such as a dynamic random access memory (DRAM) die or a static random access memory (SRAM) die, etc. Device die 105 can be a portion of a wafer (see [link to wafer diagram]). Figure 2Device die 205 is electrically bonded to device die 105. Device die 205 can be a logic die, such as a CPU die, MCU die, I / O die, baseband die, or AP die. Device die 205 can also be a memory die. Multiple device dies 205 can be bonded to device die 105, each with a different function.

[0019] The non-active structures 305 / 405 / 505 / 605 / 705 are bonded to the device die 105 and can be used to support the dielectric layer serving as the gap fill material for the package device 800 by reducing the overall thermal expansion mismatch and thus reducing warpage (see, for example, Figure 28 The gap is filled with dielectric layer 162). The passive structures 305, 405, 505, 605, and 705 are described in detail below. Each of the passive structures 305, 405, 505, and 605 is a pseudo-structure that does not provide electrical functionality in the final package (i.e., is electrically isolated from the active devices of the device die 105), but in some embodiments provides structural support and can provide heat dissipation characteristics. However, in addition to structural support and heat dissipation, the passive structure 705 can also include electrical functionality through vias, as discussed in more detail below.

[0020] In some embodiments, a plurality of passive structures 305 / 405 / 505 / 605 / 705 can be used in various combinations of passive structures 305, 405, 505, 605, and 705. In some embodiments, the passive structures 305 / 405 / 505 / 605 / 705 (see, for example) are used to form laterally surrounding the device die 205. Figure 28 The gap-filling dielectric layer 162 is made of the same material (e.g., oxide) used to bond the non-active structures 305 / 405 / 505 / 605 / 705 and device die 205 to device die 105. In another embodiment, the gap-filling dielectric layer 162 is a passivation or protective dielectric used to seal the non-active structures 305 / 405 / 505 / 605 / 705 and device die 205.

[0021] Figure 2 A package assembly 100 (which may be a wafer, as shown) with a plurality of device dies 105 defined therein is illustrated. The device dies 105 may all have the same design and function, or they may have different designs and functions. Dashed lines indicate dicing lines 106, where the device dies 105 will be separated from each other in a subsequent dicing process.

[0022] Figures 3 to 5 A cross-sectional view of an intermediate stage in the formation of a SoIC package is shown according to some embodiments of the present invention. Figure 3A cross-sectional view is shown in the formation of package assembly 100. According to some embodiments of the invention, package assembly 100 is a portion of a device wafer including integrated circuit devices 122, such as active devices like transistors and / or diodes, and possibly passive devices such as capacitors, inductors, resistors, etc. Package assembly 100 may include a plurality of device dies 105; portions of device die 105a and device die 105b are shown. It should be understood that these views are illustrative only and not limiting.

[0023] According to other embodiments of the invention, the package assembly 100 includes passive devices (no active devices). In some embodiments, and as referenced in the discussion below, the package assembly 100 may be a device wafer. Embodiments of the invention may also be applied to other types of package assemblies, such as interposer wafers.

[0024] According to some embodiments of the present invention, wafer 100 includes a semiconductor substrate 120 and components formed on the top surface of the semiconductor substrate 120. The semiconductor substrate 120 may be formed of crystalline silicon, crystalline germanium, crystalline silicon-germanium, and / or III-V compound semiconductors such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. The semiconductor substrate 120 may also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 120 to isolate active regions in the semiconductor substrate 120. Although not shown, vias extending into the semiconductor substrate 120 may be formed, and these vias are used to electrically couple components on opposite sides of the wafer 100. An example of such vias is... Figure 4 The through-hole 216 can be integrated into Figure 3 middle.

[0025] According to some embodiments of the present invention, wafer 100 includes an integrated circuit device 122 formed on the top surface of semiconductor substrate 120. Exemplary integrated circuit device 122 may include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit device 122 are not shown herein. According to other embodiments, wafer 100 is used to form an interposer layer, wherein semiconductor substrate 120 may be a semiconductor substrate or a dielectric substrate.

[0026] An interlayer dielectric (ILD) 124 is formed above a semiconductor substrate 120 to fill the gaps between the gate stacks (not shown) of transistors in the integrated circuit device 122. According to some embodiments, the ILD 124 is made of silicon oxide formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethyl orthosilicate (TEOS), etc. The ILD 124 can be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0027] Contact plugs 128 are formed in ILD 124 for electrically connecting integrated circuit device 122 to metal lines 134 and vias 136 thereon. According to some embodiments of the invention, contact plugs 128 are formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. Forming contact plugs 128 may include: forming contact openings in ILD 124; filling the contact openings with conductive material; and performing planarization (such as a chemical mechanical polishing (CMP) process) to make the top surface of contact plugs 128 flush with the top surface of ILD 124.

[0028] An interconnect structure 130 is present above the ILD 124 and the contact plug 128. The interconnect structure 130 includes a dielectric layer 132 and metal lines 134 and vias 136 formed in the dielectric layer 132. The dielectric layer 132 is optionally referred to below as an inter-metal dielectric (IMD) layer 132. According to some embodiments of the invention, at least the lower dielectric layer 132 is formed of a low-k dielectric material having a dielectric constant (k value) of less than about 3.0 or about 2.5. The dielectric layer 132 may be formed of Black Diamond (a registered trademark of Applied Materials), a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to alternative embodiments of the invention, some or all of the dielectric layer 132 is formed of a non-low-k dielectric material, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbonitride oxycarbonate (SiOCN), etc. According to some embodiments of the present invention, forming the dielectric layer 132 includes: depositing a dielectric material containing a pore-forming agent; and then performing a curing process to remove the pore-forming agent, and thus the remaining dielectric layer 132 becomes porous. An etch stop layer (not shown), which may be formed of silicon carbide, silicon nitride, etc., may be formed between the IMD layers 132, and is not shown for simplicity.

[0029] Metal lines 134 and vias 136 are formed in dielectric layer 132. Metal lines 134 at the same level are collectively referred to below as metal layers. According to some embodiments of the invention, interconnect structure 130 includes multiple metal layers interconnected vias 136. Metal lines 134 and vias 136 may be formed of copper or a copper alloy, and they may also be formed of other metals. Formation processes may include single damascene and double damascene processes. In a single damascene process, a trench is first formed in one of the dielectric layers 132, and then the trench is filled with a conductive material. A planarization process, such as CMP, is then performed to remove excess conductive material above the top surface of the IMD layer, leaving metal lines in the trench. In a double damascene process, trenches and via openings are formed in the IMD layer, the via openings being below and connected to the trench. Conductive material is then filled into the trenches and via openings to form metal lines and vias, respectively. The conductive material may include a diffusion barrier and a copper-containing metal material above the diffusion barrier. Diffusion barrier components may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0030] Metal line 134 includes metal line 134A, which may be referred to as the top metal line. Top metal line 134A is also collectively referred to as the top metal layer. The corresponding dielectric layer 132A may be formed of a non-low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, etc. Dielectric layer 132A may also be formed of a low-k dielectric material, which may be selected from similar materials to the underlying IMD layer 132.

[0031] According to some embodiments of the present invention, dielectric layers 138 and 152 are formed over a top metal line 134A. Dielectric layers 138 and 152 may be formed of silicon oxide, silicon oxynitride, silicon oxycarbide, etc., and in some embodiments, dielectric layer 138 may be formed of, for example, multiple dielectric layers 138A, 138B, and 138C. First, dielectric layer 138A may be formed. Next, a via opening corresponding to via 146 may be formed in dielectric layer 138A using a photolithography process, which utilizes, for example, a photoresist and / or a hard mask formed and patterned over dielectric layer 138A to aid in forming the via opening corresponding to via 146. Anisotropic etching may be used to form these trenches through the photoresist and / or hard mask.

[0032] Vias 146 and metal components 144 can be formed above dielectric layer 138A. Vias 146 and metal components 144 can be formed using a process similar to that used to form vias 136 and metal lines 134 as described above, but other suitable processes can be used. Metal components 144 and vias 146 can be formed of copper or a copper alloy, and they can also be formed of other metals. In embodiments, metal components 144 and / or vias 146 can be formed of aluminum or an aluminum-copper alloy. In some embodiments, metal components 144 can be used for die testing.

[0033] In some embodiments, the metal part 144 can be directly probed for performing chip probe (CP) testing on the wafer 100. Optionally, solder regions (e.g., solder balls or solder bumps) can be provided on the metal part 144, and these solder regions can be used to perform CP testing on the wafer 100. CP testing can be performed on the wafer 100 to determine whether each device die 105 of the wafer 100 is a known good die (KGD). Therefore, only KGD device dies 105 are subsequently processed for packaging, and dies that fail the CP test are not packaged. After testing, the solder regions (if present) can be removed in subsequent processing steps.

[0034] Then, a dielectric layer 138B can be deposited over the metal component 144 until the desired thickness is achieved. In some embodiments, the dielectric layer 138B can then be planarized to flatten the top surface, while in other embodiments, the planarization step can be omitted. In some embodiments, a dielectric layer 138C is then deposited. In other embodiments, the dielectric layer 138C may not be used and can be omitted.

[0035] Next, bonding pad vias 156 and 157 can be formed. Bonding pad via 156 extends through the entire dielectric layer 138 to the interconnect structure 130, and bonding pad via 157 extends to and is electrically coupled to the metal part 144. A photoresist (not shown) and / or a hard mask (not shown) formed and patterned over the dielectric layer 138 can be used to help form openings for bonding pad vias 156 and 157. According to some embodiments of the invention, anisotropic etching is performed to form the openings. The etching can stop on the metal part 144 for bonding pad via 157 or on the metal line 134 of the interconnect structure 130 for bonding pad via 156.

[0036] Next, the openings for bonding pad vias 156 and 157 can be filled with a conductive material. First, a conductive diffusion barrier (not shown) can be formed. According to some embodiments of the invention, the conductive diffusion barrier can be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive diffusion barrier can be formed, for example, using atomic layer deposition (ALD), physical vapor deposition (PVD), etc. The conductive diffusion barrier may include a layer in the openings for bonding pad vias 156 and 157, and a layer extending above the upper surface of the dielectric layer 138.

[0037] Next, a metal material is deposited to form bonding pad vias 156 and 157, for example, by electrochemical plating (ECP). Metal material is deposited on the conductive diffusion barrier to fill the remaining openings for bonding pad vias 156 and 157. The metal material may also extend over the top surface of the dielectric layer 138. The metal material may include copper or a copper alloy. Bonding pad vias 156 and 157 can be formed simultaneously.

[0038] A planarization process, such as chemical mechanical polishing (CMP), can then be performed to remove excess metal material and diffusion barriers until the dielectric layer 138 is exposed. The remaining diffusion barriers and metal material include bonding pad vias 156 and 157.

[0039] Next, a dielectric bonding layer 152 may be formed over the dielectric layer 138 and the opening formed therein for the bonding pad 154. The opening may be formed using a photoresist (not shown) and / or a hard mask (not shown) formed and patterned over the dielectric bonding layer 152 to aid in forming the opening for the bonding pad 154. According to some embodiments of the invention, anisotropic etching or wet etching is performed to form the opening for the bonding pad 154. In some embodiments, etching may be stopped on the dielectric layer 138C, which may act as an etch stop. In other embodiments, the dielectric bonding layer 152 may have etch selectivity over the dielectric layer 138, such that etching does not pass through the dielectric layer 138 after etching through the dielectric bonding layer 152. In some embodiments, etching may be time-based. The opening for the bonding pad 154 may expose the upper surfaces of the bonding pad vias 156 and 157.

[0040] Next, a diffusion barrier and metallic material can be deposited in the opening to form a bonding pad 154. The bonding pad 154 can be formed using processes and materials similar to those described above for forming bonding pad vias 156 and 157. A planarization process, such as chemical mechanical polishing (CMP), can then be performed to remove excess portions of the metallic material and diffusion barrier until the dielectric bonding layer 152 is exposed. The remaining portions of the diffusion barrier and metallic material comprise the bonding pad 154 subsequently used for bonding to another device. It should be understood that metal lines can also be formed simultaneously as bonding pads 154.

[0041] In some embodiments, bonding pad vias 156 and 157 may be formed simultaneously with bonding pad 154. In such embodiments, after forming dielectric bonding layer 152, openings are formed in dielectric bonding layer 152 as described above. Further openings are then made in dielectric layer 138 for bonding pad vias 156 and 157, as described above. Conductive diffusion barriers and metal material can then be formed for bonding pad vias 156 and 157 and bonding pad 154 in the same process, as described above. A planarization process, such as CMP, can then be used to remove excess metal material and diffusion barriers until dielectric bonding layer 152 is exposed. The remaining portion of diffusion barriers and metal material comprises bonding pads 154 subsequently used for bonding to another device. Metal lines may also be formed simultaneously as bonding pads 154.

[0042] The location and number of bonding pads 154 can be adjusted based on the devices to which they will be bonded in subsequent processes. In some embodiments, one or more of the bonding pads 154 may not be electrically connected to any device in the device die 105. Such pads 154 can be considered dummy bonding pads. In some embodiments, dummy bonding pads 154 may continue across the surface of the device die 105, while in other embodiments, bonding pads 154 including dummy bonding pads may be located only at locations where other devices are to be attached.

[0043] Figure 4 A wafer 200 is shown, which includes device dies 205 (e.g., device dies 205a and device dies 205b). According to some embodiments of the invention, device die 205 is a logic die, which may be a CPU die, an MCU die, an I / O die, a baseband die, or an AP die. Device die 205 may also be a memory die. Wafer 200 includes a semiconductor substrate 220, which may be a silicon substrate.

[0044] Device die 205 may include integrated circuit device 222, ILD 224 above integrated circuit device 222, and contact plug 228 electrically connected to integrated circuit device 222. Device die 205 may also include interconnect structure 230 for connecting active and passive devices in device die 205. Interconnect structure 230 includes metal lines 234 and through holes 236.

[0045] A through-silicon via (TSV) 216 (sometimes referred to as a semiconductor via or simply via) is formed to penetrate into the semiconductor substrate 220 (and ultimately through the semiconductor substrate 220 by being exposed from the opposite side). The TSV 216 is used to connect devices and metal lines formed on the front side (top side shown) of the semiconductor substrate 220 to the back side. The TSV 216 can be formed using processes and materials similar to those discussed above for forming the bonding pad via 156, and will not be repeated here, including, for example, time-based etching processes, such that the TSV 216 can have a bottom disposed between the top and bottom surfaces of the semiconductor substrate 220.

[0046] Device die 205 may include a dielectric layer 238 and a dielectric bonding layer 252. Vias 246 and metal components 244 may be formed in the dielectric layer 238 (which may include multiple dielectric layers 238A, 238B, and 238C). Bonding pad vias 256 and 257 are also formed in the dielectric layer 238, and bonding pads 254 are formed in the dielectric bonding layer 252.

[0047] The processes and materials used to form the various components of device die 205 can be similar to those used to form the same components in device die 105, and therefore will not be repeated here. Identical components between device die 105 and device die 205 share the same last two reference numerals in their labels.

[0048] The wafer 200 is divided into a plurality of discrete device dies 205, including, for example, device die 205a and device die 205b.

[0049] Figure 5 The diagram illustrates bonding device dies 205 (such as device die 205a) to device die 105. In the illustrated embodiment, each of device dies 105 remains within wafer 100. In some embodiments, each of the KGD device dies 105 may be diced from wafer 100 and, for example, attached to a carrier substrate for further processing. Each device die 205 bonded to device die 105 may have been tested and determined to be KGD prior to bonding to device die 105.

[0050] Although one die 205 is shown bonded to die 105, it should be understood that other dies, like die 205, may be bonded to die 105. These other dies may be the same as or different from die 205. For example, die 205 and the other dies may be different types of dies selected from those listed above. Furthermore, die 205 and the other dies may be formed using different technologies such as 45nm, 28nm, 20nm, etc. Moreover, die 205 may be a digital circuit die, while the other dies may be analog circuit dies. Dies 105 and 205 (and other dies, if present) are combined to serve as a system. Dividing the system's functionality and circuitry into different dies such as dies 105 and 205 optimizes the formation of these dies and can reduce manufacturing costs.

[0051] Figure 6 It shows Figure 5 A close-up of the dashed box. One of the device dies 205 (such as device die 205a) can be placed on wafer 100, for example, by a pick-and-place process. Bonding device die 205 to device die 105 can be achieved through hybrid bonding. For example, bonding pad 254 is bonded to bonding pad 154 by metal-to-metal direct bonding. According to some embodiments of the invention, the metal-to-metal direct bonding is copper-to-copper direct bonding. Bonding pad 254 can have a size greater than, equal to, or smaller than the size of the corresponding bonding pad 154. Furthermore, dielectric bonding layer 252 is bonded to dielectric bonding layer 152 by dielectric-to-dielectric bonding, which can be a fusion bonding, for example, forming Si-O-Si bonds. A gap 302 is left around device die 205 and between adjacent device dies 205.

[0052] To achieve hybrid bonding, device die 205 is positioned relative to device die 105 to align their respective bonding pads 154 and 254, and device die 105 and device die 205 are pressed together. Then, annealing is performed to allow the metals in bonding pad 154 and the corresponding upper bonding pad 254 to interdiffusion. According to some embodiments, the annealing temperature can be higher than about 350°C, and can be in the range between about 350°C and about 550°C. According to some embodiments, the annealing time can be in the range between about 1.5 hours and about 3.0 hours, and can be in the range between about 1.0 hour and about 2.5 hours. Through hybrid bonding, bonding pad 254 is bonded to the corresponding bonding pad 154 by direct metal bonding caused by metal interdiffusion. Similarly, dielectric bonding layer 252 is fused to the corresponding dielectric bonding layer 152. The bonding pads 154 / 254 of a device die 105 / 205 are not bonded to the area where they contact the dielectric bonding layer 254 / 154 of the opposite device die 205 / 105.

[0053] Figure 7 This is a top view (i.e., a plan view) of a device die 205 (such as device die 205a) on a device die 105 according to some embodiments. A gap 302 is shown surrounding the device die 205. The gap 302 may be filled using a gap-filling material (see, for example, Figure 28 The interstitial filling dielectric layer 162 may be a dielectric material, such as a resin, epoxy resin, polymer, oxide, nitride, or combination thereof. Typically, the interstitial filling material is an organic material. Some dielectric materials typically have a high coefficient of thermal expansion (CTE), which can be 10 ppm / °C or higher. This is significantly greater than the CTE of silicon (such as semiconductor substrate 220), which has a CTE of about 3 ppm / °C. Therefore, some dielectric materials can cause warping of wafer 100. If such a material is used as the interstitial filling material in this embodiment, for example, warping may occur because the semiconductor substrate 220, which includes silicon (such as pure silicon or doped silicon), Figure 4 The CTE of device die 105 has a large CTE mismatch between the gap fill material surrounding it. For example, the lateral area A1 (i.e., the coverage area or surface area) of device die 105 is more than twice the lateral area A2 (i.e., the coverage area or surface area) of device die 205. Or in other words, the lateral area A2 is less than 50% of the lateral area A1. Reducing the amount of gap fill material relative to the semiconductor substrate 220 of device die 205 will reduce warpage. However, considering subsequent processes such as the addition of top interconnects and top connectors, eliminating or reducing the gap fill material may be impractical.

[0054] Embodiments of the present invention effectively increase the total lateral area or coverage area (or surface area) of device die 205 by attaching non-active or pseudo-structures (such as non-active structures 305, 405, 505, 605 and / or 705) to the surface of device die 105, such that the lateral area A2 of device die 205 plus the lateral area of ​​one or more non-active structures (e.g., lateral area A3) is greater than 50% of the lateral area A1 of device die 105. This reduces the effective lateral mismatch between the subsequently formed gap fill material and the semiconductor substrate 220 of device die 205. Therefore, wafer 100 and the resulting packaged device 800 (see, for example, Figure 28 The warpage is significantly reduced. Non-active structures 305, 405, 505, 605 and / or 705 can be selected such that the lateral area of ​​their combination plus the lateral area of ​​device die 205 is at least 50% to about 95% of the lateral area A1 of device die 105.

[0055] Figure 8 A top view (i.e., plan view) of an active package assembly 300, 400, 500, 600, or 700 (which may be a wafer, as shown) having a plurality of passive structures 305, 405, 505, 605, or 705 defined therein is shown. For simplicity, the passive package assemblies 300, 400, 500, 600, and 700 will each be referred to as wafer 300, wafer 400, wafer 500, wafer 600, and wafer 700, respectively; however, it should be understood that the resulting package assembly may be formed from structures other than wafers. Each of the plurality of passive structures 305, 405, 505, 605, or 705 may have the same overall design. Dashed lines indicate dicing lines 306, where the passive structures 305, 405, 505, 605, or 705 will be separated from each other in a subsequent dicing process. In some embodiments, the cut lines 306 may be spaced at regular intervals or at varying intervals, such as in the illustrated embodiment, to provide several non-active structures 305, 405, 505, 605 and 705 of different sizes from the individual package components 300, 400, 500, 600 or 700.

[0056] Figure 9 A wafer 300 with a plurality of non-active structures 305 defined therein is shown according to some embodiments. The wafer 300 includes a semiconductor substrate 320, which may be made of materials as described above. Figure 3 The semiconductor substrate 320 is formed from the same candidate material described in the semiconductor substrate 120. In particular, the semiconductor substrate 320 may be formed from the same candidate material as... Figure 4 The semiconductor substrate 220 is formed of the same material.

[0057] A dielectric bonding layer 352 is formed above the semiconductor substrate 320. The dielectric bonding layer 352 can be similar to the one described above. Figure 3 The materials and processes discussed are used to form those.

[0058] The wafer 300 can be divided to form a separate non-active structure 305.

[0059] exist Figure 10 In this process, a non-active structure 305 (such as non-active structure 305a) is bonded to the device die 105 via a dielectric-to-dielectric bonding process. This dielectric-to-dielectric bonding can be a fusion bonding process, for example, forming Si-O-Si bonds. The bonding can be implemented by bringing dielectric bonding layer 352 into contact with dielectric bonding layer 152 and annealing the device to form a bond between dielectric bonding layers 152 and 352. The bonding process can be related to the above... Figure 6 The described hybrid bonding can be performed simultaneously or in different processes.

[0060] The thickness of the non-active structure 305 can differ from the thickness of the device die 205. The thickness of the non-active structure 305 can be larger or smaller than the thickness of the device die 205 by a height difference HD of approximately -200 μm and approximately 200 μm. The height difference can also be achieved in the non-active structures 405, 505, 605, and 705 discussed below.

[0061] Figure 11 A wafer 400 with a plurality of non-active structures 405 defined therein is shown according to some embodiments. The wafer 400 includes a semiconductor substrate 420, which may be made of materials as described above. Figure 3 The semiconductor substrate 320 is formed from the same candidate material described in the semiconductor substrate 120. In particular, the semiconductor substrate 320 may be formed from the same candidate material as... Figure 4 The semiconductor substrate 220 is formed of the same material.

[0062] A stretch film 424 is formed over a semiconductor substrate 420. The stretch film 424 can be formed to resist warping or twisting, providing further stability to the package after gap 302 is filled with a gap-filling material. The stretch film 424 can be formed over the semiconductor substrate 420 using a suitable semiconductor deposition process. In some embodiments, the stretch film 424 is formed of a suitable semiconductor material having inherent tensile stress. For example, the stretch film 424 can be formed of a nitride material such as silicon nitride, titanium nitride, etc. Optionally, the stretch film layer can be formed of a suitable oxide material. In some embodiments, the thickness of the stretch film 424 is approximately... Peace Treaty Between. Although Figure 11 A single stretch film (e.g., stretch film 424) is shown, but stretch film 424 can be made of multiple layers.

[0063] The stress of the stretched film 424 can be further controlled by the deposition process conditions and by adding dopants. In some embodiments, the tensile stress of the stretched film 424 can be controlled between about 20 MPa and about 200 MPa, but other values ​​can be considered and used. In the case of radio frequency (RF) assisted deposition (e.g., RF-PVD), the film stress can increase with increasing AC bias during deposition. In some embodiments, the AC bias can be between 1 kV and 20 kV. RF can be in the range of about 1 MHz to about 15 MHz. The substrate temperature during deposition also affects the film stress. In some embodiments, the substrate temperature can be between about 250 °C and about 400 °C. In some embodiments, the stretched film 424 can be doped with suitable dopants such as carbon or silicon to enhance and / or further control the film stress. Carbon can be doped up to 10 15 cm -3 and 10 18 cm -3 The concentration range is between [specific values]. Silicon can be doped to approximately 10 [units]. 15 cm -3 Peace Treaty 10 18 cm -3 The concentrations are within the range mentioned above. Other concentrations can be considered and used. Silicon or carbon can be doped in situ during the formation of the stretched film 424, or by subsequent ion implantation. Higher dopant concentrations exhibit greater stress in the stretched film 424. Choosing carbon and / or silicon with doping concentrations within the above range provides tunable film stress. Other dopant concentrations can be considered and can be used instead.

[0064] A dielectric bonding layer 452 is formed over the stretched film 424. The dielectric bonding layer 452 can be similar to the one described above. Figure 3 The dielectric bonding layer 152 is formed using the materials and processes discussed above.

[0065] The wafer 400 can be divided to form a separate non-active structure 405.

[0066] exist Figure 12 In this process, a non-active structure 405 (such as non-active structure 405a) is bonded to the device die 105 via a dielectric-to-dielectric bonding process. This dielectric-to-dielectric bonding can be a fusion bonding process, for example, forming Si-O-Si bonds. The bonding can be implemented by bringing dielectric bonding layer 452 into contact with dielectric bonding layer 152 and annealing the device to form a bond between dielectric bonding layers 152 and 452. The bonding process can be related to the above... Figure 6 The described hybrid bonding can be performed simultaneously or in different processes.

[0067] Figure 13A wafer 500 with a plurality of non-active structures 505 defined therein is shown according to some embodiments. The wafer 500 includes a semiconductor substrate 520, which may be made of materials as described above. Figure 3 The semiconductor substrate 520 is formed from the same candidate material as described in the semiconductor substrate 120. In particular, the semiconductor substrate 520 may be formed from the same candidate material as described in the semiconductor substrate 120. Figure 4 The semiconductor substrate 220 is formed of the same material.

[0068] In some embodiments, a stretch film 524 is formed over a semiconductor substrate 520. The stretch film 524 may be composed of materials related to those described above. Figure 11 The same process and material formation are described for the stretched film 424. In other embodiments, film 524 is a dielectric material, such as an ILD material, which can use materials as described above. Figure 3 The processes and materials discussed in ILD 124 are used to form those.

[0069] Metal lines 534 can be formed in the stretch film 524. The metal lines 534 provide further stretching properties to the stretch film 524 to reduce the final package size (e.g., Figure 28 Warpage of the packaged device 800. Metal lines 534 can be formed of copper or a copper alloy, and they can also be formed of other metals. Trenches can be formed in the stretched film 524, and then the trenches are filled with a conductive material. A planarization process, such as CMP, is then performed to remove excess conductive material above the top surface of the stretched film 524 layer, leaving metal lines in the trenches. The conductive material may include a diffusion barrier and a copper-containing metal material above the diffusion barrier. The diffusion barrier may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0070] In some embodiments, a dielectric layer 538 is formed over the metal line 534. The dielectric layer 538 may be formed of silicon oxide, silicon oxynitride, silicon oxycarbide, etc., and in some embodiments may be formed of multiple layers, such as dielectric layers 538A and 538B.

[0071] In some embodiments, vias 546 and metal components 544 may also be formed within the dielectric layer 538. The vias 546 and metal components 544 may further provide stretching properties to reduce the final package size (e.g., Figure 28 Warping of the packaged device (800).

[0072] As an example of forming via 546 and metal component 544, firstly, a dielectric layer 538A can be formed. Next, a via opening corresponding to via 546 can be formed in the dielectric layer 538A using a photolithography process. This photolithography process uses, for example, a photoresist and / or a hard mask formed and patterned above the dielectric layer 538A to help form the via opening corresponding to via 546. Anisotropic etching or other suitable etching can be used to form these trenches through the photoresist and / or hard mask.

[0073] A via 546 and a metal component 544 can be formed above the dielectric layer 538A. The via 546 and the metal component 544 can be formed through methods similar to those described above. Figure 3 The process described for forming the through-hole 136 and metal line 134 is used, but other suitable processes can be used. The metal component 544 and through-hole 546 can be formed of copper or a copper alloy, and they can also be formed of other metals. In an embodiment, the metal component 544 and / or through-hole 546 can be formed of aluminum or an aluminum-copper alloy.

[0074] Then, a dielectric layer 538B can be deposited over the metal component 544 until the desired thickness is achieved. In some embodiments, the dielectric layer 538B can then be planarized to flatten the top surface, while in other embodiments, the planarization step can be omitted.

[0075] A dielectric bonding layer 552 is formed above the dielectric layer 538. The dielectric bonding layer 552 can be similar to the one described above. Figure 3 The dielectric bonding layer 152 is formed using the materials and processes discussed therein. In some embodiments, the dielectric bonding layer 552 may be planarized.

[0076] The wafer 500 can be divided to form a separate non-active structure 505.

[0077] exist Figure 14 In this process, a non-active structure 505 (such as non-active structure 505a) is bonded to the device die 105 via a dielectric-to-dielectric bonding process. This dielectric-to-dielectric bonding can be a fusion bonding process, for example, forming Si-O-Si bonds. The bonding can be implemented by bringing dielectric bonding layer 552 into contact with dielectric bonding layer 152 and annealing the device to form a bond between dielectric bonding layers 152 and 552. The bonding process can be related to the above... Figure 6 The described hybrid bonding can be performed simultaneously or in different processes.

[0078] Figure 15 A wafer 600 with a plurality of non-active structures 605 defined therein is shown according to some embodiments. The wafer 600 includes a semiconductor substrate 620, which may be made of materials as described above. Figure 3The semiconductor substrate 620 is formed from the same candidate material described in the semiconductor substrate 120. In particular, the semiconductor substrate 620 may be formed from the same candidate material as... Figure 4 The semiconductor substrate 220 is formed of the same material.

[0079] In some embodiments, a stretch film 624 is formed over a semiconductor substrate 620. The stretch film 624 may be composed of materials related to those described above. Figure 11 The same process and materials are used to form the stretched film 424. In other embodiments, film 624 is a dielectric material, such as an ILD material, which can use materials as described above. Figure 3 The processes and materials discussed in ILD 124 are used to form those.

[0080] Metal wires 634 can be formed in the stretched film 624. The metal wires can be similar to those described above. Figure 13 The processes and materials discussed are used to form it. A dielectric layer 638 can be formed over the stretched film 624, and vias 646 and metal parts 644 can be formed in the dielectric layer 638. The dielectric layer 638, vias 646, and metal parts 644 can be formed using methods similar to... Figure 13 The process and materials are used to form a similar structure (dielectric layer 538, via 546 and metal part 544).

[0081] A dielectric bonding layer 652 is formed above the dielectric layer 638. The dielectric bonding layer 652 can be similar to the one described above. Figure 3 The dielectric bonding layer 652 is formed using the materials and processes discussed therein. In some embodiments, the dielectric bonding layer 652 may be planarized.

[0082] Bonding pads 654 can be formed in the dielectric bonding layer 652. Bonding pads 654 can help provide a stronger bond between the non-active structure 605 and the device die 105, further helping to reduce warpage and decrease the likelihood of the non-active structure 605 peeling off from the device die 105. Openings for the bonding pads 654 can be formed initially using a photoresist (not shown) and / or a hard mask (not shown) formed and patterned over the dielectric bonding layer 652 to help form openings for the bonding pads 654. According to some embodiments of the invention, anisotropic etching or other suitable etching is performed to form openings for the bonding pads 654. In some embodiments, etching can be stopped on a dielectric layer 638 that can act as an etch stop. In other embodiments, an etch stop layer can be disposed between the dielectric layer 638 and the dielectric bonding layer 652 (or can be a portion of the dielectric layer 638, similar to...). Figure 3 (electron layer 138C). In some embodiments, etching may be time-based.

[0083] Next, optional diffusion barriers and metallic material can be deposited in the opening to form bonding pad 654. Forming bonding pad 654 can be done using methods similar to those used for forming... Figure 3 The processes and materials for the bonding pads 154 are then used. A planarization process, such as chemical mechanical polishing (CMP), can then be performed to remove excess metal material and diffusion barriers (if used) until the upper surface of the bonding pads 654 is flush with the upper surface of the dielectric bonding layer 652. The remaining portion of the diffusion barriers (if used) and metal material constitutes the bonding pads 654 subsequently used for bonding to devices. It should be understood that metal lines can also be formed simultaneously as bonding pads 654.

[0084] The wafer 600 can be divided to form a separate non-active structure 605.

[0085] exist Figure 16 In the text, similar to the above regarding... Figure 6 In the described processes, the non-active structure 605 (such as non-active structure 605a) is bonded to the device die 105 via hybrid bonding. Corresponding bonding pads 154 can be provided in the device die 105 for metal-to-metal bonding with the bonding pads 654. Similarly, the dielectric bonding layer 652 is bonded to the dielectric bonding layer 152 using dielectric-to-dielectric bonding, which can be a fusion bonding, for example, forming Si-O-Si bonds. Bonding can be implemented by contacting the dielectric bonding layer 652 with the dielectric bonding layer 152 and contacting the bonding pads 654 with the bonding pads 154. The device is then annealed to form a bond between the dielectric bonding layers 152 and 652, and to form metal interdiffusion between the bonding pads 154 and 654. The bonding can be related to the above... Figure 6 The hybrid bonding device die 205 described can be implemented simultaneously or in different processes.

[0086] Figure 17 A wafer 700 with a plurality of non-active structures 705 defined therein is shown according to some embodiments. The wafer 700 includes a semiconductor substrate 720, which may be made of materials as described above. Figure 3 The semiconductor substrate 720 is formed from the same candidate material described in the semiconductor substrate 120. Specifically, the semiconductor substrate 720 can be formed from the same candidate material as... Figure 4 The semiconductor substrate 220 is formed of the same material.

[0087] In some embodiments, a through-silicon via (TSV) 716 (sometimes referred to as a semiconductor via or via) is formed to penetrate into the semiconductor substrate 720 (and ultimately through the semiconductor substrate 720 by being exposed from the opposite side). The TSV 716 can be used to electrically couple a metal line or metal component formed on the front side (top side shown) of the active structure 705 to the back side of the active structure 705. In a subsequent step, the back side of the semiconductor substrate 720 can be recessed to expose the TSV 716. The TSV 716 can be formed using processes and materials similar to those discussed above for forming the bonding pad via 216, and without repetition, including, for example, using a time-based etching process, such that the TSV 716 can have a bottom disposed between the top and bottom surfaces of the semiconductor substrate 720.

[0088] The TSV 716 can further reduce warpage by providing heat dissipation from the device die 105 through the passive structure 705. In some embodiments, electrical signal wiring can also be routed through the passive structure 705 via the TSV 716.

[0089] In some embodiments, a stretched film 724 is formed over the semiconductor substrate 720 and over the TSV 716. The stretched film 724 may be formed from materials related to the above. Figure 11 The same process and materials are used to form the stretched film 424. In other embodiments, film 724 is a dielectric material, such as an ILD material, which can use materials as described above. Figure 3 The processes and materials discussed in ILD 124 are used to form those.

[0090] According to some embodiments, metal wires 734 can be formed in the stretched film 724. The metal wires can use materials similar to those described above. Figure 13 The metal wire 534 is formed using the processes and materials discussed above. The metal wire 734 can be formed to be electrically and physically coupled to TSV 716.

[0091] A dielectric layer 738 may be formed over the stretched film 724. In some embodiments, a via 746 and a metal component 744 may be formed in the dielectric layer 738, while in other embodiments, the via 746 and the metal component 744 are not formed. The via 746 may be formed as a contact metal line 734. The dielectric layer 738, the via 746, and the metal component 744 may use methods similar to... Figure 13 The process and materials are used to form a similar structure (dielectric layer 538, via 546 and metal part 544).

[0092] A bonding pad via 756 can be formed in the dielectric layer 738. In some embodiments, the bonding pad via 757 can also or alternatively be formed to rest on the metal component 744. The bonding pad via 756 and / or the bonding pad via 757 can use methods similar to those described above. Figure 3 The processes and materials used to form the bonding pad vias 156 and 157 are discussed.

[0093] A dielectric bonding layer 752 is formed above the dielectric layer 738 and above the bonding pad vias 756 and / or 757. The dielectric bonding layer 752 can be similar to the one described above. Figure 3 The dielectric bonding layer 152 is formed using the materials and processes discussed above.

[0094] Similar to the above, we can use... Figure 3 The bonding pads 754, as discussed above, are formed in the dielectric bonding layer 752 using the processes and materials described. As noted above, in some embodiments, the bonding pads 754 may be formed simultaneously with the bonding pad vias 756 and / or 757.

[0095] Bond pad 754 and bond pad vias 756 and / or 757 can be used to provide a thermal connection between TSV 716 and bond pad 754. When bond pad 754 is subsequently bonded to device die 105, heat generated from active devices in device die 105 can be dissipated to TSV 716 through passive structure 705 via bond pad 754. In some embodiments, bond pad 754 may also route electrical signal wiring from device die 105 through passive structure 705. For example, in some embodiments, a material can be used to fill subsequently formed gaps (e.g., Figure 28 Through-holes are formed in the gap-filling dielectric layer 162 (e.g., Figure 28 (Through hole 170). In addition to or instead of forming a through hole in the gap filling material, the non-active structure 705 can be used to form such a through hole, thereby eliminating the need to form such a through hole later.

[0096] exist Figure 18 In the text, similar to the above regarding... Figure 6In the processes described, the non-active structure 705 (such as non-active structure 705a) is bonded to the device die 105 via hybrid bonding. Corresponding bonding pads 154 can be provided in the device die 105 for metal-to-metal bonding with the bonding pads 754. Similarly, the dielectric bonding layer 752 is bonded to the dielectric bonding layer 152 using dielectric-to-dielectric bonding, which can be a fusion bonding, for example, forming Si-O-Si bonds. Bonding can be implemented by contacting the dielectric bonding layer 752 with the dielectric bonding layer 152 and contacting the bonding pads 754 with the bonding pads 154. The device is then annealed to form a bond between the dielectric bonding layers 152 and 752, and to form metal interdiffusion between the bonding pads 154 and 754. The bonding can be related to the above... Figure 6 The hybrid bonding device die 205 described can be implemented simultaneously or in different processes.

[0097] Figure 19 The diagram illustrates an intermediate stage in the formation of a packaged device according to some embodiments, wherein multiple passive structures 305, 405, 505, 605, and / or 705 can be used in the same packaged device. The passive structures can be any combination of any variation of the passive structures 305, 405, 505, 605, and 705 described herein. The passive structures 305, 405, 505, 605, and / or 705 can have different dimensions and heights depending on the dimensions of the gap 302 (see...). Figure 6 In some embodiments, the height can vary from one active structure to another by the difference in HD2, which can be between about 0 μm and about 200 μm.

[0098] Figure 20 yes Figure 19 The top view (i.e., plan view) of the intermediate stage further illustrates multiple passive structures 305, 405, 505, 605, and / or 705. It should be understood that the layout shown is merely an example, and passive structures 305, 405, 505, 605, and / or 705 of any size (i.e., coverage area) can be used to fill the gap 302 such that the combined area of ​​the active devices attached to device die 105 (e.g., device die 205) plus the combined area of ​​the passive structures attached to device die 105 is greater than 50% of the total area of ​​device die 105. In other words, the combined area of ​​the passive and active structures is greater than the total area of ​​the gap 302.

[0099] Figure 20 The diagram illustrates intermediate stages in forming a packaged device according to some embodiments, wherein multiple non-active structures 305, 405, 505, 605 and / or 705 can be used in the same packaged device. Figure 20In the consistent embodiments shown, one or more of the non-active structures 305, 405, 505, 605, and / or 705 can span from one device die 105 of wafer 100 to an adjacent device die 105. For example, as Figure 20 As shown, the non-active structures 305, 405, 505, 605 and / or 705 are shown as spanning device die 105a and device die 105b. A cut line 106 traverses the non-active structures 305, 405, 505, 605 and / or 705.

[0100] Such embodiments can provide greater flexibility in positioning the non-active structures 305, 405, 505, 605, and / or 705. When wafer 100 is diced in a subsequent process to separate device die 105a from device die 105b, the dicing process can also cut through the non-active structures 305, 405, 505, 605, and / or 705, such that a portion of the non-active structure remains attached to device die 105a, and another portion remains attached to device die 105b. In some embodiments, the non-active structures 305, 405, 505, 605, and / or 705 can be positioned at the corners of device die 105 and overlap with three other device dies 105.

[0101] Figure 22 yes Figure 21 The top view (i.e., plan view) of the intermediate stage further illustrates multiple non-active structures 305, 405, 505, 605 and / or 705 spanning multiple device dies 105. As... Figure 22 As shown, the cut line 106 traverses the non-active structures 305, 405, 505, 605 and / or 705 that span multiple device dies 105. It should be understood that it may also include non-active structures 305, 405, 505, 605 and / or 705 that do not span multiple device dies 105.

[0102] Figures 23 to 28 Intermediate steps are shown in the process of continuing to form a packaged device including device die 105, one or more device dies 205 and one or more non-active structures 305, 405, 505, 605 and / or 705.

[0103] exist Figure 23In some embodiments, after the bonding process that bonds device die 205 and active structures 305, 405, 505, 605 and / or 705 to device die 105, back-side grinding may be performed to thin device die 205 and active structures 305, 405, 505, 605 and / or 705, for example, to a thickness between about 5 μm and about 30 μm. Thinning also reduces the aspect ratio of gap 302 to aid gap filling. Thinning may also make the height of device die 205 the same as the height of active structures 305, 405, 505, 605 and 705. After back-side grinding, TSV 216 and TSV 716 may be exposed (if applicable). Optionally, TSV 216 (and TSV 716) are not yet exposed, and back-side grinding is stopped before TSV 216 (and TSV 716) are exposed. In some embodiments, back-side grinding may be performed after the deposition of gap-filling material and may be optionally omitted at this time, for example, if the aspect ratio is sufficient to achieve gap filling.

[0104] Figure 24 A gap-filling layer comprising a dielectric layer 162 and an underlying etch-stop layer 160 is shown. The etch-stop layer 160 is formed of a dielectric material that exhibits good adhesion to the sidewalls of the device die 205, the non-active structures 305, 405, 505, 605, and / or 705, and the top surface of the dielectric bonding layer 152 and the bonding pads 154. According to some embodiments of the invention, the etch-stop layer 160 is formed of a nitride-containing material such as silicon nitride. The etch-stop layer 160 may be a conformal layer, for example, where the thickness of the horizontal portion and the thickness of the vertical portion are substantially equal to each other, for example, the difference having an absolute value of less than about 20% or less than about 10% of the two thicknesses. Deposition may include conformal deposition methods such as atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0105] The dielectric layer 162 is formed of a material different from that of the etch stop layer 160. According to some embodiments of the invention, the dielectric layer 162 is formed of silicon oxide, which may be silicon oxide formed of TEOS, or other dielectric materials such as silicon carbide, silicon oxynitride, silicon carbonitride, PSG, BSG, BPSG, etc. The dielectric layer 162 can be formed using CVD, high-density plasma chemical vapor deposition (HDPCVD), flowable CVD, spin coating, etc. The dielectric layer 162 completely fills the remaining gaps 302 ( Figure 23 ).

[0106] refer to Figure 25A planarization process, such as CMP or mechanical polishing, is performed to remove excess portions of the gap fill layers 160 and 162, exposing the device die 205 and the non-active structures 305, 405, 505, 605, and / or 705. Additionally, TSV 216 (and 716, if applicable) are exposed. The dielectric layer 162 and the etch stop layer 160 together may be referred to as gap fill material 164.

[0107] Figure 26 The etching of dielectric layer 162 is shown to form an opening 166 for optional vias through gap filler material 164. According to some embodiments of the invention, a photoresist (not shown) is formed and patterned, and the patterned photoresist is used as an etching mask to etch dielectric layer 162. This forms an opening 166 extending downwards to an etch stop layer 160 serving as an etch stop layer. According to some embodiments of the invention, dielectric layer 162 comprises an oxide, and the etching can be performed by dry etching. The etching gas may include a mixture of NF3 and NH3 or a mixture of HF and NH3. Next, the etch stop layer 160 is etched such that the opening 166 extends downwards to bonding pad 154. According to some embodiments of the invention, etch stop layer 160 is formed of silicon nitride, and the etching is performed using dry etching. The etching gas may include a mixture of CF4, O2, and N2, a mixture of NF3 and O2, SF6, or a mixture of SF6 and O2.

[0108] Figure 27 The formation of filling opening 166 is shown. Figure 26 And connected to the bonding pad 154 via 170. According to some embodiments of the invention, forming the via 170 includes performing a plating process such as an electrochemical plating process or a chemical plating process. The via 170 may include a metallic material such as tungsten, aluminum, copper, etc. A conductive barrier layer (such as titanium, titanium nitride, tantalum, tantalum nitride, etc.) may also be formed under the metallic material. Planarization such as CMP is performed to remove excess portions of the plated metallic material, and the remaining portion of the metallic material forms the via 170. The via 170 may have substantially straight and vertical sidewalls. Furthermore, the via 170 may have a tapered profile with a top width slightly greater than the corresponding bottom width.

[0109] In some embodiments, the non-active structure 705 can be used as a through-hole. In some embodiments, a TSV 216 can be formed in the device die 205 using a process and materials similar to those used for through-hole 170. For example, in forming opening 166 ( Figure 26Before or after etching device die 205 to form additional openings (occupied by TSV 216 shown). The additional openings and opening 166 in device die 205 can be filled simultaneously to form TSV 216 and via 170. The resulting TSV 216 may have an upper portion wider than the corresponding lower portion, which is consistent with... Figure 27 The opposite of what is shown.

[0110] The redistribution line (RDL) 172 and the dielectric layer 174 are formed by the redistribution structure. According to some embodiments of the invention, the dielectric layer 174 is formed of an oxide such as silicon oxide, a nitride such as silicon nitride, etc. The RDL 172 can be formed using a damascene process, which includes: etching the dielectric layer 174 to form an opening; depositing a conductive barrier layer into the opening; plating a metal material such as copper or a copper alloy; and performing planarization to remove excess portions of the metal material.

[0111] Figure 27 The diagram also shows the formation of a passivation layer, metal pads, and an overlying dielectric layer. A passivation layer 176 is formed over the dielectric layer 174, and a via 178 electrically connected to RDL 172 is formed within the passivation layer 176. Metal pads 180 electrically coupled to RDL 172 via the via 178 are formed over the passivation layer 176. The metal pads 180 can be aluminum pads or aluminum-copper pads, and other metal materials can be used.

[0112] Similarly, Figure 27 As shown, a passivation layer 182 is formed over a passivation layer 176. Each of passivation layers 176 and 182 can be a single layer or a composite layer, and can be formed of a non-porous material. According to some embodiments of the invention, one or both of passivation layers 176 and 182 are composite layers comprising a silicon oxide layer (not shown separately) and a silicon nitride layer (not shown separately) above the silicon oxide layer. Passivation layers 176 and 182 can also be formed of other non-porous dielectric materials, such as undoped silicate glass (USG), silicon oxynitride, etc.

[0113] Next, the passivation layer 182 is patterned such that some portions of the passivation layer 182 cover the edge portions of the metal pad 180, and some portions of the metal pad 180 are exposed through openings in the passivation layer 182. Then, a polymer layer 184 is formed and then patterned to expose the metal pad 180. The polymer layer 184 may be formed of polyimide, polybenzoxazole (PBO), etc.

[0114] refer to Figure 28The passivated interconnect (PPI) 186 is formed, which may include: forming a metal seed layer and a patterned mask layer (not shown) over a metal seed layer; and depositing the PPI 186 in the patterned mask layer. The overlapping portions of the patterned mask layer and the metal seed layer with the patterned mask layer are then removed in an etching process. A polymer layer 188 is then formed, which may be formed from PBO, polyimide, etc.

[0115] Next, an under-bump metal (UBM) 190 is formed, and the UBM 190 extends into the polymer layer 188 to connect to the PPI 186. According to some embodiments of the invention, each of the UBM 190 includes a barrier layer (not shown) and a seed layer (not shown) above the barrier layer. The barrier layer may be a titanium layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, or a layer formed of a titanium alloy or a tantalum alloy. The material of the seed layer may include copper or a copper alloy. Other metals, such as silver, gold, aluminum, palladium, nickel, nickel alloys, tungsten alloys, chromium, chromium alloys, and combinations thereof, may also be included in the UBM 190. The formation process for forming the UBM 190 and the electrical connector 192 includes: depositing a blanket UBM layer; forming and patterning a mask (which may be a photoresist, not shown), a portion of the blanket UBM layer being exposed through openings in the mask. The exposed portions can then be removed by an etching process. The mask can then be removed to expose the UBM 190.

[0116] Similarly, Figure 28 As shown, an electrical connector 192 is formed. After forming the UBM 190, the package shown can be placed in a plating solution (not shown), and a plating step can be performed to form the electrical connector 192 on the UBM 190. According to some embodiments of the invention, the electrical connector 192 includes a non-solder portion (not shown) that does not melt in the subsequent reflow process. The non-solder portion can be formed of copper and is therefore referred to hereinafter as a copper bump, but it can be formed of other non-solder materials. Each of the electrical connectors 192 may also include a cap layer (not shown) selected from nickel layers, nickel alloys, palladium layers, gold layers, silver layers, or multiples thereof. The cap layer is formed over the copper bump. The cap layer of the electrical connector 192 may include solder, which can be formed of Sn-Ag alloys, Sn-Cu alloys, Sn-Ag-Cu alloys, etc., and can be lead-free or lead-containing.

[0117] Figure 28 The dicing process, for example, using a die saw 810, is also shown, but another suitable process can be used. The resulting structure is a packaged device 800.

[0118] Figure 29A packaged device 800 with an active structure 305 disposed therein is shown according to some embodiments. Other active structures 305, 405, 505, 605, and 705 may also be disposed therein. The above-described... Figures 9 to 10 The described process and materials are used to form an active structure 305 bonded to device die 105. The active structure 305 is a pseudo-structure and does not provide electrical connections to the active device 122 of device die 105. The active structure 305 provides better warpage control in the package because substrate 320 can have a CTE similar to that of substrate 220 of device die 205. The thermal conductivity of the active structure 305 can be improved compared to the material of the gap-filling dielectric layer 162, thereby providing better heat dissipation for device die 105.

[0119] Figure 30 A packaged device 800 with an active structure 405 disposed therein is shown according to some embodiments. Other active structures 305, 405, 505, 605, and 705 may also be disposed therein. The above-described... Figures 11 to 12 The described process and materials are used to form an active structure 405 bonded to device die 105. The active structure 405 is a pseudo-structure and does not provide electrical connections to the active device 122 of device die 105. The active structure 405 provides better warpage control in the package because substrate 420 can have a CTE similar to that of substrate 220 of device die 205. Furthermore, the use of a stretch film 424 can help resist warpage. The thermal conductivity of the active structure 405 can be improved compared to the material of the gap-filling dielectric layer 162, thereby providing better heat dissipation for device die 105.

[0120] Figure 31 A packaged device 800 with an active structure 505 disposed therein is shown according to some embodiments. Other active structures 305, 405, 505, 605, and 705 may also be disposed therein. The above-described... Figures 13 to 14The described processes and materials are used to form an active structure 505 bonded to device die 105. The active structure 505 is a pseudo-structure and does not provide electrical connections to the active device 122 of device die 105. The active structure 505 provides better warpage control in the package because substrate 520 can have a CTE similar to substrate 220 of device die 205. Furthermore, the use of stretch film 524, metal lines 534, vias 546, and metal components 544 can increase the stretchability of the active structure 505 to help resist warpage. The thermal conductivity of the active structure 505 can be improved compared to the material of the gap-filling dielectric layer 162, thereby providing better heat dissipation for device die 105. Metal lines 534, vias 546, and metal components 544 can also be used to increase the thermal conductivity of the active structure 505.

[0121] Figure 32 A packaged device 800 with an active structure 605 disposed therein is shown according to some embodiments. Other active structures 305, 405, 505, 605, and 705 may also be disposed therein. The above-described... Figures 15 to 16 The described processes and materials are used to form an active structure 605 bonded to device die 105. In some embodiments, the active structure 605 is a dummy structure and does not provide electrical connections to the active device 122 of device die 105. In other embodiments, bonding pads of the active structure 605 may be electrically coupled to the active device 122, and in some embodiments, signal routing may be provided in the bonding pad layer of the active structure 605. In some embodiments, signals are not routed through the active structure 605, and the active structure 605 has no electrical coupling to the active device 122.

[0122] The passive structure 605 provides better warpage control within the package because the substrate 620 can have a CTE similar to that of the substrate 220 of the device die 205. Furthermore, the use of stretch film 624, metal lines 634, vias 646, metal parts 644, and bonding pads 654 increases the stretchability of the passive structure 605 to help resist warpage. The thermal conductivity of the passive structure 605 can be improved compared to the material of the gap-filling dielectric layer 162, thus providing better heat dissipation for the device die 105. Metal lines 634, vias 646, metal parts 644, and bonding pads 654 can also be used to increase the thermal conductivity of the passive structure 605.

[0123] Figure 33 A packaged device 800 with an active structure 705 disposed therein is shown according to some embodiments. Other active structures 305, 405, 505, 605, and 705 may also be disposed therein. The above-described... Figures 17 to 18The described processes and materials are used to form an active structure 705 bonded to device die 105. In some embodiments, the active structure 705 is a dummy structure and does not provide electrical connections to the active device 122 of device die 105. In other embodiments, bonding pads 754 of the active structure 705 may be electrically coupled to the active device 122, and in some embodiments, signal routing may be provided in the bonding pad layer or metal line 734 of the active structure 705. In some embodiments, TSV 716, together with metal line 734, bonding pad via 756, and bonding pad 754, may provide signal routing similar to vias through gap-filled dielectric layer 162. In some embodiments, signals are not routed through the active structure 705, and the active structure 705 has no electrical coupling to the active device 122.

[0124] The passive structure 705 provides better warpage control in the package because the substrate 720 can have a CTE similar to that of the substrate 720 of the device die 705. Furthermore, the use of stretch film 724, metal lines 734, bonding pads 754, bonding pad vias 756, and TSV 716 increases the stretchability of the passive structure 705 to help resist warpage. The thermal conductivity of the passive structure 705 can be improved compared to the material of the gap-filling dielectric layer 162, thus providing better heat dissipation for the device die 105. The bonding pads 754, bonding pad vias 752, metal lines 734, and TSV 716 can provide effective thermal bridges between the device die 105 and the overlying layers, and therefore can be used to increase the thermal conductivity of the passive structure 705.

[0125] Figure 34 A packaged device 800, according to some embodiments, is shown having a combination of multiple active structures 305 / 405 / 505 / 605 / 705 disposed therein. Other active structures 305, 405, 505, 605, and 705 may also be disposed therein. The above-described... Figures 9 to 18 The described process and materials are used to form the non-active structure 305 / 405 / 505 / 605 / 705 bonded to the device die 105.

[0126] Figure 35 A packaged device 800 according to some embodiments is shown. As discussed above (e.g., regarding...) Figure 21The non-active structures 305, 405, 505, 605, and / or 705 may span multiple device dies 105, such that the resulting packaged device 800 has sidewalls made of a first portion of the non-active structures 305, 405, 505, 605, and / or 705. Matching second portions of the different non-active structures 305, 405, 505, 605, and / or 705 from opposite sides of adjacent device dies 105 may be disposed at a sidewall opposite to the first portion of the non-active structure.

[0127] Figures 29 to 35 The packaged device 800 shown has a face-to-face structure, wherein the device die 205 has a front side facing the device die 105. However, Figure 36 and Figure 37 A back-facing structure is shown, wherein device die 205 has a front facing the back of device die 105. Figure 36 and Figure 37 In each of them, the device die 105 includes a TSV 116 extending through the semiconductor substrate 120 and the dielectric bonding layer 117. Figure 36 Other aspects were provided, similar to those about Figures 29 to 34 The illustrations shown are of the face-to-back embodiments. Figure 37 Other aspects are similar Figure 35 The illustrations show the face-to-face embodiments of those shown. Figure 36 and Figure 37 The dashed area 119 in the diagram indicates that a connection structure can be formed (such as the one mentioned above). Figures 27 to 28 The area described. According to some embodiments of the invention, TSV 116 and dielectric bonding layer 117 can use a similar... Figure 3 The bonding pad through-hole 156 is formed using the process and materials.

[0128] Embodiments of the present invention advantageously provide non-active structures to reduce the amount of gap filler material required around the attached device die. When the cumulative area of ​​the attached device die is less than half the area of ​​the device die to which it is attached (e.g., device die 105), a CTE mismatch between the gap filler material and the attached device die can cause excessive warpage in the packaged device. Therefore, in some embodiments, adding non-active structures to occupy the space between those non-active structures, which include material layers more similar to the attached device (i.e., silicon substrate, metal parts, etc.) and the stretch film, can achieve reduced warpage.

[0129] One embodiment is a method including providing a first device die, the first device die including an active device disposed therein, the first device die having a first surface area. The method further includes bonding a second device die to the first device die, the second device die having a second surface area less than half the first surface area. The method further includes bonding one or more non-active structures to the first device die, the one or more non-active structures having a cumulative third surface area, the second surface area and the cumulative third surface area together being greater than half the first surface area. The method further includes filling gaps laterally surrounding the second device die and the one or more non-active structures with a gap-filling material.

[0130] In embodiments, the method may include forming vias in a gap-filling material. In embodiments, bonding a first non-active structure of one or more non-active structures to a first device die may include: placing the first non-active structure on the first device die; pressing the first non-active structure onto the first device die; and annealing the combination of the first non-active structure and the first device die. In embodiments, the first non-active structure overlaps with a dicing line of the first device die and covers a portion of a third device die, the third device die being adjacent to the first device die. In embodiments, the method may include: forming a redistribution structure over a gap-filling material; forming a connector structure over the redistribution structure; and dicing the first device die from a wafer to form a divided device package including at least a portion of the first device die, a second device die, and one or more non-active structures. In embodiments, the dicing includes a dicing process, wherein the dicing process cuts through the first non-active structure of one or more non-active structures. In an embodiment, bonding a second device die to a first device die may include: aligning a second bonding pad of the second device die with a first bonding pad of the first device die; pressing the second bonding pad against the first bonding pad; and annealing the second device die and the first device die to allow the metal materials of the first bonding pad and the second bonding pad to diffuse into each other. In an embodiment, bonding the second device die is performed simultaneously with bonding one or more non-active structures to the first device die.

[0131] Another embodiment is a packaged device, comprising: a first device die having a first coverage area; and a second device die bonded to the first device die, the second device die having a second coverage area less than half the first coverage area, the second device die including a semiconductor substrate. The packaged device further includes: one or more non-active structures bonded to the first device die adjacent to the second device die, wherein the one or more non-active structures include a semiconductor substrate without any active devices. The packaged device further includes: a gap-filling material laterally surrounding the second device die and the one or more non-active structures. The packaged device further includes: a connector structure disposed above the gap-filling material, the connector structure being electrically coupled to the second device die.

[0132] In an embodiment, a first non-active structure in one or more non-active structures may include: a semiconductor substrate; and a dielectric bonding layer fused to the dielectric bonding layer of a first device die. In an embodiment, the first non-active structure may include a stretched film layer. In an embodiment, the first non-active structure may include a metallization layer. In an embodiment, the first non-active structure may include bonding pads disposed in the dielectric bonding layer, the bonding pads bonding to corresponding bonding pads of the first device die without the use of solder. In an embodiment, the first non-active structure may include vias extending through the thickness of the semiconductor substrate, the vias configured to dissipate heat from the first device die. In an embodiment, the package device may include: a first redistribution structure, situated between a gap filler material and a connector structure; and vias disposed in the gap filler material, the vias electrically coupling bonding pads of the first device die to the first redistribution structure.

[0133] Another embodiment is a packaged device, including: a first device die; and a second device die, bonded to the first device die. The packaged device further includes: one or more non-active structures bonded to the first device die, wherein the cumulative area of ​​the second device die and the one or more non-active structures is greater than 50% of the area of ​​the first device die. The packaged device further includes: a dielectric layer laterally surrounding the second device die and the one or more non-active structures. The packaged device further includes: a connector structure disposed above the dielectric layer, the connector structure being electrically coupled to the second device die.

[0134] In an embodiment, the first passive structure in one or more passive structures may include a semiconductor substrate, a dielectric bonding layer and a stretched film, a metal line, a bonding pad disposed in the dielectric bonding layer, or one or more vias disposed in the semiconductor substrate. In an embodiment, the first passive structure in one or more passive structures has a first sidewall aligned with the sidewall of the first device die. In an embodiment, the connector of the connector structure is electrically coupled to the first device die through the first passive structure in one or more passive structures. In an embodiment, the cumulative area of ​​the second device die and the one or more passive structures is less than 95% of the area of ​​the first device die.

[0135] Embodiments of this application provide a method for forming a packaged device, comprising: providing a first device die, the first device die including an active device disposed therein, the first device die having a first surface area; bonding a second device die to the first device die, the second device die having a second surface area less than half of the first surface area; bonding one or more non-active structures to the first device die, the one or more non-active structures having a cumulative third surface area, the second surface area and the cumulative third surface area together being greater than half of the first surface area; and filling a gap laterally surrounding the second device die and the one or more non-active structures with a gap-filling material. In some embodiments, the method further comprises: forming a through-hole in the gap-filling material. In some embodiments, bonding a first non-active structure of the one or more non-active structures to the first device die comprises: placing the first non-active structure on the first device die; pressing the first non-active structure onto the first device die; and annealing the combination of the first non-active structure and the first device die. In some embodiments, the first non-active structure overlaps with a cut line of the first device die and covers a portion of a third device die, the third device die being adjacent to the first device die. In some embodiments, the method further includes: forming a redistribution structure over the gap filler material; forming a connector structure over the redistribution structure; and dicing the first device die from the wafer to form a diced device package including the first device die, the second device die, and at least a portion of the one or more non-active structures. In some embodiments, the dicing includes a dicing process, wherein the dicing process cuts through the first non-active structure in the one or more non-active structures. In some embodiments, bonding the second device die to the first device die includes: aligning a second bonding pad of the second device die with a first bonding pad of the first device die; pressing the second bonding pad against the first bonding pad; and annealing the second device die and the first device die to cause the metal materials of the first bonding pad and the metal materials of the second bonding pad to interdiffusion. In some embodiments, the one or more non-active structures do not have an active device electrically coupled to the first device die.

[0136] Other embodiments of this application provide a packaged device comprising: a first device die having a first coverage area; a second device die bonded to the first device die, the second device die having a second coverage area less than half the first coverage area, the second device die including a semiconductor substrate; one or more passive structures bonded to the first device die adjacent to the second device die, the one or more passive structures including a semiconductor substrate without any active devices; a gap filler material laterally surrounding the second device die and the one or more passive structures; and a connector structure disposed over the gap filler material, the connector structure being electrically coupled to the second device die. In some embodiments, the first passive structure of the one or more passive structures includes: a semiconductor substrate; and a dielectric bonding layer fused to the dielectric bonding layer of the first device die. In some embodiments, the first passive structure further includes a stretch film layer. In some embodiments, the first passive structure further includes a metallization layer. In some embodiments, the first passive structure further includes bonding pads disposed in the dielectric bonding layer, the bonding pads being bonded to corresponding bonding pads of the first device die without the use of solder. In some embodiments, the first non-active structure further includes a via extending through the thickness of the semiconductor substrate, the via being configured to dissipate heat from the first device die. In some embodiments, the one or more non-active structures do not have any active devices electrically coupled to the first device die.

[0137] This application provides, in several embodiments, a packaged device including: a first device die; a second device die bonded to the first device die; one or more non-active structures bonded to the first device die, wherein the cumulative area of ​​the second device die and the one or more non-active structures is greater than 50% of the area of ​​the first device die; a dielectric layer laterally surrounding the second device die and the one or more non-active structures; and a connector structure disposed above the dielectric layer, the connector structure being electrically coupled to the second device die. In some embodiments, the first non-active structure of the one or more non-active structures includes a semiconductor substrate, a dielectric bonding layer, and one or more of a stretch film, a metal wire, a bonding pad disposed in the dielectric bonding layer, or a via disposed in the semiconductor substrate. In some embodiments, the first non-active structure of the one or more non-active structures has a first sidewall aligned with a sidewall of the first device die. In some embodiments, a connector of the connector structure is electrically coupled to the first device die through the first non-active structure of the one or more non-active structures. In some embodiments, the cumulative area of ​​the second device die and the one or more non-active structures is less than 95% of the area of ​​the first device die.

[0138] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method of forming a packaged device, comprising: A first device die is provided, the first device die including an active device disposed therein, the first device die having a first surface area; A second device die is bonded to a first device die, the second device die having a second surface area less than half the surface area of ​​the first device die; One or more non-active structures are bonded to the first device die, the one or more non-active structures having a cumulative third surface area, the second surface area and the cumulative third surface area together being greater than half of the first surface area; as well as The gaps that laterally surround the second device die and the one or more non-active structures are filled with a gap-filling material. The first non-active structure of the one or more non-active structures includes a stretched membrane. The film stress of the stretched film is controlled by deposition process conditions or dopant doping, or metal wires are formed in the stretched film to provide further stretching properties.

2. The method according to claim 1, further comprising: Through holes are formed in the gap filling material. The first non-active structure includes: a semiconductor substrate, the stretched film on the semiconductor substrate, a dielectric layer on the stretched film, and a dielectric bonding layer on the dielectric layer.

3. The method according to claim 1, wherein, Bonding the first non-active structure of the one or more non-active structures to the first device die includes: The first non-active structure is placed on the first device die; Press the first non-active structure onto the first device die; and Anneal the combination of the first non-active structure and the first device die.

4. The method according to claim 3, wherein, The first non-active structure overlaps with the cut line of the first device die and covers a portion of the third device die, wherein the third device die is adjacent to the first device die.

5. The method according to claim 1, further comprising: A redistribution structure is formed above the gap-filling material; A connecting structure is formed above the redistribution structure; as well as The first device die is diced from the wafer to form a diced device package comprising the first device die, the second device die, and at least a portion of the one or more non-active structures.

6. The method according to claim 5, wherein, The segmentation includes a cutting process, wherein the cutting process cuts through a first non-active structure in one or more non-active structures.

7. The method according to claim 1, wherein, Bonding the second device die to the first device die includes: Align the second bonding pad of the second device die with the first bonding pad of the first device die; Press the second bonding pad against the first bonding pad; and Annealing the second device die and the first device die causes the metal material of the first bonding pad to diffuse into the metal material of the second bonding pad.

8. The method according to claim 1, wherein, The one or more non-active structures are not electrically coupled to the active device of the first device die.

9. A packaged device, comprising: A first device die, the first device die having a first coverage area; A second device die is bonded to the first device die, the second device die having a second coverage area less than half the first coverage area, and the second device die including a semiconductor substrate. One or more non-active structures are bonded to a first device die adjacent to a second device die, the one or more non-active structures comprising a semiconductor substrate without any active devices. A gap-filling material laterally surrounds the second device die and the one or more non-active structures; as well as A connector structure is disposed above the gap filling material, and the connector structure is electrically coupled to the second device die. The first non-active structure of the one or more non-active structures includes a stretched membrane. The stretched film may contain metal wires that provide further stretching properties, or the stretched film may contain dopants that enhance and / or control film stress.

10. The packaging device according to claim 9, wherein, The first non-active structure in the one or more non-active structures includes: Semiconductor substrates; and A dielectric bonding layer, which is fused to the dielectric bonding layer of the first device die.

11. The packaging device according to claim 10, wherein, The dopant is carbon or silicon.

12. The packaging device according to claim 10, wherein, The first non-active structure also includes a metallization layer.

13. The packaging device according to claim 12, wherein, The first non-active structure further includes bonding pads disposed in the dielectric bonding layer, the bonding pads being bonded to corresponding bonding pads of the first device die without the use of solder.

14. The packaging device according to claim 12, wherein, The first non-active structure also includes a via through the thickness of the semiconductor substrate, the via being configured to dissipate heat from the first device die.

15. The packaging device according to claim 9, wherein, The one or more non-active structures are not electrically coupled to the active devices of the first device die.

16. A packaged device, comprising: First device die; The second device die is bonded to the first device die; One or more non-active structures are bonded to the first device die, wherein the cumulative area of ​​the second device die and the one or more non-active structures is greater than 50% of the area of ​​the first device die; A dielectric layer, laterally surrounding the second device die and the one or more non-active structures; and A connector structure is disposed above the dielectric layer, and the connector structure is electrically coupled to the second device die. The first non-active structure of the one or more non-active structures includes a stretched membrane. The stretched film may contain metal wires that provide further stretching properties, or the stretched film may contain dopants that enhance and / or control film stress.

17. The packaging device according to claim 16, wherein, The first non-active structure in the one or more non-active structures further includes a semiconductor substrate, a dielectric bonding layer, a metal line, a bonding pad disposed in the dielectric bonding layer, or one or more vias disposed in the semiconductor substrate.

18. The packaging device according to claim 16, wherein, The first non-active structure in the one or more non-active structures has a first sidewall aligned with the sidewall of the first device die.

19. The packaged device according to claim 16, wherein, The connector of the connector structure is electrically coupled to the first device die through a first non-active structure in one or more non-active structures.

20. The packaging device according to claim 16, wherein, The cumulative area of ​​the second device die and the one or more non-active structures is less than 95% of the area of ​​the first device die.

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