Integrated circuit structure and method for bipolar transistors with an extrinsic base aligned with a FET gate

Abstract

The present disclosure relates to an integrated circuit structure and method for a bipolar transistor having an extrinsic base aligned with a FET gate. Aspects of the present disclosure provide an integrated circuit (IC) structure having a bipolar transistor stack within a substrate. The bipolar transistor stack can include a collector, a base on the collector, and an emitter on a first portion of the base. The emitter has a horizontal width that is less than a horizontal width of the base, and an upper surface of the emitter is substantially coplanar with an upper surface of the substrate. An extrinsic base structure is on a second portion of the base of the bipolar transistor stack and horizontally adjacent to the emitter. The extrinsic base structure includes an upper surface that is above the upper surface of the substrate.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to integrated circuit (IC) structures. More specifically, various embodiments of this disclosure provide an IC structure having a stack of bipolar transistors located within a substrate and related methods for forming the IC. Background Technology

[0002] In the microelectronics industry, and in other industries involving the construction of microstructures, there has always been a desire to reduce the size of structural features and microelectronic devices and / or to provide a greater volume of circuitry for a given chip size. Miniaturization typically allows for improved performance (more processing per clock cycle and less heat generation) at lower power levels and lower costs. Current technology is at the stage of atomically scaling certain miniature devices, such as logic gates, transistors, resistors, capacitors, etc. Circuit chips with millions of such devices are common.

[0003] One type of transistor architecture is the bipolar junction transistor (BJT). A BJT is a transistor formed from three adjacent semiconductor regions (called the emitter, base, and collector, respectively) with alternating conductivity types (e.g., NPN or PNP). What distinguishes a BJT from other types of transistors is that it is a "current-controlled device," meaning the current flowing to the transistor's base controls the current flow between the emitter and collector. BJTs can take various shapes and can include vertically stacked semiconductor layers (i.e., a vertical BJT) or a horizontal array of semiconductor material (i.e., a lateral BJT). In the case of a vertical BJT, a persistent technological consideration is the ability to fabricate BJT components on a scale similar to that of field-effect transistors (FETs) formed on the same substrate. In conventional processing, the layers of a vertical BJT are vertically positioned above the substrate and / or above the source / drain regions of a FET on the same substrate. This results in significant differences in the dimensions of the BJT and FET contacts, which may require larger interconnect areas and / or lead to performance degradation. Summary of the Invention

[0004] This disclosure provides an integrated circuit (IC) structure comprising: a bipolar transistor stack located within a substrate, the bipolar transistor stack including: a collector, a base located on the collector, and an emitter located on a first portion of the base, wherein the horizontal width of the emitter is smaller than the horizontal width of the base, and the upper surface of the emitter is substantially coplanar with the upper surface of the substrate; and an outer base structure located on a second portion of the base in the bipolar transistor stack and horizontally adjacent to the emitter; wherein the outer base structure includes an upper surface located above the upper surface of the substrate.

[0005] Another aspect of this disclosure provides an integrated circuit (IC) structure, comprising: a doped semiconductor region located within a substrate; a first trench isolation (TI) horizontally adjacent to the doped semiconductor region; a bipolar transistor (BPT) stack located within the substrate, above the doped semiconductor region, and adjacent to the first trench isolation (TI) region, the BPT stack including a collector on the doped semiconductor region, a base on the collector, and an emitter on a first portion of the base, wherein the horizontal width of the emitter is smaller than the horizontal width of the base, and the upper surface of the emitter is substantially coplanar with the upper surface of the substrate; a first external base located on a second portion of the base in the BPT stack and adjacent to the first TI, wherein the first external base is horizontally adjacent to the emitter; and a second external base located on the first external base, wherein the second external base includes an upper surface located above the upper surface of the substrate.

[0006] Another aspect of this disclosure provides a method for forming an integrated circuit (IC) structure, the method comprising: forming a bipolar transistor stack within a substrate, the bipolar transistor stack including: a collector on the substrate, a base on the collector, and an emitter on a first portion of the base, wherein the horizontal width of the emitter is smaller than the horizontal width of the base, and the upper surface of the emitter is substantially coplanar with the upper surface of the substrate; and forming an outer base structure on a second portion of the base in the bipolar transistor stack and horizontally adjacent to the emitter, wherein the outer base structure includes an upper surface located above the upper surface of the substrate. Attached Figure Description

[0007] These and other features of the present disclosure will be more readily understood in conjunction with the accompanying drawings describing various embodiments of the present disclosure, and in accordance with the following detailed description of various aspects of the present disclosure, wherein:

[0008] Figure 1 A cross-sectional view of a preliminary structure for forming an IC structure according to an embodiment of the present disclosure is provided.

[0009] Figure 2 A cross-sectional view of a trench isolation (TI) region formed within an IC structure according to an embodiment of the present disclosure is provided.

[0010] Figure 3 A cross-sectional view of an opening formed in a substrate according to an embodiment of the present disclosure is provided.

[0011] Figure 4 A cross-sectional view of a doped semiconductor region formed in a substrate according to an embodiment of the present disclosure is provided.

[0012] Figure 5A cross-sectional view of a bipolar transistor stack formed in a substrate according to an embodiment of the present disclosure is provided.

[0013] Figure 6 A cross-sectional view of an opening formed within a bipolar transistor stack according to an embodiment of the present disclosure is provided.

[0014] Figure 7 A cross-sectional view of a second TI region formed by a horizontal stack of bipolar transistors according to an embodiment of the present disclosure is provided.

[0015] Figure 8 A cross-sectional view is provided showing a portion of the emitter removed to reduce its width according to an embodiment of the present disclosure.

[0016] Figure 9 A cross-sectional view of a spacer liner formed according to an embodiment of the present disclosure is provided.

[0017] Figure 10 A cross-sectional view of forming a pair of first outer bases according to an embodiment of the present disclosure is provided.

[0018] Figure 11 A cross-sectional view of the formation of an additional semiconductor layer according to an embodiment of the present disclosure is provided.

[0019] Figure 12 A cross-sectional view is shown of a portion of an additional semiconductor layer removed to form a second outer base according to an embodiment of the present disclosure.

[0020] Figure 13 A cross-sectional view of an IC structure according to an embodiment of the present disclosure is provided.

[0021] Figure 14 Enlarged cross-sectional views of the first and second external bases in an IC structure according to embodiments of the present disclosure are provided.

[0022] Figure 15 Cross-sectional views of bipolar transistors and FETs in an IC structure according to embodiments of the present disclosure are provided.

[0023] Figure 16 Cross-sectional views of bipolar transistors and FETs in an IC structure according to additional embodiments of the present disclosure are provided.

[0024] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict typical aspects of this disclosure and should therefore not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0025] In this description, reference is made to the accompanying drawings, which form a part of the invention, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made within the scope of the present teachings. Therefore, the description herein is merely illustrative.

[0026] Embodiments of this disclosure provide an integrated circuit (IC) structure having a bipolar junction transistor (BJT) stack located within a substrate and a related method for forming the same. The BJT stack can be, for example, NPN, PNP, heterojunction (HBT) NPN, or HBT PNP. This structure may include a doped semiconductor region located within the substrate and a BJT stack located on the doped semiconductor region. The BJT stack includes a collector located on the doped semiconductor region, a base located on the collector, and an emitter located on a portion of the base. The horizontal width of the emitter is smaller than the horizontal width of the base. A first outer base is located on another portion of the base, such that the first outer base is at least partially located within the substrate and horizontally adjacent to the emitter. Therefore, the BJT stack and the first outer base are at least partially located within the substrate. A second outer base is located on the first outer base and has an upper surface located above the upper surface of the substrate. Therefore, contacts through the doped semiconductor region to the emitter, base, and collector can be formed at a scale similar to that of a field-effect transistor (FET) device also formed on the substrate.

[0027] BJT structures, such as those in the embodiments of this disclosure, operate using multiple "PN junctions". The term "PN" refers to two adjacent materials with different conductivity types (i.e., P-type and N-type), the conductivity type being induced by dopants within the adjacent materials. When formed in a device, a PN junction can function as a diode. A diode is a two-terminal element that behaves differently than the conductive or insulating materials between two electrical contacts. Specifically, a diode provides high conductivity from one contact to another in one voltage bias direction (i.e., the "forward" direction), but provides almost no conductivity in the opposite direction (i.e., the "reverse" direction). In the case of a PN junction, the orientation of the diode in the forward and reverse directions depends on the type and magnitude of the bias applied to the composition of the materials at one or both terminals, which affects the size of the barrier. In the case of a junction between two semiconductor materials, the barrier will form along the interface between the two semiconductor materials. The IC structure according to this disclosure uses doped semiconductor materials to create a BJT within a substrate for use as a device layer, while also providing an outer base structure at least partially located above the substrate. Forming an external base structure above the upper part of the substrate can increase device scalability, improve operational reliability, and make it easier to integrate vertical BJTs into IC layouts.

[0028] refer to Figure 1 This document illustrates a preliminary structure 100 (hereinafter referred to as the "structure") suitable for forming an IC structure according to embodiments of the present disclosure. The preliminary structure 100 may be processed as described herein to produce one or more vertical BJT structures having an outer base at least partially located above a substrate. However, it should be understood that in other embodiments, other techniques, process sequences, etc., may be implemented to produce the same or similar BJT structures. Figure 1 A cross-sectional view of a structure 100 having a substrate 102 comprising, for example, one or more semiconductor materials is shown. The substrate 102 may comprise any semiconductor material now known or later developed, which may include, but is not limited to, silicon, germanium, silicon carbide, and materials substantially composed of one or more semiconductor materials having the formula Al. X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 The semiconductor material is defined as a group III-V compound semiconductor, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero, and X1 + X2 + X3 + Y1 + Y2 + Y3 + Y4 = 1 (where 1 is the total relative molar amount). Other suitable substrates include those with the composition Zn. A1 Cd A2 Se B1 Te B2 The semiconductor is a group II-VI compound semiconductor, wherein A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). Furthermore, the entire substrate 102 or a portion thereof may be subjected to strain.

[0029] Substrate 102 may optionally include embedded elements for electrically isolating the active material formed thereon from other regions and / or materials within substrate 102. Resistive region 104 may be formed within substrate 102, for example by converting the silicon material within substrate 102 into a high-resistivity material such as polycrystalline silicon or amorphous silicon (poly-Si). Resistive region 104 may extend horizontally throughout substrate 102 and / or may be selectively formed below the location where the active material is formed, examples of which are discussed elsewhere herein. In other implementations, resistive region 104 may include oxygen doping to form a dielectric insulator or buried oxide (“BOX”) layer beneath substrate 102 to electrically isolate the overlying active semiconductor material. In other implementations, resistive region 104 may include other implanted elements or molecules, such as Ge, N, or Si. However, the size of resistive region 104 may be designed to be as narrow as possible to provide better interaction with the overlying semiconductor material, and in various embodiments, resistive region 104 may have a thickness of up to about 25 nanometers (nm) to about 500 nm. Some portions of the substrate 102 may not have the resistive region 104, and / or multiple resistive regions 104 may be formed at different depths within the substrate 102. An example of this implementation is... Figure 15 The following are shown and discussed elsewhere in this document. In addition, various conductive particles (“dopants”) may be introduced into the substrate 102 via a process known as “pre-doping” targeting the substrate 102 above the resistive region 104.

[0030] The method according to this disclosure may include removing selected portions of a substrate 102 through a mask 106 to form a set of trenches 108. Reactive ion etching (RIE), performed by using a mask 106 at appropriate locations on the substrate 102, is a suitable technique for forming trenches 108 in which a dielectric material can be formed. Etching generally refers to the removal of material from a substrate (or a structure formed on the substrate) and is typically performed using patterned material such as a mask 106 at appropriate locations to selectively remove material from specific regions of the substrate while leaving material in other regions of the substrate unaffected. There are generally two types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (e.g., acid) and has the ability to selectively dissolve a given material (e.g., oxide) while leaving another material (e.g., polysilicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching typically isotropically etches homogeneous materials (e.g., oxides), but it can also anisotropically etch single-crystal materials (e.g., silicon wafers). Dry etching can be performed using plasma. Plasma systems can operate in several modes by adjusting plasma parameters. Conventional plasma etching generates neutrally charged high-energy free radicals that react on the wafer surface. Because neutral particles attack the wafer from all angles, this process is isotropic. Ion milling or sputtering etching bombards the wafer with high-energy ions from rare gases that approach the wafer from roughly one direction, making this process highly anisotropic. Reactive ion etching (RIE) operates under conditions between sputtering and plasma etching and can be used to produce deep, narrow features suitable for forming similar elements, such as the vertically extending circular electrodes discussed herein.

[0031] Turning Figure 2 Embodiments of this disclosure may include trench 108 ( Figure 1A set of trench isolations (TIs) 110 are formed within the substrate 102. TIs 110 can be formed by filling trenches 108 with an insulating material, such as an oxide, to isolate a region of substrate 102 from adjacent regions of substrate 102. Various portions of the IC structure (including active semiconductor material for BJTs and / or other suitable devices) can be disposed within the regions isolated by the TIs 110. According to one example, four TIs 110 are formed, with three portions of substrate 102 horizontally positioned between corresponding pairs of the four TIs. A portion of substrate 102 can be processed to form doped regions for the BJTs, while other portions of substrate 102 can be processed to form conductive coupling to a terminal of the BJT structure. TIs 110 can be formed prior to the formation of active material within substrate 102, but this is not the case in all implementations. Each TI110 can be formed from any material now known or later developed for providing electrical insulation, such as: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ethers, spin-coated silicon-carbon polymer materials, near-frictionless carbon (NFC), or layers thereof. Furthermore, a set of pad insulators 111 can be formed on portions of semiconductor material located horizontally between the TI 110s to protect these semiconductor material regions from removal and / or from use in subsequent operations for selected epitaxial growth. The pad insulators 111 can have a thickness not exceeding about 25 nanometers (nm). Controlling the thickness of the pad insulators 111 allows for subsequent doping of the semiconductor material beneath them.

[0032] Turning Figure 3 Embodiments of this disclosure may include forming an opening 112 within a substrate 102. Reactive ion etching (RIE), performed using a mask 106a appropriately positioned on the substrate 102, is a suitable technique for forming the opening 112 within the substrate 102. The formation of the opening 112 can be controlled such that the opening 112 exposes a portion of the substrate 102 above the resistive region 104. The opening 112 may be horizontally located between the TIs 110 and may be configured for use in subsequent processing to form a stack of bipolar junction transistor (BJT) terminals. In some cases, the depth of the opening 112 within the substrate 102 may be the same as that of the TIs 110. Compared to other processing paradigms for forming vertical BJT structures, the collector layer, base layer, and emitter layer of a vertical BJT may each be located within the opening 112, and therefore within the substrate 102. Some of the outer base regions of the BJT may also be formed within the substrate 102, while other outer base materials may be at least partially located outside and above the substrate 102.

[0033] Turning Figure 4 Subsequent processing may include initial doping of the substrate 102 through opening 112 to form a doped semiconductor region 114. In some cases, the introduction of dopant into the substrate 102 is not hindered by the presence of a relatively thin pad insulator 111, as noted elsewhere herein. Forming the doped semiconductor region 114 prepares the substrate 102 for the formation of active semiconductor material in a BJT stack. The initial doping of the substrate 102 used to form the doped semiconductor region 114 may be a relatively low concentration of P-type or N-type dopant compared to the subsequently formed doped material. A P-type dopant is an element introduced into the substrate 102 to generate free holes by “accepting” electrons from semiconductor atoms and thus “releasing” holes. The acceptor atom must have one less valence electron than the host semiconductor. Suitable P-type dopants for the substrate 102 may include, but are not limited to, boron (B), indium (In), and gallium (Ga). Boron (B) is the most common acceptor in silicon technology. Other alternatives include indium and gallium (Ga). Gallium (Ga) has high diffusivity in silicon dioxide (SiO2), therefore oxides cannot be used as masks during Ga diffusion. N-type dopants are elements introduced into semiconductor materials to generate free electrons, for example, by "donating" electrons to the semiconductor. An N-type dopant must have one more valence electron than the semiconductor. Common N-type donors in silicon (Si) include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb).

[0034] In the example implementation, using Figure 3 The masking layer 106a shown is used to dope the doped semiconductor region 114 with an N-type dopant, although in other implementations the doped semiconductor region 114 may be P-type doped. Although the doped semiconductor region 114 has a uniform dopant distribution, different regions of the doped semiconductor region 114 may be structurally different. For example, a first portion 114a of the doped semiconductor region 114 may be a portion of the doped semiconductor region 114 located vertically below the opening 112 and TI 110 (if applicable). A second portion 114b of the doped semiconductor region 114 may be horizontally adjacent to the first portion 114a and may extend vertically from the upper surface J of the substrate 102 to a predetermined depth. In the example, the first portion 114a extends from the upper surface J into the resistive region 104 within the substrate 102. The portions 114a and 114b of the doped semiconductor region 114 may be formed using different doping instances (e.g., double implantation). In the figures, dashed lines separate the first portion 114a from the second portion 114b, indicating their locations. However, it should be understood that the structural composition of the doped semiconductor region 114 can be uniform throughout the first part 114a and the second part 114b.

[0035] Turn now Figure 5 A patterned masking layer 106b is formed by depositing a dielectric such as SiN, photolithographically patterning openings, etching the dielectric, and stripping off the remaining photoresist material. Embodiments of this disclosure include selectively forming alternately doped semiconductor materials to form NPN or PNP junctions, thereby forming the active region of a vertical BJT. Therefore, subsequent processing may be included on the first portion 114a of the doped semiconductor region 114 and in the opening 112 ( Figure 4 A BJT stack 116 is formed within the opening 112. The BJT stack 116 can be formed, for example, by depositing and / or epitaxially growing silicon germanium (SiGe) (e.g., as a single layer) within the opening 112. “Deposition” can include any technique now known or later developed suitable for the material to be deposited, including but not limited to, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), subatmospheric pressure CVD (SACVD) and high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), finite reaction process CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin coating, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporation.

[0036] The BJT stack 116 can be formed by selectively depositing silicon-germanium (SiGe) or similar materials, wherein a mask (not shown) may be used at appropriate locations above other portions of the substrate 102 to prevent the formation of active semiconductor material on those portions. The BJT stack 116 may include a collector 116a, which may be doped N-type or P-type, and more specifically, may have the same polarity as the doped semiconductor region 114 beneath it. The collector 116a may have less doping than the doped semiconductor region 114 and may be doped in situ during its deposition and growth within the opening 112. Next, the base 116b of the BJT stack 116 can be formed on the collector 116, for example, by selective deposition and etching on the collector 116a. The base 116b may also be formed of SiGe or other semiconductor materials and may have the opposite doping type to the collector 116a, for example, P-type when the collector 116a is N-type and vice versa. Similar to collector 116a, base 116b can be in-situ doped to any desired concentration. Emitter 116c can be formed on base 116b by deposition and / or epitaxial growth, and emitter 116c can have the same doping type as collector 116a of BJT stack 116. Emitter 116c can be doped to any desired concentration and can have approximately the same doping concentration as collector 116a. Emitter 116c material can be pre-doped or in-situ doped after epitaxial growth. Some portions of the doped semiconductor material within BJT stack 116 can be removed in subsequent processing, as discussed herein. In combination, collector 116a, base 116b, and emitter 116c can form NPN or PNP junctions depending on their formation and doping, thus defining three active terminals of a vertical BJT.

[0037] Figure 6 and 7 An optional process is illustrated for removing selected portions of a BJT stack 116 to form additional insulating material. These selectively removed portions of the BJT may form crystal defects during selective epitaxial growth, which can degrade the BJT's function or reliability. For example, Figure 6 This illustrates a set of openings B (only) formed in the opposite lateral ends of the BJT stack 116. Figure 6This exposes a first portion 114a of the doped semiconductor region 114 beneath it. An opening B can be horizontally positioned between the previously formed TI 110 and the remaining portions of the collector 116a, base 116b, and emitter 116c. The opening B can be formed by removing the exposed portions of the BJT stack 116 using a deposition mask (not shown) and, for example, by RIE or other etching. Additional insulating material can be formed within the opening B to form a set of additional TI 117 horizontally positioned between the TI 110 and the BJT stack 116. The additional TI 117 can comprise any conceivable insulating material, including one or more of those discussed herein relative to the TI 110. Thus, in some implementations, the additional TI 117 can have the same material composition as the TI 110. However, in this case, the physical boundary between the TI 110 and the additional TI 117 is detectable, for example, because there may be a time difference in the formation of the material for each TI 110 and additional TI 117. After formation, TI 110 and additional TI 117 can be horizontally arranged around adjacent structural components. For example, additional TI 117 can be horizontally arranged around and thus surround BJT stack 116, while TI 110 can be horizontally arranged around and thus surround additional TI 117. Figure 7 The portions of the TI 110 and the additional TI 117 shown can therefore be portions of a single material region.

[0038] Go to Figure 8 A portion of the BJT stack 116 can be removed to allow the formation of electrical terminals on the base 116b. Initially, the emitter 116c can completely cover the base 116b of the BJT stack 116. Subsequent processing may include forming an emitter mask 118 on the emitter 116c. The emitter mask 118 may have a horizontal width W1 smaller than the horizontal width W2 of the base 116b. With the emitter mask 118 in place, portions of the emitter 116c not covered by the emitter mask 118 can be removed (e.g., by vertical RIE or other etching techniques) such that the emitter 116c also has a horizontal width W1 smaller than the horizontal width W2 of the base 116b. Removing portions of the emitter 116c can expose portions of the base 116b to allow subsequent formation of the outer base material.

[0039] Now for reference Figure 9Subsequent processing may include, for example, forming a spacer liner 120 on the sidewalls and top surface of the emitter 116c by performing conformal deposition and etching on the exposed surface of the emitter 116c. The spacer liner 120 may be formed of a nitride insulator and / or other insulating materials described elsewhere herein with respect to TI 110, 117, and / or other insulating materials. The spacer liner 120 may also be formed on the sidewalls of TI 110, 117, for example, above the base 116b. Other portions of the spacer liner 120 formed on the exposed portions of the TI 110, 117, pad insulator 111, base 116b, etc., may be removed by vertical etching. This vertical etching may be achieved using a mask (not shown) above the emitter 116c to prevent removal of the spacer liner 120 from the emitter 116c. Once formed, the spacer liner 120 electrically separates the emitter 116c from other materials formed on the base 116b.

[0040] Figure 10 One or more first outer bases 122 are shown formed on an inner base 116b, wherein a portion of the emitter 116c has been pre-removed. The first outer bases 122 can be formed by deposition and / or epitaxial growth of silicon and / or other semiconductor materials and can have the same doping type as the base 116b below it. However, the first outer bases 122 can have a higher dopant concentration than the base 116b (also referred to as the “inner base” to distinguish it from the outer base 122). The higher doping concentration in the first outer bases 122 can increase the conductivity between the base 116b and any contacts coupled to the first outer bases 122, thereby controlling the current flow through the BJT stack 116. Despite the higher dopant concentration, the first outer bases 122 can have the same material composition as the BJT stack 116 and can therefore include SiGe. Concurrently with the formation of the first outer bases 122, a set of masks (not shown) can be formed on Ti 110, pad insulator 111, spacer liner 120, and / or other materials. When using such a mask, the first outer base 122 can be formed by selectively epitaxially growing additional semiconductor material on the exposed portion of the base 116b. In this case, the first outer base 122 may have an upper surface that is substantially coplanar with the upper surface J of the substrate 102, Ti 110, 117 and / or the doped semiconductor region 114 formed thereafter. When the first outer base 122 is formed by selective growth, it can be planarized using chemical mechanical planarization (CMP) so that its upper surface is substantially coplanar with the upper surface J.

[0041] Turning Figure 11An additional semiconductor layer 124 can be formed on the substrate 102, Ti 110, 117, doped semiconductor region 114, emitter 116c, and first external base 122. The additional semiconductor layer 124 can be patterned into a set of second external bases 126 on the first external base 122. Figure 12 The additional semiconductor layer 124 can be formed as a single layer, for example, by deposition. In this case, portions of the additional semiconductor layer 124 can contact the underlying first external base 122 to form a vertical junction between the first external base 122 and the additional semiconductor layer 124. The additional semiconductor layer 124 can comprise the same and / or different materials as the substrate 102 and can be processed into a second external base 126. According to an example, the additional semiconductor material 124 can comprise, for example, a deposited layer of polysilicon (poly-Si). In this case, the polysilicon material can be doped after deposition to have the same polarity as the underlying first external base 122. However, in this case, the additional semiconductor material 124 can have a different material composition than the first external base 122, although having the same doping polarity and / or a similar dopant concentration.

[0042] Also refer to Figure 11 and 12 This can be achieved by forming a set of masks 127 on the additional semiconductor layer 124. Figure 12 ), to add semiconductor layer 124 ( Figure 11 The additional semiconductor layer 124 is partially patterned as a second external base 126. With the mask 127 in place, portions of the semiconductor layer 124 not covered by the mask 127 can be removed by etching the semiconductor material. A pad insulator 111 pre-formed on the second portion 114b of the doped semiconductor region 114 can prevent the semiconductor region 114 from being etched when the target portion of the additional semiconductor layer 124 is removed. Therefore, the additional semiconductor region 124 can be patterned as a second external base 126 above the first external base 122. The remaining portion of the additional semiconductor layer 124 above the first external base 122 thus becomes one or more second external bases 126. Each second external base 126 is located above a corresponding first external base 122. Forming the second external base 126 in this way results in the second external base 126 being vertically positioned above the substrate 102 and the material formed therein (including Ti 110, 117, doped semiconductor region 114, emitter 116c, first external base 124, etc.). The formation of the second outer base 126 allows for the formation of contacts to the BJT stack 116 and the first outer base 122 in subsequent processing. Although the second outer base region 126 is shown to completely cover the first outer base region 122, it may also only partially cover the first outer base region 122.

[0043] Figure 13An interlayer dielectric (ILD) layer 128 is shown formed over a substrate 102, including Ti 110, 117 and doped semiconductor regions 114, as well as a BJT stack 116 and a second outer base 126. The ILD layer 128 can be formed, for example, by depositing an insulating material on the structure or by forming it using other techniques. The ILD layer 128 may include the same insulating material as Ti 110, 117, or it may include a different electrically insulating material. The ILD layer 128 and Ti 110, 117 still constitute different components, for example, because Ti 110, 117 are formed within portions of the substrate 102 rather than on it. In other embodiments (not shown), a silicide layer known in the art may be formed on the exposed semiconductor surface prior to the deposition of the ILD layer 128. For example, Co, Ti, Ni, Pt, or similar self-aligned silicides (silicides) may be formed prior to the deposition of the ILD layer 128. During mid-process and / or back-processing, an additional metallization layer (not shown) may be formed on the ILD layer 128. To electrically couple the various components discussed herein to such a metallization layer, emitter contacts 130a may be formed on the emitter 116c of the BJT stack 116 and within the ILD 130. When forming the emitter contacts 130a, portions of the spacer liner 120 on the upper surface of the emitter 116c may be removed by vertical etching (e.g., by RIE), while other portions of the spacer liner 120 may remain intact. Similarly, one or more base contacts 130b may be formed on the second outer base 126 and within the ILD 130. Additionally, one or more collector contacts 130c may be formed on the doped semiconductor region 114 (e.g., at its second portion 114b) by etching portions of the ILD layer 128 and the pad insulator 111 to expose a second portion 114b of the doped semiconductor region 114 beneath it. At this stage, the doped semiconductor region 114 electrically couples the collector contact 130c to the collector 116a.

[0044] One or more contacts 130a, 130b, 130c to overlying circuit elements can be formed within a predetermined portion of the ILD layer 128 by forming openings at one or more contact locations through controlled vertical etching and then filling these openings with a conductor. Each contact 130a, 130b, 130c may include any known or later-developed conductive material configured for electrical contact, such as copper (Cu), aluminum (Al), gold (Au), etc. Contacts 130a, 130b, 130c may additionally include a refractory metal liner (not shown) disposed transversely to the ILD layer 128 to prevent electromigration degradation, short circuits with other components, etc. Additionally, selected portions of the doped semiconductor region 114, emitter 116c, and second outer base 126 may include silicide regions (i.e., semiconductor portions annealed in the presence of an overlying conductor to increase the conductivity of the semiconductor region) to increase their conductivity at the physical interface with contacts 130a, 130b, 130c, where appropriate.

[0045] Embodiments of this disclosure provide an IC structure 150 in which a doped semiconductor region 114, a BJT stack 116, a first outer base 122, and a second outer base 126 collectively define components of a vertical BJT 160. The ability of current to flow from the collector 116a to the emitter 116c is controlled by applying current to the base 116b via the outer bases 122, 126 located above the base 116b. As discussed herein, the base 116b may have a lighter doping concentration than the outer bases 122, 126 to control the sensitivity of the base 116b to current within the base contact 130b. The outer bases 122, 126 have significantly higher doping concentrations than the base 116b, and the second outer base 126 may have a different material composition (e.g., as a result of separate formation and / or doping operations discussed herein). The second outer base 126 may also be located at least partially above the substrate 102 and the various components formed therein.

[0046] Figure 14An enlarged cross-sectional view of a vertical BJT 160 is shown, including a BJT stack 116, a first outer base 122, and a second outer base 126. In some implementations, the second outer base 126 may include an outer portion 162 (shown in dashed lines) representing semiconductor material not removed from the TI 110, 117, spacer liner 120, and / or other materials disposed transversely to the first outer base 122. However, the lower surface S1 of the second outer base 126 on the first outer base 124 may be substantially coplanar with the first outer base 124 and the upper surface S1 of the substrate 102. Additionally, the upper surface S2 of the second outer base 126, including the outer portion 162, may be vertically positioned above the upper surface S1 of the substrate 102. In this configuration, the second outer base 126 may be characterized as a “raised outer base,” referring to a portion of the outer base material formed above the substrate 102. This configuration allows highly doped semiconductor materials for the outer bases 122 and 126 to be formed within and on the substrate 102, while the BJT stack 116 including the collector 116a, base 116b, emitter 116c and the first outer base 124 are formed within the substrate 102, for example, below its upper surface S1.

[0047] Referring also to 13 and 15, IC structure 150 may include a vertical BJT 160 and a field-effect transistor (FET) 164 located in substrate 102. Figure 12 A cross-sectional view of IC structure 150 shows substrate 102 as a single layer, where TI 110 horizontally separates vertical BJT 160 from FET 164. The region in substrate 102 where BJT 160 is formed may define a first portion 102a of substrate 102. The region in substrate 102 where FET 164 is formed defines a second portion 102b of substrate 102. FET 164 may be formed to include a gate structure 166. The formation of FET 164 may allow gate structure 166 to have an upper surface substantially coplanar with the upper surface of the second outer base 126 along a horizontal line P. Gate structure 166 may also include a lower surface substantially coplanar with the upper surface of emitter 116c. The configuration of the vertical BJT 160, having a second external base 126 located above the substrate 102, allows the FET and BJT to be implemented together in a single device layer, wherein the dimensions of the contacts 130a, 130b, 130c to the vertical BJT 160 are similar to those of the other conductors. For example, the contacts 130a, 130b, 130c may have substantially the same or similar dimensions to the additional contacts 130d located within the ILD layer 128 to the gate structure 166 of the FET 164.

[0048] refer to Figure 15 and 16FET 164 can be formed above one or more resistive regions 104 on substrate 102, and can have its own doped regions, terminals, contacts, etc., in addition to FET gate stacks or similar components. Figure 15 In the example, a single resistive region 104 can extend horizontally through the substrate 102, with a portion located below the vertical BJT 160 and another portion located below the FET 164. Figure 16 In the alternative example shown, the substrate 102 may include a plurality of resistive regions 104 located at different positions within the substrate 102 and respectively below the vertical BJT 160 or FET 164. With a plurality of resistive regions 104, each resistive region 104 may have a different depth within the substrate 102 based on the shape of the BJT 160 and / or FET 164 above it. Figure 16 An example is shown in which the trench isolation 110 has a lower surface in contact with the buried resistor region 104 below it. In an embodiment, for Figure 15 and 16 In the structure of the BJT 160 and / or FET 164, the trench isolation 110 can contact the buried resistor region 104.

[0049] The embodiments of this disclosure provide various technical and commercial advantages, examples of which are discussed herein. Embodiments of this disclosure provide an IC structure 150 with a vertical BJT 160, wherein a BJT stack 116 and a first external base 124 are located within a substrate 102. In this configuration, a second external base 126 is at least partially located above the substrate 102. These physical aspects of the vertical BJT 160 allow contacts 130a, 130b, 130c thereto to be formed with dimensions similar to other contacts to a FET 164 and / or other components formed elsewhere on the same layer of the substrate 102. These physical features of the vertical BJT 160 are achieved in part by forming a doped semiconductor region 114 and the BJT stack 116 within an opening in the substrate 102 and horizontally adjacent to TI 110, 117. Furthermore, the dimensions of the BJT stack 116 allow it to be formed with an opening size similar to that used for forming the TI 110, 117. Furthermore, the second outer base 126 may comprise a different material than the base 116b and / or the first outer base 122, thereby allowing for better control over the sensitivity of the vertical BJT 160 to voltage variations at its base terminals.

[0050] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0052] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0053] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. An integrated circuit (IC) structure, comprising: A bipolar transistor stack located within a substrate, the bipolar transistor stack comprising: collector, The base located on the collector, and An emitter located on a first portion of the base, wherein the horizontal width of the emitter is smaller than the horizontal width of the base; An outer base structure located on the second portion of the base in the bipolar transistor stack and horizontally adjacent to the emitter; wherein the outer base structure includes an upper surface located above the upper surface of the substrate; A doped semiconductor region located within the substrate, wherein the doped semiconductor region includes a first portion extending vertically from the upper surface of the substrate to a depth below the bipolar transistor stack, and a second portion horizontally adjacent to the first portion and located below the bipolar transistor stack; A first trench isolation TI horizontally located between the doped semiconductor region and the bipolar transistor stack; and A second TI is horizontally located between the bipolar transistor stack and the first TI and contacts the bipolar transistor stack and the first TI, wherein there is a physical boundary between the first TI and the second TI.

2. The IC structure according to claim 1, wherein, A portion of the outer base structure is located above the first TI or the second TI.

3. The IC structure according to claim 1 further includes: At least one resistive region located within the substrate beneath the bipolar transistor stack, wherein the resistive region comprises polycrystalline silicon.

4. The IC structure according to claim 1, further comprising: A field-effect transistor (FET) located on a portion of the substrate laterally shifted from the bipolar transistor stack, wherein the FET includes a gate structure having a lower surface substantially coplanar with the upper surface of the emitter.

5. The IC structure according to claim 1, wherein, The outer base structure comprises doped polycrystalline silicon.

6. An integrated circuit (IC) structure, comprising: Doped semiconductor regions located within the substrate; The first trench isolation TI is horizontally adjacent to the doped semiconductor region. A bipolar transistor stack located within the substrate, above the doped semiconductor region, and adjacent to the first trench isolation TI region, the bipolar transistor stack including a collector on the doped semiconductor region, a base on the collector, and an emitter on a first portion of the base, wherein the horizontal width of the emitter is smaller than the horizontal width of the base; A second TI is horizontally located between the bipolar transistor stack and the first TI and contacts the bipolar transistor stack and the first TI, wherein there is a physical boundary between the first TI and the second TI; A first external base located on the second portion of the base in the bipolar transistor stack and adjacent to the first TI, wherein the first external base is horizontally adjacent to the emitter; as well as A second outer base located on the first outer base, wherein the second outer base includes an upper surface located above the upper surface of the substrate.

7. The IC structure according to claim 6, wherein, The doped semiconductor region includes a first portion extending vertically from the upper surface of the substrate to a depth below the bipolar transistor stack, and a second portion horizontally adjacent to the first portion and located below the bipolar transistor stack.

8. The IC structure according to claim 6, further comprising: A field-effect transistor (FET) located on a portion of the substrate laterally shifted from the bipolar transistor stack, wherein the FET includes a gate structure having an upper surface substantially coplanar with the upper surface of the second outer base.

9. The IC structure according to claim 8, further comprising: A third TI is horizontally adjacent to the FET, wherein the lower surface of the third TI is located on a resistive region within the substrate.

10. The IC structure according to claim 9, wherein, A portion of the second external base is located above the first TI or the second TI.

11. The IC structure according to claim 6, further comprising: At least one resistive region located within the substrate beneath the bipolar transistor stack, wherein the resistive region comprises polycrystalline silicon.

12. The IC structure according to claim 6, wherein, The second outer base electrode comprises doped polycrystalline silicon.

13. A method for forming an integrated circuit (IC) structure, the method comprising: A bipolar transistor stack is formed within a substrate, the bipolar transistor stack comprising: The current collector located on the substrate, The base located on the collector, and An emitter located on a first portion of the base, wherein the horizontal width of the emitter is smaller than the horizontal width of the base; An outer base structure is formed on the second portion of the base in the bipolar transistor stack and horizontally adjacent to the emitter, wherein the outer base structure includes an upper surface located above the upper surface of the substrate. Forming a doped semiconductor region within the substrate, wherein forming the doped semiconductor region includes: forming a first portion of the doped semiconductor region within the substrate, the first portion extending from the upper surface of the substrate to a depth below the upper surface of the substrate; and forming a second portion of the doped semiconductor region horizontally adjacent to the first portion and located below the bipolar transistor stack; Forming a first trench isolation TI horizontally located between the doped semiconductor region and the bipolar transistor stack; and A second TI is formed horizontally between the bipolar transistor stack and the first TI and in contact with the bipolar transistor stack and the first TI, wherein there is a physical boundary between the first TI and the second TI.

14. The method of claim 13, further comprising: A field-effect transistor (FET) is formed on a portion of the substrate laterally shifted from the bipolar transistor stack, wherein the FET includes a gate structure having an upper surface substantially coplanar with the upper surface of the outer base structure.

15. The method of claim 13, further comprising: An emitter contact is formed on the upper surface of the emitter of the bipolar transistor stack; A base contact is formed on the outer base structure; as well as A collector contact is formed on a portion of the substrate adjacent to the bipolar transistor stack, wherein a doped portion of the substrate electrically couples the collector contact to the collector of the bipolar transistor stack.

16. The method according to claim 13, wherein, Forming the bipolar transistor stack includes growing a single silicon-germanium (SiGe) layer within a substrate and doping a portion of the single SiGe layer to define the base within the single SiGe layer.

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