Analog-to-digital converter, integrated circuit, electronic device and calibration method

Abstract

The embodiment of the present application provides an analog-to-digital converter, an integrated circuit, an electronic device and a correction method, wherein the analog-to-digital converter includes a capacitor array, a comparator and a logic control circuit; the capacitor array includes a first capacitor array and a second capacitor array, the first capacitor array includes N-bit capacitors, the P-th capacitor to the N-th capacitor are capacitor units, and each capacitor unit includes an inherent capacitor and a compensation capacitor unit; the logic control circuit is configured to obtain a first error of each inherent capacitor in the first capacitor array based on the second capacitor array and the comparator; control the corresponding compensation capacitor unit to flip to a compensation state according to the first error of each inherent capacitor; keep the compensation capacitor unit in the compensation state, and obtain the second error of each inherent capacitor based on the second capacitor array and the comparator; and compensate the conversion result of the analog-to-digital converter according to the second error. The analog-to-digital converter provided by the present application can effectively improve the correction efficiency of the analog-to-digital converter.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital conversion, and in particular to an analog-to-digital converter, an integrated circuit, an electronic device, and a correction method. Background Art

[0002] Successive approximation register ADC (SAR ADC) is a structure that uses a capacitor flipping strategy to achieve medium conversion accuracy and medium sampling speed. Since SAR ADC does not require a static power consumption module, it has been widely used in the low power consumption field.

[0003] In practical applications, due to process deviations in the manufacturing process of SAR ADC, SAR ADC will produce errors, affecting accuracy. The traditional way to correct SAR ADC errors is to measure and compensate the errors of the main capacitor array through the auxiliary capacitor array. However, due to the large error of the high-order capacitance of the main capacitor array, the auxiliary capacitor array needs to compensate for a larger value. The auxiliary capacitor array also produces errors due to process deviations, so the value compensated by the auxiliary capacitor array to the main capacitor array also has a large error, resulting in low correction efficiency of the SAR ADC. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide an analog-to-digital converter, an integrated circuit, an electronic device and a calibration method to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides an analog-to-digital converter, comprising a capacitor array, a comparator, and a logic control circuit; the capacitor array comprises a first capacitor array and a second capacitor array, wherein the first capacitor array comprises N-bit capacitors, and the P-th capacitor to the N-th capacitor from low to high are capacitor units, each of the capacitor units comprises an inherent capacitor and a compensation capacitor unit, N and P are positive integers respectively, and P≤N; at least one input end of the comparator is connected to the capacitor array; the logic control circuit is connected to the capacitor array and the comparator, and the logic control circuit is configured to: obtain a first error of each inherent capacitor in the first capacitor array based on a first comparison result between the second capacitor array and the comparator; control the corresponding compensation capacitor unit to flip to a compensation state according to the first error of each inherent capacitor; keep the compensation capacitor unit in the compensation state, and obtain a second error of each inherent capacitor based on a second comparison result between the second capacitor array and the comparator; compensate the conversion result of the analog-to-digital converter according to the second error.

[0006] In a second aspect, an embodiment of the present application further provides an integrated circuit, comprising the above-mentioned analog-to-digital converter.

[0007] In a third aspect, an embodiment of the present application further provides an electronic device, including a device body and the integrated circuit as described above.

[0008] In a fourth aspect, an embodiment of the present application also provides a correction method for an analog-to-digital converter, which is applied to an analog-to-digital converter, wherein the analog-to-digital converter includes a capacitor array and a comparator, wherein the capacitor array includes a first capacitor array and a second capacitor array, the first capacitor array includes N-bit capacitors, and the P-th capacitor to the N-th capacitor from low to high are capacitor units, each of the capacitor units includes an inherent capacitor and a compensation capacitor unit, N and P are positive integers respectively, and P≤N; at least one input end of the comparator is connected to the capacitor array; the method includes: based on a first comparison result between the second capacitor array and the comparator, obtaining a first error of each inherent capacitor in the first capacitor array; controlling the corresponding compensation capacitor unit to flip to a compensation state according to the first error of each inherent capacitor; keeping the compensation capacitor unit in the compensation state, and obtaining a second error of each inherent capacitor based on a second comparison result between the second capacitor array and the comparator; and compensating the conversion result of the analog-to-digital converter according to the second error.

[0009] The analog-to-digital converter, integrated circuit, electronic device and correction method provided by the embodiments of the present application are provided with a capacitor array, a comparator and a logic control circuit; the capacitor array includes a first capacitor array and a second capacitor array, wherein the first capacitor array includes N-bit capacitors, and the P-th capacitor to the N-th capacitor from low to high are capacitor units, each of the capacitor units includes an inherent capacitor and a compensation capacitor unit, N and P are positive integers respectively, and P≤N; at least one input end of the comparator is connected to the capacitor array; the logic control circuit is connected to the capacitor array and the comparator, and the logic control circuit is configured to obtain a first error of each inherent capacitor in the first capacitor array based on a first comparison result between the second capacitor array and the comparator; control the corresponding compensation capacitor unit to flip to a compensation state according to the first error of each inherent capacitor; keep the compensation capacitor unit in the compensation state, and obtain a second error of each inherent capacitor based on a second comparison result between the second capacitor array and the comparator; and compensate according to the conversion result of the second error logarithmic converter. The analog-to-digital converter provided in the embodiment of the present application can perform two corrections on the SARADC, wherein the first correction is a first compensation for the first error generated by the analog-to-digital converter, and the second correction is a second compensation for the second error generated in the compensation process of the first error. Through the two corrections, the error generated by the second capacitor array in the correction process can be effectively reduced, thereby improving the correction efficiency of the analog-to-digital converter.

[0010] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A block diagram of an analog-to-digital converter module provided in an embodiment of the present application is shown.

[0013] Figure 2 A schematic structural diagram of an analog-to-digital converter provided in an embodiment of the present application is shown.

[0014] Figure 3 A schematic structural diagram of a capacitor unit provided in an embodiment of the present application is shown.

[0015] Figure 4 A schematic structural diagram of a 12-bit SAR ADC provided in an embodiment of the present application is shown.

[0016] Figure 5 Shows Figure 4 Schematic diagram of the structure of the capacitor unit.

[0017] Figure 6 A schematic flow chart of a calibration method for an analog-to-digital converter provided in an embodiment of the present application is shown.

[0018] Figure 7 A schematic flow chart of another method for calibrating an analog-to-digital converter provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0020] Successive approximation register ADC (SAR ADC) is a structure that uses a capacitor flipping strategy to achieve medium conversion accuracy and medium sampling speed. Since SAR ADC does not require a static power module, it has been widely used in the field of low power consumption. In practical applications, due to process deviations in the production process of SAR ADC, SAR ADC will produce errors, affecting accuracy. The traditional way to correct SAR ADC errors is to measure and compensate for the errors of the main capacitor array through an auxiliary capacitor array. However, due to the large error of the high-order capacitance of the main capacitor array, the auxiliary capacitor array needs to compensate for a larger value. The auxiliary capacitor array also produces errors due to process deviations, so that the value compensated by the auxiliary capacitor array to the main capacitor array also has a large error, resulting in low correction efficiency of the SAR ADC.

[0021] In order to solve the above technical problems, the inventors have proposed an analog-to-digital converter, an integrated circuit, an electronic device and a correction method according to an embodiment of the present application after long-term research. The analog-to-digital converter is provided with a capacitor array, a comparator and a logic control circuit; the capacitor array includes a first capacitor array and a second capacitor array, wherein the first capacitor array includes N-bit capacitors, and the P-th capacitor to the N-th capacitor from low to high are capacitor units, each of the capacitor units includes an inherent capacitor and a compensation capacitor unit, N and P are positive integers respectively, and P≤N; at least one input end of the comparator is connected to the capacitor array; the logic control circuit is connected to the capacitor array and the comparator, and the logic control circuit is configured to obtain a first error of each inherent capacitor in the first capacitor array based on a first comparison result between the second capacitor array and the comparator; control the corresponding compensation capacitor unit to flip to a compensation state according to the first error of each inherent capacitor; keep the compensation capacitor unit in the compensation state, and obtain a second error of each inherent capacitor based on a second comparison result between the second capacitor array and the comparator; and compensate according to the conversion result of the second error logarithmic converter. The analog-to-digital converter provided in the embodiment of the present application can perform two corrections on the SAR ADC, wherein the first correction is a first compensation for the first error generated by the analog-to-digital converter, and the second correction is a second compensation for the second error generated in the process of compensating the first error. Through the two corrections, the error generated by the second capacitor array in the correction process can be effectively reduced, thereby improving the correction efficiency of the analog-to-digital converter.

[0022] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0023] like Figure 1 As shown, Figure 1The module block diagram of the analog-to-digital converter 100 provided in an embodiment of the present application is schematically shown. The analog-to-digital converter 100 includes a capacitor array 110, a comparator 120 and a logic control circuit 130. The capacitor array 110 includes a first capacitor array 111 and a second capacitor array 112, wherein the first capacitor array 111 includes N-bit capacitors, and the P-th capacitor to the N-th capacitor from the low position to the high position are capacitor units 1110, and each capacitor unit 1110 includes an inherent capacitor 1111 and a compensation capacitor unit 1112; the input end of the comparator 120 is connected to the capacitor array 110; the logic control circuit 130 is connected to the capacitor array 110 and the comparator 120. N and P are positive integers, respectively, and P≤N.

[0024] The first capacitor array 111 can be a main capacitor array, which can sample input signals during the conversion of the analog-to-digital converter 100. The input signal can be a differential input signal or a single-ended input signal, without limitation. The P-th capacitor to the N-th capacitor in the first capacitor array 111 are high-order capacitors in the first capacitor array 111, and the first capacitor to the P-1-th capacitor in the first capacitor array 111 are low-order capacitors in the first capacitor array 111. The error generated by the P-th capacitor to the N-th capacitor in the first capacitor array 111 is large and needs to be corrected; the error generated by the first capacitor to the P-1-th capacitor is small and within the error tolerance range. It is worth noting that the value of P can depend on the accuracy required by the analog-to-digital converter 100. The smaller the value of P, the more capacitors are corrected in the first capacitor array 111, and the higher the accuracy of the analog-to-digital converter 100; conversely, the larger the value of P, the fewer capacitors are corrected in the first capacitor array 111, and the accuracy of the analog-to-digital converter 100 is relatively low.

[0025] In the present embodiment, each capacitor from the P-th capacitor to the N-th capacitor in the first capacitor array 111 is configured as a capacitor unit 1110, that is, the P-th capacitor is the capacitor unit 1110, the P+1-th capacitor is the capacitor unit 1110, and the N-th capacitor is the capacitor unit 1110. The capacitor unit 1110 in the first capacitor array 111 is a high-position capacitor, and the other capacitors in the first capacitor array 1111 except the capacitor unit 1110 are low-position capacitors. Each capacitor unit 1110 includes an inherent capacitor 1111 and a compensation capacitor unit 1112, and the compensation capacitor unit 1112 can be used to compensate for the error generated by the inherent capacitor 1111 in the same capacitor unit 1110. For example, the P-th capacitor includes an inherent capacitor 1111 and a compensation capacitor unit 1112, and the compensation capacitor unit 1112 in the P-th position can be used to compensate for the error generated by the inherent capacitor 1111 in the P-th capacitor.

[0026] The second capacitor array 112 may be an auxiliary capacitor array, which may measure and compensate for the error of the first capacitor array 111. In this embodiment, the second capacitor array 112 may be used to measure and compensate for the error generated from the Pth capacitor to the Nth capacitor of the first capacitor array 111.

[0027] The comparator 120 is configured to compare the input signal at its input terminal. Specifically, the comparator 120 includes a first input terminal and a second input terminal. If the capacitor array 110 is used to sample a differential input signal, the first input terminal and the second input terminal of the comparator 120 are both connected to a capacitor array 110, and the comparator 120 can compare the voltage on the capacitor plate connected to the first input terminal with the voltage on the capacitor plate connected to the second input terminal; if the capacitor array 110 is used to sample a single-ended input signal, one of the first input terminal and the second input terminal of the comparator 120 is connected to the capacitor array 110, and the other is used to access a preset reference voltage, and the comparator 120 can compare the voltage on the connected capacitor plate with the reference voltage.

[0028] In this embodiment, the logic control circuit 130 can obtain the comparison result of the comparator 120, and the logic control circuit 130 is configured to obtain the first error of each inherent capacitor 1111 in the first capacitor array 111 based on the first comparison result of the second capacitor array 112 and the comparator 120; then control the corresponding compensation capacitor unit 1112 to flip to a compensation state according to the first error of each inherent capacitor 111; then keep the compensation capacitor unit 1112 in the compensation state, and obtain the second error of each inherent capacitor 1111 based on the second comparison result of the second capacitor array 112 and the comparator 120; finally, compensate the conversion result of the analog-to-digital converter 100 according to the second error.

[0029] The analog-to-digital converter 100 provided in the embodiment of the present application can calibrate the high-order capacitors in the first capacitor array 111 twice. During the first calibration, the logic control circuit 130 can measure the error of each inherent capacitor 1111 from the P-th capacitor to the N-th capacitor in the first capacitor array 111 based on the first comparison result of the second capacitor array 112 and the comparator 120, and then obtain the first error corresponding to each inherent capacitor 1111; after obtaining the first error corresponding to each inherent capacitor 1111, the logic control circuit 130 can control the capacitor in the compensation capacitor unit 1112 in the same capacitor unit 1110 as the inherent capacitor 1111 to flip according to the first error of each inherent capacitor 1111. In the embodiment of the present application, the state of the capacitor in the compensation capacitor unit 1112 after flipping according to the first error is called the compensation state. When the capacitor in the compensation capacitor unit 1112 is flipped to the compensation state according to the first error, the error generated by the inherent capacitor 1111 in the same capacitor unit 1110 as the compensation capacitor unit 1112 is compensated for for the first time.

[0030] Taking the P-th capacitor as an example, the logic control circuit 130 can measure the error caused by the inherent capacitance in the P-th capacitor based on the first comparison result of the second capacitor array 112 and the comparator 120, and obtain a first error corresponding to the inherent capacitance 1111; then control the capacitance in the compensation capacitor unit 1112 in the P-th capacitor to flip to a compensation state according to the first error. When the capacitance in the compensation capacitor unit 1112 is in the compensation state, the inherent capacitance 1111 in the P-th capacitor is corrected for the first time. At this time, the capacitor unit 1110 composed of the inherent capacitance 1111 and the compensation capacitor unit 1112 is the P-th capacitor after the first correction.

[0031] During the second calibration period, the logic control circuit 130 can keep the compensation capacitor units 1112 in the P-th capacitor to the N-th capacitor of the first capacitor array 111 in their respective compensation states, and at the same time measure the error of each inherent capacitor 1111 in the P-th capacitor to the N-th capacitor of the first capacitor array 111 based on the second comparison result of the second capacitor array 112 and the comparator 120, and then obtain the second error corresponding to each inherent capacitor 1111; after obtaining the second error corresponding to each inherent capacitor 1111, the logic control circuit 130 can compensate for the conversion result of the analog-to-digital converter 100 according to the second error during the conversion stage of the analog-to-digital converter 100. It should be noted that since the second capacitor array 112 itself also has a certain error, the first error of each inherent capacitor 1111 obtained based on the second capacitor array 112 itself also has a certain error. Therefore, during the second calibration period, while keeping each compensation capacitor unit 1112 in its respective compensation state, the second error corresponding to each inherent capacitor 1111 in the P-th capacitor to the N-th capacitor of the first capacitor array 111 obtained based on the second capacitor array 112 is the error remaining after compensating for the first error corresponding to each inherent capacitor 1111 during the first calibration period.

[0032] Similarly, taking the P-th capacitor as an example, assuming that a 20% error will be generated due to the capacitor process deviation, and the P-th capacitor size is 100C, the actual error size of the P-th capacitor is 20C. During the first calibration period, since the second capacitor array 112 itself has a certain error, the first error of the inherent capacitor 1111 in the P-th capacitor obtained by the logic control circuit 130 based on the second capacitor array 112 may be 16C. After the compensation capacitor unit 1112 in the P-th capacitor is flipped according to the first error to compensate for the inherent capacitor 1111, the error remaining during the first calibration period is 4C, and the actual error size of the P-th capacitor also becomes 4C. During the second calibration period, the compensation capacitor unit 1112 is kept in a compensation state, and the second calibration at this time is performed on the basis of the first calibration. It should be noted that since the second capacitor array 112 itself has a certain error, the second error of the inherent capacitor 1111 in the P-th capacitor obtained by the logic control circuit 130 based on the second capacitor array 112 during the second calibration period may be 3.2C. Finally, during the conversion period of the analog-to-digital converter 100, the compensation capacitor unit 1112 is also kept in the compensation state. At this time, after the inherent capacitance 1111 of the P-th capacitor is compensated according to the second error, the actual error of the inherent capacitance 1111 in the P-th capacitor is 0.8C. It can be seen that, compared with the traditional method of only performing a single correction, by correcting the inherent capacitance 1111 in the P-th capacitor twice, the error of the P-th capacitor is reduced from 4C to 0.8C, which effectively reduces the error of the P-th capacitor.

[0033] Therefore, the analog-to-digital converter provided in the embodiment of the present application can calibrate the high-order capacitors in the first capacitor array twice, wherein the second calibration is to compensate for the residual error after the first calibration. Compared with the calibration method of the traditional analog-to-digital converter, the analog-to-digital converter of the embodiment of the present application can effectively reduce the error of the analog-to-digital converter, thereby improving the correction efficiency, and at the same time can effectively improve the accuracy of the analog-to-digital converter.

[0034] Specifically, if Figure 2 As shown, the diagram shows the structural diagram of the analog-to-digital converter 100 provided by the embodiment of the present application. It should be noted that the present application is only illustrated by single-ended structure. In fact, the analog-to-digital converter 100 may not be limited to the single-ended structure, for example, it may also be a differential structure. It is understandable that on the basis of the analog-to-digital converter 100 provided in the present application, there are no substantial improvements that all belong to the scope protected by the present application.

[0035] The capacitor array 110 includes a first capacitor array 111 and a second capacitor array 112. The first capacitor array 111 and the second capacitor array 112 are both connected to the first input terminal of the comparator 120. The second input terminal of the comparator 120 can receive a preset reference voltage. In this embodiment, the preset reference voltage can be a common mode voltage Vcm. As a method, the first capacitor array 111 and the second capacitor array 112 can be connected to the non-inverting input terminal of the comparator 120, and the inverting input terminal of the comparator 120 can be connected to the preset reference voltage.

[0036] The first capacitor array 111 is a main capacitor array, which includes N capacitors, which are Nth capacitor Cn-1, N-1th capacitor Cn-2, ..., first capacitor C0 from high to low, and the capacitance values ​​from the Nth capacitor Cn-1 to the first capacitor C0 can be 2 N-2 C0···2 i-2 C0···2 2 C0,2 1 C0, C0, C0; i is the number of bits of each capacitor in the first capacitor array 111, and i and N are both positive integers. Among them, the P-th capacitor Cp-1 to the N-th capacitor Cn-1 in the first capacitor array 111 are high-bit capacitors, and each capacitor in the P-th capacitor Cp-1 to the N-th capacitor Cn-1 is configured as a capacitor unit; P is a positive integer and P is less than or equal to N. Specifically, the P-th capacitor Cp-1 is a capacitor unit, the P+1-th capacitor Cp is a capacitor unit...the N-th capacitor Cn-1 is a capacitor unit. Figure 3As shown, each capacitor unit 1110 includes an inherent capacitor 1111 and a compensation capacitor unit 1112. Among them, the P-th capacitor Cp-1 includes an inherent capacitor Csp-1 and a compensation capacitor unit Ccp-1... The i-th capacitor Ci includes an inherent capacitor Csi-1 and a compensation capacitor unit Cci-1... The N-th capacitor Cn-1 includes an inherent capacitor Csn-1 and a compensation capacitor unit Ccp-1. It should be noted that, in the P-th capacitor Cp-1 to the N-th capacitor Cn-1, the capacitance value of the inherent capacitor 1111 in each capacitor is used as the capacitance value of the capacitor unit 1110. For example, the capacitance value of the P-th capacitor Cp-1 refers to the capacitance value of the inherent capacitor Csp-1 in the P-th capacitor Cp-1, and the capacitance value of the inherent capacitor Csp-1 is 2 P-2 C0.

[0037] Each compensation capacitor unit 1112 may include K capacitors, which are K-th capacitor Cak-1, K-1-th capacitor Cak-2, ..., first capacitor Ck0, and the capacitance values ​​from the K-th capacitor Cak-1 to the first capacitor Ca0 may be 2 K-2 C0···2 l-2 C0···2 2 C0,2 1 C0, C0, C0; l are the number of bits of each capacitor in the compensation capacitor unit, and i and K are both positive integers. In this embodiment, the number of bits of capacitors in the compensation capacitor unit 1112 of each capacitor in the P-th capacitor Cp-1 to the N-th capacitor Cn-1 of the first capacitor array 111 is the same, that is, the value of K in the compensation capacitor unit 1112 of each capacitor in the P-th capacitor Cp-1 to the N-th capacitor Cn-1 of the first capacitor array 111 is the same, for example, the compensation capacitor unit Ccp-1 in the P-th capacitor Cp-1 may include 9-bit capacitors, and the compensation capacitor unit Ccp in the P+1-th capacitor Cp also includes 9-bit capacitors. In some embodiments, the number of capacitor bits in the compensation capacitor unit 1112 of each capacitor in the P-th capacitor Cp-1 to the N-th capacitor Cn-1 of the first capacitor array 111 may also be different, that is, the value of K in the compensation capacitor unit 1112 of each capacitor in the P-th capacitor Cp-1 to the N-th capacitor Cn-1 of the first capacitor array 111 may be different, for example, the compensation capacitor unit Ccp-1 in the P-th capacitor Cp-1 may include a 9-bit capacitor, and the compensation capacitor unit Ccp in the P+1-th capacitor Cp may include a 10-bit capacitor.

[0038] The second capacitor array 112 is an auxiliary capacitor array, which includes M capacitors, which are the Mth capacitor CAm-1, the M-1th capacitor CAm-2, ..., the first capacitor CA0 from high to low, and the capacitance values ​​from the Mth capacitor CAm-1 to the first capacitor CA0 can be 2 M-2 C0···2 I-2 C0···2 2 C0,2 1 C0, C0, C0; I is the number of bits of each capacitor in the first capacitor array 111, and I and M are both positive integers.

[0039] It is worth noting that, in the present embodiment, the number of capacitors in the second capacitor array 112 is less than or equal to the number of low-order capacitors in the first capacitor array 111, and the number of capacitors in each compensation capacitor unit 1112 is less than or equal to the number of low-order capacitors in the first capacitor array 111, that is, the number of bits of capacitors in the second capacitor array 112 is less than or equal to the number of bits of low-order capacitors in the first capacitor array 111, and the number of bits of capacitors in each compensation capacitor unit 1112 is also less than or equal to the number of bits of low-order capacitors in the first capacitor array 111, that is, M is less than or equal to P-1, and K is less than or equal to P-1. Since the errors generated by the first capacitor C0 to the P-1 capacitor Cp-2 in the first capacitor array 111 are within the error tolerance range, and the P-th capacitor Cp-1 to the N-th capacitor Cn-1 are objects that need to correct errors, the number of bits of capacitors in the second capacitor array 112 and the number of bits of capacitors in each compensation capacitor unit 1112 are set to be less than or equal to the number of bits of low-order capacitors in the first capacitor array 111, which can avoid intolerable errors in the correction process, thereby improving the accuracy of correction. In addition, in this embodiment, the number of capacitors in each compensation capacitor unit 1112 is less than or equal to the number of capacitors in the second capacitor array 112, that is, the number of bits of capacitors in the second capacitor array 112 is greater than or equal to the number of bits of capacitors in each compensation capacitor unit 1112, that is, M is greater than or equal to K. By setting the number of bits of capacitors in the second capacitor array 112 to be greater than or equal to the number of bits of capacitors in each compensation capacitor unit 1112, it can be ensured that the first error of the inherent capacitor 1111 is completely compensated by the compensation capacitor unit 1112 during the correction process.

[0040] Furthermore, if Figure 2 and Figure 3As shown, the first ends of all capacitors in the capacitor array 110 are connected to the first input end of the comparator 120, and the second ends of all capacitors in the capacitor array 110 selectively receive different control signals through a multi-way switch, wherein the first end of the capacitor is the upper plate of the capacitor, and the second end of the capacitor is the lower plate of the capacitor, that is, the upper plates of all capacitors in the capacitor array 110 are connected to the first input end of the comparator 120, and the lower plates of all capacitors in the capacitor array 110 selectively receive different control signals through a multi-way switch. It should be noted that all capacitors in the capacitor array 110 include all low-order capacitors, all high-order capacitors in the first capacitor array 111, and all capacitors in the second capacitor array 112, wherein all high-order capacitors include the inherent capacitors 1111 in each capacitor unit 1110 and all capacitors in the compensation capacitor unit 1112.

[0041] The control signal includes a first control signal, a second control signal and a third control signal. In this embodiment, the first control signal can be a common mode voltage Vcm, the second control signal can be a reference voltage Vref, and the third control signal can be a zero potential voltage Gnd. The logic control circuit 130 can control the on and off of the multi-way switch through a clock to switch the control signal of each capacitor in the capacitor array 110 between the first control signal, the second control signal and the third control signal. The logic control circuit 130 is also connected to the output end of the comparator 120 to receive the output signal of the comparator 120 and control the control signal selected by the multi-way switch accordingly.

[0042] Furthermore, the analog-to-digital converter 100 further includes a sampling switch K1 and a reset switch K2. One end of the sampling switch K1 receives an input signal Vin, and the other end is connected to the first end of each capacitor in the capacitor array 110. When the sampling switch K1 is closed, the capacitor array 110 can sample and convert the input signal Vin. One end of the reset switch K2 is connected to the first end of each capacitor in the capacitor array 110, and the other end is connected to receive a first control signal. When the reset switch K2 is closed, the first end of each capacitor in the capacitor array 110 receives the first control signal.

[0043] In this embodiment, due to the existence of process deviation, the comparator 120 has a mismatch error. In order to ensure the accuracy of the comparison result of the comparator 120 and the accuracy of the correction of the first capacitor array 111, before the first capacitor array 111 is corrected, the logic control circuit 130 can be configured to measure the mismatch error of the comparator 120. Specifically, during the mismatch correction of the comparator 120, the logic control circuit 130 is configured to control all capacitors in the capacitor array 110 to flip to the mismatch correction state, and then control the M-th capacitor CAm-1 to the first capacitor CA0 in the second capacitor array 112 to flip in order from high to low, and after each capacitor flips, the flip direction of the next capacitor is determined according to the mismatch comparison result of the comparator 120, and then the mismatch digital sequence is obtained according to the multiple mismatch comparison results output by the comparator 120. It should be noted that in the embodiment of the present application, capacitor flipping refers to changing the control signal of the lower plate of the capacitor by controlling the multi-way switch.

[0044] In the embodiment of the present application, during the mismatch correction of the comparator 120 and the correction of the first capacitor array 111, the reset switch K2 can be closed to allow the upper plates of all capacitors in the capacitor array 110 to receive the first control signal, wherein the first control signal can be the common mode voltage Vcm.

[0045] Further, the mismatch correction state refers to that the lower plates of all capacitors in the capacitor array 110 receive the first control signal. That is, the logic control circuit 130 controls the lower plates of all capacitors in the capacitor array 110 to receive the common mode voltage Vcm by controlling the multi-way switch. Then, the logic control circuit 130 can control the comparator 120 to compare the signal at the input end of the comparator 120, wherein each mismatch comparison result of the comparator 120 corresponds to a mismatch code value O, and the logic control circuit 130 can control the current position capacitor in the second capacitor array 112 to flip according to the mismatch code value O, and after the current position capacitor is flipped, the comparator 120 performs the next comparison and outputs the next mismatch comparison result. When all the capacitors corresponding to the second capacitor array 112 are flipped, the mismatch digital sequence can be obtained according to the mismatch code value O obtained corresponding to each capacitor in the second capacitor array 112.

[0046] Specifically, when all capacitors in the capacitor array 110 are in a mismatch correction state, the comparator 120 compares the signal at its input end and obtains a mismatch code value O[M-1], which corresponds to the M-th capacitor CAm-1 in the second capacitor array 112. The logic control circuit 130 can control the M-th capacitor CAm-1 in the second capacitor array 112 to flip according to the result of the mismatch code value O[M-1]. For example, if the mismatch code value O[M-1] is 1, the control signal of the lower plate of the M-th capacitor CAm-1 is switched to the third control signal. If the mismatch code value O[M-1] is 0, the control signal of the lower plate of the M-th capacitor CAm-1 is switched to the second control signal. In the embodiment of the present application, the second control signal is the reference voltage Vref, and the third control signal is the zero potential voltage Gnd. Further, the comparator 120 continues to compare the signal at its input end to obtain the mismatch code value O[M-2], which corresponds to the M-1th capacitor CAm-2 in the second capacitor array 112. The logic control circuit 130 can control the flipping of the M-1th capacitor CAm-2 in the second capacitor array 112 according to the result of the mismatch code value O[M-2]. For example, if the mismatch code value O[M-2] is 1, the control signal of the lower plate of the M-1th capacitor CAm-2 is switched to the third control signal. If the mismatch code value O[M-2] is 0, the control signal of the lower plate of the M-1th capacitor CAm-2 is switched to the second control signal. In this way, the comparator 120 compares the signals at its input end in sequence until the first bit capacitor CA0 in the second capacitor array 112 is flipped. At this time, the logic control circuit 130 can obtain the mismatch digital sequence O[M-1:0] according to the mismatch code value O obtained by comparing each bit capacitor in the second capacitor array 112. The mismatch digital sequence O[M-1:0] is the mismatch error of the comparator 120.

[0047] After completing the measurement of the mismatch error of the comparator 120, the logic control circuit 130 can start to calibrate the high-order capacitors in the first capacitor array 111. During the first calibration, the logic control circuit 130 is configured to sequentially obtain the first errors of the inherent capacitors 1111 in the P-th to N-th capacitors in the first capacitor array 111 based on the first comparison results of the second capacitor array 112 and the comparator 120. That is, the calibration starts from the P-th capacitor Cp-1, and is successively corrected to the N-th capacitor Cn-1. Since the comparison result corresponding to the high-order capacitor can be equivalent to the sum of the comparison results corresponding to the low-order capacitor, in this embodiment, the accuracy of the capacitor calibration is ensured by sequentially correcting from the lower-order capacitor to the higher-order capacitor in the P-th to N-th capacitors.

[0048] In this embodiment, during the first calibration of each capacitor in the P-th capacitor Cp-1 to the N-th capacitor Cn-1 of the first capacitor array 111, the logic control circuit 130 is configured to control the flipping of the M-th capacitor to the second capacitor in the second capacitor array 112 in sequence from high to low, and after each capacitor is flipped, determine the flipping direction of the next capacitor according to the first comparison result of the comparator 120, and then obtain a first digital sequence according to multiple first comparison results output by the comparator 120, and the first digital sequence is used to represent the first error.

[0049] In this embodiment, when a certain capacitor among the P-th capacitor Cp-1 to the N-th capacitor Cn-1 is calibrated for the first time, the capacitor can be flipped to a calibration state, wherein the calibration state can be to control the current calibration capacitor to receive a third control signal, and to control the low-order capacitors in the first capacitor array 111 to receive a second control signal, that is, to control the current calibration capacitor to receive a zero potential voltage GND, and to control the low-order capacitors in the first capacitor array 111 to receive a reference voltage Vref. It should be noted that, in the embodiment of the present application, the flipping state of each capacitor among the P-th capacitor Cp-1 to the N-th capacitor Cn-1 refers to the flipping state of the fixed capacitor in the capacitor, for example, controlling the P-th capacitor Cp-1 to receive a first control signal refers to controlling the fixed capacitor Csp-1 in the P-th capacitor Cp-1 to receive the first control signal.

[0050] In one implementation scenario, assuming that the P-th capacitor Cp-1 is calibrated, the P-th capacitor Cp-1 can be flipped to the calibration state. Specifically, the logic control circuit 130 controls the P-th capacitor Cp-1 to receive the third control signal, that is, controls the inherent capacitor Csp-1 in the P-th capacitor Cp-1 to receive the third control signal, and then controls the P-1-th capacitor Cp-2 to the first capacitor C0 in the first capacitor array 111 to receive the second control signal.

[0051] Further, when the current correction capacitor among the P-th capacitor Cp-1 to the N-th capacitor Cn-1 is in the correction state, the logic control circuit 130 can control the comparator 120 to compare the signal at the input end of the comparator 120, wherein each first comparison result of the comparator 120 corresponds to a code value DA, and the logic control circuit 130 can control the current capacitor in the second capacitor array 112 to flip according to the code value DA, and after the current capacitor flips, the comparator 120 performs the next comparison and outputs the next first comparison result. When the M-th capacitor CAm-1 to the second capacitor CA1 in the second capacitor array 112 are flipped, the first digital sequence can be obtained according to the code value DA obtained corresponding to the M-th capacitor CAm-1 to the second capacitor CA1.

[0052] Specifically, when the current correction capacitor among the P-th capacitor Cp-1 to the N-th capacitor Cn-1 is in the correction state, the comparator 120 compares the signal at its input end and obtains the code value DA[M-1], which corresponds to the M-th capacitor CAm-1 in the second capacitor array 112. The logic control circuit 130 can control the flipping of the M-th capacitor CAm-1 in the second capacitor array 112 according to the result of the code value DA[M-1]. For example, if the code value DA[M-1] is 1, the control signal of the lower plate of the M-th capacitor CAm-1 is switched to the third control signal. If the code value DA[M-1] is 0, the control signal of the lower plate of the M-th capacitor CAm-1 is switched to the second control signal. Further, the comparator 120 continues to compare the signal at its input end to obtain a code value DA[M-2], which corresponds to the M-1th capacitor CAm-2 in the second capacitor array 112. The logic control circuit 130 can control the flipping of the M-1th capacitor CAm-2 in the second capacitor array 112 according to the result of the code value DA[M-2]. For example, if the code value DA[M-2] is 1, the control signal of the lower plate of the M-1th capacitor CAm-2 is switched to the third control signal. If the code value DA[M-2] is 0, the control signal of the lower plate of the M-1th capacitor CAm-2 is switched to the second control signal. In this way, the comparator 120 compares the signals at its input end in sequence until the second capacitor CA1 in the second capacitor array 112 is flipped. At this time, the logic control circuit 130 can obtain the first digital sequence DA[M-1:1] according to the code value DA obtained by comparing each bit of capacitance. The first digital sequence DA[M-1:1] is the first error of the current correction capacitor from the P-th capacitor Cp-1 to the N-th capacitor Cn-1, that is, the first error of the inherent capacitance 1111 in the current correction capacitor.

[0053] The logic control circuit 130 can perform a first calibration on the P-th capacitor Cp-1 to the N-th capacitor Cn-1 in the first capacitor array 111 in sequence according to the above process, and obtain a first digital sequence corresponding to each capacitor. The logic control circuit 130 is also configured to control the compensation capacitor unit 1112 corresponding to the inherent capacitor to flip to a compensation state according to the first digital sequence corresponding to each inherent capacitor.

[0054] The first digital sequence includes a plurality of code values, each of which corresponds to a first comparison result of the comparator 120, and each capacitor in the compensation capacitor unit 1112 corresponds to a code value. The logic control circuit 130 controls the capacitor in the compensation capacitor unit 1112 to flip according to the code value corresponding to each capacitor of the compensation capacitor unit in the first digital sequence, so that the compensation capacitor unit 1112 flips to a compensation state.

[0055] Specifically, the logic control circuit 130 switches the control signal of the capacitance of the compensation capacitance unit 1112 in each capacitance according to the first digital sequence DA[M-1:1] corresponding to each capacitance in the P-th capacitance Cp-1 to the N-th capacitance Cn-1, wherein if the code value in the first digital sequence DA[M-1:1] is 1, the control signal corresponding to the capacitance in the compensation capacitance unit 1112 is always switched to be the same as the inherent capacitance 1111; if the code value in the first digital sequence DA[M-1:1] is 0, the control signal corresponding to the capacitance in the compensation capacitance unit 1112 is switched to the first control signal. Taking the P-th capacitor Cp-1 as an example, the logic control circuit 130 can switch the control signal of each capacitor in the compensation circuit array Ccp-1 in the P-th capacitor Cp-1 according to the first digital sequence DA[M-1:1] corresponding to the P-th capacitor Cp-1. If the code value of a certain bit in the first digital sequence DA[M-1:1] is 1, the control signal of the capacitor of the corresponding bit in the compensation capacitor unit Ccp-1 is always switched to be the same as the inherent capacitance Csp-1; if the code value of a certain bit in the first digital sequence DA[M-1:1] is 1, the control signal of the capacitor of the corresponding bit in the compensation capacitor unit Ccp-1 is always switched to the first control signal.

[0056] When the capacitance in the compensation capacitor unit 1112 is flipped, the capacitance in the compensation capacitor unit 1112 is in a compensation state. Further, since the comparator 120 has a mismatch error, in order to ensure the accuracy of the compensation state of the compensation capacitor unit 1112, the logic control circuit 130 can jointly determine the first error of the inherent capacitance according to the first digital sequence and the mismatch digital sequence. That is, the logic control circuit 130 can jointly control the capacitance flipping in the compensation capacitor unit 1112 according to the first digital sequence DA[M-1:1] and the mismatch digital sequence O[M-1:0], and make the capacitance in the compensation capacitor unit 1112 in a compensation state.

[0057] The logic control circuit 130 controls the compensation capacitor unit 1112 of each capacitor from the Pth capacitor Cp-1 to the Nth capacitor Cn-1 in the first capacitor array 111 to be in a compensation state according to the compensation process, thereby completing the first calibration of the high-order capacitors in the first capacitor array 111.

[0058] During the second correction of the high-order capacitors in the first capacitor array 111, the logic control circuit 130 can be configured to keep the capacitors in each compensation capacitor unit 1112 in a compensation state according to the first digital sequence; and control the flipping of the M-th capacitor to the second-order capacitor in the second capacitor array 112 in sequence from high to low, and determine the flipping direction of the next-order capacitor according to the second comparison result of the comparator 120 after each capacitor is flipped, and then obtain the second digital sequence according to multiple second comparison results output by the comparator 120, and the second digital sequence is used to represent the second error.

[0059] In this embodiment, when a certain capacitor among the P-th capacitor Cp-1 to the N-th capacitor Cn-1 is calibrated for the second time, the capacitor can be flipped to the calibration state. The specific process is the same as the first calibration state described above, and will not be repeated. When the current calibration capacitor among the P-th capacitor Cp-1 to the N-th capacitor Cn-1 is in the calibration state, the logic control circuit 130 can control the comparator 120 to compare the signal at the input end of the comparator 120, wherein each second comparison result of the comparator 120 corresponds to a code value Da, and the logic control circuit 130 can control the current capacitor in the second capacitor array 112 to flip according to the code value Da, and after the current capacitor is flipped, the comparator 120 performs the next comparison and outputs the next second comparison result. When the M-th capacitor CAm-1 to the first capacitor CA0 in the second capacitor array 112 are flipped, the second digital sequence can be obtained according to the code value Da obtained corresponding to the M-th capacitor CAm-1 to the first capacitor CA0.

[0060] Specifically, when the current correction capacitor among the P-th capacitor Cp-1 to the N-th capacitor Cn-1 is in the correction state, the comparator 120 compares the signal at its input end and obtains the code value Da[M-1], which corresponds to the M-th capacitor CAm-1 in the second capacitor array 112. The logic control circuit 130 can control the flipping of the M-th capacitor CAm-1 in the second capacitor array 112 according to the result of the code value Da[M-1]. For example, if the code value Da[M-1] is 1, the control signal of the lower plate of the M-th capacitor CAm-1 is switched to the third control signal. If the code value Da[M-1] is 0, the control signal of the lower plate of the M-th capacitor CAm-1 is switched to the second control signal. Further, the comparator 120 continues to compare the signal at its input end to obtain a code value Da[M-2], which corresponds to the M-1th capacitor CAm-2 in the second capacitor array 112. The logic control circuit 130 can control the flipping of the M-1th capacitor CAm-2 in the second capacitor array 112 according to the result of the code value Da[M-2]. For example, if the code value Da[M-2] is 1, the control signal of the lower plate of the M-1th capacitor CAm-2 is switched to the third control signal. If the code value Da[M-2] is 0, the control signal of the lower plate of the M-1th capacitor CAm-2 is switched to the second control signal. In this way, the comparator 120 compares the signals at its input end in sequence until the first capacitor CA0 in the first capacitor array 111 is flipped. At this time, the logic control circuit 130 can obtain the second digital sequence Da[M-1:1] according to the code value Da obtained by comparing each bit of capacitance. The second digital sequence Da[M-1:1] is the residual error of the current correction capacitors in the P-th capacitor Cp-1 to the N-th capacitor Cn-1 after the first correction, that is, the second error of the inherent capacitance 1111 in the current correction capacitors.

[0061] The logic control circuit 130 can perform a second correction on the P-th capacitor Cp-1 to the N-th capacitor Cn-1 in the first capacitor array 111 in sequence according to the above process, and obtain a second error corresponding to each capacitor. After obtaining the second error of each capacitor in the P-th capacitor Cp-1 to the N-th capacitor Cn-1 of the first capacitor array 111, the logic control circuit 130 can compensate for the conversion result of the analog-to-digital converter 100 during the conversion period of the analog-to-digital converter 100, thereby completing the entire correction of the analog-to-digital converter 100.

[0062] When the analog-to-digital converter 100 is in the conversion period, the logic control circuit 130 can control the sampling switch K1 to be closed and the reset switch K2 to be opened. At this time, the upper plates of all capacitors in the capacitor array 110 can sample the external input signal Vin and convert the external input signal Vin in combination with the comparator 120.

[0063] Further, during the conversion period of the analog-to-digital converter 100, the logic control circuit 130 is configured to obtain a compensation value corresponding to each capacitor in the P-th capacitor to the N-th capacitor according to the second error of each capacitor in the P-th capacitor to the N-th capacitor and the corresponding conversion result during the conversion period corresponding to the P-th capacitor to the N-th capacitor; and during the conversion period corresponding to each capacitor, control the flipping of each capacitor in the second capacitor array 112 according to the compensation value of each capacitor.

[0064] The comparator 120 sequentially converts from the high-order capacitor to the low-order capacitor of the first capacitor array 111, that is, converts from the N-th capacitor Cn-1 to the first capacitor C0 of the first capacitor array 111. During the conversion period corresponding to each capacitor in the P-th capacitor to the N-th capacitor, according to the conversion result corresponding to the current capacitor and the second error of the current capacitor, the logic control circuit 130 can calculate the compensation value corresponding to the current capacitor, and control each capacitor in the second capacitor array 112 to flip according to the compensation value corresponding to the current capacitor during the comparison period corresponding to the current capacitor.

[0065] Specifically, the logic control circuit 130 is configured to decode the compensation value of each capacitor into a compensation digital sequence, and control the flipping of each capacitor in the second capacitor array 112 according to the compensation digital sequence. If the compensation value is zero, the lower plate of each capacitor in the second capacitor array 112 can be controlled to receive the first control signal; if the compensation value is positive, the capacitor corresponding to the code value of 1 of the compensation digital sequence in the second capacitor array 112 can be controlled to receive the second control signal, and the capacitor corresponding to the code value of 0 of the compensation digital sequence can receive the first control signal; if the compensation value is negative, the capacitor corresponding to the code value of 1 of the compensation digital sequence in the second capacitor array 112 can be controlled to receive the third control signal, and the capacitor corresponding to the code value of 0 of the compensation digital sequence can receive the first control signal.

[0066] According to the above process, the logic control circuit 130 controls the capacitor flipping in the second capacitor array 112 during the conversion period corresponding to each capacitor in the N-th capacitor Cn-1 to the P-th capacitor Cp-1 of the first capacitor array 111, and then performs a second compensation on the conversion results corresponding to each capacitor in the N-th capacitor Cn-1 to the P-th capacitor Cp-1. The second compensation is essentially a further compensation for the residual error of the first correction.

[0067] Therefore, the analog-to-digital converter 100 provided in the embodiment of the present application performs two corrections, wherein the second correction is a further compensation for the residual error of the first correction, so that the correction efficiency of the analog-to-digital converter 100 is improved, the error of the analog-to-digital converter 100 is greatly reduced, and the conversion accuracy of the analog-to-digital converter 100 is improved.

[0068] The following describes an analog-to-digital converter according to an embodiment of the present application in detail by taking an N-1-bit SAR ADC as an example.

[0069] like Figure 4 and Figure 5 As shown, the N-1-bit SAR ADC is a 13-bit SAR ADC, and the SAR ADC is only exemplified by a single-ended structure. The first capacitor array 111 includes 14-bit capacitors (C0~C13), wherein capacitors C13~capacitor C10 are high-bit capacitors, and capacitors C9~capacitor C0 are low-bit capacitors. In capacitors C13~capacitor C10, each bit of capacitor is a capacitor unit 1110, and includes a fixed capacitor 1111 to compensate for capacitor unit 1112. In this embodiment, the number of capacitors in each compensation capacitor unit 1112 is the same, and each compensation capacitor unit 1112 includes 10-bit capacitors (Ca9~Ca0). In some embodiments, the number of capacitors in each compensation capacitor unit 1112 may be different. The second capacitor array 112 also includes 10-bit capacitors (CA9~CA0). The lower plates of all capacitors in the capacitor array can selectively receive the first control signal Vcm, the second control signal Vref and the third control signal Gnd.

[0070] The analog-to-digital converter 100 may include a comparator 120 mismatch correction phase, a first correction phase, a second correction phase, and a conversion phase.

[0071] Comparator 120 mismatch correction stage: the logic control circuit 130 controls the sampling switch K1 to be disconnected, and controls the reset switch K2 to be closed, so that the upper plates of all capacitors in the capacitor array 110 receive the first control signal Vcm, and at the same time, the logic control circuit 130 controls the lower plates of all capacitors in the capacitor array 110 to also receive the first control signal Vcm for reset.

[0072] The comparator 120 compares the signals at its input end and obtains a mismatch code value O[9], which corresponds to the capacitor CA9 in the second capacitor array 112. If the mismatch code value O[9] is 1, the logic control circuit 130 switches the control signal of the lower plate of the capacitor CA9 to the third control signal Gnd; if the mismatch code value O[9] is 1, the logic control circuit 130 switches the control signal of the lower plate of the capacitor CA9 to the second control signal Vref. The comparator 120 continues to compare the signals at its input end and obtains a mismatch code value O[8], which corresponds to the capacitor CA8 in the second capacitor array 112. If the mismatch code value O[8] is 1, the logic control circuit 130 switches the control signal of the lower plate of the capacitor CA8 to the third control signal Gnd; if the mismatch code value O[8] is 1, the logic control circuit 130 switches the control signal of the lower plate of the capacitor CA8 to the second control signal Vref. Thus, the comparator 120 compares the capacitors CA7-CA0 in the second capacitor array 112, and the logic control circuit 130 also controls the control signal of the lower plate of the capacitors CA7-CA0 according to the mismatch code value O obtained in each comparison. Finally, the logic control circuit 130 obtains the mismatch digital sequence O[9:0].

[0073] First calibration stage: the logic control circuit 130 keeps controlling the sampling switch K1 to be disconnected, and controls the reset switch K2 to be closed, and at the same time controls the lower plates of all capacitors in the capacitor array 110 to receive the first control signal Vcm for reset.

[0074] In the first calibration phase, the capacitors C10 to C13 in the first capacitor array 111 are calibrated in sequence. When calibrating the capacitor C10, the logic control circuit 130 controls the lower plate of the capacitor C10 to receive the third control signal Gnd, that is, controls the lower plate of the inherent capacitor Cs10 in the capacitor C10 to receive the third control signal. Next, the comparator 120 compares the signal at its input end and obtains the code value DA[9], which corresponds to the capacitor CA9 in the second capacitor array 112. If the code value DA[9] is 1, the logic control circuit 130 switches the control signal of the lower plate of the capacitor CA9 to the third control signal Gnd; if the code value DA[9] is 1, the logic control circuit 130 switches the control signal of the lower plate of the capacitor CA9 to the second control signal Vref. The comparator 120 continues to compare the signal at its input end and obtains the code value DA[8], which corresponds to the capacitor CA8 in the second capacitor array 112. If the code value DA[8] is 1, the logic control circuit 130 switches the control signal of the lower plate of the capacitor CA8 to the third control signal Gnd; if the code value DA[8] is 1, the logic control circuit 130 switches the control signal of the lower plate of the capacitor CA8 to the second control signal Vref. In this way, the comparator 120 compares the capacitors CA7-CA1 in the second capacitor array 112, and the logic control circuit 130 also controls the control signal of the lower plate of the capacitors CA7-CA1 according to the code value DA obtained in each comparison. Finally, the logic control circuit 130 obtains the first digital sequence DA[9:1].

[0075] Further, the logic control circuit 130 calculates the first error of the capacitor C10 according to the mismatch digital sequence O[9:0] and the first digital sequence DA[9:1]. Specifically, the first error can be calculated by the following formula:

[0076] DA[9:1]-O[9:0]+10b′1000000000

[0077] Among them, 10b' means 10 bits.

[0078] Further, the calculation result of DA[9:1]-O[9:0]+10b′1000000000 is copied to D C10 and D C10 As the first error. It is worth noting that if the number of bits of DA[9:1] is greater than D C10 The number of bits is then copied to D[9:1]-O[9:0]+10b′1000000000 in sequence. C10 middle.

[0079] The logic control circuit 130 controls the capacitors in the compensation capacitor unit Cc10 in the capacitor C10 to flip according to the first error. For example, the first code value in the first error controls the first capacitor in the compensation capacitor unit Cc10 to flip, and the second code value controls the second capacitor in the compensation capacitor unit Cc10 to flip. If the code value in the first error is 1, the logic control circuit 130 controls the control signal received by the corresponding capacitor in the compensation capacitor Cc10 to always be the same as the control signal received by the inherent capacitor Cs10 in the capacitor C10; if the code value in the first error is 1, the logic control circuit 130 controls the corresponding capacitor in the compensation capacitor Cc10 to always receive the first control signal Vcm. After flipping, each capacitor in the compensation capacitor unit Cc10 is in a compensation state.

[0080] The logic control circuit 130 calibrates the capacitors C11 to C13 in the first capacitor array 111 in sequence according to the above process, and controls the compensation capacitor units of the capacitors C11 to C13 to be in their respective compensation states, and finally obtains the D values ​​of the corresponding capacitors C10 to C13 in sequence. C10 ~D C13 .

[0081] Second calibration stage: the logic control circuit 130 keeps controlling the sampling switch K1 to be disconnected, and controls the reset switch K2 to be closed, and at the same time controls the lower plates of all capacitors in the capacitor array 110 to receive the first control signal Vcm for reset.

[0082] Similarly, in the second calibration phase, calibration is performed sequentially from capacitors C10 to C13 in the first capacitor array 111, while maintaining the compensation capacitor units in each capacitor in a compensation state. When calibrating capacitor C10, the logic control circuit 130 controls the lower plate of capacitor C10 to receive the third control signal Gnd, that is, controls the lower plate of the inherent capacitor Cs10 in capacitor C10 to receive the third control signal. Next, the comparator 120 compares the signal at its input end and obtains a code value DA[9], which corresponds to capacitor CA9 in the second capacitor array 112. If the code value DA[9] is 1, the logic control circuit 130 switches the control signal of the lower plate of capacitor CA9 to the third control signal Gnd; if the code value DA[9] is 1, the logic control circuit 130 switches the control signal of the lower plate of capacitor CA9 to the second control signal Vref. The comparator 120 continues to compare the signal at its input end and obtains a code value DA[8], which corresponds to capacitor CA8 in the second capacitor array 112. If the code value DA[8] is 1, the logic control circuit 130 switches the control signal of the lower plate of the capacitor CA8 to the third control signal Gnd; if the code value DA[8] is 1, the logic control circuit 130 switches the control signal of the lower plate of the capacitor CA8 to the second control signal Vref. In this way, the comparator 120 compares the capacitors CA7-CA0 in the second capacitor array 112, and the logic control circuit 130 also controls the control signal of the lower plate of the capacitors CA7-CA0 according to the code value DA obtained in each comparison. Finally, the logic control circuit 130 obtains the first digital sequence DA[9:0].

[0083] Next, the calculation result of DA[9:0]-O[9:0] is converted to decimal and stored in E10.

[0084] The logic control circuit 130 calibrates the capacitors C11 to C13 in the first capacitor array 111 in sequence according to the above process, and finally obtains E10 to E13 corresponding to the capacitors C10 to C13 in sequence.

[0085] Furthermore, the logic control circuit 130 can calculate the second error of each capacitance according to the following formula.

[0086]

[0087] Wherein, i=(10,11,12,13). The logic control circuit 130 sets EC i As the second error of each capacitor, the EC corresponding to capacitors C10 to C13 is finally obtained. 10 ~EC 13 .

[0088] Conversion stage: the logic control circuit 130 keeps controlling the sampling switch K1 to be closed to sample the external input signal Vin; at the same time, controls the reset switch K2 to be open, and controls the lower plates of all capacitors in the capacitor array 110 to also receive the first control signal Vcm for reset.

[0089] After the sampling is completed, the logic control circuit 130 controls the sampling switch K1 to be turned off. The comparator 120 performs comparisons corresponding to the capacitors C13 to C0 in the first capacitor array 111 in sequence.

[0090] Specifically, the comparator 120 compares the signal at its input end and obtains the code value D

[13] . If the code value D

[13] is 1, the logic control circuit 130 controls the lower plate of the capacitor C13 to receive the third control signal Gnd, that is, controls the lower plate of the inherent capacitor Cs13 in the capacitor C13 to receive the third control signal Gnd; if the code value D

[13] is 0, the logic control circuit 130 controls the lower plate of the capacitor C13 to receive the second control signal Vref, that is, controls the lower plate of the inherent capacitor Cs13 in the capacitor C13 to receive the second control signal Vref. It should be noted that in the conversion stage, each compensation capacitor unit 1112 in the capacitor C13 to the capacitor C10 is maintained in a compensation state.

[0091] Furthermore, the logic control circuit 130 calculates the compensation value corresponding to each capacitor according to the following formula:

[0092] Temp=Temp'+(1-2D[i])*EC i

[0093] Wherein, Temp is the compensation value corresponding to the current capacitance, Temp' is the compensation value corresponding to the previous capacitance, and i=(13, 12, 11, 10).

[0094] The initial value of Temp is zero, so during the switching period corresponding to the capacitor C13, Temp'=0.

[0095] Furthermore, the compensation value Temp corresponding to the capacitor C13 is decoded into an unsigned 9-bit binary code value, and then the capacitors CA9 to CA1 in the second capacitor array 112 are controlled to flip according to the binary code value. Specifically, if the compensation value Temp is 0, the logic control circuit 130 controls the lower plates of the capacitors CA9 to CA1 to receive the first control signal Vcm; if the compensation value Tenp is positive, the logic control circuit 130 controls the lower plates of the capacitors CA9 to CA1 corresponding to the code value 1 in the binary code value to receive the second control signal Vref; if the compensation value Tenp is negative, the logic control circuit 130 controls the lower plates of the capacitors CA9 to CA1 corresponding to the code value 1 in the binary code value to receive the third control signal Gnd.

[0096] The logic control circuit 130 sequentially performs the above process on the current capacitor during the conversion period corresponding to the capacitors C13 to C10. After the conversion corresponding to the capacitor C10 is completed, the compensation value Temp corresponding to the capacitor C10 is kept unchanged, that is, the flip state of the second capacitor array 112 is kept unchanged during the conversion period of the capacitor C10.

[0097] After the comparator 120 completes the conversion corresponding to the capacitors C13 to C10, it sequentially converts the capacitors C9 to C0, and during the conversion corresponding to the capacitors C9 to C0, the second capacitor array 112 is kept in a flipped state corresponding to the compensation value Temp of the capacitor C10. Finally, the logic circuit can obtain the conversion code value D[13:0] corresponding to the capacitors C13 to C0.

[0098] Finally, the logic control circuit 130 calculates the value of D[13:0]-O[9:0], which is the final conversion result of the corrected analog-to-digital converter 100. Therefore, after the first correction and the second correction of the residual error after the first correction, the final conversion result error of the analog-to-digital converter 100 is significantly reduced, and the accuracy of the conversion result is higher.

[0099] The analog-to-digital converter of the embodiment of the present application is provided with a capacitor array, a comparator and a logic control circuit; the capacitor array includes a first capacitor array and a second capacitor array, wherein the first capacitor array includes N-bit capacitors, and the P-th capacitor to the N-th capacitor from low to high are capacitor units, each of the capacitor units includes an inherent capacitor and a compensation capacitor unit, N and P are positive integers respectively, and P≤N; the comparator input terminal is connected to the capacitor array and is configured to compare the input signal of the input terminal; the logic control circuit is connected to the capacitor array and the comparator, and the logic control circuit is configured to obtain a first error of each inherent capacitor in the first capacitor array based on a first comparison result between the second capacitor array and the comparator; control the corresponding compensation capacitor unit to flip to a compensation state according to the first error of each inherent capacitor; keep the compensation capacitor unit in the compensation state, and obtain the second error of each inherent capacitor based on the first comparison result between the second capacitor array and the comparator; compensate according to the conversion result of the second error logarithmic converter. The analog-to-digital converter provided in the embodiment of the present application can perform two corrections on the SAR ADC, wherein the first correction is a first compensation for the first error generated by the analog-to-digital converter, and the second correction is a second compensation for the second error generated in the process of compensating the first error. Through the two corrections, the error generated by the second capacitor array in the correction process can be effectively reduced, thereby improving the correction efficiency of the analog-to-digital converter.

[0100] An embodiment of the present application also provides an integrated circuit, comprising the above-mentioned analog-to-digital converter.

[0101] The integrated circuit provided in the embodiment of the present application can perform two corrections, wherein the first correction is a first compensation for the first error generated by the analog-to-digital converter, and the second correction is a second compensation for the second error generated in the process of compensating the first error. Through the two corrections, the error generated by the second capacitor array in the correction process can be effectively reduced, thereby improving the correction efficiency of the analog-to-digital converter.

[0102] An embodiment of the present application further provides an electronic device, which includes a device body and the above-mentioned integrated circuit, wherein the integrated circuit is disposed in the device body.

[0103] The electronic device provided in the embodiment of the present application can perform two corrections, wherein the first correction is a first compensation for the first error generated by the analog-to-digital converter, and the second correction is a second compensation for the second error generated in the process of compensating the first error. Through the two corrections, the error generated by the second capacitor array in the correction process can be effectively reduced, thereby improving the correction efficiency of the analog-to-digital converter.

[0104] like Figure 6 As shown, the embodiment of the present application also provides a calibration method 200 for an analog-to-digital converter, which is applied to an analog-to-digital converter, such as Figure 1 As shown, the analog-to-digital converter includes a capacitor array 110 and a comparator 120, wherein the capacitor array 110 includes a first capacitor array 111 and a second capacitor array 112, the first capacitor array 111 includes N-bit capacitors, and the P-th capacitor to the N-th capacitor from the low position to the high position are capacitor units 1110, each capacitor unit 1110 includes an inherent capacitor 1111 and a compensation capacitor unit 1112, N and P are positive integers, and P≤N; the input end of the comparator 120 is connected to the capacitor array 110, and is configured to compare the input signal of the input end. In this embodiment, the calibration method 200 of the analog-to-digital converter may include the following steps S210 to S240:

[0105] Step S210: obtaining a first error of each inherent capacitor in the first capacitor array based on a first comparison result between the second capacitor array and the comparator.

[0106] The analog-to-digital converter can calibrate the high-order capacitors in the first capacitor array twice. During the first calibration, the error of each inherent capacitor from the Pth capacitor to the Nth capacitor in the first capacitor array can be measured based on the first comparison result between the second capacitor array and the comparator, thereby obtaining the first error corresponding to each inherent capacitor.

[0107] Step S220: controlling the corresponding compensation capacitor unit to flip to a compensation state according to the first error of each inherent capacitor.

[0108] After obtaining the first error corresponding to each inherent capacitor, the capacitor in the compensation capacitor unit in the same capacitor unit as the inherent capacitor can be controlled to flip according to the first error of each inherent capacitor. In the embodiment of the present application, the state of the capacitor in the compensation capacitor unit after flipping according to the first error is referred to as the compensation state. When the capacitor in the compensation capacitor unit is flipped to the compensation state according to the first error, the error generated by the inherent capacitor in the same capacitor unit as the compensation capacitor unit is compensated for the first time.

[0109] Step S230: maintaining the compensation capacitor unit in a compensation state, and obtaining a second error of each inherent capacitor based on a second comparison result between the second capacitor array and the comparator.

[0110] During the second calibration, the compensation capacitor units from the Pth capacitor to the Nth capacitor in the first capacitor array can be kept in their respective compensation states, and at the same time, the error of each inherent capacitor from the Pth capacitor to the Nth capacitor in the first capacitor array is measured based on the second comparison result between the second capacitor array and the comparator, so as to obtain the second error corresponding to each inherent capacitor.

[0111] Step S240: compensating the conversion result of the analog-to-digital converter according to the second error.

[0112] After obtaining the second error corresponding to each inherent capacitor, the conversion result of the analog-to-digital converter can be compensated according to the second error during the conversion phase of the analog-to-digital converter. It should be noted that since the second capacitor array itself also has a certain error, the first error of each inherent capacitor obtained based on the second capacitor array itself also has a certain error. Therefore, during the second calibration period, while keeping each compensation capacitor unit in its respective compensation state, the second error corresponding to each inherent capacitor from the Pth capacitor to the Nth capacitor of the first capacitor array obtained based on the second capacitor array is the error remaining after compensating for each inherent capacitor according to its first error during the first calibration period.

[0113] The analog-to-digital conversion method provided in this embodiment obtains the first error of each inherent capacitor in the first capacitor array based on the first comparison result of the second capacitor array, and then controls the corresponding compensation capacitor unit to flip to the compensation state according to the first error of each inherent capacitor, and then keeps the compensation capacitor unit in the compensation state, and obtains the second error of each inherent capacitor based on the second comparison result of the second capacitor array and the comparator, and finally compensates the conversion result of the analog-to-digital converter according to the second error, so that two corrections can be performed, wherein the first correction is the first compensation for the first error generated by the analog-to-digital converter, and the second correction is the second compensation for the second error generated in the compensation process of the first error. Through the two corrections, the error generated by the second capacitor array in the correction process can be effectively reduced, thereby improving the correction efficiency of the analog-to-digital converter.

[0114] like Figure 7 As shown, the embodiment of the present application also provides a calibration method 300 for an analog-to-digital converter, which is applied to an analog-to-digital converter, such as Figure 1 As shown, the analog-to-digital converter includes a capacitor array 110 and a comparator 120, wherein the capacitor array 110 includes a first capacitor array 111 and a second capacitor array 112, the first capacitor array 111 includes N-bit capacitors, and the P-th capacitor to the N-th capacitor from the low position to the high position are capacitor units 1110, each capacitor unit 1110 includes an inherent capacitor 111 and a compensation capacitor unit 1112, N and P are positive integers, and P≤N; the input end of the comparator 120 is connected to the capacitor array 111, and is configured to compare the input signal of the input end. In this embodiment, the calibration method 300 of the analog-to-digital converter may include the following steps S301 to S31:

[0115] Step S301: controlling all capacitors in the capacitor array to flip to a mismatch correction state.

[0116] In this embodiment, due to the existence of process deviation, the comparator has a mismatch error. In order to ensure the accuracy of the comparison result of the comparator and the accuracy of the correction of the first capacitor array, the mismatch error of the comparator can be measured before the first capacitor array is corrected. Specifically, during the mismatch correction of the comparator, all capacitors in the capacitor array are controlled to flip to a mismatch correction state.

[0117] The mismatch correction state refers to the lower plates of all capacitors in the capacitor array receiving the first control signal. In this embodiment, the first control signal may be a common mode voltage Vcm. That is, the lower plates of all capacitors in the capacitor array receive the common mode voltage Vcm by controlling the multi-way switch.

[0118] Step S302: in order from high to low, the Mth capacitor to the first capacitor in the second capacitor array are controlled to flip in sequence, and after each capacitor is flipped, the flip direction of the next capacitor is determined according to the mismatch comparison result of the comparator.

[0119] In this embodiment, the comparator can be controlled to compare the signal at the input end of the comparator, wherein each mismatch comparison result of the comparator corresponds to a mismatch code value, and the current capacitor in the second capacitor array is controlled to be flipped according to the mismatch code value, and after the current capacitor is flipped, the comparator performs the next comparison and outputs the next mismatch comparison result, and then continues to control the next capacitor to be flipped according to the mismatch code value corresponding to the next mismatch comparison result of the comparator.

[0120] Step S303: obtaining a mismatch digital sequence according to multiple mismatch comparison results output by the comparator.

[0121] When all the capacitors corresponding to the second capacitor array are flipped, the mismatch digital sequence can be obtained according to the mismatch code value obtained corresponding to each capacitor in the second capacitor array.

[0122] Step S304: in order from high to low, sequentially control the Mth capacitor to the second capacitor in the second capacitor array to flip, and after each capacitor is flipped, determine the flipping direction of the next capacitor according to the first comparison result of the comparator.

[0123] After completing the measurement of the comparator mismatch error, the high-order capacitors in the first capacitor array are corrected. During the first correction period, the first errors of the inherent capacitors in the P-th to N-th capacitors in the first capacitor array are obtained in sequence based on the second capacitor array. That is, the correction starts from the P-th capacitor and is corrected to the N-th capacitor one by one. Since the comparison result corresponding to the high-order capacitor can be equivalent to the sum of the comparison results corresponding to the low-order capacitors, in this embodiment, the accuracy of the capacitor correction can be ensured by successively correcting from the lower-order capacitors to the higher-order capacitors in the P-th to N-th capacitors.

[0124] Furthermore, when a certain capacitor among the P-th capacitor to the N-th capacitor is calibrated for the first time, the capacitor can be flipped to the calibration state. Then, the comparator is controlled to compare the signal at the input end of the comparator, wherein each first comparison result of the comparator corresponds to a code value DA, and the current capacitor in the second capacitor array is controlled to be flipped according to the code value DA, and after the current capacitor is flipped, the comparator performs the next comparison and outputs the next first comparison result, and then continues to control the next capacitor to be flipped according to the code value corresponding to the next first comparison result of the comparator.

[0125] Step S305: obtaining a first digital sequence according to the multiple first comparison results output by the comparator and the mismatch digital sequence.

[0126] After the M-th capacitor to the second capacitor in the second capacitor array are flipped, the first digital sequence can be obtained according to the code value DA obtained corresponding to the M-th capacitor to the second capacitor. The first digital sequence is the first error of the current correction capacitor from the P-th capacitor to the N-th capacitor, that is, the first error of the inherent capacitor in the current correction capacitor.

[0127] According to the above process, the first calibration is performed on the P-th capacitor to the N-th capacitor in the first capacitor array in sequence, and a first digital sequence corresponding to each capacitor is obtained.

[0128] Step S306: According to the first digital sequence corresponding to each inherent capacitor, control the compensation capacitor unit corresponding to the inherent capacitor to flip to a compensation state.

[0129] The control signal for switching the capacitance of the compensation capacitance unit in each capacitance is switched according to a first digital sequence corresponding to each capacitance in the Pth capacitance to the Nth capacitance.

[0130] Furthermore, since the comparator has a mismatch error, in order to ensure the accuracy of the compensation state of the compensation capacitor unit, the capacitor in the compensation capacitor unit is flipped according to the first digital sequence and the mismatch digital sequence, and the capacitor in the compensation capacitor unit is in a compensation state.

[0131] The first digital sequence includes a plurality of code values, each of which corresponds to a second comparison result of the comparator, and each capacitor in the compensation capacitor unit corresponds to a code value. In this embodiment, the capacitor in the compensation capacitor unit can be controlled to flip according to the code value corresponding to each capacitor of the compensation capacitor unit in the first digital sequence, so that the compensation capacitor unit flips to a compensation state.

[0132] According to the above process, the compensation capacitor unit of each capacitor from the Pth capacitor to the Nth capacitor in the first capacitor array is controlled to be in a compensation state, thereby completing the first correction of the high-position capacitor in the first capacitor array.

[0133] Step S307: maintaining the capacitance in each of the compensation capacitance units in a compensation state according to the first digital sequence.

[0134] During the second calibration of the high-order capacitors in the first capacitor array, the capacitors in each compensation capacitor unit are kept in a compensation state according to the first digital sequence.

[0135] Step S308: in order from high to low, sequentially control the Mth capacitor to the second capacitor in the second capacitor array to flip, and after each capacitor is flipped, determine the flipping direction of the next capacitor according to the second comparison result of the comparator.

[0136] When a certain capacitor among the P-th capacitor to the N-th capacitor is calibrated for the second time, the capacitor can be flipped to the calibration state. Then, when the current calibration capacitor among the P-th capacitor to the N-th capacitor is in the calibration state, the comparator is controlled to compare the signal at the input end of the comparator, wherein each second comparison result of the comparator corresponds to a code value Da, and the current capacitor in the second capacitor array is controlled to flip according to the code value Da, and after the current capacitor is flipped, the comparator performs the next comparison and outputs the next second comparison result, and then continues to control the next capacitor to flip according to the code value corresponding to the next second comparison result of the comparator.

[0137] Step S309: obtaining a second digital sequence according to multiple second comparison results output by the comparator.

[0138] When the M-th capacitor to the first capacitor in the second capacitor array are flipped, the second digital sequence can be obtained according to the code value Da obtained corresponding to the M-th capacitor to the first capacitor. The second digital sequence is the residual error of the current correction capacitor in the P-th capacitor to the N-th capacitor after the first correction, that is, the second error of the inherent capacitance in the current correction capacitor.

[0139] Step S310: during the conversion period corresponding to the Pth capacitor to the Nth capacitor, a compensation value corresponding to each capacitor among the Pth capacitor to the Nth capacitor is obtained according to the second error corresponding to each capacitor among the Pth capacitor to the Nth capacitor and the corresponding conversion result.

[0140] During the conversion period of the analog-to-digital converter, the comparator sequentially converts from the high-order capacitor to the low-order capacitor of the first capacitor array, that is, converts from the Nth capacitor to the first capacitor C0 of the first capacitor array.

[0141] During the conversion period corresponding to each capacitance from the P-th capacitance to the N-th capacitance, a compensation value corresponding to the current capacitance is calculated according to the conversion result corresponding to the current capacitance and the second error of the current capacitance.

[0142] Step S311: Decode the compensation value of each bit of capacitance into a compensation digital sequence.

[0143] Step S312: controlling each capacitor in the second capacitor array to flip according to the compensation digital sequence.

[0144] Among them, if the compensation value is zero, the lower plate of each capacitor in the second capacitor array can be controlled to receive the first control signal; if the compensation value is positive, the capacitor corresponding to the code value of 1 in the compensation digital sequence in the second capacitor array can be controlled to receive the second control signal, and the capacitor corresponding to the code value of 0 in the compensation digital sequence can receive the first control signal; if the compensation value is negative, the capacitor corresponding to the code value of 1 in the second capacitor array can be controlled to receive the third control signal, and the capacitor corresponding to the code value of 0 in the compensation digital sequence can receive the first control signal.

[0145] Therefore, the analog-to-digital converter provided in the embodiment of the present application performs two corrections, wherein the second correction is a further compensation for the residual error of the first correction, so that the correction efficiency of the analog-to-digital converter is improved, the error of the analog-to-digital converter is greatly reduced, and the conversion accuracy of the analog-to-digital converter is improved.

[0146] The correction method of the analog-to-digital converter provided in the embodiment of the present application obtains the first error of each inherent capacitor in the first capacitor array based on the first comparison result of the second capacitor array, controls the corresponding compensation capacitor unit to flip to the compensation state according to the first error of each inherent capacitor, and then keeps the compensation capacitor unit in the compensation state, and obtains the second error of each inherent capacitor based on the second comparison result of the second capacitor array and the comparator, and finally compensates the conversion result of the analog-to-digital converter according to the second error, so that two corrections can be performed, wherein the first correction is the first compensation for the first error generated by the analog-to-digital converter, and the second correction is the second compensation for the second error generated in the compensation process of the first error. Through the two corrections, the error generated by the second capacitor array in the correction process can be effectively reduced, thereby improving the correction efficiency of the analog-to-digital converter.

[0147] The above are only preferred embodiments of the present application and are not intended to limit the present application in any form. Although the present application has been disclosed as a preferred embodiment as above, it is not intended to limit the present application. Any technical personnel in this field can make some changes or modifications to equivalent embodiments based on the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An analog-to-digital converter, characterized in that: include: A capacitor array, comprising a first capacitor array and a second capacitor array, wherein the first capacitor array comprises N capacitors, and the Pth capacitor to the Nth capacitor from the lowest to the highest are capacitor units, each of the capacitor units comprises an inherent capacitor and a compensation capacitor unit, N and P are positive integers respectively, and P≤N; A comparator, at least one input terminal of which is connected to the capacitor array; as well as A logic control circuit is connected to the capacitor array and the comparator, and the logic control circuit is configured as follows: Based on a first comparison result between the second capacitor array and the comparator, obtaining a first error of each inherent capacitor in the first capacitor array; According to the first error of each of the inherent capacitors, the corresponding compensation capacitor unit is controlled to flip to a compensation state, thereby achieving a first correction of the inherent capacitor; Maintaining the compensation capacitor unit in the compensation state, and obtaining a second error of each of the inherent capacitors based on a second comparison result between the second capacitor array and the comparator; wherein the second error is a residual error after compensating for the first error corresponding to each of the inherent capacitors during the first calibration period; The conversion result of the analog-to-digital converter is compensated according to the second error, thereby achieving a second correction of the inherent capacitance.

2. The analog-to-digital converter according to claim 1, wherein: During the period when the logic control circuit obtains the first error of each of the inherent capacitors in the first capacitor array based on the first comparison result of the second capacitor array and the comparator, the logic control circuit sequentially obtains the first errors of the inherent capacitors in the Pth to Nth capacitors in the first capacitor array based on the first comparison result of the second capacitor array and the comparator.

3. The analog-to-digital converter according to claim 1, wherein: The second capacitor array includes M capacitors, where M is a positive integer; during the period in which the logic control circuit obtains the first error of each inherent capacitor in the first capacitor array based on the first comparison result between the second capacitor array and the comparator, the logic control circuit is configured as follows: In order from high to low, sequentially control the Mth capacitor to the second capacitor in the second capacitor array to flip, and after each capacitor is flipped, determine the flip direction of the next capacitor according to the first comparison result of the comparator; as well as A first digital sequence is obtained according to multiple first comparison results output by the comparator, and the first digital sequence is used to represent the first error of the corresponding inherent capacitance; wherein the comparator outputs a first comparison result after each capacitance flip.

4. The analog-to-digital converter according to claim 3, wherein: During the period when the corresponding compensation capacitor unit is controlled to flip to the compensation state according to the first error of each inherent capacitor, the logic control circuit is configured to: control the compensation capacitor unit corresponding to the inherent capacitor to flip to the compensation state according to the first digital sequence corresponding to each inherent capacitor.

5. The analog-to-digital converter according to claim 4, characterized in that The first digital sequence includes multiple code values, each code value corresponds to a first comparison result of the comparator; the compensation capacitor unit includes at least one capacitor, and each capacitor in the compensation capacitor unit corresponds to a code value in the first digital sequence; the logic control circuit controls the compensation capacitor unit corresponding to the inherent capacitor to flip to a compensation state according to the first digital sequence corresponding to each inherent capacitor, and is configured to: control the capacitor in the compensation capacitor unit to flip according to the code value of each capacitor corresponding to the compensation capacitor unit in the first digital sequence, so that the compensation capacitor unit flips to the compensation state.

6. The analog-to-digital converter according to claim 5, characterized in that The logic control circuit is configured to: keep the capacitance in the compensation capacitance unit in the compensation state and obtain the second error of each inherent capacitance based on the second comparison result between the second capacitance array and the comparator as follows: Keeping the capacitance in each of the compensation capacitance units in the compensation state according to the first digital sequence; In order from high to low, sequentially control the M-th capacitor to the second capacitor in the second capacitor array to flip, and after each capacitor is flipped, determine the flip direction of the next capacitor according to the second comparison result of the comparator; as well as A second digital sequence is obtained according to multiple second comparison results output by the comparator, and the second digital sequence is used to represent the second error of the corresponding inherent capacitance; wherein the comparator outputs a second comparison result after each capacitance flip.

7. The analog-to-digital converter according to claim 1, wherein: During the period of compensating the conversion result of the analog-to-digital converter according to the second error, the logic control circuit is configured as follows: During the conversion period corresponding to the P-th capacitor to the N-th capacitor, a compensation value corresponding to each capacitor from the P-th capacitor to the N-th capacitor is obtained according to the second error of each capacitor from the P-th capacitor to the N-th capacitor and the corresponding conversion result; as well as During the conversion period corresponding to each bit of capacitance, each bit of capacitance in the second capacitance array is controlled to be flipped according to the compensation value of each bit of capacitance.

8. The analog-to-digital converter according to claim 7, characterized in that During the period of controlling the flipping of each capacitor in the second capacitor array according to the compensation value of each capacitor, the logic control circuit is configured as follows: Decoding the compensation value of each capacitor into a compensation digital sequence; as well as According to the compensation digital sequence, each capacitor in the second capacitor array is controlled to flip.

9. The analog-to-digital converter according to claim 3, wherein: Before obtaining the first error of each inherent capacitor in the first capacitor array based on the first comparison result between the second capacitor array and the comparator, the logic control circuit is further configured as follows: Controlling all capacitors in the capacitor array to flip to a mismatch correction state; In order from high to low, sequentially control the Mth capacitor to the first capacitor in the second capacitor array to flip, and after each capacitor is flipped, determine the flip direction of the next capacitor according to the mismatch comparison result of the comparator; as well as Obtaining a mismatch digital sequence according to multiple mismatch comparison results output by the comparator, wherein the comparator outputs a mismatch comparison result after each capacitance flip; During the process of obtaining the first digital sequence based on multiple mismatch comparison results output by the comparator, the logic control circuit is configured to obtain the first digital sequence based on multiple mismatch comparison results output by the comparator and the mismatch digital sequence.

10. The analog-to-digital converter according to any one of claims 1 to 9, characterized in that: The capacitor units in the first capacitor array are high-position capacitors, and the other capacitors in the first capacitor array except the capacitor units are low-position capacitors; the number of capacitors in the second capacitor array is less than or equal to the number of low-position capacitors in the first capacitor array.

11. The analog-to-digital converter according to any one of claims 1 to 9, characterized in that: The number of capacitors in each of the compensation capacitor units is less than or equal to the number of capacitors in the second capacitor array.

12. An integrated circuit, characterized in that: The analog-to-digital converter comprises any one of claims 1 to 11.

13. An electronic device, characterized in that: The device comprises a device body and the integrated circuit as claimed in claim 12.

14. A calibration method for an analog-to-digital converter, characterized in that: Applied to an analog-to-digital converter, the analog-to-digital converter includes a capacitor array and a comparator, wherein the capacitor array includes a first capacitor array and a second capacitor array, the first capacitor array includes N-bit capacitors, and the P-th capacitor to the N-th capacitor from the lowest to the highest are capacitor units, each of the capacitor units includes an inherent capacitor and a compensation capacitor unit, N and P are positive integers respectively, and P≤N; At least one input terminal of the comparator is connected to the capacitor array; the method comprises: Based on a first comparison result between the second capacitor array and the comparator, obtaining a first error of each inherent capacitor in the first capacitor array; According to the first error of each of the inherent capacitors, the corresponding compensation capacitor unit is controlled to flip to a compensation state, thereby achieving a first correction of the inherent capacitor; Maintaining the compensation capacitor unit in the compensation state, and obtaining a second error of each of the inherent capacitors based on a second comparison result between the second capacitor array and the comparator; wherein the second error is a residual error after compensating for the first error corresponding to each of the inherent capacitors during the first calibration period; and The conversion result of the analog-to-digital converter is compensated according to the second error, thereby achieving a second correction of the inherent capacitance.

15. The calibration method of the analog-to-digital converter according to claim 14, characterized in that: The method of obtaining a first error of each inherent capacitor in the first capacitor array based on a first comparison result between the second capacitor array and the comparator includes: obtaining first errors of the inherent capacitors in the Pth to Nth capacitors in the first capacitor array in sequence based on the first comparison result between the second capacitor array and the comparator.

16. The calibration method of the analog-to-digital converter according to claim 14, characterized in that: The second capacitor array includes M capacitors, where M is a positive integer; and obtaining a first error of each inherent capacitor in the first capacitor array based on a first comparison result between the second capacitor array and the comparator includes: In order from high to low, sequentially control the M-th capacitor to the second capacitor in the second capacitor array to flip, and after each capacitor is flipped, determine the flip direction of the next capacitor according to the first comparison result of the comparator; and A first digital sequence is obtained according to multiple first comparison results output by the comparator, and the first digital sequence is used to represent the first error of the corresponding inherent capacitance; wherein the comparator outputs a first comparison result after each capacitance flip.

17. The calibration method of the analog-to-digital converter according to claim 16, characterized in that: Controlling the corresponding compensation capacitor unit to flip to a compensation state according to the first error of each inherent capacitor includes: controlling the compensation capacitor unit corresponding to the inherent capacitor to flip to a compensation state according to the first digital sequence corresponding to each inherent capacitor.

18. The calibration method of the analog-to-digital converter according to claim 17, characterized in that: The first digital sequence includes a plurality of code values, each code value corresponds to a first comparison result of the comparator; the compensation capacitor unit includes at least one compensation capacitor, each of the compensation capacitors corresponds to a code value in the first digital sequence; The method of controlling the compensation capacitor unit corresponding to each inherent capacitor to flip to a compensation state according to the first digital sequence corresponding to the inherent capacitor includes: controlling each compensation capacitor to flip according to a code value corresponding to each compensation capacitor in the first digital sequence, so that the compensation capacitor unit flips to the compensation state.

19. The calibration method of the analog-to-digital converter according to claim 17, characterized in that: The maintaining the compensation capacitor unit in the compensation state and obtaining a second error of each inherent capacitor based on a second comparison result between the second capacitor array and the comparator includes: Keeping the compensation capacitor in each of the compensation capacitor units in the compensation state according to the first digital sequence; In order from high to low, sequentially control the M-th capacitor to the second capacitor in the second capacitor array to flip, and after each capacitor is flipped, determine the flip direction of the next capacitor according to the second comparison result of the comparator; and A second digital sequence is obtained according to multiple second comparison results output by the comparator, and the second digital sequence is used to represent the second error of the corresponding inherent capacitance; wherein the comparator outputs a second comparison result after each capacitance flip.

20. The calibration method of an analog-to-digital converter according to claim 14, characterized in that: The compensating the conversion result of the analog-to-digital converter according to the second error includes: During the conversion period corresponding to the P-th capacitor to the N-th capacitor, a compensation value corresponding to each capacitor in the P-th capacitor to the N-th capacitor is obtained according to a second error corresponding to each capacitor in the P-th capacitor to the N-th capacitor and a corresponding conversion result; and During the conversion period corresponding to each bit of capacitance, each bit of capacitance in the second capacitance array is controlled to be flipped according to the compensation value of each bit of capacitance.

21. The calibration method of an analog-to-digital converter according to claim 20, characterized in that: The method of controlling the flipping of each capacitor in the second capacitor array according to the compensation value of each capacitor comprises: Decoding the compensation value of each capacitor into a compensation digital sequence; and According to the compensation digital sequence, each capacitor in the second capacitor array is controlled to flip.

22. The calibration method of an analog-to-digital converter according to claim 14, characterized in that: Before obtaining the first error of each inherent capacitor in the first capacitor array based on the first comparison result between the second capacitor array and the comparator, the method further includes: In order from high to low, sequentially control the Mth capacitor to the first capacitor in the second capacitor array to flip, and after each capacitor is flipped, determine the flip direction of the next capacitor according to the mismatch comparison result of the comparator; and Obtaining a mismatch digital sequence according to multiple mismatch comparison results output by the comparator, wherein the comparator outputs a mismatch comparison result after each capacitance flip; During the process of obtaining the first digital sequence based on multiple mismatch comparison results output by the comparator, the method is configured to obtain the first digital sequence based on the multiple mismatch comparison results output by the comparator and the mismatch digital sequence.

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