A three-dimensional ferroelectric memory, its fabrication method, and an electronic device.

Abstract

This application provides a method for fabricating a three-dimensional ferroelectric memory (FEM), which can ensure good durability of the FEM while reducing the etching difficulty during the fabrication process. The method includes: forming a stacked layer on a substrate, the stacked layer including stacked and alternately arranged isolation layers and sacrificial layers; forming multiple rows of first voltage lines in the stacked layer, and forming isolation grooves between any two adjacent rows of first voltage lines; etching away the sacrificial layer in the stacked layer, and forming a metal layer stacked and alternately arranged with the isolation layers to obtain a memory layer, the metal layer including a ferroelectric layer and multiple second voltage lines, the ferroelectric layer surrounding the portions of the multiple second voltage lines and the multiple rows of first voltage lines located in the metal layer, thereby forming an MFM structure in the metal layer, ensuring the durability of the three-dimensional ferroelectric memory. Simultaneously, since the sacrificial layer is a readily corroded material, the etching difficulty during the fabrication process can be reduced.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a three-dimensional ferroelectric memory, its fabrication method, and an electronic device. Background Technology

[0002] With the development of electronic technology, data storage technology has rapidly improved. Among these advancements, memory fabricated using ferroelectric materials whose polarization direction changes under an electric field is called Ferroelectric Random Access Memory (FRAM), or simply "ferroelectric memory." The memory cells in a ferroelectric memory can include ferroelectric field-effect transistors (FeFETs) based on a metal-ferroelectric layer-insulator-semiconductor (MFIS) structure, and ferroelectric capacitors based on a metal-ferroelectric layer-metal (MFM) structure. Compared to MFIS structures, MFM structures offer better durability and are therefore widely used in 1T-1C (one transistor-one capacitor) architecture FRAMs.

[0003] In related technologies, a method for fabricating a three-dimensional ferroelectric memory based on the working principle of an MFM-structured ferroelectric diode (Fe-diode) is provided. The specific method involves: preparing SiO₂... x In a multilayer stacked structure of TiN, the TiN metal layer serves as the word line (WL). Deep-hole etching (DIE) is used to vertically etch an array of deep holes through the stacked structure, exposing the WL sidewalls. A ferroelectric layer is then deposited on the sidewalls of these deep holes as the storage medium, and a TiN / W bilayer metal layer is deposited as the bit line (BL), forming the MFM (Multilayer Ferroelectric Membrane) memory cell. However, in this technology, the deep-hole etching of the multilayer metal becomes increasingly difficult as the number of stacked layers increases. Therefore, this method for fabricating three-dimensional ferroelectric memories has high process requirements. Summary of the Invention

[0004] This application provides a three-dimensional ferroelectric memory, a fabrication method, and an electronic device, which reduces the etching difficulty during the fabrication process of the three-dimensional ferroelectric memory while ensuring its durability.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] Firstly, a method for fabricating a three-dimensional ferroelectric memory is provided. The method includes: forming a stacked layer on a substrate, where the substrate can be a silicon wafer, die, or silicon integrated circuit, etc. The stacked layer includes stacked and alternately arranged isolation layers and sacrificial layers. The isolation layer can be an electrically insulating material and is used to isolate two adjacent sacrificial layers. The sacrificial layer can be a layer that will be subsequently removed or sacrificed, and the sacrificial layer is made of an easily corroded material, such as silicon nitride (SiN). x The stacked layer comprises multiple rows of first voltage lines extending along the depth direction of the stacked layer (for example, one end of the multiple rows of first voltage lines is located on the surface of the stacked layer away from the substrate, and the other end is located on the surface of the stacked layer close to the substrate). The first voltage lines can be bit lines. An isolation groove penetrating the stacked layer is formed between any two adjacent rows of first voltage lines, that is, the isolation groove physically isolates the two adjacent rows of first voltage lines. The sacrificial layer in the stacked layer is etched away to obtain a first frame, that is, the first frame includes multiple layers of spaced isolation layers and multiple rows of first voltage lines, and the multiple rows of first voltage lines are fixed on the isolation layers. A metal layer is formed in the first frame, stacked and alternately arranged with the isolation layers, to obtain a storage layer. The metal layer includes a ferroelectric layer (also called a ferroelectric thin film) and multiple second voltage lines. The ferroelectric layer surrounds the multiple second voltage lines and the portion of the multiple rows of first voltage lines located in the metal layer, so that the first voltage lines, the ferroelectric layer and the second voltage lines form a metal-ferroelectric layer-metal MFM structure in the metal layer. The second voltage lines can be word lines.

[0007] In the above technical solution, the stacked layer includes stacked and alternately arranged isolation layers and sacrificial layers. Since the sacrificial layer is an easily corroded material, multiple rows of first voltage lines and isolation grooves are set on the stacked layer. When the sacrificial layer is etched away, the etching difficulty of the first voltage lines and isolation grooves using etching processes can be greatly reduced. In addition, in the final memory layer, the metal layer and isolation layer are stacked and alternately arranged, and the first voltage line, ferroelectric layer and second voltage line in the metal layer form a memory cell with an MFM structure. Since the memory cell with an MFM structure can be equivalent to a ferroelectric diode, compared with the ferroelectric field-effect transistor equivalent to the memory cell with an MFIS structure, the structure is simple and there is no ferroelectric layer-insulator interface that easily traps charges, so the interface defects are small, thereby ensuring that the three-dimensional ferroelectric memory has good durability.

[0008] In one possible implementation of the first aspect, multiple rows of first voltage lines are formed in the stacked layer, including: forming multiple rows of vias in the stacked layer, for example, forming multiple rows of vias in the stacked layer using a deep etching process, wherein the multiple rows of vias extend along the depth direction of the stacked layer, for example, one end of the multiple rows of vias is located on the surface of the storage layer away from the substrate, and the other end of the multiple rows of vias extends along the depth direction of the stacked layer; filling the multiple rows of vias with first voltage lines to obtain multiple rows of first voltage lines, for example, growing conductive material on the sidewalls of the multiple rows of vias using a deposition method until the conductive material completely fills the multiple rows of vias. In the above possible implementation, since the sacrificial layer is easily etchable SiN... x The materials used reduce the etching difficulty of multi-row vias compared to metal etching in existing technologies; furthermore, the etching difficulty is further reduced as the number of stacked layers increases.

[0009] In one possible implementation of the first aspect, a storage layer is obtained by forming metal layers stacked and alternately arranged with the isolation layers in a first frame, comprising: growing a ferroelectric material on the surface of the first frame, the thickness of the ferroelectric material being less than a first distance, the first distance being the distance between two adjacent isolation layers in the first frame; growing a conductive material on the surface of the ferroelectric material, the sum of the thickness of the conductive material and the thickness of the ferroelectric material being greater than or equal to the distance between two adjacent isolation layers to obtain a storage layer substrate, wherein the ferroelectric material between two adjacent isolation layers in the storage layer substrate forms a ferroelectric layer, and the conductive material between two adjacent isolation layers forms a plurality of second voltage lines, the ferroelectric layer and the plurality of second voltage lines forming a metal layer; and removing the ferroelectric material and conductive material from the surface of the storage layer substrate, for example, removing the ferroelectric material and conductive material from the sides of the storage layer substrate (e.g., around the perimeter of the storage layer substrate) and the surface away from the substrate (e.g., the upper surface of the storage layer substrate and within the isolation grooves) to obtain a storage layer, the storage layer comprising stacked and alternately arranged isolation layers and metal layers. In the above possible implementations, since the sacrificial layer is a corrosive material, etching away the sacrificial layer and forming a metal layer can greatly reduce the etching difficulty.

[0010] In one possible implementation of the first aspect, any two adjacent columns of first voltage lines are arranged at intervals. In the above possible implementation, when any two adjacent columns of first voltage lines are arranged at intervals, multiple first voltage lines belonging to the same column can be located in the same region, and first voltage lines belonging to different columns can be located in different regions, thereby facilitating the setting of isolation grooves between adjacent columns of first voltage lines.

[0011] In one possible implementation of the first aspect, the method further includes: filling the isolation groove with an electrically insulating material; optionally, the electrically insulating material includes: silicon oxide (SiO2). xIn the above possible implementations, by filling the isolation groove with electrical insulating material, the two adjacent columns of first voltage lines can be isolated by the electrical insulating material, thereby avoiding interference between the two adjacent columns of first voltage lines.

[0012] In one possible implementation of the first aspect, the axial margin of the portion of the first voltage line located in the metal layer is greater than the axial margin of the portion of the first voltage line located in the isolation layer. For example, if the cross-section of the first voltage line is circular, then the radius of the portion of the first voltage line located in the metal layer is greater than the radius of the portion of the first voltage line located in the isolation layer. In the above possible implementations, the memory cell of the MFM structure formed by the first voltage line, the ferroelectric layer, and the second voltage line in the metal layer can have better performance, thereby further improving the performance of the three-dimensional ferroelectric memory.

[0013] In one possible implementation of the first aspect, the first voltage line or the second voltage line comprises at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO) x The possible implementations described above include TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and compounds of silicon and metals. These implementations enhance the flexibility and versatility of the first or second voltage line.

[0014] In one possible implementation of the first aspect, the ferroelectric layer comprises at least one of the following materials: hafnium dioxide (HfO2), doped HfO2, lead zirconium titanate (PbZrTiO3), doped PbZrTiO3, strontium bismuth tantalate (SrBi2Ta2O9), doped SrBi2Ta2O9, lithium niobate (LiNbO3), doped LiNbO3, lithium tantalate (LiTaO3), doped Li TaO3, bismuth ferrite (BiFeO3), doped BiFeO3, barium titanate (BaTiO3), doped BaTiO3; optionally, the dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La); for example, doped HfO2 can be HfO2 doped with at least one of Si, Zr, Y, Al, Gd, S, and La. The above possible implementations can improve the flexibility and diversity of the ferroelectric layer.

[0015] In one possible implementation of the first aspect, the first voltage line is a bit line and the second voltage line is a word line. This possible implementation reduces the etching difficulty during the formation of the bit line and the word line.

[0016] In one possible implementation of the first aspect, the first voltage line is perpendicular to the second voltage line.

[0017] In one possible implementation of the first aspect, each column of first voltage lines in the plurality of columns of first voltage lines includes a plurality of first voltage lines, and the method further includes: forming an electrical connection layer on the storage layer, the electrical connection layer being located on the side of the storage layer away from the substrate, wherein the plurality of first voltage lines are electrically connected in the electrical connection layer.

[0018] Secondly, a three-dimensional ferroelectric memory is provided, comprising: a substrate, wherein the substrate may be a silicon wafer, die, or silicon integrated circuit, etc.; a memory layer located on the substrate, wherein the memory layer has multiple rows of first voltage lines and isolation grooves located between any two adjacent rows of first voltage lines, the multiple rows of first voltage lines extending along the depth direction of the memory layer (for example, one end of the multiple rows of first voltage lines is located on the surface of the memory layer away from the substrate, and the other end of the multiple rows of first voltage lines is located on the surface of the memory layer close to the substrate), and the isolation grooves penetrating the memory layer; wherein the memory layer includes stacked and alternately arranged isolation layers and metal layers, the isolation layers may be electrically insulating materials and used to isolate two adjacent metal layers, the metal layers have ferroelectric layers and multiple second voltage lines disposed therein, the ferroelectric layers surrounding the multiple second voltage lines and the portions of the multiple rows of first voltage lines located in the metal layer, so that the first voltage lines, the ferroelectric layers and the second metal lines form a metal-ferroelectric layer-metal MFM structure in the metal layer, that is, the first voltage lines, the ferroelectric layers and the second voltage lines form a memory cell with an MFM structure.

[0019] In the above technical solution, the storage layer of the three-dimensional ferroelectric memory has a stacked and alternately arranged metal layer and isolation layer. The first voltage line, ferroelectric layer and second voltage line in the metal layer form a storage cell with an MFM structure. Since the storage cell of the MFM structure can be equivalent to a ferroelectric diode, compared with the ferroelectric field-effect transistor equivalent of the storage cell of the MFIS structure, the structure is simple and there is no ferroelectric layer-insulator interface that easily traps charges, resulting in small interface defects and thus ensuring that the three-dimensional ferroelectric memory has good durability. In addition, the metal layer in the three-dimensional ferroelectric memory includes a ferroelectric layer and multiple second voltage lines, and the ferroelectric layer surrounds the multiple second voltage lines and the portions of the multiple columns of first voltage lines located in the metal layer. This is because the ferroelectric layer is formed during the process of etching away the sacrificial layer in the stacked structure of isolation layer and sacrificial layer and forming the metal layer. This can greatly reduce the etching difficulty of the first voltage line and isolation groove, and at the same time ensure the quality of ferroelectric layer growth, thereby ensuring the good performance of the storage cell and the three-dimensional ferroelectric memory.

[0020] In one possible implementation of the second aspect, any two adjacent columns of first voltage lines are arranged at intervals, that is, multiple first voltage lines belonging to the same column are located in the same area, and first voltage lines belonging to different columns are located in different areas, thereby facilitating the setting of isolation grooves between two adjacent columns of first voltage lines.

[0021] In one possible implementation of the second aspect, the isolation groove is filled with an electrically insulating material; optionally, the electrically insulating material includes silicon oxide (SiO2). x In the above possible implementations, by filling the isolation groove with electrical insulating material, adjacent columns of first voltage lines can be isolated by the electrical insulating material, thereby avoiding interference between adjacent columns of first voltage lines.

[0022] In one possible implementation of the second aspect, the axial distance of the portion of the first voltage line located in the metal layer is greater than the axial distance of the portion of the first voltage line located in the isolation layer. For example, if the cross-section of the first voltage line is circular, then the radius of the portion of the first voltage line located in the metal layer is greater than the radius of the portion of the first voltage line located in the isolation layer.

[0023] In one possible implementation of the second aspect, the first voltage line or the second voltage line comprises at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO) x ), TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and compounds of silicon and metals.

[0024] In one possible implementation of the second aspect, the ferroelectric layer comprises at least one of the following materials: hafnium dioxide (HfO2), doped HfO2, lead zirconium titanate (PbZrTiO3), doped PbZrTiO3, strontium bismuth tantalate (SrBi2Ta2O9), doped SrBi2Ta2O9, lithium niobate (LiNbO3), doped LiNbO3, lithium tantalate (LiTaO3), doped Li TaO3, bismuth ferrite (BiFeO3), doped BiFeO3, barium titanate (BaTiO3), doped BaTiO3; optionally, the dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La); for example, doped HfO2 can be HfO2 doped with at least one of Si, Zr, Y, Al, Gd, S and La.

[0025] In one possible implementation of the second aspect, the first voltage line is a bit line and the second voltage line is a word line.

[0026] In one possible implementation of the second aspect, the first voltage line is perpendicular to the second voltage line.

[0027] In one possible implementation of the second aspect, each column of first voltage lines in the multiple columns of first voltage lines includes a plurality of first voltage lines, and the three-dimensional ferroelectric memory further includes an electrical connection layer located on the storage layer, wherein the plurality of first voltage lines are electrically connected in the electrical connection layer.

[0028] Thirdly, an electronic device is provided, comprising a circuit board and a three-dimensional ferroelectric memory connected to the circuit board, wherein the three-dimensional ferroelectric memory is provided by the second aspect or any possible implementation thereof.

[0029] Fourthly, a method for fabricating a three-dimensional ferroelectric memory is provided. The method includes: forming a memory layer on a substrate, where the substrate can be a silicon wafer, die, or silicon integrated circuit, etc. The memory layer includes stacked and alternately arranged isolation layers and polysilicon layers. The isolation layer can be an electrically insulating material and is used to isolate two adjacent polysilicon layers. The polysilicon layers are poly-Si layers and are easily etched; forming a ferroelectric layer and multiple rows of first voltage lines in the memory layer, the ferroelectric layer surrounding the multiple rows of first voltage lines, the multiple rows of first voltage lines extending along the depth direction of the memory layer (for example, one end of the multiple rows of first voltage lines is located on the surface of the memory layer away from the substrate, and the other end is located on the surface of the memory layer close to the substrate); forming an isolation groove penetrating the memory layer between any two adjacent rows of first voltage lines, resulting in multiple second voltage lines in the polysilicon layer. The first voltage lines, the ferroelectric layer, and the second voltage lines form an MFM structure in the polysilicon layer, i.e., the first voltage lines, the ferroelectric layer, and the second voltage lines form a memory cell with an MFM structure.

[0030] In the above technical solution, the storage layer includes stacked and alternately arranged isolation layers and polysilicon layers. Since the polysilicon layer is an easily corroded material, the etching difficulty of etching the first voltage lines and isolation grooves when multiple rows of first voltage lines and isolation grooves are formed on the storage layer can be greatly reduced. In addition, the first voltage lines, ferroelectric layer and second voltage lines in the polysilicon layer form a storage cell with an MFM structure. Since the storage cell with an MFM structure can be equivalent to a ferroelectric diode, compared with the ferroelectric field-effect transistor equivalent of the storage cell with an MFIS structure, the structure is simple and there is no ferroelectric layer-insulator interface that easily traps charges, thus the interface defects are small, thereby ensuring that the three-dimensional ferroelectric memory has good durability.

[0031] In one possible implementation of the fourth aspect, a ferroelectric layer and multiple rows of first voltage lines are formed in the memory layer, including: forming multiple rows of vias in the memory layer, which extend along the depth direction of the memory layer, for example, forming multiple rows of vias in the memory layer using a deep etching process, with one end of the multiple rows of vias located on the surface of the memory layer away from the substrate and the other end located on the surface of the memory layer close to the substrate; forming a ferroelectric layer in the multiple rows of vias, for example, growing a ferroelectric layer on the sidewall of each via; and filling the multiple rows of vias after the ferroelectric layer has been grown with first voltage lines to obtain multiple rows of first voltage lines, for example, growing a conductive material on the surface of the ferroelectric layer using a deposition method until the conductive material completely fills the multiple rows of vias, thus obtaining multiple rows of first voltage lines. In the above possible implementations, since the polysilicon layer is an easily etchable material, the etching difficulty of the multiple rows of vias is reduced compared to metal etching in the prior art; furthermore, as the number of stacked layers increases, the etching difficulty is further reduced.

[0032] In one possible implementation of the fourth aspect, any two adjacent columns of first voltage lines are arranged at intervals, that is, multiple first voltage lines belonging to the same column are located in the same area, and first voltage lines belonging to different columns are located in different areas, thereby facilitating the setting of isolation grooves between two adjacent columns of first voltage lines.

[0033] In one possible implementation of the fourth aspect, the isolation groove is filled with an electrically insulating material; optionally, the electrically insulating material includes silicon oxide (SiO2). x In the above possible implementations, by filling the isolation groove with electrical insulating material, the two adjacent columns of first voltage lines can be isolated by the electrical insulating material, thereby avoiding interference between the two adjacent columns of first voltage lines.

[0034] In one possible implementation of the fourth aspect, the axial margin of the portion of the first voltage line located in the metal layer is greater than the axial margin of the portion of the first voltage line located in the isolation layer. For example, if the cross-section of the first voltage line is circular, then the radius of the portion of the first voltage line located in the metal layer is greater than the radius of the portion of the first voltage line located in the isolation layer. In the above possible implementations, the memory cell of the MFM structure formed by the first voltage line, the ferroelectric layer, and the second voltage line in the metal layer can have better performance, thereby further improving the performance of the three-dimensional ferroelectric memory.

[0035] In one possible implementation of the fourth aspect, the first voltage line or the second voltage line comprises at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO)x The possible implementations described above include TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and compounds of silicon and metals. These implementations enhance the flexibility and versatility of the first or second voltage line.

[0036] In one possible implementation of the fourth aspect, the ferroelectric layer comprises at least one of the following materials: hafnium dioxide (HfO2), doped HfO2, lead zirconium titanate (PbZrTiO3), doped PbZrTiO3, strontium bismuth tantalate (SrBi2Ta2O9), doped SrBi2Ta2O9, lithium niobate (LiNbO3), doped LiNbO3, lithium tantalate (LiTaO3), doped Li TaO3, bismuth ferrite (BiFeO3), doped BiFeO3, barium titanate (BaTiO3), doped BaTiO3; optionally, the dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La); for example, doped HfO2 can be HfO2 doped with at least one of Si, Zr, Y, Al, Gd, S, and La. The above possible implementations can improve the flexibility and diversity of the ferroelectric layer.

[0037] In one possible implementation of the fourth aspect, the first voltage line is a bit line and the second voltage line is a word line. The above-described possible implementation can reduce the etching difficulty during the formation of the bit line and the word line.

[0038] In one possible implementation of the fourth aspect, the first voltage line is perpendicular to the second voltage line.

[0039] In one possible implementation of the fourth aspect, each column of first voltage lines in the multiple columns of first voltage lines includes a plurality of first voltage lines, and the method further includes: forming an electrical connection layer on the storage layer, the electrical connection layer being located on the side of the storage layer away from the substrate, and the plurality of first voltage lines being electrically connected in the electrical connection layer.

[0040] Fifthly, a three-dimensional ferroelectric memory is provided, comprising: a substrate, which may refer to a silicon wafer, die, or silicon integrated circuit, etc.; a memory layer located on the substrate, wherein a ferroelectric layer (also referred to as a ferroelectric thin film) and multiple rows of first voltage lines are disposed in the memory layer, the ferroelectric layer surrounding the multiple rows of first voltage lines, the multiple rows of first voltage lines extending along the depth direction of the memory layer (for example, one end of the multiple rows of first voltage lines is located on the surface of the memory layer away from the substrate, and the other end of the multiple rows of first voltage lines is located on the surface of the memory layer close to the substrate); wherein the memory layer comprises stacked and Alternating isolation layers and polysilicon (poly-Si) layers are provided in the storage layer. The isolation layer can be an electrically insulating material and is used to isolate two adjacent polysilicon layers. The polysilicon layer is a poly-Si layer, which is easily corroded. In addition, the storage layer is provided with an isolation groove located between any two adjacent columns of first voltage lines in the multiple columns of first voltage lines. The isolation groove penetrates the storage layer. Multiple second voltage lines are provided in the polysilicon layer. The first voltage lines, ferroelectric layer and second metal lines form a metal-ferroelectric layer-metal MFM structure in the polysilicon layer. That is, the first voltage lines, ferroelectric layer and second voltage lines form an MFM structure storage cell.

[0041] In one possible implementation of the fifth aspect, any two adjacent columns of first voltage lines are arranged at intervals, that is, multiple first voltage lines belonging to the same column are located in the same area, and first voltage lines belonging to different columns are located in different areas, thereby facilitating the setting of isolation grooves between two adjacent columns of first voltage lines.

[0042] In one possible implementation of the fifth aspect, the isolation groove is filled with an electrically insulating material, thereby isolating two adjacent columns of first voltage lines and preventing interference between them; optionally, the electrically insulating material includes silicon oxide (SiO2). x ).

[0043] In one possible implementation of the fifth aspect, the axial distance of the portion of the first voltage line located in the metal layer is greater than the axial distance of the portion of the first voltage line located in the isolation layer. For example, if the cross-section of the first voltage line is circular, then the radius of the portion of the first voltage line located in the metal layer is greater than the radius of the portion of the first voltage line located in the isolation layer.

[0044] In one possible implementation of the fifth aspect, the first voltage line or the second voltage line comprises at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO) x), TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and compounds of silicon and metals.

[0045] In one possible implementation of the fifth aspect, the ferroelectric layer comprises at least one of the following materials: hafnium dioxide (HfO2), doped HfO2, lead zirconium titanate (PbZrTiO3), doped PbZrTiO3, strontium bismuth tantalate (SrBi2Ta2O9), doped SrBi2Ta2O9, lithium niobate (LiNbO3), doped LiNbO3, lithium tantalate (LiTaO3), doped Li TaO3, bismuth ferrite (BiFeO3), doped BiFeO3, barium titanate (BaTiO3), doped BaTiO3; optionally, the dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La); for example, doped HfO2 can be HfO2 doped with at least one of Si, Zr, Y, Al, Gd, S and La.

[0046] In one possible implementation of the fifth aspect, the first voltage line is a bit line and the second voltage line is a word line.

[0047] In one possible implementation of the fifth aspect, the first voltage line is perpendicular to the second voltage line.

[0048] In one possible implementation of the fifth aspect, each column of first voltage lines in the multiple columns of first voltage lines includes a plurality of first voltage lines, and the three-dimensional ferroelectric memory further includes: an electrical connection layer located on the storage layer on the side of the storage layer away from the substrate, wherein the plurality of first voltage lines are electrically connected in the electrical connection layer.

[0049] A sixth aspect provides an electronic device comprising a circuit board and a three-dimensional ferroelectric memory connected to the circuit board, the three-dimensional ferroelectric memory being the three-dimensional ferroelectric memory provided in the fifth aspect or any possible implementation thereof.

[0050] It is understood that any of the three-dimensional ferroelectric memories and electronic devices provided above contain the same or corresponding features as the three-dimensional ferroelectric memory fabrication method provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects of the method provided above, and will not be repeated here. Attached Figure Description

[0051] Figure 1 This application provides a schematic diagram of the structure of a storage system according to an embodiment of the present application.

[0052] Figure 2This is a schematic diagram of the structure of a three-dimensional ferroelectric memory provided in an embodiment of this application;

[0053] Figure 3 This is a schematic diagram of another three-dimensional ferroelectric memory provided in an embodiment of this application;

[0054] Figure 4 This is a schematic diagram of the structure of a storage unit provided in an embodiment of this application;

[0055] Figure 5 A schematic diagram of another three-dimensional ferroelectric memory provided in the embodiments of this application;

[0056] Figure 6 This is a schematic diagram of another three-dimensional ferroelectric memory provided in an embodiment of this application;

[0057] Figure 7 A schematic diagram of another three-dimensional ferroelectric memory provided in the embodiments of this application;

[0058] Figure 8 An equivalent circuit diagram of a three-dimensional ferroelectric memory provided in an embodiment of this application;

[0059] Figure 9 A schematic diagram of the energy band structure of a ferroelectric layer provided in an embodiment of this application;

[0060] Figure 10 A flowchart illustrating a method for fabricating a three-dimensional ferroelectric memory provided in an embodiment of this application;

[0061] Figure 11 A schematic diagram illustrating the fabrication of a three-dimensional ferroelectric memory provided in an embodiment of this application;

[0062] Figure 12 This is a schematic diagram of another three-dimensional ferroelectric memory provided in an embodiment of this application;

[0063] Figure 13 A schematic diagram of another three-dimensional ferroelectric memory provided in the embodiments of this application;

[0064] Figure 14 This is a schematic diagram of another three-dimensional ferroelectric memory provided in an embodiment of this application;

[0065] Figure 15 A schematic diagram of another three-dimensional ferroelectric memory provided in the embodiments of this application;

[0066] Figure 16 A schematic flowchart illustrating another method for fabricating a three-dimensional ferroelectric memory provided in an embodiment of this application;

[0067] Figure 17This is a schematic diagram illustrating the fabrication of another three-dimensional ferroelectric memory provided in an embodiment of this application. Detailed Implementation

[0068] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this description and technology, and do not limit the scope of this application.

[0069] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0070] Each circuit or other component may be described or referred to as "for" performing one or more tasks. In this context, "for" is used to imply a structure by indicating that the circuit / component includes a structure (e.g., a circuit system) that performs one or more tasks during operation. Therefore, even when the specified circuit / component is currently inoperable (e.g., not turned on), it can still be referred to as "for performing that task." Circuits / components used with the term "for" include hardware, such as circuits that perform operations.

[0071] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, in the embodiments of this application, the words "first," "second," etc., do not limit the quantity or order.

[0072] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0073] The technical solution of this application can be applied to various storage systems that employ three-dimensional ferroelectric memory. For example, the technical solution of this application can be applied to a computer, and can also be applied to a storage system that includes a memory, or includes a processor and a memory. The processor can be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor, or a neural network processor, etc.

[0074] Figure 1 This is a schematic diagram of a storage system provided in an embodiment of this application. The storage system may include a storage device, which may be a three-dimensional ferroelectric memory. Optionally, the storage system may also include a CPU, a cache, and a controller.

[0075] In one embodiment, such as Figure 1 As shown in (a), the storage system can be an embedded memory, which includes an integrated CPU, cache, and storage device. In another embodiment, as... Figure 1 As shown in (b), the storage system can be a standalone memory, comprising an integrated CPU, cache, controller, and storage device, the storage device being coupled to the cache and CPU via the controller. In another embodiment, as... Figure 1 As shown in (c), the storage system includes a storage device, and an integrated CPU, cache, controller, and dynamic random access memory (DRAM). The storage device can be coupled to the DRAM as an external storage device. The DRAM is coupled to the cache and the CPU through the controller. Figure 1 The CPU in the various memory types shown can also be replaced with a CPU core.

[0076] Figure 2 This is a schematic diagram of the structure of a three-dimensional ferroelectric memory provided in an embodiment of this application. Figure 2 Image (a) is a top view of the three-dimensional ferroelectric memory. Figure 2 (b) in the middle is Figure 2 The top view shown in (a) is a cross-sectional view perpendicular to the direction of the line HH'. See also Figure 2The three-dimensional ferroelectric memory includes: a substrate 1, which can typically refer to a silicon wafer, a die with logic circuitry, a silicon integrated circuit, or a semiconductor with logic circuitry; a memory layer 2 located on the substrate 1, which includes stacked and alternately arranged isolation layers 21 and metal layers 22. The isolation layers 21 can be electrically insulating materials used to isolate two adjacent metal layers 22. Figure 3 (a) in the figure is the front view of the three-dimensional ferroelectric memory. Figure 3 (b) in the figure is a side view of the three-dimensional ferroelectric memory.

[0077] The storage layer 2 is provided with multiple rows of first voltage lines 23 and an isolation groove 24 located between any two adjacent rows of first voltage lines 23. The multiple rows of first voltage lines 23 extend along the depth direction of the storage layer 2 (for example, one end of the multiple rows of first voltage lines 23 is located on the surface of the storage layer 2 away from the substrate 1, and the other end of the multiple rows of first voltage lines 23 extends along the depth direction of the storage layer 2, for example, to the surface of the storage layer 2 close to the substrate 1). The isolation groove 24 penetrates the storage layer 2.

[0078] Additionally, a ferroelectric layer 25 and multiple second voltage lines 26 are disposed in the metal layer 22. The ferroelectric layer 25 (also referred to as a ferroelectric thin film) surrounds the multiple second voltage lines 26 and the portions of the multiple rows of first voltage lines 23 located in the metal layer 22, so that the first voltage lines 23, the ferroelectric layer 25, and the second voltage lines 26 form a metal-ferroelectric-metal (MFM) structure in the metal layer 22. Figure 4 The diagram shown is a schematic of a memory cell with an MFM structure. This memory cell can be represented as a ferroelectric diode D connected in series with a resistor R. For a detailed description of the read / write principle of this memory cell, please refer to the following text. Figure 9 The relevant descriptions will not be repeated here in the embodiments of this application.

[0079] In one embodiment, the isolation groove 24 is filled with an electrically insulating material, which is used to achieve electrical insulation between any two adjacent rows of first voltage lines 23 in the plurality of rows of first voltage lines 23.

[0080] In another embodiment, any two adjacent columns of first voltage lines 23 are arranged at intervals, and each column of first voltage lines 23 may include multiple first voltage lines 23. Optionally, the cross-section of the first voltage line 23 may be any of the closed shapes such as circles, ellipses, or polygons. For example, the polygon may be a triangle, quadrilateral, pentagon, hexagon, etc., and the embodiments of this application do not impose specific limitations on this.

[0081] For example, such as Figure 5 As shown, the multiple columns of first voltage lines 23 may include two columns of first voltage lines 23, which may be arranged in parallel, and an isolation groove 24 is provided between the two columns of first voltage lines 23. Figure 5 Example (a) is given by taking the case where each column of first voltage lines 23 includes three first voltage lines 23 and the cross-section of the first voltage lines 23 is circular. Figure 5 Example (b) is given by taking the case where each column of first voltage lines 23 includes 3 first voltage lines 23 and the cross-section of the first voltage lines 23 is quadrilateral. Figure 5 Example (c) is given by taking the case where each column of first voltage lines 23 includes 5 first voltage lines 23 and the cross-section of the first voltage lines 23 is circular.

[0082] Furthermore, such as Figure 6 As shown, the axial distance of the portion of the first voltage line 23 located in the metal layer 22 is greater than the axial distance of the portion of the first voltage line 23 located in the isolation layer 21. For example, if the cross-section of the first voltage line 23 is circular, then the radius of the portion of the first voltage line 23 located in the metal layer 22 is greater than the radius of the portion of the first voltage line 23 located in the isolation layer 21. Figure 6 Image (a) is a top view of the three-dimensional ferroelectric memory. Figure 6 (b) in the middle is Figure 6 The top view shown in (a) is a cross-sectional view that is perpendicular to the direction of the straight line HH'.

[0083] In one embodiment, the first voltage line 23 may include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO) x Materials used include TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), and polycrystalline silicon (Si). For example, the first voltage line 23 can be made of conductive materials with good conductivity, such as W, Al, and Cu, to reduce the voltage drop (IRdrop) on the first voltage line 23, thereby reducing the voltage division effect of the first voltage line 23 and improving the integration and storage density of the three-dimensional ferroelectric memory.

[0084] Wherein, when the first voltage line 23 comprises at least two of the above-mentioned conductive materials, these at least two conductive materials can be separate, and each conductive material forms a part of the first voltage line 23. For example, the first voltage line 23 may comprise multiple layers along the axis away from the axis, each layer corresponding to a different conductive material. In this way, different conductive materials can be distinguished in the cross-section of the first voltage line 23. Figure 5As shown in (b); or, these at least two conductive materials can be mixed together to form the first voltage line 23, so that the at least two conductive materials cannot be distinguished in the cross-section of the first voltage line 23, for example... Figure 5 As shown in (a) in the figure.

[0085] Similarly, the second voltage line 26 may also include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO) x The conductive materials used in the second voltage line 26 include TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and compounds of silicon and metals. For example, the second voltage line 26 can also be made of conductive materials with good conductivity, such as W, Al, and Cu, to reduce the voltage drop (IR drop) on the second voltage line 26, reduce the voltage division effect of the second voltage line 26, and thus improve the integration and storage density of the three-dimensional ferroelectric memory. When the second voltage line 26 includes at least two of the above conductive materials, these at least two conductive materials can be separate, and each conductive material forms a part of the second voltage line 26. For example, the second voltage line 26 can include multiple layers along the direction from near the ferroelectric layer 25 away from the ferroelectric layer 25, with each layer corresponding to a different conductive material; or, these at least two conductive materials can be mixed together to form the second voltage line 26.

[0086] It should be noted that x can have different values ​​for different materials in this article, for example, SiO2. x x in the equation can be 2, RuO x x can be 4, and this application does not impose specific restrictions on this embodiment.

[0087] In another embodiment, the ferroelectric layer 25 may include at least one of the following materials: hafnium dioxide (HfO2), doped HfO2, lead zirconium titanate (PbZrTiO3), doped PbZrTiO3, strontium bismuth tantalate (SrBi2Ta2O9), doped SrBi2Ta2O9, lithium niobate (LiNbO3), doped LiNbO3, lithium tantalate (LiTaO3), doped LiTaO3, bismuth ferrite (BiFeO3), doped BiFeO3, barium titanate (BaTiO3), doped BaTiO3. The dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La); for example, HfO2 with dopant can be HfO2 doped with at least one of Si, Zr, Y, Al, Gd, S and La.

[0088] Furthermore, such as Figure 7 As shown, the three-dimensional ferroelectric memory also includes an electrical connection layer 3, which is located on the storage layer 2 and on the side away from the substrate 1. Each column of the multiple columns of first voltage lines 23 includes a plurality of first voltage lines 23, which are electrically connected in the electrical connection layer 3.

[0089] In practical applications, the first voltage line 23 can be a bit line (BL), and the second voltage line 26 can be a word line (WL). Thus, multiple columns of the first voltage line 23 constitute multiple columns of BL, and each column of BL can include multiple BLs. Multiple second voltage lines 26 constitute multiple WLs. Optionally, the first voltage line 23 and the second voltage line 26 are perpendicular, that is, BL and WL are perpendicular.

[0090] like Figure 8 The diagram shown is an equivalent circuit diagram of a three-dimensional ferroelectric memory provided in an embodiment of this application. The three-dimensional ferroelectric memory is illustrated using the following example: storage layer 2 includes three metal layers 22; multiple columns BL include five columns of BL, each column of BL including four columns B0 to B3; and multiple WL include four WL, respectively represented as W0 to W3. Figure 7 In this three-dimensional ferroelectric memory, each metal layer 22 in storage layer 2 can include multiple MFM structured memory cells (i.e., memory cells composed of WL-ferroelectric layer-BL). Each memory cell can be equivalent to a series connection of a resistor R and a ferroelectric diode D. Furthermore, the multiple columns of BL and multiple WL in this three-dimensional ferroelectric memory can be controlled to be turned on or off by transistor switches. For example, a transistor can be connected in series with each BL in the multiple columns of BL to turn the BL on or off, and a transistor can be connected in series with each WL in the multiple columns of WL to turn the WL on or off. By controlling one BL and one WL, the read and write operations of one memory cell can be controlled. Optionally, instead of a transistor connected in series with each BL in the multiple columns of BL, each column of BL can be connected together by a metal wire and then connected in series with a transistor, so that this transistor can be used to simultaneously turn the column of BL on or off.

[0091] In this three-dimensional ferroelectric memory, read and write operations for each memory cell can be achieved by applying voltages to the word line and bit line of that memory cell. Specifically, for example... Figure 9 As shown, when a "1" is written into the memory cell, the voltage applied across the memory cell is greater than the coercive voltage of the ferroelectric layer and its direction is the direction of the first electric field. Figure 9(Represented as a left-to-right direction) When the polarization intensity P of the ferroelectric layer reverses, its polarization direction is the same as the direction of the first electric field. At this time, holes accumulate near the negative ions on the left side of the ferroelectric layer, increasing the contact barrier φ1 and forming a Schottky contact, while electrons accumulate near the positive ions on the right side, decreasing the contact barrier φ2 and forming an ohmic contact. The MFM structure formed by the ferroelectric layer, word line, and bit line at this time has the conductivity of a ferroelectric diode in the direction of the first electric field. When a "0" is written into the memory cell, if the voltage applied across the memory cell is greater than the coercive voltage of the ferroelectric layer and its direction is the direction of the second electric field (i.e., opposite to the direction of the first electric field), the polarization intensity P of the ferroelectric layer reverses, its polarization direction is the same as the direction of the second electric field. At this time, electrons accumulate near the positive ions on the left side of the ferroelectric layer, decreasing the contact barrier φ1 and forming an ohmic contact, while holes accumulate near the negative ions on the right side, increasing the contact barrier φ2 and forming a Schottky contact. The MFM structure formed by the ferroelectric layer, word lines, and bit lines becomes a ferroelectric diode with conductivity in the second electric field direction. When reading data stored in this memory cell, the voltage applied across the memory cell can be less than the coercive voltage of the ferroelectric layer but greater than the threshold voltage (V) required for electrons to cross the potential barrier. th The direction is the first electric field direction. At this time, the current value of the ferroelectric diode is read, and it is determined whether the ferroelectric diode is conducting or its direction of conduction. If the conduction direction is the same as the first electric field direction, the data stored in the memory cell is determined to be "1". If the conduction direction is the same as the second electric field direction, the data stored in the memory cell is determined to be "0". The coercive voltage of the ferroelectric layer mentioned above refers to the critical voltage that causes the polarization direction of the ferroelectric layer to reverse.

[0092] In this embodiment, the three-dimensional ferroelectric memory includes a storage layer 2 consisting of a stacked and alternately arranged isolation layer 21 and a metal layer 22. Multiple rows of first voltage lines 23 are disposed in the storage layer 2. A ferroelectric layer 25 and multiple second voltage lines 26 are disposed in the metal layer 22. The ferroelectric layer 25 surrounds the portions of the multiple second voltage lines 26 and the multiple rows of first voltage lines 23 located in the metal layer 22, thereby forming an MFM-structured memory cell within the metal layer 22. Since the MFM-structured memory cell has good durability, the three-dimensional ferroelectric memory also has good durability. Furthermore, the ferroelectric layer 25 is disposed within the metal layer 22, ensuring that the thickness of the ferroelectric layer 25 is not affected by the surrounding environment during growth, guaranteeing the consistency of the ferroelectric layer thickness, and thus ensuring the good performance of the memory cell and the three-dimensional ferroelectric memory.

[0093] Figure 10 This is a flowchart illustrating a method for fabricating a three-dimensional ferroelectric memory according to an embodiment of this application. The three-dimensional ferroelectric memory can be the aforementioned... Figures 2 to 8 A three-dimensional ferroelectric memory as depicted in any of the illustrations. For example... Figure 10As shown, the method may include the following steps. Figure 11 A cross-sectional view of the three-dimensional ferroelectric memory during its fabrication.

[0094] S31: A stacked layer 02 is formed on the substrate 1. The stacked layer 02 includes stacked and alternately arranged isolation layers 21 and sacrificial layers 022. Figure 11 As shown in (a) in the figure.

[0095] The substrate 1 can typically refer to a silicon wafer, a die with logic circuitry, a silicon integrated circuit, or a semiconductor with logic circuitry. The isolation layer 21 can be an electrically insulating material used to isolate two adjacent sacrificial layers 022; for example, the isolation layer 21 can be SiO2. x The sacrificial layer 022 can refer to a layer that will be removed or sacrificed later. The sacrificial layer 022 can be made of easily corroded materials, such as silicon nitride (SiN). x ).

[0096] Specifically, an isolation layer 21 is deposited on substrate 1, followed by a sacrificial layer 022. This process is repeated until multiple stacked and alternately arranged isolation layers 21 and sacrificial layers 022 are obtained, resulting in stacked layer 02. The number of isolation layers 21 can be one more than the number of sacrificial layers 022. The specific number of isolation layers 21 and sacrificial layers 022 can be set according to actual conditions, and this embodiment does not impose specific limitations on this. For example, Figure 11 Example (a) is given by taking the stacked layer 02 as an example, where the number of isolation layers 21 is 4 and the number of sacrificial layers 022 is 3.

[0097] S32: Multiple rows of first voltage lines 23 are formed in the stacked layer 02, and the multiple rows of first voltage lines 23 extend along the depth direction of the stacked layer 02. For example, one end of the multiple rows of first voltage lines 23 is located on the surface of the stacked layer 02 away from the substrate 1, and the other end of the multiple rows of first voltage lines 23 is located on the surface of the stacked layer 02 close to the substrate 1. Figure 11 As shown in (b) and (c) in the figure.

[0098] In this embodiment, any two adjacent columns of first voltage lines 23 can be arranged at intervals, and each column of first voltage lines 23 may include multiple first voltage lines 23. Optionally, the cross-section of the first voltage line 23 can be any of the closed shapes such as circles, ellipses, or polygons. For example, the polygon can be a triangle, quadrilateral, pentagon, hexagon, etc., and this application embodiment does not impose specific limitations on this.

[0099] Specifically, multiple rows of vias are formed in the stacked layer 02. For example, a deep etching process is used to form multiple rows of vias in the stacked layer 02. One end of these vias is located on the surface of the stacked layer 02 away from the substrate 1, and the other end extends along the depth direction of the stacked layer 02. For example, the other end of the multiple rows of first voltage lines 23 is located on the surface of the stacked layer 02 close to the substrate 1. Figure 11 As shown in (b); first voltage lines are filled into these multiple rows of vias to obtain multiple rows of first voltage lines 23. For example, conductive material is grown on the sidewalls of these multiple rows of vias using a deposition method until the conductive material completely fills the multiple rows of vias, thus obtaining multiple rows of first voltage lines 23. Figure 11 As shown in (c) in the diagram. Because the sacrificial layer 022 is easily corroded SiO₂... x This reduces the difficulty of etching multi-row through-holes compared to metal etching in existing technologies.

[0100] Optionally, the first voltage line 23 may include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO) x The materials used are: TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), and polycrystalline silicon (Si). When the first voltage line 23 comprises at least two of the above conductive materials, these at least two conductive materials can be separate, with each conductive material forming a part of the first voltage line 23. For example, if the first voltage line 23 comprises two conductive materials, when filling the multiple vias with conductive materials, the first conductive material can be grown first on the sidewalls of the multiple vias, and then the second conductive material can be grown on the surface of the first conductive material. Alternatively, the at least two conductive materials can be mixed together to form the first voltage line 23. For example, if the first voltage line 23 comprises two conductive materials, when filling the multiple vias with conductive materials, the two conductive materials can be mixed, and the mixed conductive material can be grown on the sidewalls of the multiple vias.

[0101] In one embodiment, the axial margin of the portion of the first voltage line 23 located in the sacrificial layer 022 is greater than the axial margin of the portion of the first voltage line located in the isolation layer 21. Specifically, when forming multiple rows of vias in the stacked layer 02, after forming multiple rows of vias in the stacked layer 02 using a deep etching process, a lateral wet etching technique is used to perform lateral etching at the location of the multiple rows of vias in the isolation layer 21, so that the axial margin of the portion of the multiple rows of vias located in the sacrificial layer 022 is greater than the axial margin of the portion of the multiple rows of vias located in the isolation layer 21. Afterwards, conductive material can be grown in the multiple rows of vias after lateral etching to obtain multiple rows of first voltage lines 23, wherein the axial margin of the portion of the first voltage line 23 located in the sacrificial layer 022 is greater than the axial margin of the portion of the first voltage line located in the isolation layer 21.

[0102] S33: An isolation groove 24 penetrating the stacked layer 02 is formed between any two adjacent columns of first voltage lines 23 in the multi-column first voltage lines 23. For example... Figure 11 As shown in (d) in the figure.

[0103] Specifically, a deep etching process is used to create an isolation groove 24 penetrating the stacked layer 02 between any two adjacent rows of first voltage lines 23, thereby physically isolating any two adjacent rows of first voltage lines 23. One end of the isolation groove 24 can be located on the surface of the stacked layer 02 away from the substrate 1, and the other end can be located on the surface of the stacked layer 02 close to the substrate 1. Since the sacrificial layer 022 is easily etchable SiN... x This reduces the difficulty of etching the isolation grooves compared to metal etching in existing technologies.

[0104] S34: Etch away the sacrificial layer 022 in the stacked layer 02 to obtain the first frame 03. For example... Figure 11 As shown in (e) in the diagram.

[0105] Specifically, when etching away the sacrificial layer 022 in the stacked layer 02, a lateral wet etching technique can be used to remove the sacrificial layer 022 in the stacked layer 02. After removing the sacrificial layer 022, the resulting first frame 03 includes the aforementioned multi-layered spacer layer 21 and multiple rows of first voltage lines 23. The multiple rows of first voltage lines 23 are fixed on the spacer layer 21. The surface of the portion of the multiple rows of first voltage lines 23 that was originally located in the sacrificial layer 022 is exposed to the outside, which can provide a growth surface or substrate for the subsequent growth of ferroelectric layers.

[0106] S35: Metal layers 22 are formed in the first frame 03, stacked and alternately arranged with the isolation layer 21, to obtain the storage layer 2. For example... Figure 11 As shown in (f) to (h).

[0107] Specifically, a ferroelectric material is formed on the surface of the first frame 03. For example, the ferroelectric material is grown on the surface of the first frame 03 using a deposition method. The thickness of the ferroelectric material is less than a first distance, where the first distance is the distance between two adjacent isolation layers 21 in the first frame 03. Figure 11 As shown in (f). Specifically, the ferroelectric material can not only cover the surface corresponding to the etched sacrificial layer 022 in the first frame 03, i.e., the surface of the recessed portion in the first frame 03, but also the peripheral surface in the first frame 03, so that all exposed surfaces of the first frame 03 are covered by the ferroelectric material. After growing the ferroelectric material, a conductive material is formed on the surface of the ferroelectric material. For example, a conductive material is grown on the surface of the ferroelectric material by deposition. The sum of the thickness of the conductive material and the thickness of the ferroelectric material is greater than or equal to the first distance to obtain the storage layer substrate 04. Specifically, the conductive material can cover the ferroelectric material to encapsulate the surfaces of the first frame 03 after the ferroelectric material is grown, except for the surface in contact with the substrate 1. The ferroelectric material between two adjacent isolation layers 21 in the storage layer substrate 04 forms a ferroelectric layer 25, and the conductive material between two adjacent isolation layers forms a plurality of second voltage lines 26. The ferroelectric layer 25 and the plurality of second voltage lines 26 form a metal layer 22, such as Figure 11 As shown in (g) in the figure; the ferroelectric and conductive materials on the surface of the memory layer substrate 04 are removed to obtain the memory layer 2. For example, the ferroelectric and conductive materials on the sides of the memory layer substrate 04 (e.g., around the perimeter of the memory layer substrate 04) and the surface away from the substrate 1 (e.g., the upper surface of the memory layer substrate 04 and within the isolation groove 24) are removed using a dry etching process to obtain the memory layer 2. The memory layer 2 includes stacked and alternately arranged isolation layers 21 and metal layers 22, such as... Figure 11 As shown in (h).

[0108] Optionally, the second voltage line 26 may include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO) xThe materials used are: TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and compounds of silicon and metals. When the second voltage line 26 includes at least two of the above conductive materials, these at least two conductive materials can be separate, and each conductive material forms a part of the second voltage line 26. For example, the second voltage line 26 may include multiple layers along the direction from near the ferroelectric layer 25 away from the ferroelectric layer 25, with each layer corresponding to a different conductive material. Thus, the second voltage line 26 can be formed by sequentially growing different conductive materials. Alternatively, the at least two conductive materials can be mixed together to form the second voltage line 26, i.e., the second voltage line 26 can be formed by growing the mixed conductive materials.

[0109] Furthermore, the method may further include filling the isolation groove 24 with an electrically insulating material, which can be used to achieve electrical insulation between any two adjacent rows of first voltage lines 23 in the plurality of rows of first voltage lines 23. For example, the electrically insulating material may be silicon oxide (SiO2). x ).

[0110] In another embodiment, each column of first voltage lines 23 includes a plurality of first voltage lines 23, and the method further includes: forming an electrical connection layer 3 on the storage layer 2, the electrical connection layer 3 being located on the side of the storage layer 2 away from the substrate 1, and the plurality of first voltage lines 23 being electrically connected in the electrical connection layer 3.

[0111] It should be noted that the above text Figures 2-9 The descriptions of the three-dimensional ferroelectric memory provided herein can all be referenced in the fabrication method of the three-dimensional ferroelectric memory, and will not be repeated here in the embodiments of this application.

[0112] In the fabrication method of the three-dimensional ferroelectric memory provided in this application embodiment, the stacked layer 02 formed on the substrate 1 includes stacked and alternately arranged isolation layers 21 and sacrificial layers 022. Since the sacrificial layer 022 is an easily corroded material, the etching difficulty of etching vias and isolation grooves can be greatly reduced when multiple rows of first voltage lines 23 and isolation grooves 24 are formed in the stacked layer 02, and when a metal layer including a ferroelectric layer 25 and multiple second voltage lines 26 is formed after etching away the sacrificial layer 022. At the same time, the ferroelectric layer 25 in the metal layer 22 surrounds the portion of the multiple second voltage lines 26 and the multiple rows of first voltage lines 23 located in the metal layer 22, so as to form an MFM structure memory cell in the metal layer 22. Since the MFM structure memory cell has good durability, the three-dimensional ferroelectric memory has good durability. Furthermore, the ferroelectric layer 25 is formed on the surface of the first frame 03 obtained after removing the sacrificial layer 022. That is, the first frame 03 provides the surface where the first voltage line 23 required for subsequent ferroelectric layer growth is exposed in the metal layer 22, thereby ensuring the quality of ferroelectric layer growth and thus ensuring the good performance of the memory cell and the three-dimensional ferroelectric memory.

[0113] Figure 12 This is a schematic diagram of another three-dimensional ferroelectric memory provided in an embodiment of this application. Figure 12 Image (a) is a top view of the three-dimensional ferroelectric memory. Figure 12 (b) in the middle is Figure 12 The top view shown in (a) is a cross-sectional view perpendicular to the direction of the line HH'. See also Figure 12 The three-dimensional ferroelectric memory includes: a substrate 10, which can typically refer to a silicon wafer, a die with logic circuitry, a silicon integrated circuit, or a semiconductor with logic circuitry; a memory layer 20 located on the substrate 10, the memory layer 20 including stacked and alternately arranged isolation layers 201 and polysilicon (poly-Si) layers 202, the isolation layer 201 can be an electrically insulating material used to isolate two adjacent polysilicon layers 202. Figure 13 (a) in the figure is the front view of the three-dimensional ferroelectric memory. Figure 13 (b) in the figure is a side view of the three-dimensional ferroelectric memory.

[0114] The storage layer 20 includes a ferroelectric layer 203 (also known as a ferroelectric thin film) and multiple rows of first voltage lines 204. The ferroelectric layer 203 surrounds the multiple rows of first voltage lines 204, which extend along the depth direction of the storage layer 20. For example, one end of the multiple rows of first voltage lines 204 is located on the surface of the storage layer 20 away from the substrate 1, and the other end of the multiple rows of first voltage lines 204 extends along the depth direction of the storage layer 20, for example, to the surface of the storage layer 20 near the substrate 10. An isolation groove 205 is provided in the storage layer 20 between any two adjacent rows of first voltage lines 204, and the isolation groove 205 penetrates the storage layer 20.

[0115] In addition, a plurality of second voltage lines 206 are provided in the polysilicon layer 202, and the first voltage line 204, the ferroelectric layer 203, and the second voltage lines 206 form an MFM structure in the polysilicon layer 202. Optionally, the first voltage line 204 is perpendicular to the second voltage line 206.

[0116] In one embodiment, the isolation groove 205 is filled with an electrically insulating material, which is used to achieve electrical insulation between any two adjacent rows of first voltage lines 204 in the plurality of rows of first voltage lines 204. Optionally, the electrically insulating material can be silicon oxide (SiO2). x ).

[0117] In another embodiment, any two adjacent columns of first voltage lines 204 are arranged at intervals, and each column of first voltage lines 204 may include multiple first voltage lines 204. Optionally, the cross-section of the first voltage line 204 can be any of the closed shapes such as circles, ellipses, or polygons. For example, the polygon can be a triangle, quadrilateral, pentagon, hexagon, etc., and this application embodiment does not impose specific limitations on this.

[0118] Furthermore, such as Figure 14 As shown, the axial distance of the portion of the first voltage line 204 located in the polysilicon layer 202 is greater than the axial distance of the portion of the first voltage line 204 located in the isolation layer 201. For example, if the cross-section of the first voltage line 204 is circular, then the radius of the portion of the first voltage line 204 located in the polysilicon layer 202 is greater than the radius of the portion of the first voltage line 204 located in the isolation layer 201. Figure 14 Image (a) is a top view of the three-dimensional ferroelectric memory. Figure 14 (b) in the middle is Figure 14 The top view shown in (a) is a cross-sectional view that is perpendicular to the direction of the straight line HH'.

[0119] In one embodiment, the first voltage line 204 may include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO) x Materials used include TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), and polycrystalline silicon (Si). For example, the first voltage line 204 can be made of conductive materials with good conductivity, such as W, Al, and Cu, to reduce the voltage drop (IRdrop) on the first voltage line 204, thereby reducing the voltage division effect of the first voltage line 204 and improving the integration and storage density of the three-dimensional ferroelectric memory.

[0120] Wherein, when the first voltage line 204 includes at least two of the above conductive materials, these at least two conductive materials can be separate, and each conductive material forms a part of the first voltage line 204. For example, the first voltage line 204 may include multiple layers along the axis away from the axis, with each layer corresponding to a conductive material, so that different conductive materials can be distinguished in the cross-section of the first voltage line 204; or, these at least two conductive materials can be mixed together to form the first voltage line 204, so that these at least two conductive materials cannot be distinguished in the cross-section of the first voltage line 204.

[0121] It should be noted that x can have different values ​​for different materials in this article, for example, SiO2. x x in the equation can be 2, RuO x x can be 4, and this application does not impose specific restrictions on this embodiment.

[0122] In another embodiment, the ferroelectric layer 203 may include at least one of the following materials: hafnium dioxide (HfO2), doped HfO2, lead zirconium titanate (PbZrTiO3), doped PbZrTiO3, strontium bismuth tantalate (SrBi2Ta2O9), doped SrBi2Ta2O9, lithium niobate (LiNbO3), doped LiNbO3, lithium tantalate (LiTaO3), doped LiTaO3, bismuth ferrite (BiFeO3), doped BiFeO3, barium titanate (BaTiO3), doped BaTiO3. The dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), and lanthanum (La).

[0123] Furthermore, such as Figure 15As shown, the three-dimensional ferroelectric memory also includes an electrical connection layer 30, which is located on the storage layer 20 and on the side away from the substrate 1. Each column of the multiple columns of first voltage lines 204 includes a plurality of first voltage lines 204, which are electrically connected in the electrical connection layer 30.

[0124] In practical applications, the first voltage line 204 can be a bit line (BL), and the second voltage line 206 can be a word line (WL). Thus, multiple columns of first voltage lines 204 constitute multiple columns of BL, and each column of BL can include multiple BLs. Multiple second voltage lines 206 constitute multiple WLs. Optionally, the first voltage lines 204 and second voltage lines 206 are perpendicular, i.e., BL and WL are perpendicular. It should be noted that the equivalent circuit diagram of this three-dimensional ferroelectric memory and the read / write operations of each memory cell are the same as described above. Figure 8 and Figure 9 The relevant content described is consistent with the above description, and the embodiments of this application will not be repeated here.

[0125] In this embodiment, the three-dimensional ferroelectric memory includes a storage layer 2 consisting of a stacked and alternately arranged isolation layer 201 and a polysilicon layer 202. The storage layer 2 contains a ferroelectric layer 203, multiple rows of first voltage lines 204 penetrating the storage layer 2, and isolation grooves 205. The ferroelectric layer 203 surrounds the multiple rows of first voltage lines 204, and the isolation grooves 205 isolate adjacent rows of first voltage lines 204. The polysilicon layer 202 contains multiple second voltage lines 206. Thus, the multiple second voltage lines 206, the ferroelectric layer 203, and the multiple rows of first voltage lines 204 form an MFM (Mean Mixed Module) structure storage cell within the polysilicon layer 202. Since the MFM structure storage cell has good durability, the three-dimensional ferroelectric memory also has good durability. Furthermore, because the polysilicon layer 202 is easier to etch than metal, the etching difficulty of setting the multiple rows of first voltage lines 204 and isolation grooves 205 in the polysilicon layer 202 is reduced.

[0126] Figure 16 This is a flowchart illustrating a method for fabricating a three-dimensional ferroelectric memory according to an embodiment of this application. The three-dimensional ferroelectric memory can be the aforementioned... Figures 12 to 15 A three-dimensional ferroelectric memory as depicted in any of the illustrations. For example... Figure 16 As shown, the method may include the following steps. Figure 17 A cross-sectional view of the three-dimensional ferroelectric memory during its fabrication.

[0127] S41: A memory layer 20 is formed on the substrate 10, the memory layer 20 including stacked and alternately arranged isolation layers 201 and polysilicon layers 202. Figure 17 As shown in (a) in the figure.

[0128] The substrate 10 can typically refer to a silicon wafer, a die with logic circuitry, a silicon integrated circuit, or a semiconductor with logic circuitry. The isolation layer 201 can be an electrically insulating material used to isolate two adjacent polysilicon layers 202; for example, the isolation layer 201 can be SiO2. x The polycrystalline silicon layer 202 can be made of silicon or silicon germanium, etc.

[0129] Specifically, an isolation layer 201 is deposited on the substrate 10, followed by a polysilicon layer 202. Then, isolation layers 201 and polysilicon layers 202 are deposited sequentially in the same manner until multiple stacked and alternately arranged isolation layers 201 and sacrificial polysilicon layers 202 are obtained, thus forming the memory layer 20. The number of isolation layers 201 can be one more than the number of polysilicon layers 202. The specific number of isolation layers 201 and polysilicon layers 202 can be set according to actual conditions, and this embodiment does not impose specific limitations on this. For example, Figure 17 Example (a) is given by taking the storage layer 20 as an example where the number of isolation layers 201 is 4 and the number of polysilicon layers 202 is 3.

[0130] S42: A ferroelectric layer 203 and multiple rows of first voltage lines 204 are formed in the storage layer 20. The ferroelectric layer 203 surrounds the multiple rows of first voltage lines 204. One end of each row of first voltage lines 204 is located on the surface of the storage layer 20 away from the substrate 10, and the other end of each row of first voltage lines 204 extends along the depth direction of the storage layer 20 (e.g., the other end of each row of first voltage lines 204 is located on the surface of the storage layer 20 near the substrate 10). Figure 17 As shown in (b) to (d) in the text.

[0131] In this embodiment, any two adjacent columns of first voltage lines 204 can be arranged at intervals, and each column of first voltage lines 204 may include multiple first voltage lines 204. Optionally, the cross-section of the first voltage line 204 can be any of the closed shapes such as circles, ellipses, or polygons. For example, the polygon can be a triangle, quadrilateral, pentagon, hexagon, etc., and this application embodiment does not impose specific limitations on this.

[0132] Specifically, multiple rows of vias are formed in the storage layer 20. For example, a deep etching process is used to form multiple rows of vias in the storage layer 20. One end of these vias is located on the surface of the storage layer 20 away from the substrate 10, and the other end is located on the surface of the storage layer 20 close to the substrate 10. Figure 17 As shown in (b); a ferroelectric layer 203 is formed in these multiple rows of vias, for example, a ferroelectric layer 203 is grown on the sidewall of each via in these multiple rows of vias, such as... Figure 17As shown in (c); after growing the ferroelectric layer 203, the multiple rows of vias are filled with first voltage lines to obtain multiple rows of first voltage lines 204. For example, a conductive material is grown on the surface of the ferroelectric layer 203 by deposition until the conductive material completely fills the multiple rows of vias, thus obtaining multiple rows of first voltage lines 204. Figure 17 As shown in (d) in the figure. Because the polysilicon layer 202 is easily etched, the etching difficulty of multi-row vias is reduced compared with metal etching in the prior art.

[0133] Optionally, the first voltage line 204 may include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO) x The conductive materials used are: TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), and polycrystalline silicon (Si). When the first voltage line 204 comprises at least two of the above conductive materials, these at least two conductive materials can be separate, with each conductive material forming a part of the first voltage line 204. For example, if the first voltage line 204 comprises two conductive materials, when filling the multiple vias with conductive materials, the first conductive material can be grown first on the sidewalls of the multiple vias, and then the second conductive material can be grown on the surface of the first conductive material. Alternatively, the at least two conductive materials can be mixed together to form the first voltage line 204. For example, if the first voltage line 204 comprises two conductive materials, when filling the multiple vias with conductive materials, the two conductive materials can be mixed, and the mixed conductive material can be grown on the sidewalls of the multiple vias.

[0134] In one embodiment, the axial margin of the portion of the first voltage line 204 located in the polysilicon layer 202 is greater than the axial margin of the portion of the first voltage line located in the isolation layer 201. Specifically, when forming multiple rows of vias in the memory layer 20, after forming the multiple rows of vias in the memory layer 20 using a deep etching process, a lateral wet etching technique is used to perform lateral etching at the location of the multiple rows of vias in the isolation layer 201, so that the axial margin of the portion of the multiple rows of vias located in the polysilicon layer 202 is greater than the axial margin of the portion of the multiple rows of vias located in the isolation layer 201. Afterwards, a ferroelectric layer and a conductive material can be grown in the multiple rows of vias after the lateral etching to obtain a ferroelectric layer 203 and multiple rows of first voltage lines 204, wherein the axial margin of the portion of the first voltage line 204 located in the polysilicon layer 202 is greater than the axial margin of the portion of the first voltage line located in the isolation layer 201.

[0135] S43: An isolation groove 205 penetrating the storage layer 20 is formed between any two adjacent columns of first voltage lines 204 in the multi-column first voltage lines 204, resulting in multiple second voltage lines 206 in the polysilicon layer 202. For example... Figure 17 As shown in (e) in the diagram.

[0136] Specifically, a deep etching process is used to create an isolation groove 205 penetrating the storage layer 20 between any two adjacent rows of first voltage lines 204, thereby physically isolating any two adjacent rows of first voltage lines 204 and simultaneously obtaining multiple second voltage lines 206 in the polysilicon layer 202. One end of the isolation groove 205 can be located on the surface of the storage layer 20 away from the substrate 10, and the other end can be located on the surface of the storage layer 20 close to the substrate 10. Since the polysilicon layer 202 is easily etched, the etching difficulty of the isolation groove is reduced compared to metal etching in the prior art.

[0137] Furthermore, the method may further include filling the isolation groove 205 with an electrically insulating material, which can be used to achieve electrical insulation between any two adjacent rows of first voltage lines 204 in the plurality of rows of first voltage lines 204. For example, the electrically insulating material may be silicon oxide (SiO2). x ).

[0138] In another embodiment, each column of the multiple columns of first voltage lines 204 includes a plurality of first voltage lines 204. The method further includes: forming an electrical connection layer 30 on the storage layer 20, the electrical connection layer 30 being located on the side of the storage layer 20 away from the substrate 10, and the plurality of first voltage lines 204 being electrically connected in the electrical connection layer 30, such as... Figure 14 As shown in (f) in the figure.

[0139] It should be noted that the above text Figures 12 to 15 The descriptions of the three-dimensional ferroelectric memory provided in any of the illustrations can be referenced in the fabrication method of the three-dimensional ferroelectric memory, and will not be repeated here in the embodiments of this application.

[0140] In the fabrication method of the three-dimensional ferroelectric memory provided in this application embodiment, the memory layer 20 formed on the substrate 10 includes a stacked and alternately arranged isolation layer 201 and a polysilicon layer 202. Since the polysilicon layer 202 is easily etched, when multiple rows of first voltage lines 204 and isolation grooves 204 penetrating the memory layer 20 are provided in the memory layer 20, the etching difficulty of vias and isolation grooves using etching processes can be greatly reduced. At the same time, the ferroelectric layer 203 provided in the memory layer 20 surrounds the multiple rows of first voltage lines 204, so that the multiple rows of first voltage lines 204, the ferroelectric layer 203, and multiple second voltage lines 206 in the polysilicon layer 202 form an MFM structure memory cell in the polysilicon layer 202. Since the MFM structure memory cell has good durability, the three-dimensional ferroelectric memory has good durability.

[0141] Based on this, this application also provides an electronic device, which includes a circuit board and a three-dimensional ferroelectric memory connected to the circuit board. The three-dimensional ferroelectric memory can be any of the three-dimensional ferroelectric memories provided above. The circuit board can be a printed circuit board (PCB), or a flexible printed circuit board (FPC), etc. This embodiment does not limit the type of circuit board. Optionally, the electronic device can be different types of user equipment or terminal equipment such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices; the electronic device can also be network equipment such as base stations.

[0142] Optionally, the electronic device also includes a packaging substrate, which is fixed to a printed circuit board (PCB) by solder balls, and the three-dimensional ferroelectric memory is fixed to the packaging substrate by solder balls.

[0143] It should be noted that for details regarding the description of three-dimensional ferroelectric memories in electronic devices, please refer to the above. Figures 2-17 The description of the three-dimensional ferroelectric memory in the previous embodiment will not be repeated here.

[0144] In another aspect of this application, a non-transitory computer-readable storage medium for use with a computer having software for creating integrated circuits is also provided. The computer-readable storage medium stores one or more computer-readable data structures having photomask data for manufacturing the integrated circuit provided in any of the above-provided figures.

[0145] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating a three-dimensional ferroelectric memory, characterized in that, The method includes: A stacked layer is formed on a substrate, the stacked layer comprising stacked and alternately arranged isolation layers and sacrificial layers; Multiple columns of first voltage lines are provided in the stacked layer, and the multiple columns of first voltage lines extend along the depth direction of the stacked layer; An isolation groove penetrating the stacked layer is formed between any two adjacent columns of first voltage lines in the plurality of columns of first voltage lines; The sacrificial layer in the stacked layers is etched away to obtain the first frame; In the first frame, metal layers are formed stacked and alternately arranged with the isolation layer to obtain a storage layer; wherein, the metal layer includes a ferroelectric layer and a plurality of second voltage lines, the ferroelectric layer surrounds the plurality of second voltage lines and the portion of the plurality of columns of first voltage lines located in the metal layer, so that a metal-ferroelectric layer-metal MFM structure is formed in the metal layer; The three-dimensional ferroelectric memory includes multiple MFM structure storage cells, and the read and write operations of each MFM structure storage cell are realized by applying voltage to the first voltage line and the second voltage line of the storage cell.

2. The method according to claim 1, characterized in that, The provision of multiple columns of first voltage lines in the stacked layer includes: Multiple rows of through-holes are provided in the stacked layer, and the multiple rows of through-holes extend along the depth direction of the stacked layer; The multiple rows of through holes are filled with first voltage lines to obtain multiple rows of first voltage lines.

3. The method according to claim 1, characterized in that, The step of forming metal layers stacked and alternately disposed with the isolation layer in the first frame to obtain a storage layer includes: A ferroelectric material is grown on the surface of the first frame, the thickness of the ferroelectric material being less than a first distance, the first distance being the distance between two adjacent isolation layers in the first frame; A conductive material is grown on the surface of the ferroelectric material, and the sum of the thickness of the conductive material and the thickness of the ferroelectric material is greater than or equal to the first distance to obtain a storage layer substrate. The ferroelectric material between two adjacent isolation layers in the storage layer substrate forms a ferroelectric layer, and the conductive material between two adjacent isolation layers forms a plurality of second voltage lines. The ferroelectric layer and the plurality of second voltage lines form a metal layer. The ferroelectric material and the conductive material on the surface of the storage layer substrate are removed to obtain a storage layer, the storage layer comprising stacked and alternately arranged isolation layers and metal layers.

4. The method according to claim 1, characterized in that, The multiple columns of first voltage lines are arranged with any two adjacent columns spaced apart.

5. The method according to claim 1, characterized in that, The method further includes: The isolation groove is filled with an electrically insulating material.

6. The method according to claim 5, characterized in that, The electrically insulating material includes: silicon dioxide (SiO2). x ).

7. The method according to claim 1, characterized in that, The axial margin of the portion of the first voltage line located in the metal layer is greater than the axial margin of the portion of the first voltage line located in the isolation layer.

8. The method according to claim 1, characterized in that, The first voltage line or the second voltage line comprises at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO) x ), TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and compounds of silicon and metals.

9. The method according to claim 1, characterized in that, The ferroelectric layer comprises at least one of the following materials: hafnium dioxide (HfO2), doped HfO2, lead zirconium titanate (PbZrTiO3), doped PbZrTiO3, strontium bismuth tantalate (SrBi2Ta2O9), doped SrBi2Ta2O9, lithium niobate (LiNbO3), doped LiNbO3, lithium tantalate (LiTaO3), doped LiTaO3, bismuth ferrite (BiFeO3), doped BiFeO3, barium titanate (BaTiO3), doped BaTiO3.

10. The method according to claim 9, characterized in that, The dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), and lanthanum (La).

11. The method according to claim 1, characterized in that, The first voltage line is a bit line, and the second voltage line is a word line.

12. The method according to any one of claims 1-11, characterized in that, Each column of the multiple columns of first voltage lines includes a plurality of first voltage lines, and the method further includes: An electrical connection layer is formed on the storage layer, and the plurality of first voltage lines are electrically connected in the electrical connection layer.

13. A three-dimensional ferroelectric memory, characterized in that, The three-dimensional ferroelectric memory includes: Substrate; a storage layer located on the substrate, the storage layer comprising stacked and alternately arranged isolation layers and metal layers; The storage layer is provided with multiple columns of first voltage lines and an isolation groove located between any two adjacent columns of first voltage lines. The multiple columns of first voltage lines extend along the depth direction of the storage layer, and the isolation groove penetrates the storage layer. The metal layer is provided with a ferroelectric layer and a plurality of second voltage lines. The ferroelectric layer surrounds the plurality of second voltage lines and the portions of the plurality of first voltage lines located in the metal layer, so that a metal-ferroelectric layer-metal MFM structure is formed in the metal layer. The three-dimensional ferroelectric memory includes multiple MFM structure storage cells, and the read and write operations of each MFM structure storage cell are realized by applying voltage to the first voltage line and the second voltage line of the storage cell.

14. The three-dimensional ferroelectric memory according to claim 13, characterized in that, The multiple columns of first voltage lines are arranged with any two adjacent columns spaced apart.

15. The three-dimensional ferroelectric memory according to claim 13, characterized in that, The isolation groove is filled with electrical insulating material.

16. The three-dimensional ferroelectric memory according to claim 15, characterized in that, The electrically insulating material includes: silicon dioxide (SiO2). x ).

17. The three-dimensional ferroelectric memory according to claim 13, characterized in that, The axial margin of the portion of the first voltage line located in the metal layer is greater than the axial margin of the portion of the first voltage line located in the isolation layer.

18. The three-dimensional ferroelectric memory according to claim 13, characterized in that, The first voltage line or the second voltage line comprises at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), Iridium (Ir), Iridium oxide (IrO) x ), TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and compounds of silicon and metals.

19. The three-dimensional ferroelectric memory according to claim 13, characterized in that, The ferroelectric layer comprises at least one of the following materials: hafnium dioxide (HfO2), doped HfO2, lead zirconium titanate (PbZrTiO3), doped PbZrTiO3, strontium bismuth tantalate (SrBi2Ta2O9), doped SrBi2Ta2O9, lithium niobate (LiNbO3), doped LiNbO3, lithium tantalate (LiTaO3), doped LiTaO3, bismuth ferrite (BiFeO3), doped BiFeO3, barium titanate (BaTiO3), doped BaTiO3.

20. The three-dimensional ferroelectric memory according to claim 19, characterized in that, The dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), and lanthanum (La).

21. The three-dimensional ferroelectric memory according to claim 13, characterized in that, The first voltage line is a bit line, and the second voltage line is a word line.

22. The three-dimensional ferroelectric memory according to any one of claims 13-21, characterized in that, Each column of the multiple first voltage lines includes multiple first voltage lines, and the three-dimensional ferroelectric memory further includes an electrical connection layer located on the memory layer, wherein the multiple first voltage lines are electrically connected in the electrical connection layer.

23. An electronic device, characterized in that, The device includes a circuit board and a three-dimensional ferroelectric memory connected to the circuit board, wherein the three-dimensional ferroelectric memory is the three-dimensional ferroelectric memory as described in any one of claims 13-22.

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