An oscillator

Abstract

An oscillator includes two inverse amplification elements, each inverse amplification element forming a self-feedback structure through an inductor. The outputs of the two inverse amplification elements are coupled to each other through one or more inductors, and the inputs of the two inverse amplification elements are coupled to each other through a capacitor. The capacitance of the capacitor can be adjusted to change the oscillation frequency of a differential output oscillation signal output by the oscillator.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to an oscillator. Background Technology

[0002] A phase-locked loop (PLL) is a crucial unit in communication equipment, used for example as a clock generation circuit in various chips, microprocessors, digital circuits, and analog circuits, or as a local oscillator circuit in a wireless transceiver. PLLs require either a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO). For PLLs using a VCO, the performance of the VCO directly impacts the overall performance of the device. Taking a wireless transceiver as an example, a multi-mode transceiver working with a multi-transmitter chip employs a multi-transmitter and multi-receiver architecture. In Multi-input Multi-output (MIMO) mode, multiple PLLs need to operate simultaneously. For the VCOs used in these PLLs, phase noise performance is a critical factor.

[0003] Figure 1 This is a typical structure for voltage-controlled oscillators in the prior art, including two cross-coupled N-type metal-oxide-semiconductor (NMOS) transistors M100 and M200, and two cross-coupled P-type metal-oxide-semiconductor (PMOS) transistors M300 and M400. The cross-coupling of the two transistors means that the gate of one transistor is coupled to the drain of the other transistor. The sources of the two NMOS transistors M100 and M200 are grounded, and the sources of the two PMOS transistors M300 and M400 are coupled to the reference voltage source VDD. The drain of NMOS transistor M100 is coupled to the drain of PMOS transistor M300, and the drain of NMOS transistor M200 is coupled to the drain of PMOS transistor M400. Inductor L100 is coupled between the two drains of two PMOS transistors M300 and M400 and connected in parallel with two capacitors C100 and C200 connected in series. The two capacitors C100 and C200 are adjustable capacitors, and their capacitance values ​​are changed under the control of a control voltage, thereby changing the output oscillation frequency of the voltage-controlled oscillator.

[0004] However, Figure 1The structure shown is not ideal in suppressing phase noise and cannot meet the application requirements of some low-noise scenarios. Therefore, how to suppress phase noise to achieve good performance is an urgent problem to be solved in the design of voltage-controlled oscillators. Summary of the Invention

[0005] Embodiments of this application provide an oscillator to achieve good phase noise suppression.

[0006] In view of the above, a first aspect of this application provides an oscillator, comprising: a first inverting amplification element, including a first input terminal and a first output terminal; a second inverting amplification element, including a second input terminal and a second output terminal; a first inductive element coupled between the first input terminal and the first output terminal; a second inductive element coupled between the second input terminal and the second output terminal; a third inductive element coupled between the first output terminal and the second output terminal; a first capacitive element coupled between the first input terminal and the second input terminal for receiving a first control signal, the first control signal being used to adjust the capacitance value of the first capacitive element; a first signal output terminal coupled to the first inductive element for outputting a first oscillation signal; and a second signal output terminal coupled to the second inductive element for outputting a second oscillation signal, wherein the first oscillation signal and the second oscillation signal are differential output oscillation signals.

[0007] The above technical solution configures the two inverting amplification elements as a self-feedback structure, which has higher current conversion efficiency and helps suppress phase noise compared to traditional voltage-controlled oscillators with cross-coupling structures. The input terminals of the two inverting amplification elements are coupled to each other through capacitive components, such as capacitors, which doubles the equivalent capacitance, increases signal energy, and thus provides better phase noise suppression characteristics.

[0008] In conjunction with the first aspect, in a first implementation of the first aspect, the first inductive element includes a first inductor, the second inductive element includes a second inductor, and the third inductive element includes a third inductor and a fourth inductor; the first inverting amplifying element includes a first MOS transistor, the first input terminal is the gate of the first MOS transistor, the first output terminal is the drain of the first MOS transistor, the source of the first MOS transistor is used to input a first reference voltage, and the third inductor is coupled between the first output terminal and a second node having a second reference voltage; the second inverting amplifying element includes a second MOS transistor, the second input terminal is the gate of the second MOS transistor, the second output terminal is the drain of the second MOS transistor, the source of the second MOS transistor is used to input the first reference voltage, and the fourth inductor is coupled between the second output terminal and the second node having the second reference voltage. Optionally, each of the first MOS transistor and the second MOS transistor can be a PMOS transistor or an NMOS transistor. For example, the first reference voltage input to the source of the PMOS transistor is a reference voltage source, in which case the second reference voltage is ground voltage. For example, if the first reference voltage input to the source of an NMOS transistor is ground, then the second reference voltage acts as a reference voltage source. In this implementation, a single transistor is used to achieve the amplification function, resulting in a simple structural design.

[0009] In conjunction with the first aspect, in a first implementation of the second aspect, the first inductive element includes a first inductor, the second inductive element includes a second inductor, and the third inductive element includes at least one third inductor; the first inverting amplification element includes a first CMOS inverter coupled to a first node having a first reference voltage and a second node having a second reference voltage; the second inverting amplification element includes a second CMOS inverter coupled to the first node having the first reference voltage and the second node having the second reference voltage. In this implementation, a CMOS inverter is used to achieve the amplification function, thereby improving performance.

[0010] In conjunction with the first implementation of the first aspect, in the third implementation of the first aspect, the first inductor and the third inductor are formed in the first multi-port inductor, and the second inductor and the fourth inductor are formed in the second multi-port inductor. The above scheme is simple to implement.

[0011] In conjunction with the first aspect, in the fourth implementation of the first aspect, the first inductive element includes a first inductor and a fifth inductor, the second inductive element includes a second inductor and a sixth inductor, and the third inductive element includes a third inductor and a fourth inductor; the oscillator further includes: a third inverting amplification element, including a third input terminal and a third output terminal; a fourth inverting amplification element, including a fourth input terminal and a fourth output terminal; and a second capacitive element coupled between the third input terminal and the fourth input terminal; wherein the first inductor is coupled between the first input terminal and the third output terminal, the second inductor is coupled between the second input terminal and the fourth output terminal, the third inductor is coupled between the first output terminal and the third input terminal, the fourth inductor is coupled between the second output terminal and the fourth input terminal, the fifth inductor is coupled between the first output terminal and the third output terminal, and the sixth inductor is coupled between the second output terminal and the fourth output terminal. This structure is equivalent to connecting the first and third inverting amplifying elements in series, and connecting the second and fourth inverting amplifying elements in series, which can improve current utilization efficiency, increase swing, and further improve noise suppression characteristics.

[0012] In conjunction with the fourth implementation of the first aspect, in the fifth implementation of the first aspect, the second capacitive element is used to receive a second control signal, which is also used to adjust the capacitance value of the second capacitive element. In this solution, both the second and first capacitive elements can receive different control signals, allowing for the adjustment of their capacitance values ​​to regulate the output signal frequency of the oscillator, thus improving the flexibility of adjustment. Alternatively, the capacitance value of the second capacitive element can be non-adjustable.

[0013] In conjunction with the fourth or fifth implementation of the first aspect, in the sixth implementation of the first aspect, the first capacitive element and the second capacitive element include at least one of a variable capacitor, a switched capacitor network, or a variable capacitor diode.

[0014] In a seventh implementation of the first aspect, combining any of the fourth to sixth implementations, the first inverting amplification element includes a first MOS transistor, with the first input terminal being the gate of the first MOS transistor, the first output terminal being the drain of the first MOS transistor, and the source of the first MOS transistor being used to input a first reference voltage; the second inverting amplification element includes a second MOS transistor, with the second input terminal being the gate of the second MOS transistor, the second output terminal being the drain of the second MOS transistor, and the source of the second MOS transistor being used to input the first reference voltage; the third inverting amplification element includes a third MOS transistor, with the third input terminal being the gate of the third MOS transistor, the third output terminal being the drain of the third MOS transistor, and the source of the third MOS transistor being used to input a second reference voltage, wherein the third MOS transistor and the first MOS transistor are complementary transistors; the fourth inverting amplification element includes a fourth MOS transistor, with the fourth input terminal being the gate of the fourth MOS transistor, the fourth output terminal being the drain of the fourth MOS transistor, and the source of the fourth MOS transistor being used to input the second reference voltage, wherein the fourth MOS transistor and the second MOS transistor are complementary transistors. Optionally, complementary transistors mean that one transistor is a PMOS transistor and the other is an NMOS transistor. Therefore, when the first and second MOS transistors are PMOS transistors, the third and fourth MOS transistors are NMOS transistors; conversely, when the first and second MOS transistors are NMOS transistors, the third and fourth MOS transistors are PMOS transistors. For example, the reference voltage input to the source of a PMOS transistor is a reference voltage source, while the reference voltage input to the source of an NMOS transistor is ground voltage.

[0015] In conjunction with any of the fourth to sixth implementations of the first aspect, in the eighth implementation of the first aspect, the first inverting amplification element includes a first CMOS inverter coupled between a first node having a first reference voltage and a second node having a second reference voltage; the second inverting amplification element includes a second CMOS inverter coupled between the first node having the first reference voltage and the second node having the second reference voltage; the third inverting amplification element includes a third CMOS inverter coupled between the first node having the first reference voltage and the second node having the second reference voltage; and the fourth inverting amplification element includes a fourth CMOS inverter coupled between the first node having the first reference voltage and the second node having the second reference voltage.

[0016] In combination with any of the fourth to eighth implementations of the first aspect, in the ninth implementation of the first aspect, the first inductor, the third inductor and the fifth inductor are formed in the first multi-port inductor, and the second inductor, the fourth inductor and the sixth inductor are formed in the second multi-port inductor. The above scheme is simple to implement.

[0017] In a tenth implementation of the first aspect, combining the third or ninth implementation, the first multi-port inductor and the second multi-port inductor are arranged in a cross pattern on the layout. This arrangement helps improve noise immunity and reduce energy leakage from the inductors.

[0018] In conjunction with the first to tenth implementations of the first aspect, in the eleventh implementation of the first aspect, the first control signal or the second control signal can be a voltage signal or a digital signal. The oscillator to which the voltage signal is applied is a voltage-controlled oscillator. The oscillator to which the digital signal is applied is a mixed-signal oscillator.

[0019] A second aspect of this application provides a parallel structure for oscillators, comprising a plurality of oscillators as described in any one of the first to third implementations of the first aspect, wherein a plurality of first input terminals of the plurality of oscillators are coupled together, and a plurality of second input terminals of the plurality of oscillators are coupled together. This parallel structure can further reduce noise and improve performance.

[0020] A third aspect of this application provides a phase-locked loop, including an oscillator as described in any one of the first to tenth implementations of the first aspect, or a parallel structure of an oscillator as described in the second aspect.

[0021] The fourth aspect of this application provides a semiconductor chip, including an oscillator as described in any one of the first to tenth implementations of the first aspect, or a parallel structure of an oscillator as described in the second aspect, or a phase-locked loop as described in the third aspect. Optionally, the semiconductor chip is a radio frequency chip.

[0022] The fifth aspect of this application provides a communication device, including an oscillator as described in any one of the first to tenth implementations of the first aspect, or a parallel structure of an oscillator as described in the second aspect, or a phase-locked loop as described in the third aspect, or a semiconductor chip as described in the fourth aspect.

[0023] The above aspects or possible implementations of this application will become clearer and easier to understand in the following description of the embodiments. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a voltage-controlled oscillator in the prior art;

[0025] Figure 2 This is a schematic diagram of a radio frequency circuit according to an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the structure of a phase-locked loop in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of a voltage-controlled oscillator according to an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of another voltage-controlled oscillator in the embodiments of this application;

[0029] Figure 6 This is a schematic diagram of another voltage-controlled oscillator in the embodiments of this application;

[0030] Figure 7 This is a schematic diagram of various inverting amplification elements for a voltage-controlled oscillator in an embodiment of this application;

[0031] Figure 8 This is a schematic diagram of a pair of multi-port inductors used in a voltage-controlled oscillator according to an embodiment of this application;

[0032] Figure 9 This is a schematic diagram of a parallel structure of a voltage-controlled oscillator according to an embodiment of this application;

[0033] Figure 10 This is a schematic diagram of another voltage-controlled oscillator in the embodiments of this application;

[0034] Figure 11 This is a schematic diagram of a pair of multi-port inductors used in a voltage-controlled oscillator according to another embodiment of this application;

[0035] Figure 12 This is a schematic diagram of another voltage-controlled oscillator in the embodiments of this application;

[0036] Figure 13 This is a schematic diagram of a pair of multi-port inductors used in a voltage-controlled oscillator according to another embodiment of this application;

[0037] Figure 14 This is a schematic diagram of another voltage-controlled oscillator in the embodiments of this application;

[0038] Figure 15 This is a schematic diagram of a pair of multi-port inductors with a cross-arranged structure used in a voltage-controlled oscillator according to another embodiment of this application;

[0039] Figure 16 This is a schematic diagram of a pair of multi-port inductors with a cross-arranged structure, as described in another embodiment of this application. Detailed Implementation

[0040] To enable those skilled in the art to better understand the embodiments of this application, the technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The terms "first," "second," and "third," etc., in the specification, embodiments, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Thus, features defined with "first," "second," and "third" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more. In addition, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion, such as including a series of modules or units. The term "coupling" described in this embodiment can be used to realize the interconnection between different elements, components, or modules, including any form of electrical connection, such as direct contact, connection through wires or other devices, etc.

[0041] This application provides a communication device. The communication device can be a terminal, wireless router, wireless access point, base station, point-to-point communication device, short-range communication device, or other wireless communication device. The terminal includes, but is not limited to, mobile phones, tablets, wearable devices, vehicle-mounted devices, or IoT devices. The wireless communication device may internally include radio frequency circuitry. As an example, such as... Figure 2 As shown, the radio frequency circuit 01 can be used to receive and transmit wireless signals, and can also be called a wireless transceiver.

[0042] The aforementioned radio frequency circuit 01 is coupled to antenna 02. In this case, as... Figure 2 As shown, the RF circuit 01 includes a receiving path 10 for receiving signals on antenna 02 and a transmitting path 20 for transmitting signals to antenna 02. The receiving path 10 includes a low noise amplifier (LNA), a first mixer 100, an amplifier (AMP), a receiver (RX) baseband filter, and an analog-to-digital converter (ADC). The receiving path 10 converts the received RF carrier signal on antenna 02 into a digital domain intermediate frequency (IF) signal or a baseband signal. The transmitting path 20 includes a digital-to-analog converter (DAC), a transmitting filter, a second mixer 200, a pre-power amplifier (PPA), and a power amplifier (PA). The transmitting path 20 converts the digital domain IF signal or baseband signal into an RF carrier signal that can be transmitted on antenna 02.

[0043] In addition, the aforementioned radio frequency circuit 01, as Figure 2 As shown, it also includes a local oscillator generation circuit 30, which is coupled to the first mixer 100 in the receiving path 10 and the second mixer 200 in the transmitting path 20. The local oscillator generation circuit 30 provides the receiving path 10 with the local oscillator signal required for demodulation. The frequency of the local oscillator signal is mixed with the frequency of the radio frequency carrier signal received from the antenna 02 in the first mixer 100 of the receiving path 10, transforming it into an intermediate frequency (IF) signal or a baseband signal, thereby achieving signal demodulation. The local oscillator generation circuit 30 also provides the transmitting path 20 with the local oscillator signal required for modulation. The frequency of the local oscillator signal is mixed with the frequency of the IF signal or baseband signal output from the transmitting filter in the second mixer 200 of the transmitting path 20, transforming the IF signal or baseband signal into a radio frequency carrier signal that can be transmitted through the antenna 02, thereby achieving signal modulation. Optionally, Figure 2 Although only one local oscillator generation circuit 30 is shown, two local oscillator generation circuits can actually be used, so that each local oscillator generation circuit serves one of the receiving path 10 or the transmitting path 20, instead of as shown in the diagram. Figure 2 That would allow the receiving path 10 and the transmitting path 20 to share the local oscillator generation circuit, but this embodiment does not limit this.

[0044] The aforementioned local oscillator generation circuit 30 is as follows Figure 2As shown, a reference clock generator 300 is included for generating a reference clock signal. The reference clock generator 300 includes an oscillator for generating a reference clock and a reference clock circuit coupled to the oscillator, which generates the reference clock based on the reference clock. The local oscillator generation circuit 30 also includes a phase-locked loop 301 coupled to the reference clock generator 300.

[0045] The phase-locked loop 301 can acquire the phase difference between the input signal and the output signal O, and control the frequency and phase of the internal oscillation signal of the phase-locked loop 301, thereby enabling the phase-locked loop 301 to output an output signal O at a preset stable frequency. The input signal is the reference clock output by the reference clock generator 300. The phase-locked loop 301 can be used to output the output signal O based on the signal frequency of the reference clock output by the reference clock generator 300.

[0046] Furthermore, in order to ensure that the modulation and demodulation signals output by the local oscillator generation circuit 30 meet the product requirements, the local oscillator generation circuit 30 also includes a local oscillator (LO) circuit coupled to the phase-locked loop 301. This LO circuit can divide the frequency output by the phase-locked loop 301 and perform phase processing according to the requirements of the communication equipment, and finally generate the local oscillator signal as the aforementioned modulation and demodulation signals.

[0047] like Figure 3As shown, the phase-locked loop 301 includes a phase frequency detector (PFD) 311, a charge pump (CP) 321, a low-pass filter (LF) 331, a voltage-controlled oscillator (VCO) 341, and a divider 352. The PFD 311 obtains the phase difference between a reference clock provided by a reference clock generator 300 and the clock signal output by the divider 352, and provides a pulse control signal to the charge pump 321 based on this phase difference. The charge pump 321 generates a current signal matching the phase difference based on the pulse control signal. This current signal charges and discharges the low-pass filter 331. The low-pass filter 331 generates a control voltage Vc for the voltage-controlled oscillator 341 based on the current signal input from the charge pump 321. After receiving the control voltage Vc input from the low-pass filter 331, the voltage-controlled oscillator 341 can generate an output signal O of a corresponding frequency based on the control voltage Vc. Furthermore, the output signal O of the voltage-controlled oscillator 341 is frequency-divided by the frequency divider 352 in the feedback loop before being transmitted to the aforementioned frequency and phase detector 311. In this case, the frequency of the output signal O of the phase-locked loop 301 will gradually match the frequency of the reference clock signal provided by the reference clock generator 300, thereby achieving the goal of stabilizing the output signal O. Figure 3 The phase-locked loop 301 shown is an analog phase-locked loop, but Figure 3 For illustrative purposes only, it can be understood that the phase-locked loop 301 can also be a digital phase-locked loop or a hybrid digital-analog phase-locked loop, and this embodiment does not limit it in this way.

[0048] The above-described RF circuit 01 can be housed within one or more semiconductor chips. For example, the phase-locked loop 301 can be located on a single semiconductor chip along with the receiving path 10 and the transmitting path 20. Optionally, this semiconductor chip is an RF chip. Alternatively, the phase-locked loop can be located on a different semiconductor chip than the receiving path 10 or the transmitting path 20. In this RF circuit 01, the noise and pulling performance of the voltage-controlled oscillator 341 in the phase-locked loop 301 significantly affects the performance of the phase-locked loop 301, thereby affecting the performance of the entire RF circuit 01. Therefore, designing a voltage-controlled oscillator with good noise and pulling suppression performance becomes crucial. High-performance voltage-controlled oscillators can be well applied not only to the RF circuit 01 mentioned in this embodiment but also to other application scenarios.

[0049] As one embodiment of this application, Figure 4A schematic diagram of a voltage-controlled oscillator (VCO) implementation is provided. The VCO includes: a first inverting amplifier A1, a second inverting amplifier A2, a first inductor 41, a second inductor 42, a third inductor 43, and a first capacitor C1. The first inverting amplifier A1 includes a first input terminal VG1 and a first output terminal VD1. The second inverting amplifier A2 includes a second input terminal VG2 and a second output terminal VD2. The first inductor 41 is coupled between the first input terminal VG1 and the first output terminal VD1. The second inductor 42 is coupled between the second input terminal VG2 and the second output terminal VD2. The third inductor 43 is coupled between the first output terminal VD1 and the second output terminal VD2. The first capacitor C1, coupled between the first input terminal VG1 and the second input terminal VG2, receives a first voltage signal Vc, which is a first control signal, i.e., the control voltage in the previously mentioned phase-locked loop, used as the input voltage of the VCO to adjust the capacitance value of the first capacitor C1. The first signal output terminal O1 is coupled to the first inductive element 41 to output a first oscillation signal. The second signal output terminal O2 is coupled to the second inductive element 42 to output a second oscillation signal. The first signal output terminal O1 and the second signal output terminal O2 are symmetrically arranged, so that the first oscillation signal and the second oscillation signal form a differential output oscillation signal, which serves as the output signal O of the voltage-controlled oscillator. The frequency of this differential output oscillation signal changes with the capacitance value of the first capacitor C1, and is therefore controlled by the first voltage signal Vc. The positions of the first signal output terminal O1 and the second signal output terminal O2 are flexibly adjustable. For example, the first signal output terminal O1 is located at... Figure 4 The first signal output terminal O1 is located between the first inductive element 41 and the third inductive element 43, or coupled to the first output terminal VD1. Alternatively, the first signal output terminal O1 can also be located above the first inductive element 41, or coupled to the first input terminal VG1. The second signal output terminal O2 is located between the first inductive element 41 and the third inductive element 43, or coupled to the first output terminal VG1. Figure 4 The second signal output terminal O2 is coupled between the second inductive element 42 and the third inductive element 43, or in other words, coupled to the second output terminal VD2; alternatively, the second signal output terminal O2 may be coupled to the second inductive element 42 or coupled to the second input terminal VG2. Each inductive element in the above embodiments may include one or more inductors.

[0050] exist Figure 4In the illustrated technical solution, the first capacitor C1 is connected between the upper and lower signal paths. Each signal path includes an inverting amplification element and an inductive element, and the two signal paths are symmetrically arranged to obtain differential output. This halves the equivalent inductance and doubles the equivalent capacitance of the entire structure, increasing signal energy and thus providing better phase noise suppression characteristics. Because the inverting amplification elements in the two signal paths are configured with a self-feedback structure, compared to traditional voltage-controlled oscillators with cross-coupling structures, the current conversion efficiency is higher, contributing to better phase noise suppression characteristics. Furthermore, compared to traditional... Figure 1 For the voltage-controlled oscillator with cross-coupling structure shown, this structure also provides better anti-traction suppression characteristics. In particular, as the area of ​​the RF chip where the RF circuit 01 is located becomes smaller and smaller, and more and more RF paths are generated to support multiple-input multiple-output (MIMO), when multiple phase-locked loops operate simultaneously, they will generate traction between each other. The voltage-controlled oscillator provided in this embodiment can be well applied in phase-locked loops and helps to suppress the traction, thereby improving system performance.

[0051] Furthermore, in one implementation scheme, such as Figure 5 As shown, the first inductive element 41 includes a first inductor L1, the second inductive element 42 includes a second inductor L2, and the third inductive element 43 includes a third inductor L3. In another implementation, as... Figure 6 As shown, with Figure 5 Unlike other inductors, the third inductive element 43 includes a third inductor L3 and a fourth inductor L4, which are coupled to a second node having a second reference voltage V2.

[0052] For example, Figures 4 to 6The first capacitor C1 in the embodiment includes a variable capacitor, that is, a capacitor with a variable capacitance value whose capacitance value changes with the first voltage signal Vc. Alternatively, the first capacitor C1 can also be implemented using other capacitive elements with variable capacitance characteristics besides a variable capacitor, such as a switched-capacitor network or a variable-capacitor diode. Correspondingly, the first voltage signal Vc can be replaced by other types of control signals, such as switch control signals, such as digital logic signals, to change the state of one or more switches in the switched-capacitor network, thereby changing the coupling relationship of multiple capacitors in the switched-capacitor network and obtaining different capacitance values. The capacitors in the switched-capacitor network can be ordinary metal-oxide-metal (MOM) capacitors or metal-insulator-metal (MIM) capacitors, or MOS capacitors or parasitic capacitors; this embodiment does not limit this. The typical implementation of the capacitive element involved in this embodiment and subsequent embodiments is a capacitor, but this is not intended to limit it, as long as the capacitive element includes an element with a capacitance value, and optionally, the capacitance value can be changed by a control signal. The type of control signal depends on the type of capacitive element and can be digital or analog. For example, when the control signal is a voltage signal, it is used to adjust the capacitance value of a variable capacitor, realizing the function of a voltage-controlled oscillator (VCO). When the control signal is a digital signal, it can control the capacitance value of a switched-capacitor network, realizing digital control. In this case, the oscillator can be considered a hybrid digital-analog oscillator. Digitally controlled oscillators can be applied in digital phase-locked loops (PLLs), which can replace... Figure 3 The example shown is an analog phase-locked loop. Specific implementation schemes for digital phase-locked loops can be found in existing technologies, and will not be elaborated upon here.

[0053] Combination Figure 6 The structure, Figure 7 (A) and Figure 7 (B) illustrates two implementations of two inverting amplifier elements A1 and A2, which are applied to... Figure 6 The structure is as follows: The first inverting amplifier element A1 includes a first MOS transistor, the first input terminal VG1 is the gate of the first MOS transistor, and the first output terminal VD1 is the drain of the first MOS transistor. The second inverting amplifier element A2 includes a second MOS transistor, the second input terminal VG2 is the gate of the second MOS transistor, and the second output terminal VD2 is the drain of the second MOS transistor. Figure 7In (A), the first MOS transistor and the second MOS transistor are NMOS transistors Mn1 and Mn2. The first reference voltage input to the sources of the two NMOS transistors Mn1 and Mn2 is either ground voltage GND or zero voltage. Figure 6 The second reference voltage V2 can be a reference voltage source VDD. Figure 7 In (B), the first MOS transistor and the second MOS transistor are PMOS transistors Mp1 and Mp2. The first reference voltage input to the sources of the two PMOS transistors Mp1 and Mp2 is a constant reference voltage source VDD; therefore, the second reference voltage V2 can be ground voltage. Figure 7 (A) or Figure 7 In (B), since the sources of the transistors in the two inverting amplification elements A1 and A2 are only coupled to the first node with the first reference voltage, and the drains of the transistors in the two inverting amplification elements A1 and A2 are coupled to the second node with the second reference voltage through the third inductor L3 and the fourth inductor L4, a voltage difference is formed between the two reference voltages. This voltage difference forms a current path between the two reference voltages. Figure 7 (A) or Figure 7 The two inverting amplifier elements A1 and A2 shown in (B) can be well applied to applications such as... Figure 6 In the structure shown.

[0054] Figure 7 (A) or Figure 7 (B) uses a MOS transistor to implement the inverting amplification function. In an alternative implementation, the MOS transistor can be replaced by other types of amplifying devices. Furthermore, combined with... Figure 5 The structure, in Figure 5 In this configuration, since the third inductor L3 is not coupled to any node with a reference voltage, the two inverting amplifying elements A1 and A2 do not form a current path from the reference voltage source VDD to the ground voltage GND through the third inductor L3. Each of the two inverting amplifying elements A1 and A2 can then include a CMOS inverter coupled between a first node with a first reference voltage and a second node with a second reference voltage. The first reference voltage can be one of the reference voltage source VDD and the ground voltage GND, and the second reference voltage is the other of the reference voltage source VDD and the ground voltage GND. The specific implementation is as follows... Figure 7 As shown in (C), the first inverting amplification element A1 includes a first CMOS inverter coupled between a node having a reference voltage source VDD and a node having a ground voltage GND. The second inverting amplification element A2 includes a second CMOS inverter coupled between the node having the reference voltage source VDD and the node having the ground voltage GND.

[0055] exist Figure 7 In (C), the first CMOS inverter includes a PMOS transistor Mp1 and an NMOS transistor Mn1 connected in series. The second CMOS inverter includes a PMOS transistor Mp2 and an NMOS transistor Mn2 connected in series. The gates of PMOS transistor Mp1 and NMOS transistor Mn1 are coupled together and serve as the first input terminal VG1 of the first CMOS inverter. The drains of PMOS transistor Mp1 and NMOS transistor Mn1 are coupled together and serve as the first output terminal VD1 of the first CMOS inverter. The gates of PMOS transistor Mp2 and NMOS transistor Mn2 are coupled together and serve as the second input terminal VG2 of the second CMOS inverter. The drains of PMOS transistor Mp2 and NMOS transistor Mn2 are coupled together and serve as the second output terminal VD2 of the second CMOS inverter. In this example, each CMOS inverter has its own current path from the reference voltage source VDD to the ground voltage GND, which can support, for example, Figure 5 The structure shown.

[0056] for Figure 6 Specifically, the first inductor L1 and the third inductor L3 can be two inductors formed by wires. These two inductors L1 and L3 can be independent inductors, i.e., formed by two independent segments of wire. Alternatively, these two inductors L1 and L3 can be combined into a single multi-port inductor, where both inductors L1 and L3 are formed by a single segment of wire, with different inductors corresponding to different parts of that wire, simplifying implementation. The implementation of the second inductor L2 and the fourth inductor L4 is similar to that of the first inductor L1 and the third inductor L3, and will not be elaborated upon. Optionally, if the two inductors L1 and L3 are implemented using independent inductors, each inductor can also be implemented using an off-chip inductor.

[0057] For solutions using multi-port inductors, please refer to the following for details. Figure 8 The first inductor L1 and the second inductor L2 are formed in a first multi-port inductor LX, which is a conductor with multiple ports (or taps) for coupling to a first input terminal VG1, a first output terminal VD1, and a second node having a second reference voltage V2. The third inductor L3 and the fourth inductor L4 are formed in a second multi-port inductor LY, which is a conductor with multiple ports for coupling to a second input terminal VG2, a second output terminal VD2, and a second node having a second reference voltage V2. The second nodes having the second reference voltage V2 on the two conductors are as follows: Figure 6The two multi-port inductors shown can be coupled to each other. The first multi-port inductor LX and the second multi-port inductor LY are structurally symmetrical, forming a pair of multi-port inductors, thus enabling the voltage-controlled oscillator to form a differential structure. It is important to understand that... Figure 3 The voltage-controlled oscillator 341 shown does not display a differential signal; in reality, the output signal O generated by the voltage-controlled oscillator 341 can include... Figure 4 , Figure 5 , Figure 6 , Figure 9 , Figure 10 , Figure 12 or Figure 14 The first oscillation signal output from the first signal output terminal O1 and the second oscillation signal output from the second signal output terminal O2 shown in the figure, that is, the output signal O of the voltage-controlled oscillator 341 can be a differential signal.

[0058] It is necessary to understand that this appendix... Figure 8 The shape of the wire can be a straight line as shown in the figure, or it can be other forms, such as an arc or a coil. This embodiment does not limit this. Figure 8 The schematic diagram is for illustrative purposes only. In the above embodiments, inductors are formed using wires, which is flexible, convenient, and low-cost.

[0059] Another embodiment of this application provides a parallel structure for a voltage-controlled oscillator, see details below. Figure 9 The parallel structure includes n such as Figure 6 The voltage-controlled oscillators (VCOs) shown are VCO1 to VCON, where n is the number of VCOs in the parallel structure, specifically an integer greater than 1; an exemplary value for n is 2. The multiple first input terminals VG1 of the n VCOs are coupled together, and the multiple second input terminals VG2 of the n VCOs are coupled together. The first capacitor C1 in each of the n VCOs receives a first voltage signal Vc. The first signal output terminals O1 of the n VCOs are coupled together, and the second signal output terminals O2 of the n VCOs are coupled together, thus enabling the n VCOs to operate in parallel. This parallel structure can further reduce system noise and improve performance. It should be noted that this parallel structure is only used in... Figure 6 Taking a voltage-controlled oscillator as an example, the voltage-controlled oscillator used in practical applications can also be... Figure 4 or Figure 5 The voltage-controlled oscillator in this embodiment is not limited.

[0060] Another embodiment of this application provides a voltage-controlled oscillator, such as Figure 10As shown, the voltage-controlled oscillator includes: a first inverting amplification element A1, a second inverting amplification element A2, a third inverting amplification element A3, and a fourth inverting amplification element A4. The first inductive element 41 includes a first inductor L1 and a fifth inductor L5; the second inductive element 42 includes a second inductor L2 and a sixth inductor L6; and the third inductive element 43 includes a third inductor L3 and a fourth inductor L4. The voltage-controlled oscillator also includes a first capacitor C1 and a second capacitor C2. Figure 10 Voltage-controlled oscillator and Figure 6 The structural difference lies in the addition of two inverting amplification elements, A3 and A4. Furthermore, the third inductor L3 and the fourth inductor L4 in the third inductive element 43 are not directly connected but coupled through the two inverting amplification elements A3 and A4. This structure is equivalent to connecting the first inverting amplification element A1 and the third inverting amplification element A3 in series, and connecting the second inverting amplification element A2 and the fourth inverting amplification element A4 in series. This allows current to circulate between the first inverting amplification element A1 and the third inverting amplification element A3, and between the second inverting amplification element A2 and the fourth inverting amplification element A4, achieving current multiplexing, improving current utilization efficiency, increasing swing, and further improving noise suppression characteristics.

[0061] exist Figure 10 In this configuration, the third inverting amplifier A3 includes a third input terminal VG3 and a third output terminal VD3; the fourth inverting amplifier A4 includes a fourth input terminal VG4 and a fourth output terminal VD4; and the second capacitor C2 is coupled between the third input terminal VG3 and the fourth input terminal VG4. The first inductor L1 is coupled between the first input terminal VG1 and the third output terminal VD3; the second inductor L2 is coupled between the second input terminal VG2 and the fourth output terminal VD4; the third inductor L3 is coupled between the first output terminal VD1 and the third input terminal VG3; the fourth inductor L4 is coupled between the second output terminal VD2 and the fourth input terminal VG4; the fifth inductor L5 is coupled between the first output terminal VD1 and the third output terminal VD3; and the sixth inductor L6 is coupled between the second output terminal VD2 and the fourth output terminal VD4.

[0062] exist Figure 10 In this design, the upper and lower signal paths give the voltage-controlled oscillator (VCO) a differential structure as a whole. For example, the upper signal path includes a first inverting amplifier A1, a third inverting amplifier A3, a first inductor L1, a third inductor L3, and a fifth inductor L5, allowing current to circulate between the first and third inverting amplifiers A1 and A3, achieving current multiplexing. The lower and upper signal paths are symmetrically arranged to achieve differential operation. Figure 6Similarly, the first capacitor C1 is coupled between the first input terminal VG1 and the second input terminal VG2, that is, it is connected across the two signal paths; furthermore, in Figure 10 In the middle, the second capacitor C2 is coupled between the third input terminal VG3 and the fourth input terminal VG4, that is, it is connected across the two signal paths.

[0063] exist Figure 10 In this configuration, both the first capacitor C1 and the second capacitor C2 can be controlled to change their capacitance values. For example, the second capacitor C2 is controlled by a second voltage signal, which is used to adjust the capacitance value of the second capacitor. Similar to the first voltage signal Vc, this second voltage signal is a second control signal. The two control signals adjust the capacitance values ​​of the two capacitors respectively to regulate the frequency of the output signal of the voltage-controlled oscillator, improving the flexibility of adjustment. In this case, refer to... Figure 3 The control signal Vc input to the voltage-controlled oscillator 314 is two, namely, a first voltage signal Vc and a second voltage signal. Figure 3 Although this is shown, it does not affect the implementation of the technical solution.

[0064] Furthermore, optionally, if the voltage-controlled oscillator 314 is implemented as a digitally controlled oscillator, the control signal also includes two digital control signals, and the corresponding capacitive element includes a controllable switch-capacitor network, as described in the previous embodiments, which will not be repeated here.

[0065] Alternatively, in this embodiment, only one of the two capacitors may be adjustable, while the other is not adjusted by the control signal. For example, the first capacitor C1 is controlled by the first voltage signal, but the second capacitor C2 is a component with a fixed capacitance value, which does not affect the implementation of this embodiment.

[0066] right Figure 10 In the voltage-controlled oscillator (VCO), the first signal output terminal O1 can be coupled to either the first inductor L1 or the fifth inductor L5, and the second signal output terminal O2 can be coupled to either the second inductor L2 or the sixth inductor L6, with the first and second signal output terminals O1 and O2 symmetrically arranged. As mentioned earlier, coupling is a broad term for connection, including direct or indirect connections. Therefore, the first signal output terminal O1 can be located on any inductor or at any end of that inductor in the upper signal path, and the arrangement of the second signal output terminal O2 is similar. For example, in... Figure 10 The first signal output terminal O1 is coupled between the first inductor L1 and the fifth inductor L5, or in other words, coupled to the third output terminal VD3; the second signal output terminal O2 is coupled between the second inductor L2 and the sixth inductor L6, or in other words, coupled to the fourth output terminal VD4. Alternatively, such as... Figure 12 As shown, different Figure 10 The first signal output terminal O1 and the second signal output terminal O2 can be respectively located on the fifth inductor L5 and the sixth inductor L6. Alternatively, the first signal output terminal O1 can be set as the first input terminal VG1 or the first output terminal VD1, in which case the second signal output terminal O2 can be set as the second input terminal VG2 or the second output terminal VD2. This embodiment does not limit this. In this embodiment, any signal output terminal needs to be set on the corresponding signal path so that the oscillation signal in the signal path can be output to the outside through the signal output terminal.

[0067] exist Figure 10 or Figure 12 Each of the first inductor L1, second inductor L2, third inductor L3, fourth inductor L4, fifth inductor L5, and sixth inductor L6 is an independent inductor, meaning each inductor is formed by an independent segment of wire. Alternatively, if these inductors are implemented using independent inductors, each inductor can also be implemented using an off-chip inductor. In another implementation scheme, it can be combined with... Figure 8 A similar approach uses multi-port inductors, where multiple inductors can be formed from a single piece of wire, making it simple to implement. Figure 11 Detailed demonstration Figure 10 The implementation of multiple inductors within the structure is as follows: the first inductor L1, the third inductor L3, and the fifth inductor L5 are formed in the first multi-port inductor LX, and the second inductor L2, the fourth inductor L4, and the sixth inductor L6 are formed in the second multi-port inductor LY. This pair of multi-port inductors, LX and LY, are symmetrically arranged. Each multi-port inductor is a segment of wire. Figure 11 The shape of the wires used is not limited; besides the straight shape shown in the figure, they can also be curved or in the form of coils. Forming inductors using wires offers flexible and convenient design at a low cost. Specifically... Figure 11 In the first multi-port inductor LX, there are a first input terminal VG1, a first output terminal VD1, a third input terminal VG3, and a third output terminal VD3; the second multi-port inductor LY includes a second input terminal VG2, a second output terminal VD2, a fourth input terminal VG4, and a fourth output terminal VD4. For Figure 10 In the voltage-controlled oscillator structure, the first signal output terminal O1 and the second signal output terminal O2 can be coupled to, or in other words, the third output terminal VD3 and the fourth output terminal VD4, respectively.

[0068] Furthermore, Figure 13 Showing Figure 12 The implementation method of multiple inductors within the structure, and Figure 11 The difference is that, Figure 13The first signal output terminal O1 and the second signal output terminal O2 are not the third output terminal VD3 and the fourth output terminal VD4, but are instead led out from the fifth inductor L5 and the sixth inductor L6 respectively, so that the first signal output terminal O1 and the second signal output terminal O2 are symmetrically arranged. Figure 12 The voltage-controlled oscillator shown has two signal paths, one above the other. Therefore, Figure 13 Multi-port inductors Figure 11 The two multi-port inductors have two additional signal output ports, but this does not affect the effectiveness of the embodiment. The ports mentioned above can also be called taps.

[0069] Figure 14 This is a schematic diagram of another differential voltage-controlled oscillator provided in an embodiment of this application, and... Figure 10 The difference is that, Figure 14 The voltage-controlled oscillator employs a method where inductors in the upper and lower paths are interleaved, and its circuit topology is similar to... Figure 10 In essence, nothing has changed, but in terms of map implementation, Figure 14 The settings of multiple inductors in the voltage-controlled oscillator have changed. Specifically, as follows... Figure 15 As shown, the first multi-port inductor LX and the second multi-port inductor LY have a cross-arrangement structure, such that the first signal path, including the first inverting amplification element A1, the third inverting amplification element A3, the first inductor L1, the second inductor L2, and the fifth inductor L5, and the second signal path, including the second inverting amplification element A2, the fourth inverting amplification element A4, the third inductor L3, the fourth inductor L4, and the sixth inductor L6, intersect on the layout. That is to say, Figure 15 The two multi-port inductors LX and LY shown employ a figure-eight coupling structure. The intersection of the figure-eight is located at... Figure 15 The fifth inductor L5 and the sixth inductor L6 are located in the middle. This figure-eight layout design helps improve the anti-interference capability of the voltage-controlled oscillator and reduce the energy leakage of the inductors.

[0070] Figure 16 A layout schematic of a pair of figure-eight multiport inductors with a cross-arranged structure is given, and... Figure 8 , 11 The map illustrations shown in 13 or 15 are different. Figure 16 The wires forming the multi-port inductor in the layout are not direct, but have specific characteristics, but this does not change the essence of the technical solution.

[0071] Figure 10 , 12In capacitors 1 and 14, both the first capacitor C1 and the second capacitor C2 can be variable capacitors, or only one of them can be a variable capacitor. The variable capacitor can receive the input signal of the voltage-controlled oscillator and be controlled by the input signal to change the frequency of the output signal of the voltage-controlled oscillator. As mentioned above, any variable capacitor can also be implemented by other elements with variable capacitance characteristics, such as a switched-capacitor network or a variable-capacitor diode. Exemplarily, the state of one or more switches in the switched-capacitor network can be controlled by the input signal to change the capacitance value of the switched-capacitor network; this embodiment is not limited to this.

[0072] Figure 10 , 12 The implementation methods of the multiple inverting amplification elements involved in section 14 can be further referred to. Figure 7 The structure shown Figure 7 (A) Figure 7 (B) and Figure 7 (C) illustrates three different differential structure inverting amplifier designs. Specifically, Figure 10 For example, the first inverting amplification element A1 and the second inverting amplification element A2 form a differential structure, and the third inverting amplification element A3 and the fourth inverting amplification element A4 form another differential structure.

[0073] Combination Figure 10 , 12 For example, the first inverting amplification element A1 and the second inverting amplification element A2 can be adopted as follows: Figure 7 In the differential structure implemented by the NMOS transistor in (A), the source of the NMOS transistor is connected to the first reference voltage, which is ground voltage GND. Therefore, the third inverting amplification element A3 and the fourth inverting amplification element A4 can be implemented as follows: Figure 7 In (B), the differential structure implemented with a PMOS transistor has its source connected to the input second reference voltage, which is the reference voltage source VDD. Conversely, in another example, the first inverting amplification element A1 and the second inverting amplification element A2 can be implemented as follows: Figure 7 In the differential structure implemented by the PMOS transistor in (B), the source of the PMOS transistor is connected to the input first reference voltage source VDD. Then, the third inverting amplification element A3 and the fourth inverting amplification element A4 can be implemented as follows: Figure 7 In (A), the differential structure is implemented by an NMOS transistor, and the source of the NMOS transistor is connected to the second reference voltage input, which is the ground voltage GND.

[0074] Or, combine Figure 10 , 12 In another example, and 14, the first inverting amplification element A1 and the second inverting amplification element A2 employ... Figure 7In the CMOS inverter structure in (C), the third inverting amplification element A3 and the fourth inverting amplification element A4 also adopt... Figure 7 The CMOS inverter structure in (C) involves a CMOS inverter coupled between a first node having a first reference voltage and a second node having a second reference voltage. Exemplarily, the first reference voltage is a reference voltage source VDD, and the second reference voltage is ground voltage GND. Specifically, the CMOS inverter includes a PMOS transistor and an NMOS transistor connected in series. The drains of the PMOS transistor and the NMOS transistor are coupled as the output terminal of the CMOS inverter. The source of the PMOS transistor receives the reference voltage source VDD, the source of the NMOS transistor receives the ground voltage GND, and the gates of the PMOS transistor and the NMOS transistor are coupled as the input terminal of the CMOS inverter. A detailed description of the CMOS inverter structure can be found in the previous embodiments and will not be repeated here.

[0075] The inverting amplification elements described in the above embodiments employ the simplest NMOS transistor, PMOS transistor, or CMOS inverter structure. Using a single NMOS or PMOS transistor to achieve amplification results in a simple design, while using a CMOS inverter improves performance. Alternatively, the inverting amplification element can also employ a more complex inverting amplifier structure, such as including components other than MOS transistors, including bipolar transistors. The inductors described in the above embodiments can be implemented using methods other than wires, i.e., they can be implemented using other types of processes or components, such as using off-chip inductors.

[0076] The above embodiments have provided an exemplary description of the technical solution of this application. Compared to traditional solutions, the related solutions offer better phase noise suppression and pull-out suppression characteristics. For example, the related inverting amplification element can be based on a PMOS transistor, NMOS transistor, or CMOS inverter, forming an AB-class structure. This allows any transistor to operate between 100% and 50% conduction, resulting in better current conversion efficiency than traditional solutions and thus achieving superior phase noise characteristics. Furthermore, the above structure is simple to implement, and the solution in this embodiment also has advantages over traditional solutions in terms of area and power consumption.

[0077] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application. For example, some specific operations in the device embodiments can be referred to the previous method embodiments.

Claims

1. An oscillator, characterized in that, include: The first inverting amplifier element includes a first input terminal and a first output terminal; The second inverting amplifier element includes a second input terminal and a second output terminal; A first inductive element is coupled between the first input terminal and the first output terminal; A second inductive element is coupled between the second input terminal and the second output terminal; A third inductive element is coupled between the first output terminal and the second output terminal; A first capacitive element, coupled between the first input terminal and the second input terminal, is used to receive a first control signal, which is used to adjust the capacitance value of the first capacitive element. The first signal output terminal is coupled to the first inductive element to output the first oscillation signal; The second signal output terminal is coupled to the second inductive element to output a second oscillation signal, and the first oscillation signal and the second oscillation signal are differential output oscillation signals; The first inductive element includes a first inductor and a fifth inductor, the second inductive element includes a second inductor and a sixth inductor, and the third inductive element includes a third inductor and a fourth inductor. The oscillator also includes: The third inverting amplifier element includes a third input terminal and a third output terminal; The fourth inverting amplifier element includes a fourth input terminal and a fourth output terminal; A second capacitive element is coupled between the third input terminal and the fourth input terminal; wherein... The first inductor is coupled between the first input terminal and the third output terminal, the second inductor is coupled between the second input terminal and the fourth output terminal, the third inductor is coupled between the first output terminal and the third input terminal, the fourth inductor is coupled between the second output terminal and the fourth input terminal, the fifth inductor is coupled between the first output terminal and the third output terminal, and the sixth inductor is coupled between the second output terminal and the fourth output terminal.

2. The oscillator according to claim 1, characterized in that, The first inverting amplification element includes a first MOS transistor, the first input terminal is the gate of the first MOS transistor, the first output terminal is the drain of the first MOS transistor, and the source of the first MOS transistor is used to input a first reference voltage. The second inverting amplification element includes a second MOS transistor, the second input terminal is the gate of the second MOS transistor, the second output terminal is the drain of the second MOS transistor, and the source of the second MOS transistor is used to input the first reference voltage.

3. The oscillator according to claim 1, characterized in that, The first inverting amplification element includes a first CMOS inverter, which is coupled between a first node having a first reference voltage and a second node having a second reference voltage; The second inverting amplification element includes a second CMOS inverter coupled between the first node having a first reference voltage and the second node having a second reference voltage.

4. The oscillator according to claim 2, characterized in that, The first inductor and the third inductor are formed in the first multi-port inductor, and the second inductor and the fourth inductor are formed in the second multi-port inductor.

5. The oscillator according to claim 1, characterized in that, The second capacitive element is used to receive a second control signal, which is used to adjust the capacitance value of the second capacitive element.

6. The oscillator according to claim 1, characterized in that, The first inverting amplification element includes a first MOS transistor, the first input terminal is the gate of the first MOS transistor, the first output terminal is the drain of the first MOS transistor, and the source of the first MOS transistor is used to input a first reference voltage. The second inverting amplifier includes a second MOS transistor, the second input terminal is the gate of the second MOS transistor, the second output terminal is the drain of the second MOS transistor, and the source of the second MOS transistor is used to input the first reference voltage; The third inverting amplification element includes a third MOS transistor, the third input terminal is the gate of the third MOS transistor, the third output terminal is the drain of the third MOS transistor, the source of the third MOS transistor is used to input a second reference voltage, and the third MOS transistor and the first MOS transistor are complementary transistors. The fourth inverting amplification element includes a fourth MOS transistor, the fourth input terminal is the gate of the fourth MOS transistor, the fourth output terminal is the drain of the fourth MOS transistor, the source of the fourth MOS transistor is used to input the second reference voltage, and the fourth MOS transistor and the second MOS transistor are complementary transistors.

7. The oscillator according to claim 1, characterized in that, The first inverting amplification element includes a first CMOS inverter, which is coupled between a first node having a first reference voltage and a second node having a second reference voltage; The second inverting amplification element includes a second CMOS inverter, which is coupled between the first node having a first reference voltage and the second node having a second reference voltage; The third inverting amplification element includes a third CMOS inverter, which is coupled between the first node having a first reference voltage and the second node having a second reference voltage. The fourth inverting amplification element includes a fourth CMOS inverter, which is coupled between the first node having a first reference voltage and the second node having a second reference voltage.

8. The oscillator according to claim 1, characterized in that, The first inductor, the third inductor, and the fifth inductor are formed in the first multi-port inductor, and the second inductor, the fourth inductor, and the sixth inductor are formed in the second multi-port inductor.

9. The oscillator according to claim 4 or 8, characterized in that, The first multiport inductor and the second multiport inductor are arranged in a cross pattern on the layout.

10. The oscillator according to claim 3, 6 or 7, characterized in that, One of the first reference voltage and the second reference voltage is a ground voltage, and the other is a reference voltage source.

11. A semiconductor chip, characterized in that, Including the oscillator as described in any one of claims 1 to 10.

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