Communication signal processing method, device, electronic device and storage medium

Abstract

The present invention relates to the field of communication technology, and in particular to a communication signal processing method, device, electronic device and storage medium, wherein the method comprises: obtaining a preset zero insertion sequence, determining the storage space required for FFT operation; obtaining a data element from a signal data group to be inserted with zeros in sequence, and determining the number of zeros to be continuously inserted before the data element based on the current zero insertion sequence as a storage unit offset; storing the data element in a corresponding storage unit after the offset; updating the current zero insertion sequence, and returning until all the signal data groups to be inserted with zeros are stored in the storage space, and an array prepared for completing the FFT operation is obtained; based on the obtained zero insertion sequence, the array prepared for completing the FFT operation in the storage space is sequentially read to obtain an array for FFT operation; performing signal processing through FFT operation, and storing the result array obtained by processing in sequence in the storage space. The present invention can improve the efficiency of communication signal processing.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communication technology, and in particular to a communication signal processing method, device, FFT operation array zero insertion method, electronic device and storage medium. Background Art

[0002] The FFT (Fast Fourier Transformation) method is widely used in fields such as communication signal processing and is the most common method for extracting signal information. The essence of FFT operation is to divide the discrete Fourier transform calculation of a long sequence into short sequence calculations. According to the different segmentation sequences, there are different methods such as radix 2, radix 4, radix 8, etc. Different methods have corresponding requirements for the number of FFT operation points, and sequences that do not meet the operation requirements need to be padded with zeros. In addition, due to the existence of signal sampling resolution, within a limited number of points, it is also necessary to insert zeros between sampled data to improve the resolution. At present, in the process of communication signal processing, in order to adapt to different FFT operation requirements, it is often necessary to pre-process the original signal data with zero insertion, which will increase the signal processing time and reduce the signal processing efficiency.

[0003] Therefore, a communication signal processing method is needed that can quickly complete FFT operation data preparation. Summary of the invention

[0004] In response to at least some of the above-mentioned shortcomings, an embodiment of the present invention provides a communication signal processing method, device, FFT operation array zero insertion method, electronic device and storage medium, which can save time in preparing FFT operation data by quickly inserting zeros, thereby improving the communication signal processing efficiency.

[0005] In a first aspect, an embodiment of the present invention provides a communication signal processing method, comprising the following steps:

[0006] S1. Obtain a preset zero-insertion sequence and determine the storage space required for FFT operation; wherein the number of digits in the zero-insertion sequence is the same as the number of storage units in the storage space, and each digit in the zero-insertion sequence is distinguished by a single-bit binary number to mark the zero-insertion bit and the signal data bit;

[0007] S2, sequentially obtaining a data element from the signal data group to be inserted with zeros, and determining the number of zeros that need to be continuously inserted before the data element based on the current zero insertion sequence, as a storage unit offset;

[0008] S3, based on the determined storage unit offset, storing the acquired data element into the corresponding storage unit after the offset;

[0009] S4, based on the determined storage unit offset, update the current zero insertion sequence, and return to step S2, until all the signal data groups to be zero-inserted are stored in the storage space, and an array ready for completing the FFT operation is obtained;

[0010] S5. Based on the zero-insertion sequence obtained in step S1, sequentially read the arrays prepared for completing the FFT operation in the storage space to obtain the arrays used for the FFT operation;

[0011] S6. Perform signal processing through FFT operation, and store the result array obtained by processing into the storage space in order.

[0012] Optionally, determining the number of zeros that need to be continuously inserted before the data element based on the current zero insertion sequence includes:

[0013] By using the binary search method, the number of digits continuously marked as zero insertion bits starting from the start bit of the current zero insertion sequence is determined as the number of zeros that need to be continuously inserted.

[0014] Optionally, updating the current zero insertion sequence based on the determined storage unit offset includes:

[0015] If the number of storage unit offsets is Nz, the first (Nz+1) bits of the current zero insertion sequence are deleted, and (Nz+1) signal data bits are added at the end.

[0016] Optionally, the step of determining the number of digits of the current zero-insertion sequence that are continuously marked as zero-insertion bits starting from the start bit by using a binary search method comprises the following steps:

[0017] A1. Set the current zero insertion sequence as the search sequence, and clear the current number of zeros that need to be inserted continuously;

[0018] A2. If the length of the current search sequence is greater than 1, determine whether the first half of the current search sequence is all zero-inserted bits. If yes, execute step A3; otherwise, execute step A4.

[0019] If the current search sequence length is equal to 1, determine whether the digit is a zero insertion digit. If so, increase the number of consecutive zero insertions by 1 and end the search. Otherwise, end the search directly.

[0020] A3, increasing the length of the first half of the current search sequence by the number of consecutively inserted zeros, taking the second half of the current search sequence as a new search sequence, and returning to step A2;

[0021] A4. Use the first half of the current search sequence as a new search sequence and return to step A2.

[0022] In a second aspect, an embodiment of the present invention further provides a communication signal processing device, including:

[0023] A preparation module, used to obtain a preset zero-insertion sequence and determine the storage space required for FFT operation; wherein the number of digits of the zero-insertion sequence is the same as the number of storage units in the storage space, and each digit of the zero-insertion sequence is distinguished by a single-bit binary number to mark the zero-insertion bit and the signal data bit;

[0024] A zero insertion module is used to sequentially obtain a data element from the signal data group to be inserted with zeros, and determine the number of zeros that need to be continuously inserted before the data element based on the current zero insertion sequence as a storage unit offset;

[0025] A storage module, used for storing the acquired data element into a corresponding storage unit after the offset based on the determined storage unit offset;

[0026] An updating module, used for updating the current zero insertion sequence based on the determined storage unit offset, and calling the zero insertion module until all signal data groups to be zero-inserted are stored in the storage space, thereby obtaining an array ready for completing the FFT operation;

[0027] A reading module, configured to sequentially read the array prepared for the FFT operation in the storage space based on the zero insertion sequence obtained by the preparation module, to obtain an array for the FFT operation;

[0028] The operation module is used to perform signal processing through FFT operation and store the result array obtained by processing into the storage space in sequence.

[0029] Optionally, the zero insertion module determines the number of zeros that need to be continuously inserted before the data element based on the current zero insertion sequence, including performing the following operations:

[0030] By using the binary search method, the number of digits continuously marked as zero insertion bits starting from the start bit of the current zero insertion sequence is determined as the number of zeros that need to be continuously inserted.

[0031] Optionally, the updating module updates the current zero insertion sequence based on the determined storage unit offset, including performing the following operations:

[0032] If the number of storage unit offsets is Nz, the first (Nz+1) bits of the current zero insertion sequence are deleted, and (Nz+1) signal data bits are added at the end.

[0033] In a third aspect, an embodiment of the present invention further provides a method for inserting zeros in an FFT operation array, comprising the following steps:

[0034] Obtain a preset zero insertion sequence and determine the storage space required for FFT operation;

[0035] Sequentially obtain a data element from the signal data group to be inserted with zeros, and determine the number of zeros that need to be inserted continuously before the data element based on the current zero insertion sequence as a storage unit offset;

[0036] Based on the determined storage unit offset, the acquired data element is stored in the corresponding storage unit after the offset;

[0037] Based on the determined storage unit offset, the current zero insertion sequence is updated, and the step of sequentially acquiring a data element from the signal data group to be inserted with zero is returned until all the signal data groups to be inserted with zero are stored in the storage space, thereby obtaining an array ready for completing the FFT operation.

[0038] In a fourth aspect, an embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the method described in any embodiment of this specification is implemented.

[0039] In a fifth aspect, an embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed in a computer, the computer is caused to execute the method described in any embodiment of this specification.

[0040] The embodiments of the present invention provide a communication signal processing method, device, FFT operation array zero insertion method, electronic device and storage medium. The present invention stores and reads data based on a preset zero insertion sequence. When storing, the signal data group to be zero-inserted is stored according to the zero-insertion result interval, and there is no need to calculate and generate the actual storage address of the data. When reading, 0 is directly read at the zero-inserted position and the corresponding data is read at the non-zero-inserted position. During the whole process, the acquired signal data group can be written continuously, and there is no need to actually write 0 in the storage space, which reduces the difficulty of data address calculation, has high efficiency, and can meet different FFT operation requirements. It has strong flexibility and can effectively save the time of preparing FFT operation data, thereby improving the communication signal processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 is a flow chart of a communication signal processing method provided by one embodiment of the present invention;

[0043] FIG. 2( a ) is a schematic diagram of a communication signal processing method storing a signal data group provided by an embodiment of the present invention;

[0044] FIG2( b ) is a schematic diagram of a communication signal processing method for reading a signal data group provided by an embodiment of the present invention;

[0045] Figure 3 is a hardware architecture diagram of an electronic device provided by an embodiment of the present invention;

[0046] Figure 4 is a structural diagram of a communication signal processing device provided by an embodiment of the present invention;

[0047] Figure 5 The present invention provides a flowchart of a method for inserting zeros in an FFT operation array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0049] As mentioned above, FFT operations are often used to extract signal information during the processing of communication signals (including radar detection signals). In order to adapt to different FFT operation requirements, it is necessary to pre-process the original signal data with zero insertion, and this FFT operation data preparation process will inevitably increase the signal processing time and reduce the signal processing efficiency. In order to improve the signal processing efficiency, it is necessary to minimize the zero insertion pre-processing process of preparing FFT operation data. At present, there is no fast zero insertion technology for FFT operation data preparation in the prior art.

[0050] In view of this, the present invention proposes a communication signal processing method that can quickly complete FFT operation data preparation. The method has high efficiency and low time consumption in zero insertion preprocessing. It can save time in preparing FFT operation data by quickly inserting zeros, thereby improving the communication signal processing efficiency.

[0051] The specific implementation of the above concept is described below.

[0052] Please refer to Figure 1 , an embodiment of the present invention provides a communication signal processing method, the method comprising:

[0053] Step 100, obtain a preset zero-insertion sequence and determine the storage space required for FFT operation; wherein the number of digits in the zero-insertion sequence is the same as the number of storage units contained in the storage space, and each digit of the zero-insertion sequence is distinguished by a single-bit binary number to mark the zero-insertion bit and the signal data bit, that is, a single-bit 1 represents the zero-insertion bit and a single-bit 0 represents the signal data bit, or a single-bit 0 represents the zero-insertion bit and a single-bit 1 represents the signal data bit.

[0054] Different FFT operations have different requirements for arrays, and the lengths of the original signal data groups may also be different. The specific zero insertion sequence can be set according to actual needs to ensure that the array length after zero insertion meets the corresponding FFT operation requirements. The number of signal data bits in the zero insertion sequence corresponds to the length of the original signal data group, and the number of zero insertion bits in the zero insertion sequence is the number of zeros to be inserted.

[0055] step 102 , obtain a data element from the signal data group to be inserted with zeros in sequence, and determine the number of zeros that need to be inserted continuously before the data element based on the current zero insertion sequence as the storage unit offset.

[0056] The signal data group includes multiple data elements, each of which is usually not a single-bit number but multi-bit data. Therefore, the length unit of the signal data group is the number of data elements, not the number of bits.

[0057] Step 104: based on the determined storage unit offset, the acquired data element is stored in the offset corresponding storage unit.

[0058] As shown in Figure 2(a), assuming that according to the order of the signal data group and the order of the storage units in the storage space, the next data element should be stored in the x-th storage unit, and the storage unit offset is Nz, then the data element is no longer stored in the x-th storage unit in the original order, but is offset and stored in the (x+Nz)-th storage unit, thereby determining the corresponding data address.

[0059] Step 106, based on the determined storage unit offset, update the current zero insertion sequence, and return to step 102, until all signal data groups to be zero-inserted are stored in the storage space, and obtain an array ready for completing the FFT operation.

[0060] Step 108, based on the zero insertion sequence (that is, the initial zero insertion sequence) obtained in step 100, sequentially read the array in the storage space that has completed the FFT operation preparation to obtain the array for the FFT operation. When reading in sequence, if the corresponding digit in the zero insertion sequence is marked as a zero insertion bit, then zero is directly read; if the corresponding digit in the zero insertion sequence is marked as a signal data bit, then the data element in the corresponding storage unit is read.

[0061] As shown in FIG2(b), when reading, a number or zero is output according to the zero-insertion sequence. When the digit corresponding to the zero-insertion sequence is marked as a zero-insertion digit, there is no need to consider the corresponding storage space content, and no data address is required. Zero can be directly given.

[0062] Step 110: Perform signal processing on the array for FFT operation obtained in step 108 through FFT operation, and store the result array obtained by the processing into the storage space in order.

[0063] In the embodiment of the present invention, data is stored and read based on a preset zero-insertion sequence. When storing, the signal data group to be inserted with zeros is stored according to the zero-insertion result. The storage unit is determined when zeros are inserted, and there is no need to calculate and generate the actual storage address of the data. When reading, 0 is directly read at the position where zeros are inserted, and the corresponding data stored is read at the position where zeros are not inserted. During the whole process, the time for implementing zero insertion is short, the acquired signal data group can be written continuously, and there is no need to actually write 0 in the storage space, which reduces the difficulty of calculating the storage and reading data addresses, has high efficiency, can meet different FFT operation requirements, and has strong flexibility.

[0064] Described below Figure 1 How the various steps are performed.

[0065] With respect to step 102, sequentially acquiring a data element from the signal data group to be inserted with zeros may be implemented by using the signal data group stored in FIFO mode.

[0066] Optionally, determining the number of zeros that need to be continuously inserted before the data element based on the current zero insertion sequence includes:

[0067] By using the binary search method, the number of digits continuously marked as zero insertion bits starting from the start bit of the current zero insertion sequence is determined as the number of zeros that need to be continuously inserted.

[0068] If the current zero insertion sequence includes Nz consecutive zero insertion bits starting from the start bit, the number of consecutively inserted zero bits that need to be equal to Nz, Nz ≥ 1;

[0069] If the current starting bit of the zero insertion sequence is a signal data bit, there is no need to insert zero and it is directly stored, that is, the number of consecutive zeros that need to be inserted is 0.

[0070] The above embodiment adopts the binary search method, which can quickly determine the number of zeros that need to be inserted continuously, thereby improving processing efficiency.

[0071] Furthermore, the binary search method is used to determine the number of digits of the current zero insertion sequence that are continuously marked as zero insertion digits starting from the start digit, that is, the number of zeros that need to be continuously inserted Nz, including the following steps:

[0072] A1. Set the current zero insertion sequence as the search sequence, and clear the current number of consecutive zeros to be inserted Nz to zero (i.e., set Nz=0); set the length of the search sequence to NL, and initially NL is greater than or equal to the array length Nfft that meets the FFT operation requirements (usually NL=Nfft, in special cases NL>Nfft, and the excess part is set as the zero insertion position), Nfft is usually 2 to the Nth power, and N is an integer;

[0073] A2. If the length of the current search sequence is greater than 1, determine whether the first half of the current search sequence is all zero-inserted bits. If yes, execute step A3; otherwise, execute step A4.

[0074] If the current search sequence length is equal to 1, determine whether the digit is a zero insertion digit. If so, increase the number of consecutive zero insertions Nz by 1 (i.e., Nz=Nz+1) and end the search. Otherwise, end the search directly.

[0075] A3, increase the length of the first half of the current search sequence by the number of consecutively inserted zeros Nz (i.e., Nz=Nz+NL / 2), take the second half of the current search sequence as a new search sequence, and return to step A2; for the updated search sequence, its length NL=NL / 2;

[0076] A4. Use the first half of the current search sequence as a new search sequence and return to step A2; for the updated search sequence, its length NL=NL / 2.

[0077] Optionally, with respect to step 106, updating the current zero insertion sequence based on the determined storage unit offset includes:

[0078] If the number of storage unit offsets is Nz, the first (Nz+1) bits of the current zero insertion sequence are deleted, and (Nz+1) signal data bits are added at the end.

[0079] The above embodiment can be considered as a zero insertion sequence that is left-shifted and fills the signal data bits. The updated zero insertion sequence is used to determine the storage unit offset of the next data element, which is conducive to quickly determining the number of consecutive zeros that need to be inserted through the binary search method.

[0080] like Figure 3 , Figure 4 As shown, an embodiment of the present invention provides a communication signal processing device. The device embodiment can be implemented by software, or by hardware or a combination of software and hardware. From the hardware level, Figure 3 FIG. 1 is a hardware architecture diagram of an electronic device in which a communication signal processing device provided by an embodiment of the present invention is located, except Figure 3In addition to the processor, memory, network interface, and non-volatile memory shown, the electronic device in the embodiment may also include other hardware, such as a forwarding chip responsible for processing messages, etc. Taking software implementation as an example, Figure 4 As shown, as a device in a logical sense, the CPU of the electronic device in which it is located reads the corresponding computer program in the non-volatile memory into the memory and runs it. A communication signal processing device provided in this embodiment includes:

[0081] The preparation module 401 is used to obtain a preset zero-insertion sequence and determine the storage space required for the FFT operation; wherein the number of digits of the zero-insertion sequence is the same as the number of storage units in the storage space, and each digit of the zero-insertion sequence is distinguished by a single-bit binary number to mark the zero-insertion bit and the signal data bit;

[0082] The zero insertion module 402 is used to sequentially obtain a data element from the signal data group to be inserted with zeros, and determine the number of zeros that need to be continuously inserted before the data element based on the current zero insertion sequence as a storage unit offset;

[0083] A storage module 403 is used to store the acquired data element into a corresponding storage unit after the offset based on the determined storage unit offset;

[0084] An updating module 404 is used to update the current zero insertion sequence based on the determined storage unit offset, and call the zero insertion module until all signal data groups to be zero-inserted are stored in the storage space to obtain an array ready for completing the FFT operation;

[0085] The reading module 405 is used to read the array prepared for the FFT operation in the storage space in sequence based on the zero insertion sequence obtained by the preparation module to obtain the array used for the FFT operation; when reading in sequence, if the corresponding digit in the zero insertion sequence is marked as a zero insertion bit, then zero is directly read; if the corresponding digit in the zero insertion sequence is marked as a signal data bit, then the data element in the corresponding storage unit is read;

[0086] The operation module 406 is used to perform signal processing through FFT operation and store the result array obtained by the processing into the storage space in sequence.

[0087] In an embodiment of the present invention, the preparation module 401 can be used to execute step 100 in the above method embodiment, the zero insertion module 402 can be used to execute step 102 in the above method embodiment, the storage module 403 can be used to execute step 104 in the above method embodiment, the update module 404 can be used to execute step 106 in the above method embodiment, the reading module 405 can be used to execute step 108 in the above method embodiment, and the operation module 406 can be used to execute step 110 in the above method embodiment.

[0088] Optionally, the zero insertion module 402 determines the number of zeros that need to be continuously inserted before the data element based on the current zero insertion sequence, including performing the following operations:

[0089] By using the binary search method, the number of digits continuously marked as zero insertion bits starting from the start bit of the current zero insertion sequence is determined as the number of zeros that need to be continuously inserted.

[0090] Optionally, the updating module 404 updates the current zero insertion sequence based on the determined storage unit offset, including performing the following operations:

[0091] If the number of storage unit offsets is Nz, the first (Nz+1) bits of the current zero insertion sequence are deleted, and (Nz+1) signal data bits are added at the end.

[0092] like Figure 5 As shown, an embodiment of the present invention further provides a method for inserting zeros in an FFT operation array, comprising:

[0093] Step 500, obtaining a preset zero-insertion sequence to determine the storage space required for FFT operation; the zero-insertion sequence includes zero-insertion bits and signal data bits;

[0094] Step 502, sequentially obtain a data element from the signal data group to be inserted with zeros, and determine the number of zeros that need to be inserted continuously before the data element based on the current zero insertion sequence, as a storage unit offset;

[0095] Step 504, based on the determined storage unit offset, storing the acquired data element into the corresponding storage unit after the offset;

[0096] Step 506, based on the determined storage unit offset, update the current zero insertion sequence, and return to step 502, until all signal data groups to be zero-inserted are stored in the storage space, and obtain an array ready for completing the FFT operation.

[0097] The above embodiment can perform zero insertion preprocessing on the original signal data group for different FFT operations, and quickly obtain an array ready for completing the FFT operation.

[0098] For step 500, the number of digits in the zero-insertion sequence is the same as the number of storage units in the storage space, and each digit in the zero-insertion sequence is distinguished by a single-bit binary number to mark the zero-insertion bit and the signal data bit, that is, a single-bit 1 represents the zero-insertion bit and a single-bit 0 represents the signal data bit, or a single-bit 0 represents the zero-insertion bit and a single-bit 1 represents the signal data bit. The number of digits in the signal data bit is the same as the length of the signal data group to be inserted with zeros.

[0099] With respect to step 502, the determining, based on the current zero insertion sequence, the number of zeros that need to be continuously inserted before the data element includes:

[0100] By using the binary search method, the number of digits continuously marked as zero insertion bits starting from the start bit of the current zero insertion sequence is determined as the number of zeros that need to be continuously inserted.

[0101] With respect to step 506, updating the current zero insertion sequence based on the determined storage unit offset includes:

[0102] If the number of storage unit offsets is Nz, the first (Nz+1) bits of the current zero insertion sequence are deleted, and (Nz+1) signal data bits are added at the end.

[0103] It is to be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on a communication signal processing device. In other embodiments of the present invention, a communication signal processing device may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0104] The information interaction, execution process and other contents between the modules in the above-mentioned device are based on the same concept as the embodiment of the method of the present invention. For the specific contents, please refer to the description in the embodiment of the method of the present invention, and no further description is given here.

[0105] An embodiment of the present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, a communication signal processing method or an FFT operation array zero insertion method in any embodiment of the present invention is implemented.

[0106] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the processor executes a communication signal processing method or an FFT operation array zero insertion method in any embodiment of the present invention.

[0107] Specifically, a system or device equipped with a storage medium can be provided, on which software program code that implements the functions of any of the above-mentioned embodiments is stored, and a computer (or CPU or MPU) of the system or device can be enabled to read and execute the program code stored in the storage medium.

[0108] In this case, the program code itself read from the storage medium can realize the function of any one of the above-mentioned embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present invention.

[0109] The storage medium embodiments for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer by a communication network.

[0110] In addition, it should be clear that the functions of any of the above embodiments can be implemented not only by executing the program code read by the computer, but also by enabling an operating system operating on the computer to complete part or all of the actual operations based on instructions from the program code.

[0111] In addition, it can be understood that the program code read from the storage medium is written to a memory provided in an expansion board inserted into the computer or to a memory provided in an expansion module connected to the computer, and then based on the instructions of the program code, a CPU installed on the expansion board or expansion module is enabled to perform part or all of the actual operations, thereby realizing the functions of any of the above-mentioned embodiments.

[0112] In the field of digital signal processing, FFT operation modules are generally located at the middle level, obtaining input data (i.e., the original signal data group) from the upper level and providing output data (i.e., the result array obtained by processing) to the lower level. The present invention reduces the difficulty of the upper level in calculating the output data address due to different zero insertions while adapting to various complex application environments, and at the same time greatly improves the flexibility of zero insertion, saves the time of FFT data preparation, and improves signal processing efficiency.

[0113] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical factors in the process, method, article or device including the elements.

[0114] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A communication signal processing method, characterized in that: The steps include: S1. Obtain a preset zero-insertion sequence and determine the storage space required for FFT operation; wherein the number of digits in the zero-insertion sequence is the same as the number of storage units in the storage space, and each digit in the zero-insertion sequence is distinguished by a single-bit binary number to mark the zero-insertion bit and the signal data bit; S2, sequentially obtaining a data element from the signal data group to be inserted with zeros, and determining the number of zeros that need to be continuously inserted before the data element based on the current zero insertion sequence, as a storage unit offset; S3, based on the determined storage unit offset, storing the acquired data element into the corresponding storage unit after the offset; S4, based on the determined storage unit offset, update the current zero insertion sequence, and return to step S2, until all the signal data groups to be zero-inserted are stored in the storage space, and an array ready for completing the FFT operation is obtained; S5. Based on the zero-insertion sequence obtained in step S1, sequentially read the arrays prepared for completing the FFT operation in the storage space to obtain the arrays used for the FFT operation; S6. Perform signal processing through FFT operation, and store the result array obtained by processing into the storage space in order.

2. The method according to claim 1, characterized in that The determining, based on the current zero insertion sequence, the number of zeros that need to be continuously inserted before the data element includes: By using the binary search method, the number of digits continuously marked as zero insertion bits starting from the start bit of the current zero insertion sequence is determined as the number of zeros that need to be continuously inserted.

3. The method according to claim 2, characterized in that The updating of the current zero insertion sequence based on the determined storage unit offset includes: If the number of storage unit offsets is Nz, the first (Nz+1) bits of the current zero insertion sequence are deleted, and (Nz+1) signal data bits are added at the end.

4. The method according to claim 2, characterized in that: The method of determining the number of digits of the current zero insertion sequence that are continuously marked as zero insertion bits starting from the start bit by using the binary search method comprises the following steps: A1. Set the current zero insertion sequence as the search sequence, and clear the current number of zeros that need to be inserted continuously; A2. If the length of the current search sequence is greater than 1, determine whether the first half of the current search sequence is all zero-inserted bits. If yes, execute step A3; otherwise, execute step A4. If the current search sequence length is equal to 1, determine whether the digit is a zero insertion digit. If so, increase the number of consecutive zero insertions by 1 and end the search. Otherwise, end the search directly. A3, increasing the length of the first half of the current search sequence by the number of consecutively inserted zeros, taking the second half of the current search sequence as a new search sequence, and returning to step A2; A4. Use the first half of the current search sequence as a new search sequence and return to step A2.

5. A communication signal processing device, characterized in that: include: A preparation module, used to obtain a preset zero-insertion sequence and determine the storage space required for FFT operation; wherein the number of digits of the zero-insertion sequence is the same as the number of storage units in the storage space, and each digit of the zero-insertion sequence is distinguished by a single-bit binary number to mark the zero-insertion bit and the signal data bit; A zero insertion module is used to sequentially obtain a data element from the signal data group to be inserted with zeros, and determine the number of zeros that need to be continuously inserted before the data element based on the current zero insertion sequence as a storage unit offset; A storage module, used for storing the acquired data element into a corresponding storage unit after the offset based on the determined storage unit offset; An updating module, used for updating the current zero insertion sequence based on the determined storage unit offset, and calling the zero insertion module until all signal data groups to be zero-inserted are stored in the storage space, thereby obtaining an array ready for completing the FFT operation; A reading module, configured to sequentially read the array prepared for the FFT operation in the storage space based on the zero insertion sequence obtained by the preparation module, to obtain an array for the FFT operation; The operation module is used to perform signal processing through FFT operation and store the result array obtained by processing into the storage space in sequence.

6. The device according to claim 5, characterized in that The zero insertion module determines the number of zeros that need to be continuously inserted before the data element based on the current zero insertion sequence, including performing the following operations: By using the binary search method, the number of digits continuously marked as zero insertion bits starting from the start bit of the current zero insertion sequence is determined as the number of zeros that need to be continuously inserted.

7. The device according to claim 6, characterized in that The updating module updates the current zero insertion sequence based on the determined storage unit offset, including performing the following operations: If the number of storage unit offsets is Nz, the first (Nz+1) bits of the current zero insertion sequence are deleted, and (Nz+1) signal data bits are added at the end.

8. A method for inserting zeros into an FFT operation array, comprising the following steps: Obtain a preset zero insertion sequence and determine the storage space required for FFT operation; Sequentially obtain a data element from the signal data group to be inserted with zeros, and determine the number of zeros that need to be inserted continuously before the data element based on the current zero insertion sequence as a storage unit offset; Based on the determined storage unit offset, the acquired data element is stored in the corresponding storage unit after the offset; Based on the determined storage unit offset, the current zero insertion sequence is updated, and the step of sequentially acquiring a data element from the signal data group to be inserted with zero is returned until all the signal data groups to be inserted with zero are stored in the storage space, thereby obtaining an array ready for completing the FFT operation.

9. An electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 4 and 8 is implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed in a computer, the computer is caused to execute the method according to any one of claims 1 to 4 and 8.

Images