A packaging method for a packaging structure of a vertical MOSFET chip

Abstract

The present invention discloses a packaging method for a packaging structure of a vertical MOSFET chip, belonging to the technical field of semiconductor packaging. The front side of the vertical MOSFET chip is flip-chip mounted on the etched surface of the three-dimensional metal frame. By using the folding of the three-dimensional metal frame, the drain, source, and gate of the vertical MOSFET chip are distributed on the same plane, shortening the interconnection distance between the vertical MOSFET chip and the outside world, enhancing the conductive effect of the chip, and streamlining the packaging structure. At the same time, a metal conductive heat dissipation plate is used to contact the back drain region of the vertical MOSFET chip over a large area, with excellent heat dissipation performance, improving the quality of the product.

Description

Technical Field

[0001] The present invention relates to a packaging method for a packaging structure of a vertical MOSFET chip, belonging to the technical field of semiconductor packaging. Background Art

[0002] The English full name of MOSFET is Metal Oxide Semiconductor Field Effect Transistor, that is, metal oxide semiconductor field effect transistor. The vertical MOSFET is a common voltage-type control device, which has a series of advantages such as fast switching speed, high-frequency performance, high input impedance, low noise, low drive power, large dynamic range, and wide safe operating area (SOA). Therefore, it is widely used in various industries such as switching power supplies, motor control, and power tools.

[0003] With the development of the 5G industry, consumer electronics, and new energy vehicle industries, for example, the power consumption of 5G base stations has increased. The power consumption of 5G base stations is twice that of 4G. In order to meet the power consumption requirements, it is necessary to increase the requirements for low loss and high thermal stability of vertical MOSFETs, which also poses higher requirements for low on-resistance, low heat generation, and fast heat dissipation of the packaging type.

[0004] The on-resistance (RDS) is the resistance between the drain and source electrodes and is one of the main characteristic parameters of the power vertical MOSFET. The vertical MOSFET device achieves a low RDS (on) by placing the drain region on the surface opposite to the source contact. By placing the drain region on the surface opposite to the source contact, the current conduction path (conduction path) is shortened, which reduces the RDS (on).

[0005] In the traditional wire bonding packaging type, the on-resistance is equal to the sum of the on-resistance of the chip and the parasitic resistance of the packaging, that is, the on-resistance RDS(on)=R L +R D +R W +Rds(on), where R L is the lead frame resistance, R D is the resistance between the chip drain and the frame, R W is the bond wire resistance, and Rds(on) is the internal resistance of the chip. The traditional wire bonding packaging is all in the form of wire bonding, and the bond wire resistance R w is relatively large, which will increase the on-resistance of the entire packaging and ultimately affect the current-carrying capacity of the product; moreover, in the traditional vertical MOSFET packaging form, the chip is completely wrapped in the plastic package of the packaging, resulting in the heat generated by the chip during operation not being dissipated in time, which restricts the performance improvement of the product. Summary of the Invention

[0006] In order to overcome the deficiencies of the implementation method of the traditional vertical MOSFET wire bonding package structure, the present invention provides a packaging method for the packaging structure of a vertical MOSFET chip, enabling the vertical MOSFET chip adopting this packaging method to achieve the purposes of low on-resistance, high current-carrying capacity, excellent heat dissipation performance, and a simple packaging structure.

[0007] The technical solution of the present invention:

[0008] The present invention provides a packaging method for the packaging structure of a vertical MOSFET chip, and its process method is as follows:

[0009] Step 1: Prepare the incoming wafers, pick out the qualified wafers through the incoming inspection process, and perform a cleaning process to remove dust, oil, etc. There are neatly arranged transverse and longitudinal cutting channels Ⅰ on the wafer. The cutting channels Ⅰ pre-divide the wafer into a plurality of vertical MOSFET chips. The front of each vertical MOSFET chip is provided with a source region and a gate region, and the back is set as a drain region;

[0010] Step 2: Respectively form a source conductive pad in the source region of the vertical MOSFET chip and set a gate conductive pad in its gate region by means of sputtering, etching, chemical deposition, printing or spraying liquid metal in sequence;

[0011] Step 3: Form a silver particle sintered body with high conductivity as a conductive circuit layer in the drain region of the vertical MOSFET chip through the low-temperature sintered silver connection technology;

[0012] Step 4: Adopt a cutting process to form a plurality of independent vertical MOSFET chips along the cutting channels Ⅰ;

[0013] Step 5: Prepare a metal conductive heat dissipation original plate, and neatly attach the back of the vertical MOSFET chips to the metal conductive heat dissipation original plate in sequence. There are transverse and longitudinal cutting channels Ⅱ between the vertical MOSFET chips;

[0014] Step 6: Cut the metal conductive heat dissipation original plate along the cutting channels Ⅱ to form a metal conductive heat dissipation plate attached to the back of the vertical MOSFET chip, forming a new chip monomer;

[0015] Step 7: Prepare a three-dimensional metal frame strip with its etched surface facing up, and array a plurality of hollow patterns, transverse cutting channels Ⅲ, longitudinal cutting channels Ⅲ and alignment points on it. The transverse cutting channels Ⅲ are arranged on the upper and lower sides of the three-dimensional metal frame strip,

[0016] Each of the hollow patterns is a continuous figure within the area of the upper and lower horizontal cutting channels III. The upper and lower horizontal cutting channels III respectively pass through the upper and lower edges of each hollow pattern. The horizontal cutting channel III and the vertical cutting channel III pre-divide the three-dimensional metal frame strip into a plurality of three-dimensional metal frames. Each three-dimensional metal frame has discontinuous source metal sheets and gate metal sheets. The source metal sheet and the gate metal sheet respectively extend inwards to form source metal piers and gate metal piers. The hollow pattern forms a gap between the source metal sheet and the gate metal sheet, and the gap separates the source metal sheet and the gate metal sheet;

[0017] Source metal pins and gate metal pins are formed on the left side of the etched surface of the source metal sheet and the right side of the etched surface of the gate metal sheet. The source metal pins and the gate metal pins together with the three-dimensional metal frame form a cavity;

[0018] Step eight: In turn, the front side of the chip monomer is flip-chip placed into the cavity of the three-dimensional metal frame strip. Through alignment of the alignment points, its source conductive pad and gate conductive pad are respectively fixedly connected to the source metal pier and the gate metal pier, realizing electrical conduction between the source and the gate of the vertical MOSFET chip and the source metal pins and the gate metal pins on the lead frame;

[0019] Step nine: The three-dimensional metal frame strip and the vertical MOSFET chip are coated with a plastic encapsulation material by a thin-film assisted single-sided plastic encapsulation process, and the hollow pattern is filled;

[0020] Step ten: Through a grinding process, the etched surfaces of the source metal pins and the gate metal pins of the three-dimensional metal frame strip, and the surface II of the metal conductive heat dissipation plate on the back side of the vertical MOSFET chip are exposed;

[0021] Step eleven: Conductive metal layer I, conductive metal layer II, and conductive metal layer III are respectively fabricated on the etched surface of the source metal pin, the etched surface of the gate metal pin, and the surface II of the metal conductive heat dissipation plate in turn by sputtering, etching, chemical deposition, printing, or spraying a liquid metal;

[0022] Step twelve: The above encapsulation body is divided into a plurality of encapsulation structure monomers of vertical MOSFET chips along the horizontal cutting channel III and the vertical cutting channel III, and the source and the gate of the vertical MOSFET chip are led upwards through the three-dimensional metal frame to the same plane as the drain of the vertical MOSFET chip.

[0023] Further, in step seven, the forming process of the source metal pins and the gate metal pins: on the left side of the etched surface of the source metal sheet and the right side of the etched surface of the gate metal sheet, source metal pins and gate metal pins are formed on the etched surface of the three-dimensional metal frame in turn by sputtering etching, chemical deposition, printing, or spraying.

[0024] Further, in step seven, the forming process of the source metal pin and the gate metal pin: through photolithography and metal deposition, a plurality of metal columns with the same height are formed, and the bottoms of the metal columns are connected to the etched surface on the left side of the source metal sheet and the etched surface on the right side of the gate metal sheet through a welding process, respectively forming the source metal pin and the gate metal pin.

[0025] Further, in step seven, the forming process of the source metal pin and the gate metal pin: prepare a metal thin sheet, and use a high-repetition-rate laser to form a plurality of metal columns with the same height through a laser cutting process, and connect the bottoms of the metal columns to the left side of the etched surface of the source metal sheet and the right side of the etched surface of the gate metal sheet through a welding process, respectively forming the source metal pin and the gate metal pin.

[0026] Further, in step seven, the forming process of the source metal pin and the gate metal pin: prepare the raw material of the three-dimensional metal frame bar, remove the redundant metal material through multiple semi-etching processes, and form a three-dimensional metal frame bar with the source metal pin, the gate metal pin and a hollow pattern, and the source metal pin and the gate metal pin are in the shape of concave arc columns.

[0027] Further, in step seven, it also includes the forming method of the rough surfaces of the source metal pin and the gate metal pin as follows: roughen the surfaces of the source metal pin and the gate metal pin and the etched surface of the three-dimensional metal frame bar together by plasma etching process, and the control range of the surface roughness Ra is: Ra is 0.2 - 0.4.

[0028] Further, in step seven, the hollow pattern is in the shape of the number 2.

[0029] Beneficial effects

[0030] The packaging method of a vertical MOSFET chip packaging structure of the present invention provides a low-temperature solder connection technology represented by sintered silver, realizes the connection between the metal heat dissipation plate and the drain region of the vertical MOSFET chip, avoids the use of the traditional wire bonding method, increases the current-carrying capacity, reduces the resistance R between the chip drain and the lead frame D , reduces the bond wire resistance R W, thus achieving the purpose of reducing the on-resistance RDS (on) of the packaged product. This packaging method can improve production efficiency and has the advantage of reducing production costs. The formed packaging structure of the vertical MOSFET chip uses the front side of the vertical MOSFET chip to be flip-chip mounted on the etched surface of the three-dimensional metal frame. Through the folding use of the three-dimensional metal frame, the drain, source, and gate of the vertical MOSFET chip are distributed on the same plane, shortening the interconnection distance between the vertical MOSFET chip and the outside world, enhancing the conductive effect of the chip, and streamlining the packaging structure. At the same time, a metal conductive heat dissipation plate is used to contact the back drain region of the vertical MOSFET chip over a large area, with excellent heat dissipation performance, improving the quality of the product. In addition, the source metal pin and gate metal pin of the three-dimensional metal frame are in a concave arc shape, enhancing the bonding force between the metal column and the plastic encapsulation material, achieving the purpose of increasing the reliability of the product. Description of the Drawings

[0031] Figure 1 is a flowchart of the packaging method of a packaging structure of a vertical MOSFET chip according to the present invention;

[0032] Figure 2 is a schematic diagram of the cross-sectional structure of an embodiment of a packaging structure of a vertical MOSFET chip according to the present invention;

[0033] Figure 3 is Figure 2 a schematic diagram of the relative positions of the vertical MOSFET chip and the three-dimensional metal frame;

[0034] Figure 4 is a schematic diagram of the cross-sectional structure of an embodiment of a packaging structure of a vertical MOSFET chip according to the present invention;

[0035] Figures 5A to 5Q is a flowchart of the technological process of the packaging method of a packaging structure of a vertical MOSFET chip according to the present invention;

[0036] Wherein: vertical MOSFET chip 10

[0037] source conductive pad 13

[0038] gate conductive pad 15

[0039] three-dimensional metal frame 20

[0040] metal frame body 21

[0041] source metal sheet 211

[0042] source metal pier 212

[0043] gate metal sheet 213

[0044] Gate metal pier 214

[0045] Source metal pin 22

[0046] Etched surface of the source metal pin 221

[0047] Gate metal pin 24

[0048] Etched surface of the gate metal pin 241

[0049] Gap 25

[0050] Cavity 26

[0051] Conductive circuit layer 30

[0052] Metal conductive heat dissipation plate 40

[0053] Surface Ⅰ of the metal conductive heat dissipation plate 42

[0054] Surface Ⅱ of the metal conductive heat dissipation plate 43

[0055] Conductive metal layer Ⅰ 61

[0056] Conductive metal layer Ⅱ 63

[0057] Conductive metal layer Ⅲ 65

[0058] Plastic encapsulation material 90;

[0059] Wafer 100

[0060] Cutting lane Ⅰ 110

[0061] Three-dimensional metal frame bar 200

[0062] Hollow pattern 220

[0063] Horizontal cutting lane Ⅲ 210

[0064] Vertical cutting lane Ⅲ 230

[0065] Alignment point 250

[0066] Metal conductive heat dissipation original plate 400

[0067] Cutting lane Ⅱ 410. Specific implementation mode

[0068] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the relevant invention and not to limit the invention. Additionally, it should be noted that for the sake of description, only the parts related to the relevant invention are shown in the drawings. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and embodiments.

[0069] The flowchart of the packaging method of a packaging structure of a vertical MOSFET chip according to the present invention is as Figure 1 shown:

[0070] S1: Prepare the incoming wafers, pre-divide the wafers into a plurality of vertical MOSFET chips. The front surface of each vertical MOSFET chip is provided with a source region and a gate region, and the back surface is set as the drain region;

[0071] S2: Respectively form a source conductive pad in the source region of the vertical MOSFET chip and set a gate conductive pad in its gate region by means of sputtering, etching, chemical deposition, printing or spraying liquid metal in sequence;

[0072] S3: Form a silver particle sintered body with high conductivity as a conductive circuit layer in the drain region of the vertical MOSFET chip through a low-temperature sintered silver connection technology;

[0073] S4: Adopt a cutting process to form a plurality of independent vertical MOSFET chips;

[0074] S5: Prepare a metal conductive heat dissipation original plate, and neatly attach the back surfaces of the vertical MOSFET chips to the metal conductive heat dissipation original plate in sequence;

[0075] S6: Cut the metal conductive heat dissipation original plate to form a metal conductive heat dissipation plate attached to the back surface of the vertical MOSFET chip, forming a new chip monomer;

[0076] S7: Prepare a three-dimensional metal frame strip, form a source metal sheet, a gate metal sheet, and source metal pins and gate metal pins provided on the etched surfaces of the source metal sheet and the gate metal sheet, and jointly form a cavity by the source metal pins and the gate metal pins and the three-dimensional metal frame;

[0077] S8: Invert and place the front surfaces of the new chip monomers into the cavities of the three-dimensional metal frame strip in sequence, so that the source and gate of the vertical MOSFET chip are respectively electrically connected to the source metal pins and the gate metal pins on the lead frame;

[0078] S9: Coating the three-dimensional metal frame strip and the vertical MOSFET chip with a plastic encapsulation material through a thin-film assisted single-sided plastic encapsulation forming process;

[0079] S10: Expose the etched surfaces of the source metal pins and the gate metal pins of the three-dimensional metal frame strip, as well as the surface II of the metal conductive heat dissipation plate on the back of the vertical MOSFET chip, through a grinding process;

[0080] S11: Sequentially fabricate a conductive metal layer I, a conductive metal layer II, and a conductive metal layer III on the etched surface of the source metal pin, the etched surface of the gate metal pin, and the surface II of the metal conductive heat dissipation plate by sputtering, etching, chemical deposition, printing, or spraying;

[0081] S12: Divide the above-mentioned package into a plurality of package structure monomers of vertical MOSFET chips.

[0082] The embodiments are as follows:

[0083] For a package structure of a vertical MOSFET chip according to the present invention, the front surface of the vertical MOSFET chip 10 is provided with a source region and a gate region, and the back surface is set as a drain region, as Figure 2 shown.

[0084] A source conductive pad 13 is arranged in the source region of the vertical MOSFET chip 10, and a gate conductive pad 15 is arranged in its gate region. The cross-sections of the source conductive pad 13 and the gate conductive pad 15 are circular, rectangular, or octagonal, and their materials are composite conductive metal layers, such as Cu / Sn layer or Ni / Au layer. A conductive circuit layer 30 is arranged in the drain region of the vertical MOSFET chip 10. The conductive circuit layer 30 can form a silver particle sintered body with high electrical conductivity in the drain region of the vertical MOSFET chip 10 through a low-temperature sintered silver connection technology, or can also use a finished welding material, such as conductive adhesive, soft solder, solder paste, etc., to be laid in the drain region of the vertical MOSFET chip 10, or can also be a combination of one or several materials of copper, silver, nickel, gold, tin, tin-silver, such as Cu / Sn layer or Ni / Au layer.

[0085] The back drain region of the vertical MOSFET chip 10 is fixedly connected to the metal conductive heat dissipation plate 40 through the conductive circuit layer 30 to achieve electrical conduction. The cross-sectional size of the metal conductive heat dissipation plate 40 is not less than the cross-sectional size of the vertical MOSFET chip 10, and its material is preferably metal copper with excellent electrical conductivity. The metal conductive heat dissipation plate 40 is in large-area contact with the drain region 17, achieving excellent heat dissipation performance of the package product.

[0086] Its three-dimensional metal frame 20 includes a metal frame body 21, a plurality of source metal pins 22, and a plurality of gate metal pins 24. The cross-sections of the source metal pins 22 and the gate metal pins 24 are all circular, rectangular, hexagonal, etc., Figure 3 which is schematically shown as circular in

[0087] The metal frame body 21 includes a discontinuous source metal sheet 211 and a gate metal sheet 213, and the source metal sheet 211 and the gate metal sheet 213 extend inwardly to form a source metal bridge pier 212 and a gate metal bridge pier 214, respectively. The cross-sectional shapes of the source metal bridge pier 212 and the gate metal bridge pier 214 match the shapes of the source region and the gate region of the vertical MOSFET chip 10, respectively. A gap 25 is set between the source metal bridge pier 212 and the gate metal bridge pier 214, and the gap 25 allows the liquid plastic encapsulation material 90 to flow more smoothly therebetween, thereby isolating the source metal sheet 211 and the gate metal sheet 213 from each other. The source metal bridge pier 212 and the gate metal bridge pier 214 are respectively fixedly connected to the source conductive pad 13 and the gate conductive pad 15 of the vertical MOSFET chip 10, and have directionality. Figure 3 In the figure, the source metal bridge pier 212 is L-shaped and rotated 90 degrees clockwise, and the gate metal bridge pier 214 is in a straight line shape. The etched surfaces of the source metal sheet 211 and the gate metal sheet 213 are respectively fixed to the source metal pin 22 and the gate metal pin 24. The etched surfaces of the source metal sheet 211 and the gate metal sheet 213 are etched surfaces for implementing the etching process, and have a certain roughness. The roughness Ra range is: Ra is 0.2~0.4, which enhances the connection strength between the source metal sheet 211 and the gate metal sheet 213 and the source metal pin 22 and the gate metal pin 24. The metal frame body 21 and the source metal pin 22 and the gate metal pin 24 form a cavity 26. The cavity 26 is used to carry the vertical MOSFET chip 10. The front side of the vertical MOSFET chip 10 is flipped in this cavity 26 and is electrically connected to the three-dimensional metal frame 20.

[0088] In an optional embodiment, the source metal sheet 211 and the gate metal sheet 213 are integrated with the source metal pin 22 and the gate metal pin 24 respectively.

[0089] The source metal pin 22 and the gate metal pin 24 are of equal height, and the etched surface 221 of the source metal pin and the etched surface 241 of the gate metal pin are flush with the surface II43 of the metal conductive heat sink, so that the source, gate, and drain of the vertical MOSFET chip 10 are distributed in the same plane, shortening the interconnection distance between the vertical MOSFET chip 10 and the outside world, enhancing the conductive effect of the chip, avoiding the use of traditional wire bonding, and reducing the resistance R between the chip drain and the lead frame. D , reducing the bond wire resistance R W , thereby achieving the purpose of reducing the on-resistance RDS (on) of the packaged product.

[0090] The plastic encapsulation material 90 fills and encapsulates the vertical MOSFET chip 10, the three-dimensional metal frame 20, and the gap 25 as a whole, only exposing the surface II 43 of the metal conductive heat dissipation plate, the etched surface 221 of the source metal pin, the etched surface 241 of the gate metal pin, and the outer side surface of the metal frame body 21. The plastic encapsulation material 90 provided between the vertical MOSFET chip 10, its metal conductive heat dissipation plate 40, the source metal pin 22, and the gate metal pin 24 can effectively prevent short circuits caused by voltage breakdown and improve the reliability of the product.

[0091] In an alternative embodiment, the source metal pin 22 and the gate metal pin 24 are in the shape of concave arc columns, and their radian R is generated due to the difference in etching rates during the semi-etching process of the three-dimensional metal frame 20. As Figure 4 shown, by controlling the semi-etching process to obtain the actually required radian R, the bonding force between the source metal pin 22, the gate metal pin 24, and the plastic encapsulation material 90 can also be increased, achieving the purpose of increasing the reliability of the product.

[0092] The packaging structure of a vertical MOSFET chip of the present invention further includes a conductive metal layer I 26, a conductive metal layer II 27, and a conductive metal layer III 28. The conductive metal layer I 26 is disposed on the etched surface 221 of the source metal pin, the conductive metal layer II 27 is disposed on the etched surface 241 of the gate metal pin, and the conductive metal layer III 28 is disposed on the surface II 43 of the metal conductive heat dissipation plate, which is convenient for electrical connection with other external devices.

[0093] The packaging method of the packaging structure of a vertical MOSFET chip of the present invention has the following process methods:

[0094] Step 1: As Figure 5A shown, prepare the incoming wafer 100, pick out qualified wafers through the incoming inspection process, and perform a cleaning process to remove dust, oil, etc. There are neatly arranged transverse and longitudinal cutting channels I 110 on the wafer 100. The cutting channels I 110 pre-divide the wafer 100 into a plurality of vertical MOSFET chips 10. Each vertical MOSFET chip 10 has a source region and a gate region on the front side and a drain region on the back side.

[0095] Step 2: As Figure 5B shown, respectively fabricate a source conductive pad 13 in the source region of the vertical MOSFET chip 10 and a gate conductive pad 15 in its gate region by means of sputtering corrosion, chemical deposition, printing, or spraying liquid metal in sequence; when fabricating a composite conductive metal layer such as a Cu / Sn layer or a Ni / Au layer, the process of Step 2 needs to be repeated multiple times to form a conductive metal layer of the corresponding material.

[0096] Step 3: AsFigure 5C As shown, a silver particle sintered body with high conductivity is formed as a conductive line layer 30 in the drain region of the vertical MOSFET chip 10 through a low-temperature sintered silver connection technology.

[0097] Step Four: As Figure 5D and Figure 5E shown, a plurality of independent vertical MOSFET chips 10 are formed along the dicing lane I 110 by a dicing process. Figure 5E FIG. is a front view thereof. A source conductive pad 13 is provided in the source region of the vertical MOSFET chip 10, and a gate conductive pad 15 is provided in its gate region.

[0098] Step Five: As Figure 5F shown, a metal conductive heat dissipation original plate 400 is prepared, and the back surfaces of the vertical MOSFET chips 10 are neatly attached to the metal conductive heat dissipation original plate 400 in sequence. There are transverse and longitudinal dicing lanes II 410 between the vertical MOSFET chips 10.

[0099] Step Six: As Figure 5G shown, along the dicing lane II 410, the metal conductive heat dissipation original plate 400 is cut to form a metal conductive heat dissipation plate 40 attached to the back surface of the vertical MOSFET chip 10, forming a new chip unit 11.

[0100] Step Seven: As Figure 5H and Figure 5I 、 Figure 5J shown, a three-dimensional metal frame strip 200 is prepared. The etched surface on its back is facing up as the working surface. The material of the three-dimensional metal frame strip 200 is selected with reference to the lead frame for the chip carrier of the integrated circuit.

[0101] A plurality of hollow patterns 220 and transverse dicing lanes III 210 are arranged in an array on the etched surface of the three-dimensional metal frame strip 200.

[0102] The longitudinal cutting channel III 230 and the alignment point 250, and the transverse cutting channel III 210 are arranged on the upper and lower sides of the three-dimensional metal frame strip 200; each hollow pattern 220 is a continuous pattern within the area of the upper and lower transverse cutting channels III 210, such as the number 2 pattern; the upper and lower transverse cutting channels III 210 respectively pass through the upper and lower edges of each hollow pattern 220, and the transverse cutting channel III 210 and the longitudinal cutting channel III 230 pre-divide the three-dimensional metal frame strip 200 into a plurality of three-dimensional metal frames 20. Each three-dimensional metal frame 20 has discontinuous source metal sheets 211 and gate metal sheets 213. The source metal sheets 211 and the gate metal sheets 213 respectively extend inwards to form source metal piers 212 and gate metal piers 214. The hollow pattern 220 forms a gap 25 between the source metal sheet 211 and the gate metal sheet 213. The gap 25 separates the source metal sheet 211 and the gate metal sheet 213, and at the same time plays a role in guiding the flow of current.

[0103] On the left side of the etched surface of the source metal sheet 211 and the right side of the etched surface of the gate metal sheet 213, a source metal pin 22 and a gate metal pin 24 are formed in sequence by sputtering corrosion and chemical deposition of metallic copper. The source metal pin 22 and the gate metal pin 24 together with the three-dimensional metal frame 20 form a cavity 26, as Figure 5I shown.

[0104] Alternatively, a plurality of metal columns with the same height are formed by photoresist patterns and metal deposition methods. The bottoms of the metal columns are respectively connected to the left etched surface of the source metal sheet 211 and the right etched surface of the gate metal sheet 213 through a welding process to respectively form the source metal pin 22 and the gate metal pin 24. The solder used for welding can be one or a combination of titanium, copper, silver, nickel, gold, tin, and tin-silver.

[0105] Alternatively, prepare a metal sheet, and use a high-reflection laser to form a plurality of metal columns with the same height through a laser cutting process. The bottoms of the metal columns are respectively connected to the left etched surface of the source metal sheet 211 and the right etched surface of the gate metal sheet 213 through a welding process to respectively form the source metal pin 22 and the gate metal pin 24. The bottoms of the metal columns are respectively connected to the left side of the etched surface of the source metal sheet 211 and the right side of the etched surface of the gate metal sheet 213 through a welding process to respectively form the source metal pin 22 and the gate metal pin 24. The solder used for welding can be one or a combination of titanium, copper, silver, nickel, gold, tin, and tin-silver.

[0106] Alternatively, when forming the three-dimensional metal frame strip 200, the raw material of the three-dimensional metal frame strip 200 is subjected to multiple semi-etching processes to remove the redundant metal materials, thereby forming the three-dimensional metal frame strip 200 with the source metal pins 22, the gate metal pins 24, and the hollow-out pattern 220. The source metal pins 22 and the gate metal pins 24 are in a concave arc column shape. After the three-dimensional metal frame strip 200 is cut into the three-dimensional metal frame 20, the source metal pins 22 and the gate metal pins 24 are integrally structured with the source metal sheet 211 and the gate metal sheet 213 of the three-dimensional metal frame 20 respectively.

[0107] In this step, the surfaces of the source metal pins 22 and the gate metal pins 24 and the etched surface of the three-dimensional metal frame strip 200 can also be roughened by a plasma etching process, and the control range of the roughness Ra is: Ra is 0.2 to 0.4.

[0108] Step Eight: As Figure 5K and Figure 5L shown, the front side of the new chip unit 11 is successively placed face-down into the cavity 26 of the three-dimensional metal frame strip 200, and through alignment with the alignment point 250, its source conductive pad 13 and gate conductive pad 15 are respectively fixedly connected to the source metal bridge pier 23 and the gate metal bridge pier 25, so as to realize the electrical connection of the source and the gate of the vertical MOSFET chip 10 with the source metal pins 22 and the gate metal pins 24 on the lead frame respectively.

[0109] Step Nine: As Figure 5M shown, the three-dimensional metal frame strip 200 and the vertical MOSFET chip 10 are coated with a plastic encapsulation material 90 by a film-assisted single-sided plastic encapsulation forming process (FAM), and the hollow-out pattern 220 is filled.

[0110] Step Ten: As Figure 5N shown, the etched surface 221 of the source metal pin and the etched surface 241 of the gate metal pin of the three-dimensional metal frame strip 200, as well as the surface II 43 of the metal conductive heat dissipation plate on the back of the vertical MOSFET chip 10, are exposed through a grinding process.

[0111] Step Eleven: As Figure 5O shown, a conductive metal layer I 61, a conductive metal layer II 63, and a conductive metal layer III 65 are respectively fabricated on the etched surface 221 of the source metal pin, the etched surface 241 of the gate metal pin, and the surface II 43 of the metal conductive heat dissipation plate by means of sputtering corrosion, chemical deposition, printing, or spraying. The conductive metal layer I 61, the conductive metal layer II 63, and the conductive metal layer III 65 are used for subsequent mounting of the packaged chip.

[0112] Step Twelve: As Figure 5P and Figure 5QAs shown in the figure, the above-mentioned package is divided into plural single package structures of vertical MOSFET chips along the transverse cutting path III 210 and the longitudinal cutting path III 230, and the source electrode and the gate electrode of the vertical MOSFET chip 10 are led upward through the three-dimensional metal frame 20 to the same plane as the drain electrode of the vertical MOSFET chip 10.

[0113] As described above, only the preferred specific embodiments of the present invention are provided, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A packaging method for a packaging structure of a vertical MOSFET chip, and its process method is as follows: Step 1: Prepare the incoming wafer (100). There are neatly arranged transverse and longitudinal cutting channels I (110) on the wafer (100). The cutting channels I (110) pre-divide the wafer (100) into a plurality of vertical MOSFET chips (10). The front of each vertical MOSFET chip (10) is provided with a source region and a gate region, and the back is set as a drain region; Step 2: Respectively form a source conductive pad (13) in the source region of the vertical MOSFET chip (10) and set a gate conductive pad (15) in its gate region by means of sputtering, etching, chemical deposition, printing or spraying liquid metal in sequence; Step 3: Form a silver particle sintered body with high conductivity as a conductive circuit layer (30) in the drain region of the vertical MOSFET chip (10) by means of low-temperature sintered silver connection technology; Step 4: Adopt a cutting process to form a plurality of independent vertical MOSFET chips (10) along the cutting channels I (110); Step 5: Prepare a metal conductive heat dissipation original plate (400). Neatly attach the back of the vertical MOSFET chip (10) to the metal conductive heat dissipation original plate (400) in sequence. There are transverse and longitudinal cutting channels II (410) left between the vertical MOSFET chips (10); Step 6: Cut the metal conductive heat dissipation original plate (400) along the cutting channels II (410) to form a metal conductive heat dissipation plate (40) attached to the back of the vertical MOSFET chip (10), forming a new chip monomer (11); Step 7: Prepare a three-dimensional metal frame strip (200). The etched surface on its back is facing up. Array a plurality of hollow patterns (220), transverse cutting channels III (210), longitudinal cutting channels III (230) and alignment points (250) on it. The transverse cutting channels III (210) are arranged on the upper and lower sides of the three-dimensional metal frame strip (200), Each of the hollow patterns (220) is a continuous pattern in the area of the upper and lower transverse cutting channels III (210). The upper and lower transverse cutting channels III (210) respectively pass through the upper and lower edges of each hollow pattern (220). The transverse cutting channels III (210) and the longitudinal cutting channels III (230) pre-divide the three-dimensional metal frame strip (200) into a plurality of three-dimensional metal frames (20). Each three-dimensional metal frame (20) has discontinuous source metal sheets (211) and gate metal sheets (213). The source metal sheets (211) and the gate metal sheets (213) respectively extend inwards to form source metal piers (212) and gate metal piers (214). The hollow patterns (220) form gaps (25) between the source metal sheets (211) and the gate metal sheets (213). The gaps (25) separate the source metal sheets (211) and the gate metal sheets (213); Source metal pins (22) and gate metal pins (24) are formed on the left side of the etched surface of the source metal sheet (211) and the right side of the etched surface of the gate metal sheet (213). The source metal pins (22) and the gate metal pins (24) together with the three-dimensional metal frame (20) form a cavity (26). The forming process of the source metal pins (22) and the gate metal pins (24): Prepare the raw material of the three-dimensional metal frame strip (200), and remove the redundant metal materials through multiple semi-etching processes to form a three-dimensional metal frame strip (200) with source metal pins (22), gate metal pins (24), and a hollow pattern (220). The source metal pins (22) and the gate metal pins (24) are in the shape of concave arc columns. Step eight: In turn, the front side of the chip monomer (11) is flip-chip placed into the cavity (26) of the three-dimensional metal frame strip (200). Through alignment by the alignment point (250), its source conductive pad (13) and gate conductive pad (15) are respectively fixedly connected to the source metal pier (212) and the gate metal pier (214), so that the source and the gate of the vertical MOSFET chip (10) are respectively electrically connected to the source metal pins (22) and the gate metal pins (24) on the lead frame. Step nine: Use the plastic encapsulation material (90) to encapsulate the three-dimensional metal frame strip (200) and the vertical MOSFET chip (10) through a thin-film assisted single-sided plastic encapsulation forming process, and fill the hollow pattern (220). Step ten: Through a grinding process, expose the etched surface (221) of the source metal pins and the etched surface (241) of the gate metal pins of the three-dimensional metal frame strip (200), and the surface II (43) of the metal conductive heat dissipation plate on the back of the vertical MOSFET chip (10). Step eleven: Respectively fabricate a conductive metal layer I (61), a conductive metal layer II (63), and a conductive metal layer III (65) on the etched surface (221) of the source metal pins, the etched surface (241) of the gate metal pins, and the surface II (43) of the metal conductive heat dissipation plate by means of sputtering corrosion, chemical deposition, printing, or spraying in sequence. Step twelve: Divide the above-mentioned package into plural package structure monomers of vertical MOSFET chips along the transverse cutting path III (210) and the longitudinal cutting path III (230), and lead the source and the gate of the vertical MOSFET chip (10) upward through the three-dimensional metal frame (20) to the same plane as the drain of the vertical MOSFET chip (10).

2. The encapsulation method according to claim 1, wherein In step seven, it also includes the following forming method for the rough surfaces of the source metal pins (22) and the gate metal pins (24): Roughen the surfaces of the source metal pins (22) and the gate metal pins (24) and the etched surface of the three-dimensional metal frame strip (200) together by means of a plasma etching process, and the control range of the surface roughness Ra is: Ra is 0.2 - 0.

4.

3. The encapsulation method according to claim 1 or 2, characterized in that, In step seven, the hollow pattern (220) is in the shape of the number 2.

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