Chip packaging structure

Abstract

The present invention provides a chip packaging structure, which relates to the technical field of electronic packaging. It includes a substrate and at least one chip disposed thereon. A solder mask layer is provided on the surface of the substrate. The chip has a functional surface provided with an electrical connection structure and a non-functional surface opposite thereto. The functional surface of the chip faces the substrate and is flip-chip mounted thereon, and is electrically connected to the substrate through the electrical connection structure. An underfill is filled between the chip and the substrate. At least one groove is provided on the surface of the solder mask layer, and the underfill is filled in the groove. The groove includes at least the orthographic projection area of one vertex of the functional surface of the chip on the solder mask layer. The underfill in the groove is thicker than the underfill in other areas, which plays a role in the transition of heat stress transfer and the buffering of heat stress, making the stress streamline smoother, effectively dispersing the heat stress. Moreover, the thicker underfill can increase the structural strength at this place, reduce the stress concentration coefficient, and thus reduce the failure risk at this place, realizing the effect of relieving heat stress from multiple dimensions.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic packaging, and particularly to a chip packaging structure. Background Art

[0002] In the chip packaging process, due to the difference in the coefficient of thermal expansion between the chip and the underfill, after the chip packaging structure undergoes multiple process steps such as reflow soldering and reliability tests such as temperature cycle tests, the expansion and contraction degrees of the chip and the underfill are different, resulting in the problem of thermal stress concentration at the contact interface. When the thermal stress value exceeds the ultimate strength, the chip will warp and detach or crack from the underfill, causing the failure of the packaging structure. Moreover, with the increase in the chip size in packaging structures such as flip chip ball grid array, this problem becomes more serious. Especially at the vertex of the chip side, since the morphology at this point is close to a right angle, the stress is more concentrated than in other areas, and the risk of the above-mentioned failure is more likely to occur. Summary of the Invention

[0003] The purpose of the present invention is to provide a chip packaging structure.

[0004] The present invention provides a chip packaging structure, including a substrate and at least one chip disposed thereon. A solder mask layer is provided on the surface of the substrate. The chip has a functional surface provided with an electrical connection structure and a non-functional surface opposite thereto. The functional surface of the chip is flip-chip disposed on the substrate and electrically connected to the substrate through the electrical connection structure. An underfill is filled between the chip and the substrate. At least one groove is provided on the surface of the solder mask layer, and the underfill is filled in the groove. The groove includes at least the orthographic projection area of one vertex of the functional surface of the chip on the solder mask layer.

[0005] As a further improvement of the present invention, four grooves are provided on the surface of the solder mask layer, and each groove respectively includes the orthographic projection area of one vertex of the chip on the solder mask layer.

[0006] As a further improvement of the present invention, a curved surface structure is formed at the top of the functional surface of the chip. The functional surface of the chip transitions to the side surface of the chip along the curved surface structure. The underfill covers the curved surface structure, and the groove includes at least the orthographic projection area of the curved surface structure region on the solder mask layer.

[0007] As a further improvement of the present invention, an S-shaped curved surface structure is formed at the top of the functional surface of the chip. The S-shaped curved surface structure includes a first curved surface structure protruding outward along the surface of the chip and a second curved surface structure recessed inward along the surface of the chip. The functional surface of the chip transitions to the side surface of the chip along the first curved surface structure and the second curved surface structure in sequence.

[0008] As a further improvement of the present invention, along the longitudinal section direction of the encapsulation structure, the length of the curved surface structure in the orthographic projection area of the solder mask layer is L, and the outer end of the groove extends at least L / 2 beyond the outer end of the orthographic projection area of the curved surface structure in the solder mask layer.

[0009] As a further improvement of the present invention, along the longitudinal section direction of the encapsulation structure, the length of the curved surface structure in the orthographic projection area of the solder mask layer is L, and the inner end of the groove extends at least L / 2 beyond the inner end of the orthographic projection area of the curved surface structure in the solder mask layer.

[0010] As a further improvement of the present invention, the depth of the groove is 50% of the thickness of the solder mask layer.

[0011] As a further improvement of the present invention, the inner wall surface and the outer wall surface of the groove are in the shape of an arc-shaped curved surface.

[0012] As a further improvement of the present invention, the inner wall surface and the outer wall surface of the groove are a combination of multiple vertical surfaces extending along the outer contour of the curved surface structure.

[0013] As a further improvement of the present invention, circular chamfers are formed at the four vertices of the bottom surface of the groove.

[0014] The beneficial effects of the present invention are as follows: By providing a groove on the surface of the solder mask layer and including the orthographic projection area of the chip vertex on the solder mask layer within the groove, the underfill at this location is thicker than that in other areas, playing a role in the transition of thermal stress transfer and buffering of thermal stress, making the stress streamline smoother, effectively dispersing the thermal stress, and the thicker underfill can increase the structural strength at this location, reducing the stress concentration coefficient, thereby reducing the failure risk at this location, and achieving the effect of relieving thermal stress from multiple dimensions. In addition, the present invention further provides a curved surface structure in the top region of the chip, and the uniformly transitioning interface can make the stress transfer more continuous and uniform, thus avoiding the occurrence of obvious thermal stress concentration regions. Description of the Drawings

[0015] Figure 1 is a schematic diagram of the chip packaging structure in Embodiment 1 of the present invention.

[0016] Figure 2 is a schematic diagram of the chip packaging structure in Embodiment 2 of the present invention.

[0017] Figure 3 is a top view of the chip packaging structure in Embodiment 2 of the present invention (the inner wall surface of the groove is arc-shaped, and for the sake of easy understanding, some structures are omitted).

[0018] Figure 4 is a top view of the chip packaging structure in Embodiment 2 of the present invention (the inner wall surface of the groove is polygonal, and for the sake of easy understanding, some structures are omitted).

[0019] Figure 5 It is a schematic diagram of the chip packaging structure in Embodiment 3 of the present invention.

[0020] Figure 6 It is a schematic diagram of the chip packaging structure in Embodiment 4 of the present invention. Detailed implementation manners

[0021] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below in conjunction with the specific implementation manners of the present application and the corresponding drawings. Obviously, the described implementation manners are only a part of the implementation manners of the present application, rather than all of them. Based on the implementation manners in the present application, all other implementation manners obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0022] The following details the implementation manners of the present invention. The examples of the implementation manners are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The implementation manners described below with reference to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention.

[0023] For convenience of description, terms representing relative spatial positions are used herein, such as "upper", "lower", "rear", "front", etc., to describe the relationship of one unit or feature shown in the drawings relative to another unit or feature. The terms of relative spatial positions may include different orientations of the device in use or operation other than the orientations shown in the drawings. For example, if the device in the drawing is flipped, the unit described as being "below" or "above" other units or features will be located "below" or "above" other units or features. Therefore, the exemplary term "below" can encompass both the lower and upper spatial orientations.

[0024] Embodiment 1

[0025] As Figure 1 shown, Embodiment 1 of the present invention provides a chip packaging structure, which includes a substrate 1 and at least one chip 2 disposed thereon.

[0026] A circuit layer is provided in the substrate 1, and a solder mask layer 11 and solder pads are provided on the surface of the substrate 1. The solder pads are electrically connected to the circuit layer. The solder mask layer 11 is a layer of solder resist paint coated on the area of the substrate 1 except for the solder pads, which can prevent solder from overflowing and protect the substrate 1, etc.

[0027] The chip 2 has a functional surface 2a provided with an electrical connection structure and a non-functional surface 2b opposite thereto. The functional surface 2a of the chip faces the substrate 1 and is flip-chip mounted thereon. The chip 2 is welded to the surface pads of the substrate 1 through the electrical connection structure, thereby being electrically connected to the circuit layer. Specifically, in Embodiment 1, the electrical connection structure of the functional surface 2a of the chip is solder balls provided on the surface of the chip 2. In other embodiments of the present invention, the chip 2 may also be of other structures or be electrically connected to the substrate 1 in other ways, and the present invention does not make specific limitations thereto.

[0028] An underfill 3 is filled between the chip 2 and the substrate 1. The underfill 3 fills the gap between the substrate 1 and the chip 2. It usually uses epoxy resin with additives as the matrix material. The underfill 3 can protect the connection solder joints between the chip 2 and the substrate 1, protecting the device from moisture, ionic contaminants, radiation, and harmful operating environments such as mechanical stretching, shearing, twisting, and vibration. Moreover, the underfill 3 can also reduce the problem of mismatch in the coefficient of thermal expansion between the chip 2 and the substrate 1, improving the reliability of the packaging structure.

[0029] In a conventional packaging structure, the underfill 3 usually completely fills the gap between the substrate 1 and the chip 2 and extends upward along the side of the chip 2, partially covering the side area of the chip 2, and at least completely covering the four vertex areas of the functional surface 2a of the chip.

[0030] Furthermore, at least one groove 111 is provided on the surface of the solder mask layer 11. The underfill 3 is filled in the groove 111. The groove 111 at least includes the orthographic projection area of one vertex of the functional surface 2a of the chip on the solder mask layer 11, that is, the orthographic projection of the vertex of the functional surface 2a of the chip on the solder mask layer 11 is completely located within the groove 111.

[0031] The morphology at the side vertex of the chip 2 is close to a right-angle structure, and there will be a relatively serious stress concentration in the area where the cross-section structure changes suddenly. When the chip packaging structure undergoes processes such as reflow soldering and temperature test cycles, due to the difference in the coefficient of thermal expansion between the chip 2 and the underfill 3, the thermal stress values at the side vertex of the chip 2 and the underfill 3 in contact therewith gradually increase. When it exceeds the ultimate strength at that place, warping of the chip 2 will occur, resulting in delamination or crack initiation between the chip 2 and the underfill 3, thus causing the failure of the packaging structure. And during long-term use, there may also be a possibility of fatigue failure, reducing the reliability of the packaging structure.

[0032] In the present invention, by forming a groove 111 on the solder mask layer 11 under the vertex of the chip functional surface 2a, the underfill 3 at this location is thicker than that in other areas. Moreover, the groove 111 encompasses the vertex area, playing a role in the transition of thermal stress transmission and buffering of thermal stress, making the stress streamline smoother, effectively dispersing the thermal stress, thereby reducing the thermal stress concentration at this location and decreasing the maximum stress peak. And the thicker underfill 3 can increase the structural strength at this location, reduce the stress concentration coefficient, thereby reducing the failure risk at this location, and realizing the alleviation of thermal stress from multiple dimensions.

[0033] Preferably, in Embodiment 1, the depth of the groove 111 is 50% of the thickness of the solder mask layer 11. Here, the depth of the groove 111 is limited to half of the depth of the solder mask layer 11. On the one hand, it can ensure that the groove 111 can play a role in alleviating thermal stress concentration. On the other hand, it can avoid the risk of failure due to the too thin solder mask layer 11. In other embodiments of the present invention, the depth of the groove 111 can be adjusted according to the different thicknesses of the solder mask layer 11 as long as the solder mask layer 11 does not fail. The present invention only gives a preferred solution and does not make specific limitations thereto.

[0034] Specifically, in Embodiment 1, four grooves 111 are provided on the surface of the solder mask layer 11, and each groove 111 respectively includes the orthographic projection area of a vertex of the chip 2 on the solder mask layer 11, thereby playing a role in alleviating thermal stress concentration at the four vertices of the chip 2, making the overall stress on the chip 2 and the underfill 3 more uniform, and increasing the reliability of the chip packaging structure.

[0035] Preferably, the planar shape of the groove 111 can be a shape composed of curves such as a circle or an ellipse, avoiding the appearance of sharp corner regions. Through a uniformly transitioning interface, the force transmission is more continuous and uniform, thereby further reducing the situation of thermal stress concentration.

[0036] In the present embodiment, only one chip 2 is described. In an actual packaging structure, multiple chips or other passive devices may be provided on the substrate 1. When multiple chips 2 are provided, grooves 111 can be formed in the solder mask layer 11 areas corresponding to the vertices of each chip functional surface 2a, or grooves 111 can also be provided in the solder mask layer 11 areas corresponding to some vertices of some chips 2 according to specific parameters such as the size or type of the chip 2. The present invention does not make specific limitations thereto.

[0037] Embodiment 2

[0038] As Figure 2 shown, Embodiment 2 of the present invention provides a chip packaging structure, whose structure is generally similar to that of Embodiment 1. The difference between it and Embodiment 1 lies in:

[0039] A curved surface structure 2a1 is formed at the top of the chip functional surface 2a. The chip functional surface 2a transitions to the side surface of the chip 2 along the curved surface structure 2a1. The underfill 3 covers the curved surface structure 2a1. The groove 111 includes at least the orthographic projection area of the curved surface structure 2a1 region on the solder mask layer 11.

[0040] It should be noted that the statement of "at the top of the chip functional surface 2a" here is for the convenience of description. In the actual structure, due to the formation of the curved surface structure 2a1 at this position, there is no exact topmost position, and it actually refers to the entire curved surface area.

[0041] In Embodiment 2, the top region of the chip 2 is formed into a curved surface structure 2a1, so as to avoid the formation of sharp angular structures at the joint surface of the chip 2 and the underfill 3. As described above, a uniformly transitioning interface can make the stress transfer more continuous and uniform, thereby avoiding the occurrence of obvious thermal stress concentration regions.

[0042] Specifically, in Embodiment 2, the curved surface structure 2a1 is an arc surface protruding outward along the surface of the chip 2, and an elliptical arc surface can be formed, so as to play a better transition role.

[0043] By forming the groove 111 in the solder mask layer 11 and forming the curved surface structure 2a1 at the top of the chip functional surface 2a, the combined effect is to reduce the thermal stress concentration, thereby significantly improving the reliability of the chip packaging structure.

[0044] Preferably, in Embodiment 2, along the longitudinal section direction of the packaging structure, the length of the orthographic projection area of the curved surface structure 2a1 on the solder mask layer 11 is L. The outer end of the groove 111 extends at least beyond the outer end of the orthographic projection area of the curved surface structure 2a1 on the solder mask layer 11 by L / 2; and the inner end of the groove 111 extends at least beyond the inner end of the orthographic projection area of the curved surface structure 2a1 on the solder mask layer 11 by L / 2. That is, along the longitudinal section direction of the packaging structure, when the length of the orthographic projection area of the curved surface structure 2a1 on the solder mask layer 11 is L, the width of the groove 111 is at least 2L. Here, by limiting the width of the groove 111 based on the width of the outer contour of the curved surface structure 2a1, it is ensured that there is a sufficient distance between the two ends of the groove 111 and the curved surface structure 2a1 respectively, avoiding the situation where the stress strongest area at the joint surface of the chip 2 and the underfill 3 coincides with the stress strongest area at the joint surface of the solder mask layer 11 and the underfill 3, which may instead cause stress concentration and lead to the separation or fracture of the packaging structure interface.

[0045] It can be understood that since the projected widths of different regions of the curved surface structure 2a1 on the solder mask layer 11 are different, that is, in the plane aspect, the minimum width of the groove 111 is also dynamically changing. For the convenience of the slotting process implementation, the maximum value among different minimum widths can be selected as the overall minimum width of the groove 111.

[0046] In other embodiments of the present invention, the width of each groove and the length by which the groove 111 extends beyond the projection area of the curved surface structure 2a1 on the solder mask layer 11 may also be specifically adjusted according to factors such as the size characteristics of the chip 2 and the radian of the curved surface structure 2a1. The present invention only gives a preferred solution and does not make specific restrictions thereon.

[0047] Specifically, as Figure 3 shown, in this embodiment, the inner wall surface and the outer wall surface of the groove 111 are circular arc-shaped curved surfaces, including the curved surface structure 2a1 therein.

[0048] As Figure 4 shown, in some other embodiments, the inner wall surface and the outer wall surface of the groove 111 are a combination of multiple vertical surfaces extending along the outer contour of the curved surface structure 2a1, and the overall planar shape forms a polygon similar to a "c". During the production process, the groove 111 structure formed by the combination of vertical surfaces is easier to achieve through processes such as laser cutting.

[0049] Embodiment 3

[0050] As Figure 5 shown, Embodiment 3 of the present invention provides a chip packaging structure, the structure of which is generally similar to that of Embodiment 1, and the difference between it and Embodiment 1 lies in:

[0051] An S-shaped curved surface structure 2a1 is formed at the top of the chip functional surface 2a. The S-shaped curved surface structure 2a1 includes a first curved surface structure protruding outward along the surface of the chip 2 and a second curved surface structure recessed inward along the surface of the chip 2. The chip functional surface 2a transitions to the side of the chip 2 along the first curved surface structure and the second curved surface structure in sequence.

[0052] Compared with the completely arc-shaped curved surface structure 2a1, the S-shaped curved surface structure 2a1 is easier to achieve through process manufacturing such as laser cutting during the production process.

[0053] Embodiment 4

[0054] As Figure 6 shown, Embodiment 4 of the present invention provides a chip packaging structure, the structure of which is generally similar to that of Embodiment 3, and the difference between it and Embodiment 1 lies in:

[0055] Circular chamfers are formed at the four vertices of the bottom surface of the groove 111. As described above, by forming smooth circular chamfers at the bottom surface of the groove 111, the transmission of stress can be made more continuous and uniform, thereby further reducing the concentration of thermal stress at this place.

[0056] In summary, in the present invention, a groove is provided on the surface of the solder mask, and the groove includes the orthographic projection area of the chip vertex on the solder mask, so that the underfill at this place is thicker than that in other areas, playing a role in the transition of heat stress transfer and buffering of heat stress, making the stress streamline smoother and effectively dispersing the heat stress. Moreover, the thicker underfill can increase the structural strength at this place, reduce the stress concentration coefficient, thereby reducing the failure risk at this place, and realizing the effect of relieving heat stress from multiple dimensions. In addition, a curved surface structure is further provided in the top area of the chip, and the uniformly transitioning interface can make the stress transfer more continuous and uniform, thus avoiding the occurrence of obvious heat stress concentration areas.

[0057] It should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0058] The series of detailed descriptions listed above are only specific descriptions of the feasible embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any equivalent embodiments or changes made without departing from the technical spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip packaging structure, comprising a substrate and at least one chip disposed thereon. A solder mask layer is provided on the surface of the substrate. The chip has a functional surface provided with an electrical connection structure and a non-functional surface opposite thereto. The functional surface of the chip faces the substrate and is flip-chip mounted thereon, and is electrically connected to the substrate through the electrical connection structure. An underfill is filled between the chip and the substrate, and is characterized in that, at least one groove is provided on the surface of the solder mask layer, and the underfill is filled in the groove; the groove at least includes the orthographic projection area of one vertex of the functional surface of the chip on the solder mask layer; four grooves are provided on the surface of the solder mask layer, and each groove respectively includes the orthographic projection area of one vertex of the chip on the solder mask layer; a curved surface structure is formed at the top end of the functional surface of the chip, and the functional surface of the chip transitions to the side surface of the chip along the curved surface structure. The underfill covers the curved surface structure, and the groove at least includes the orthographic projection area of the curved surface structure area on the solder mask layer; the inner wall surface and the outer wall surface of the groove are circular arc-shaped curved surfaces; or, the inner wall surface and the outer wall surface of the groove are a combination of multiple vertical surfaces extending along the outer contour of the curved surface structure, forming a polygon in the shape of "c"; circular chamfers are formed at the four vertices of the bottom surface of the groove.

2. The chip packaging structure according to claim 1, wherein, an S-shaped curved surface structure is formed at the top end of the functional surface of the chip. The S-shaped curved surface structure includes a first curved surface structure protruding outward along the surface of the chip and a second curved surface structure recessed inward along the surface of the chip. The functional surface of the chip sequentially transitions to the side surface of the chip along the first curved surface structure and the second curved surface structure.

3. The chip packaging structure according to claim 2, wherein Along the longitudinal section direction of the packaging structure, the length of the orthographic projection area of the curved surface structure on the solder mask layer is L, and the outer end of the groove at least extends beyond the outer end of the orthographic projection area of the curved surface structure on the solder mask layer by L / 2.

4. The chip packaging structure according to claim 3, wherein, Along the longitudinal section direction of the packaging structure, the length of the orthographic projection area of the curved surface structure on the solder mask layer is L, and the inner end of the groove at least extends beyond the inner end of the orthographic projection area of the curved surface structure on the solder mask layer by L / 2.

5. The chip packaging structure according to claim 1, characterized in that, The depth of the groove is 50% of the thickness of the solder mask layer.

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