A flip chip power semiconductor device with a pedestal bump and a manufacturing method thereof

Abstract

The application discloses a bottom protruding inverted packaging power semiconductor device and a manufacturing method, a chip source is directly welded to a packaging frame bottom, most of the chip heat is conducted to the outside through the source on the front of the chip and the packaging frame bottom, and a small part of the chip heat is conducted to the outside through the pin of the device and the packaging shell; the corresponding welding areas of the source and the gate of the frame and the chip are in a protruding shape, the frame is made by punching the extruded copper strip into a shape; the manufacturing method aligns and bonds the source and the gate of the power chip to the packaging frame for welding the protruding part of the source and the gate, prepositions a soldering sheet or solder in the area of the source and the gate between the chip and the frame which needs to be welded, and welds the frame and the chip by heating to realize the physical connection and the electrical connection of the chip and the frame. The power semiconductor device of the scheme has obviously improved heat dissipation performance and greatly improved current carrying capacity.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device manufacturing technology, specifically relating to a structural form, manufacturing method, and application for improving the performance of power semiconductor devices. Background Technology

[0002] Currently manufactured power semiconductor devices such as BJTs, MOS, and IGBTs typically have three electrodes: a source or emitter and a gate or base on the front side of the chip, and a drain or collector on the back side (i.e., emitter E and base B on the front side of a BJT device, and collector C on the back side; source S and gate G on the front side of a MOS device, and drain D on the back side; emitter E and gate G on the front side of an IGBT device, and collector C on the back side). The following explanation uses a MOS device as an example; BJT and IGBT power devices can be understood by analogy.

[0003] Early semiconductor device design and manufacturing were relatively rudimentary, so production processes prioritized simplicity and ease of execution. Clearly, a single electrode on the back of the chip is easier to solder to the package base, while the two electrodes on the front are more easily achieved through wire bonding. However, with two electrodes on the front, aligning them with the frame base presents several challenges: firstly, the chip's source and gate electrodes must be precisely aligned with the frame's source and gate electrodes, requiring extremely high positioning accuracy; secondly, the extremely small gap between the electrodes makes short circuits very easy to occur, leading to difficulty in controlling the soldering process and compromising production efficiency. Furthermore, early manufacturing technologies and processes were less advanced, resulting in lower power outputs and smaller chip sizes, making the alignment of the two electrodes even more challenging. Therefore, traditional semiconductor device manufacturing involved soldering or bonding the chip's drain, i.e., the back of the chip, to the package base. Soldering the single electrode on the back of the chip to the package base required less precise positioning. Consequently, the surfaces connecting the traditional package base and the chip were flat, allowing a single package base to accommodate chips of various sizes and specifications, reducing manufacturing and development costs. After the back of the chip is soldered to the frame, the source and gate are connected to the frame leads on the front side by wire bonding.

[0004] The semiconductor discrete device industry has evolved from low-frequency and low-power devices to high-frequency and high-power devices as applications upgrade, with increasingly higher frequency, power, and power density requirements.

[0005] In recent years, in order to meet the increasing demand for semiconductor devices, it is necessary to reduce the package impedance and improve the heat dissipation problem of power devices. The CLIP jumper technology developed in recent years is an innovative manufacturing process to improve the package impedance, but its package base has never been separated from the planar structure.

[0006] Since all electronic components generate heat and experience temperature rise whenever current flows through them, excessively high temperatures can cause device damage and failure. Therefore, for high-power applications, the primary issue to ensure the reliability of power chips and the normal operation of power devices is controlling device heat generation through chip design, chip manufacturing materials, and chip processing technology. Another key measure is to improve heat dissipation and reduce the temperature rise of power devices by optimizing packaging design, packaging materials, and packaging processes.

[0007] In existing power semiconductor devices, the back of the chip is connected to the package base. Since the back of a power chip is typically at a high or fluctuating potential, traditional power device applications require an insulating layer between the chip and the external heatsink for electrical isolation. This can be achieved by adding an insulating pad between the metal base and the heatsink, adding internal ceramic insulation within the package, or using a plastic encapsulation layer for electrical isolation. Because electrical isolation is necessary, the chip's heat must pass through the insulating layer for dissipation. However, the insulating layer has low thermal conductivity and high thermal resistance, severely hindering system heat dissipation. Whether it's adding an insulating layer made of mica, ceramic, or plastic between the metal base and the heatsink, directly using plastic encapsulation (where the encapsulation layer acts as the insulating layer), or having an internal insulating layer, the heat generated by the power chip is conducted through the back of the chip to the package base, then through the insulating layer, and finally dissipated by the heatsink.

[0008] However, electrically isolated insulating layers typically have low thermal conductivity, high thermal resistance, and difficulty in heat dissipation. In practical applications, the temperature rise of power devices is mainly controlled by increasing the area of ​​the power chip, reducing the internal resistance of the chip, and controlling the heat generated by the chip, so as to ensure that the power chip operates within a reasonable temperature range. Although this can meet the needs of practical applications, the increase in chip area means an increase in cost; the larger chip area also increases the junction capacitance, which limits the high-frequency application of power devices.

[0009] Therefore, reducing the thermal resistance of power semiconductor devices, improving the heat dissipation performance of power semiconductor devices, reducing the high-frequency radiation of the power device casing, and improving the switching frequency characteristics of power devices are urgent problems that need to be solved in the current power semiconductor device industry. Summary of the Invention

[0010] To address the issues of high thermal resistance and poor heat dissipation in existing power semiconductor device technologies, and to meet the growing market demand for higher power and power density in power semiconductor applications, it is urgently necessary to reduce high-frequency radiation from power semiconductor device packages, lower the thermal resistance of power semiconductor device systems, improve the heat dissipation performance of power semiconductor devices, and significantly improve the temperature rise, current carrying capacity, reliability, and lifespan of power semiconductor devices. Therefore, this invention adopts the following technical solution:

[0011] A flip-chip power semiconductor device with a raised base has its chip source directly soldered to the package frame base. Most of the heat generated by the chip is conducted outward through the source on the front of the chip and the package frame base, while a small portion of the heat generated by the chip is dissipated outward through the device pins and the package shell.

[0012] In source-grounded applications, the power devices manufactured using this invention do not require electrical isolation between the power chip and the external heat sink. Eliminating the insulation layer saves costs while significantly reducing system thermal resistance by eliminating the thermal resistance of the insulation layer, thus improving system heat dissipation and reducing the temperature rise of the power chip. Furthermore, grounding the package base directly shields the electromagnetic radiation from the package shell, thereby greatly improving the electromagnetic radiation of the power device.

[0013] However, unlike the single electrode on the back, the front of a chip has two electrodes. In addition to the source electrode, there is also a gate electrode, and the gap between the two electrodes is very small. When the front of the chip is aligned and soldered to the package substrate, short circuits between the two electrodes on the front of the power chip, as well as short circuits between the front and back electrodes, are highly likely to occur. Although the problem of solder bridging and short circuits can be solved using IC flip-chip packaging with ball-mounting technology, the cost of this process is too high and cannot meet the cost requirements for power semiconductor device manufacturing applications.

[0014] In this invention application, the areas where the source and gate electrodes on the front of the frame and the power chip are welded are higher than the large plane of the package base, forming a raised state. More space is left around the raised area between the package base and the chip, which can be used to solve the problem of overflowing solder accumulation and effectively avoid short circuits between electrodes.

[0015] In addition, different specifications of chips will have different sizes, and the source and gate sizes and corresponding positions will also be different. It is difficult for a single base to accommodate multiple different specifications of chips. Flip packaging will increase the investment in product development. However, for products with large market demand, these initial investments are well worth it because they can significantly improve performance and cost-effectiveness.

[0016] As attached Figure 2 The strip of copper is formed by extrusion. The left part of the area where the lower surface of the strip of copper is raised and the frame thickness is reduced is used to make the heat dissipation base of the packaging frame; the right part of the area where the lower surface is raised and the frame thickness is reduced is used to make the electrical connection pin part of the frame; the raised part of the upper surface of the strip of copper in the middle part is used to make the welding area corresponding to the source and gate metal of the power chip.

[0017] The manufacturing method of the power semiconductor device: the source and gate of the power chip are aligned and attached to the protrusions of the source and gate for welding on the packaging frame. Solder pads or solder are pre-placed in the source and gate regions between the chip and the frame to achieve welding. The frame and the chip are welded by heating to achieve physical and electrical connection between the chip and the frame.

[0018] The main purpose of the raised frame is to make the soldering surface of the package base protrude, leaving more space around the protrusion between the package base and the chip. This can be used to solve the problem of overflowing solder accumulation, ensure the voltage breakdown distance between the drain on the back of the chip and the source of the device frame, and ensure the device's resistance to voltage breakdown. The raised frame can allow overflowing solder to flow to the copper frame under the chip, avoiding lateral solder extension that could cause solder bridging or short circuits between the source and gate on the front of the chip, and between the source and gate on the front of the chip and the drain on the back of the chip.

[0019] Due to the tin-repellent properties of the passivation layers around the chip source and gate, the tin-affinity properties of the frame copper material, and the gravity of the solder, the solder that overflows after heating during device soldering will flow towards the lower frame of the chip, such as... Figure 4 As shown in (b), 4(c), and 4(d), solder bridging and short circuits between the electrodes of power devices can be effectively avoided during the soldering process.

[0020] The source and gate of the frame and the chip have a raised welding area. The frame is made by extruding copper into strips and then punching it. Other methods such as chemical etching and mechanical cutting can also be used to process the required frame, but the processing efficiency is low and the production cost is too high. It is not suitable for large-scale production except for research and development of new products and trial production, and it lacks mass production value.

[0021] First, a strip of copper material is used to create the packaging frame. This strip of copper material protrudes from the area where the power chip's source and gate are welded. The height of the protrusion depends on multiple factors, including the application voltage requirements of the power device, the chip area (i.e., current or power consumption) requirements, and the frame forming and punching process.

[0022] Specifically: the higher the required source and drain breakdown voltage, the greater the required bump height; the larger the chip area (or rated current), the more solder may overflow during the soldering process, thus requiring a greater bump height; the greater the bump height, the more copper is consumed, leading to increased packaging frame costs; at the same time, the greater the bump height, the more difficult the mechanical punching becomes, increasing production difficulty, and even increasing the punching distance between the source and gate of the frame, reducing the actual soldering area of ​​the source, resulting in a corresponding increase in package thermal resistance; therefore, the frame bump height needs to be determined after comprehensively considering the above multiple factors, and the bump height is generally 0.1-1mm.

[0023] After the strip copper material is extruded, the raised areas that are welded to the chip source and gate are retained, while other parts are removed by mechanical punching. Figure 3 (a) and 3(b) ensure the insulation distance between the chip drain and the source of the package frame; other parts (such as the right electrode lead part, the left bolt fixing hole, etc.) are punched together to form the package frame; the surface treatment of the package frame is consistent with the conventional semiconductor device packaging method.

[0024] With the continuous development of semiconductor manufacturing technology, the processing precision and manufacturing technology have kept pace with the times. In addition, with the improvement of frame design and the addition of packaging base welding bosses, it is now possible to meet the production needs of aligning and welding the two electrodes on the front of the flip chip with the two electrodes of the packaging frame. This is a necessary condition for the flip power device of this application to achieve actual production.

[0025] Although a small number of manufacturers have recently launched source-bottom MOS products that connect the chip source to the package base, the surface where the package base connects to the chip has always been flat, whether it is the traditional upright packaging process, the CLIP jumper packaging process, or the newly developed source-bottom packaging process. Furthermore, source-bottom MOS products have only been launched in a small number of low-power, low-voltage, surface-mount packages and have not been promoted to the high-voltage, high-power device category.

[0026] For planar frame bases, the solder overflowing between the chip and the frame base during the soldering process can easily cause short circuits between electrodes, reducing the breakdown voltage between electrodes, which is one of the key issues. After the soldering surface of the package base protrudes, more space is left around the boss, which can be used to solve the problem of overflowing solder accumulation, effectively avoid short circuits between electrodes during the production of flip-package power devices, reduce the manufacturing difficulty of flip-package power devices, improve product yield, and effectively manage the manufacturing cost of flip-package power devices.

[0027] After the chip is flipped, the chip's source is connected to the package socket. This is a common scenario... Figure 7 , Figure 8 In applications where the source electrode is grounded, there is no need to use an electrical isolation insulation layer between the flip-chip power device and the heat sink. Typically, the thermal resistance of the electrical isolation insulation layer accounts for more than 70% of the system thermal resistance. The technical solution of this invention can save the cost of the insulation layer, while significantly reducing the thermal resistance of the power device system, improving the heat dissipation performance of the power device, reducing the operating temperature rise of the power device chip, increasing the service life of the power device, and improving the current carrying capacity of the power device.

[0028] For power devices used in switching circuits, such as switching power supplies, inverters, frequency converters, and motor drives, the radiation emitted by their metal casings is closely related to the pulse frequency, pulse voltage, and the shape of the package. Theoretically, with a fixed pulse frequency and package size, the radiation is proportional to the square of the voltage. However, this invention introduces flip-chip technology, connecting the chip's source to the package. Whether the power device's source is grounded or connected to a low potential in practical applications, this undoubtedly significantly reduces the electromagnetic radiation emitted by the power device's package.

[0029] See Figure 9 The resistivity of the epitaxial layer of power device chips is typically three orders of magnitude higher than that of the substrate. The chip's internal resistance is mainly concentrated in the epitaxial layer, and heat generation is a product of current flowing through the resistance, thus primarily concentrated in the epitaxial layer. Typically, the substrate thickness of a wafer is about several hundred micrometers, while the epitaxial layer thickness is generally a few to tens of micrometers; the higher the breakdown voltage, the thicker the epitaxial layer. Clearly, when a chip is flip-chip mounted, the heat dissipation path from the source (the front side of the chip) is shorter than from the drain (the back side of the chip). In other words, flip-chip mounting can reduce the chip's thermal resistance and improve the heat dissipation performance of power devices.

[0030] For high-power devices, it is crucial to carefully consider the impact of the chip substrate on heat dissipation, minimizing the temperature rise of the power device. Traditional manufacturing methods involve grinding away a portion or most of the substrate after wafer fabrication to reduce thermal resistance and improve heat dissipation. Currently, the best-performing technology in the power semiconductor device industry reduces substrate thickness from approximately 700µm (the thickness of an 8” wafer is typically 700µm; thinner substrates are prone to breakage during production, causing significant losses) to approximately 50µm. Domestic power chip thickness is generally 150-200µm, with a few manufacturers reducing it to approximately 120µm. While thinning reduces thermal resistance and improves heat dissipation, the cost of thinning accounts for approximately 15% or more of the chip manufacturing cost, representing a significant expense and requiring considerable time. This invention addresses this issue by applying heat dissipation from the front of the chip, effectively avoiding the heavy reliance on chip thinning in power devices, saving time, effort, and costs.

[0031] The power semiconductor devices in this application can be high-power devices such as BJTs, MOS, and IGBTs made of silicon-based, silicon carbide, gallium nitride, or other compound semiconductor materials; the package can be a commonly used standard through-hole package such as TO-220 and TO-247, a standard surface mount package such as TO-263, DFN5*6, DFN8*8, and TOLL, as well as a module or other custom non-standard package structure.

[0032] The main difference between the power semiconductor device of this application and the prior art is that:

[0033] As attached Figure 1 The gate of the power chip is located at one corner of the chip; unlike the current chip design principles of manufacturing processes, the gate of currently manufactured chips is generally located in the middle of one side of the chip.

[0034] During frame extrusion molding, the protrusions used for soldering the source and gate electrodes of the chip will protrude from the bottom plane of the frame. The determination of the protrusion height depends on multiple factors, including the application voltage requirements of the power device, the chip area (power consumption or rated current) requirements, and the frame molding and punching process. To prevent short circuits between chip electrodes caused by solder, the protruding parts of the frame around the chip are removed during frame manufacturing using punching or other processing methods during frame molding. Figure 3 (a) Figure 3 (b);

[0035] On the front side of the chip, the source and gate metal regions used for electrical connections are attached to the raised areas of the frame corresponding to the soldering points, soldering the source on the front side of the chip to the package base. This differs from traditional semiconductor device packaging processes where the drain on the back of the chip is soldered to the frame base. In many practical applications, the source of power devices is grounded. In this case, electrical isolation between the heat sink and the source of the power device is not required. This changes the heat dissipation path of the power chip from the traditional packaging heat dissipation mode: chip heat dissipation via (chip drain → package base → electrical isolation layer → heat sink) to an improved packaging heat dissipation mode: chip heat dissipation via (chip source → package base → heat sink). First, it saves the cost of electrical isolation layer material. More importantly, the electrical isolation layer has low thermal conductivity, high thermal resistance, and is difficult to conduct heat. Typically, the thermal resistance of the electrical isolation layer accounts for more than 70% of the system thermal resistance. Saving on the electrical isolation layer will greatly improve the heat dissipation performance of the power device, increase the current carrying capacity of the power device, reduce the operating temperature rise of the power chip, improve the operating environment of the power chip, and improve the reliability and lifespan of the power device.

[0036] During the chip mounting process, a chip flipping step is added. In existing semiconductor device packaging technologies, the back of the chip is soldered to the packaging frame base. During manufacturing, only the chip needs to be picked up and placed onto the packaging frame base. The technical solution in this application, however, involves attaching the front of the chip to the frame base, requiring an additional chip flipping step. Furthermore, it necessitates ensuring the accurate alignment of the chip's source and gate terminals with the corresponding positions on the frame, placing high demands on chip positioning. Existing processing equipment technology can fully meet the chip positioning requirements for flip-chip product manufacturing.

[0037] In traditional semiconductor chip packaging, the drain is soldered to the package substrate on the back side, while the source and gate on the front side are mostly electrically connected via wire bonding. The front side of the chip is typically an aluminum metal layer, which is sufficient for wire bonding or aluminum strip bonding. However, if a copper frame needs to be bonded, the aluminum-copper bonding performance is poor. Flip-chip designs use a bonding process for the source and gate. The original aluminum metal layer on the front side of the chip needs to be electroplated with copper, silver or silver alloy, gold or gold alloy, or other plating suitable for bonding with the copper frame to facilitate bonding of the chip's source, gate, and copper frame. The drain metal layer on the back side of the chip is selected based on the specific requirements of the jumper bonding process. Although wire bonding is simpler and more convenient, CLIP jumper bonding packages have lower internal resistance, lower parasitic inductance, and superior overall performance. Therefore, this application prefers to use copper, silver or silver alloy, or gold or gold alloy plating on the back side of the chip during processing, and to use CLIP jumper bonding to achieve electrical connection of the drain electrode on the back side of the chip during power device packaging.

[0038] Other manufacturing technologies and requirements, such as copper wire bonding, aluminum wire bonding, aluminum strip bonding, or jumper wire connection between chips and frame leads, frame surface treatment, and molding, are consistent with those of traditional power semiconductor device manufacturing.

[0039] Beneficial effects

[0040] The performance improvement of this invention is very significant. Taking N-channel MOS as an example, since the source of the power chip is soldered to the package base, and the source of the power device is usually connected to a low potential in actual applications, or even grounded in many applications, theoretically the high-frequency radiation energy is proportional to the square of its pulse voltage. Obviously, connecting the shell to a low potential can significantly reduce the high-frequency radiation of the power device package shell.

[0041] As attached Figure 10 This is a schematic diagram of the potential waveforms of the drain and source of a switching MOSFET in a conventional 220V switching power supply. Electromagnetic radiation is mainly related to pulse frequency, pulse voltage, and the shape of the device package. Theoretically, electromagnetic radiation is proportional to the square of the voltage. With the pulse frequency and device shape remaining constant, the electromagnetic radiation from the source connected to the package base is approximately 1 / 100,000 that from the drain connected to the package base, significantly reducing electromagnetic radiation. It is said that power supply design engineers spend about 1 / 4 to 1 / 3 of their time optimizing and improving electromagnetic radiation when developing a high-end switching power supply, demonstrating how difficult it is to solve this problem.

[0042] Taking an N-channel MOSFET as an example, in source-grounded applications, the metal casing base of the power device manufactured in this application is connected to the chip source, and the package casing base can be directly connected to the heat sink and grounded. This differs from traditional packaged chips where the drain is connected to the package casing. The drain is at a high potential and undergoes potential changes, requiring electrical isolation when connecting to the heat sink. The electrical isolation insulation layer has very high thermal resistance, making heat dissipation difficult. Power devices manufactured using the method of this application can omit the insulation layer, significantly improving heat dissipation performance in power device applications. This achieves practical effects such as enhancing the heat dissipation capacity and current carrying capacity of power semiconductor devices, as well as improving switching frequency characteristics.

[0043] Traditional packaging involves soldering the back drain of the power chip to the package substrate, as shown in the attached image. Figure 6 Typically, an electrically insulating layer 6-2 is required between the power device package base 6-3 and the heat sink 6-1. Heat generated by the chip is conducted from the back of the chip to the package base, then through the electrically insulating layer, and finally dissipated outwards by the heat sink. The thermal resistance of the insulating layer accounts for more than 70% of the total thermal resistance of the (chip + package + insulating layer + heat sink) system, severely impacting system heat dissipation, resulting in poor heat dissipation and increased operating temperature of the power chip. The power device produced by the method described in this invention can omit the electrically insulating layer, significantly reducing system thermal resistance, improving system heat dissipation capacity, and reducing chip operating temperature rise.

[0044] As attached Figure 7 This is a typical FB-FB inverter circuit diagram, in which the four power MOSFETs Q2, Q4, Q6, and Q8 have their sources grounded. If conventionally packaged power devices are used, because the base of the conventional package is connected to the drain, and the drain is at a high potential and changing potential, an electrically isolated insulating layer must be added when connecting an external heat sink. However, if the flip-chip power devices of this invention are used, since the outer shell is connected to the source and the source is grounded in the circuit application, an electrically isolated insulating layer is not required, which reduces the system thermal resistance and greatly improves the heat dissipation capacity of the power devices.

[0045] As attached Figure 8 This is a typical LLC half-bridge circuit diagram, in which the three power MOSFETs Q2, Q3, and Q4 have their sources grounded. If conventionally packaged power devices are used, because the base of the conventional package is connected to the drain, and the drain is at a high potential and changing potential, an electrically isolated insulating layer must be added when connecting an external heat sink. However, if the flip-chip power device of this invention is used, since the outer shell is connected to the source and the source is grounded in the circuit application, an electrically isolated insulating layer is not required, reducing the system thermal resistance and greatly improving the heat dissipation capacity of the power device. There are countless similar application scenarios, which will not be listed here. This is only used to illustrate the wide application of flip-chip power devices, and the application value of this application is very broad.

[0046] In this application, the frame base corresponding to the welding of the front electrode of the chip is designed to be raised. Due to the tin-repellent properties of the passivation protection layer around the chip source and gate, the tin-affinity properties of the frame copper material, and the gravity of the solder, the solder overflowing after heating during the device welding process will flow to the lower frame of the chip. This helps to avoid short circuits between the source and gate, source and drain, and gate and drain caused by overflowing solder during the welding process between the chip and the frame. The actual effect is to reduce the manufacturing difficulty of power devices, increase the production yield, and reduce manufacturing costs.

[0047] In this application, the frame base corresponding to the electrode on the front of the chip is designed to be raised, which increases the creepage distance between the chip drain and the frame source, as well as between the chip drain and the frame gate. This can improve the voltage breakdown resistance of power devices and meet the practical application requirements of flip-chip technology in high-voltage MOS and IGBT fields of power semiconductor devices.

[0048] As attached Figure 9 To briefly explain the manufacturing structure of a MOS device, first a substrate is fabricated, then an epitaxial layer is grown on the substrate, and finally the source is fabricated on the epitaxial layer. Typically, the resistivity of the epitaxial layer is more than three orders of magnitude higher than that of the substrate. The chip's internal resistance is mainly concentrated in the epitaxial layer, so heat generation is also concentrated in the epitaxial layer. During chip fabrication, if the substrate thickness is too thin, it can easily cause wafer breakage and damage. Typically, the substrate thickness of an 8” wafer is about 700µm, and the epitaxial layer is generally several micrometers to tens of micrometers thick. The higher the breakdown voltage, the thicker the epitaxial layer. Obviously, after flipping the chip, the heat dissipation path from the source (the front side of the chip) is shorter than that from the drain (the back side of the chip). Clearly, flipping the chip can reduce the chip's thermal resistance.

[0049] For low-power devices, the temperature rise is not significant due to the small current and low heat generation. However, for high-power devices, it is crucial to consider improving heat dissipation and reducing temperature rise. Traditional manufacturing methods involve grinding away a portion of the substrate after wafer fabrication, before dicing and packaging. Currently, the best-performing technology in the power semiconductor device industry is reducing wafer thickness from approximately 700µm to approximately 50µm. While thinning reduces chip thermal resistance, the cost accounts for approximately 15% or more of the chip manufacturing cost, representing a significant expense, and it also takes a considerable amount of time. Therefore, the solution proposed in this application saves time, effort, and cost.

[0050] The power semiconductor devices produced by this application, compared with traditionally packaged power semiconductor devices, can achieve the same shape and pin arrangement, but with a thermal resistance reduced by more than half, significantly improved heat dissipation performance, greatly increased current carrying capacity, significantly reduced power device temperature rise, and significantly increased reliability and lifespan. While ensuring significantly improved power device performance, the pin arrangement can be adjusted to meet the actual needs of different users. Attached Figure Description

[0051] Taking MOS as an example (the emitter of IGBT corresponds to the source of MOS, the gate of IGBT corresponds to the gate of MOS, and the collector of IGBT corresponds to the drain of MOS; the emitter of BJT corresponds to the source of MOS, the base of BJT corresponds to the gate of MOS, and the collector of BJT corresponds to the drain of MOS):

[0052] Figure 1 This is a schematic diagram of the power chip structure of the present invention;

[0053] Figure 2 This is a schematic diagram of the strip-shaped copper material structure produced by extrusion processing according to the present invention;

[0054] Figure 3 (a) is a schematic diagram of the copper frame structure of the power semiconductor device of the present invention;

[0055] Figure 3 (b) is a partial enlarged view of the frame structure of the present invention;

[0056] Figure 4 (a) is a schematic diagram of the chip mounting and soldering process of the present invention;

[0057] Figure 4 (b) Figure 4 (c) Figure 4 (d) are partial enlarged detailed views of the source welding region, drain region and gate welding region of the present invention, respectively;

[0058] Figure 5 This is a schematic diagram of the finished power semiconductor device structure after plastic encapsulation according to an embodiment of the present invention.

[0059] 1-Power chip, 11-Power chip source metal, 111-Power chip source solder layer, 12-Power chip drain metal, 13-Power chip gate metal, 131-Power chip gate solder layer, 14-Power chip passivation layer protection zone.

[0060] 2-Copper frame, 21-Copper frame source or source pin, 211-Copper frame to chip source metal bonding area, 22-Copper frame drain or drain pin, 23-Copper frame gate or gate pin, 231-Copper frame to chip gate metal bonding area. 2L-Left side of copper frame, 2M-Middle side of copper frame, 2R-Right side of copper frame.

[0061] Figure 6 : Schematic diagram of power device application; 6-1 is the heat sink of the power device, 6-2 is the electrical isolation insulation layer between the heat sink and the power device, and 6-3 is the copper base of the power device package (in this example, the copper base is coated with thermal grease, so the original color of the copper material is not visible).

[0062] Figure 7 A typical FB-FB inverter circuit diagram;

[0063] Figure 8 A typical LLC half-bridge circuit diagram;

[0064] Figure 9 A simplified structural diagram of a MOS device;

[0065] Figure 10 Waveforms of the drain and source of the switching transistor in a conventional 220V switching power supply. Detailed Implementation

[0066] Taking a power MOS device as an example, this technical solution is explained in detail with reference to the accompanying drawings:

[0067] 1. Power chip design and fabrication:

[0068] Power chip design and fabrication, such as Figure 1 The power semiconductor device chip is designed and manufactured according to the application parameter requirements of the power device. The power chip 1 includes a source 11 and a gate 13 on the front side of the chip, a passivation protection layer 14 between the electrodes, and a drain 12 on the back side of the chip. The gate 13 of the power chip is located at one corner of the chip to maximize the welding area of ​​the source 11 as much as possible.

[0069] The power chip source 11 is directly soldered to the package frame 2, where it is attached to the raised package copper frame and the chip source metal soldering area 211, forming a source connection after soldering. Most of the heat generated by the power chip 1 is conducted through the source 11, through the package frame 2, and dissipated to the outside through the heat sink connected to the package base; a small portion of the heat generated by the power chip 1 is dissipated to the outside through the gate pin 23, the drain pin 22, and the plastic package shell.

[0070] The power chip drain 12 is soldered to the package frame 2 via CLIP jumper wire, and is electrically connected to the drain pin 22 of the package copper frame.

[0071] The power chip gate 13 is directly soldered to the package frame 2, and is attached to the protruding package copper frame and the chip gate metal soldering area 231, forming a gate connection after soldering.

[0072] The power chip in this embodiment is a high-voltage planar MOS device with dimensions of 4.5mm*3.1mm, a design breakdown voltage of 650V, and a design current of 10A.

[0073] 2. Fabrication of a dedicated frame for inverted packaging:

[0074] The specific frame manufacturing method is as follows: This embodiment is a standard TO-220 iron-sealed package. First, metallic copper is extruded into strips of copper material, such as... Figure 2 As shown, the strip copper material is formed by extrusion. The left part 2L of the raised and thinned area on the lower surface of the copper strip is used to make the heat sink base of the power device. In practical applications, it is responsible for connecting the device and the heat sink and conducting the heat of the power chip 1 to the heat sink. The right part 2R of the raised and thinned area on the lower surface is used to make the electrode pins, namely the source pin 21, the drain pin 22, and the gate pin 23. In practical applications, it is responsible for the electrical connection between each electrode of the power device and the application circuit. The upward protruding part on the upper surface of the middle area 2M is used to process the copper frame and the chip source metal welding area 211 and the copper frame and the chip gate metal welding area 231, which are welded to the source 11 and the gate 13 electrodes of the chip respectively to realize the connection between the source and the gate of the power device.

[0075] like Figure 3 ,according to Figure 2 The extruded strip of copper material is mechanically punched and bent to form a copper frame 2 for formal packaging; the right part 2R is punched and bent to form the source pin 21, drain pin 22, and gate pin 23 of the device.

[0076] like Figure 3 (a) Figure 3 (b) For the raised portion on the upper surface of the frame, except for the source 11 welding area 211 and the gate welding area 231, the other raised areas around the chip 1 and the area between the source 11 and the gate 13 are removed by mechanical punching.

[0077] Regarding the protrusion height of the frame: The higher the required breakdown voltage of the source and drain, the greater the required protrusion height is needed to ensure sufficient creepage distance between the source and drain. Higher power requires a larger chip area, potentially leading to more solder overflow during soldering and increasing the likelihood of short circuits between electrodes. Therefore, to increase the physical space around the protrusion to address solder overflow and minimize short circuits, a greater protrusion height is required. However, a larger protrusion height results in higher copper consumption and increased costs. Furthermore, a larger protrusion height leads to a thicker frame, making mechanical punching more difficult and increasing production complexity. This may even necessitate increasing the punching distance between the source and gate, reducing the actual soldering area of ​​the source, and consequently increasing the package thermal resistance. Therefore, the frame protrusion height is determined after considering these multiple factors. In this embodiment, the protrusion height is 0.3mm, and the distance between the source and gate is 0.6mm.

[0078] After completing chip design and manufacturing, and the preparation of the dedicated frame, the next steps are packaging and testing, similar to those for manufacturing ordinary power semiconductor devices. The specific steps are briefly described below:

[0079] 3. Tinning:

[0080] Solder paste is printed on the corresponding parts of the source 211 and gate 231 in the raised area of ​​the copper frame, or solder pads or solder are placed in advance;

[0081] 4. Core loading:

[0082] like Figure 4 (a) Unlike conventional power semiconductor device manufacturing methods, the power chip 1 is flipped over and correspondingly attached to the copper frame 2; as shown in the image. Figure 4 As shown in (a), the source 11 and gate 13 on the front side of chip 1 are aligned and bonded with the source 211 and gate 231 of the frame protrusion area. Since the front mounting process involves soldering the chip to the back side, i.e., the drain, onto the packaging frame base, it is only necessary to place the chip onto the frame base, without the need for the flipping process. Even if there is a misalignment in chip positioning, it has little impact. Therefore, the chip mounting process is a key process in the manufacturing technology of this invention.

[0083] 5. Drain jumper:

[0084] Place an electrical connection piece and an appropriate amount of solder between the chip drain 12 and the frame drain 22 pins;

[0085] 6. Heating and welding:

[0086] like Figure 4(a) After aligning and bonding the source 11 and gate 13 of the power chip 1 with the source welding area 211 and gate welding area 231 of the frame, the bonded chip and frame are heated and soldered together to weld the chip 1 and the frame 2; at the same time, electrical connections are formed between the chip 1 and the frame 2, between the chip source 11 and the frame 21, between the chip gate 13 and the frame 23, and between the chip drain 12 and the frame 22.

[0087] The chip drain 12 and frame 22 can also be electrically connected by other means after the source and gate are soldered.

[0088] like Figure 4 (b), 4(c), and 4(d) show the enlarged details of the soldering process. Due to the tin-repellent properties of the passivation layer 14 of chip 1, the tin-affinity properties of the copper frame 2, and the gravity of the solder, the solder overflowing between chip 1 and frame 2 during the soldering process will flow down to the copper frame 2, rather than extending laterally across the passivation layer 14 and causing a short circuit between the source 11 and the gate 13. It will also not cross the passivation layer 14 and extend upwards, causing a short circuit between the source 11 and the drain 12, or between the gate 13 and the drain 12.

[0089] 7. Clean welding residue:

[0090] Similar to the packaging process of ordinary semiconductor devices, the welding process involves heating and then cleaning up the welding residue to increase the reliability and lifespan of the device.

[0091] 8. Molding:

[0092] like Figure 5 This case involves a standard TO-220 iron seal. After processing such as patch mounting and soldering, it is not yet the final product and requires plastic sealing for protection. For example... Figure 5 As shown, the power semiconductor device products manufactured by the present application can meet the requirements of having the same shape and pin arrangement as ordinary packaged power semiconductor devices; of course, the package shape and pin arrangement can also be adjusted according to the needs of different users.

[0093] 9. Test:

[0094] The prepared product is tested and screened according to the technical requirements. Unqualified products are removed, and the formal product required by this invention is thus prepared.

Claims

1. A flip-chip power semiconductor device with a raised base, characterized in that, The source of the power chip is soldered to the package frame base, the gate of the power chip is disposed at one corner of the chip, and the area where the package frame base is soldered to the source and gate metal layers of the power chip protrudes from the plane of the package frame base. The packaging frame is formed by mechanically punching pre-fabricated strip copper material, which is also formed by mechanically extruding metallic copper. It is raised in the areas corresponding to the source and gate electrodes of the power chip. The left side of the raised and thinned area on the lower surface of the strip copper material is used to create a heat sink for the power device, while the right side is used to create electrode leads, namely the source lead, drain lead, and gate lead. The upward-protruding portion on the upper surface of the middle area is used to process the copper frame-to-chip source metal welding area and the copper frame-to-chip gate metal welding area, respectively welded to the source and gate electrodes of the chip. The protrusion height of the raised areas is determined by a combination of the application voltage of the power semiconductor device, the chip area, and the frame forming and punching process. The source and gate of the power chip are aligned and attached to the package frame for welding the protrusions of the source and gate. The source and gate areas that need to be welded between the chip and the package frame are pre-placed with solder pads or solder. The package frame and the chip are welded by heating to achieve the physical and electrical connection between the chip and the package frame. The source of the power device is grounded. During the packaging process of power devices, the drain electrode on the back of the chip is electrically connected using CLIP jumper wire soldering.

2. The flip-chip power semiconductor device as described in claim 1, characterized in that, The power device chips are BJT, MOS, or IGBT high-power devices made of silicon-based, silicon carbide, gallium nitride, or other compound semiconductor materials.

3. The flip-chip power semiconductor device as described in claim 1, characterized in that, The packaging is in the form of standard TO-220 and TO-247 through-hole packages, standard TO-263, DFN5*6, DFN8*8, and TOLL surface mount packages, as well as module or other custom non-standard packaging structures.

4. The flip-chip power semiconductor device as described in claim 1, characterized in that, The source and gate metal layers on the front side of the power chip are plated, and the metal on the plated surface is copper, silver or silver alloy, gold or gold alloy, or other metal layers that are easy to weld to the copper frame. The metal on the back drain surface of the power chip is copper, silver or silver alloy, gold or gold alloy, or other metal layers that are easy to solder to the copper frame. The back drain of the power chip is connected to the package pins via CLIP process.

5. The method for manufacturing the flip-chip power semiconductor device as described in claim 1, comprising the following specific steps: 1) Power chip design: The power chip has two electrodes, the active electrode and the gate electrode, on the front side and one electrode, the drain electrode, on the back side. The gate electrode on the front side of the power chip is located at one corner of the chip. 2) Copper metal is extruded into strips; 3) Strip copper material is punched to form a power device packaging frame: Extruded strip copper material is punched to form a copper frame for power device packaging. 4) Soldering: Solder paste is printed on the corresponding parts of the source and gate of the copper frame protrusion area, or solder pads or solder are placed in advance; 5) Core loading; 6) Drain jumper: Place an electrical connection piece and an appropriate amount of solder between the chip drain and the frame drain pin; 7) Heating and welding: After aligning and bonding the source and gate of the power chip with the source and gate welding areas of the frame, the bonded chip and frame are heated and soldered together; at the same time, electrical connections are formed between the chip and the frame, the chip source and the frame, the chip gate and the frame, and the chip drain and the frame. 8) Cleaning welding residue: Clean and remove welding residue after heating and welding; 9) Molding: Molding protection is performed, and the package shape and pin arrangement are adjusted according to the needs of different users; 10) Testing: The prepared products will be tested and screened according to the technical requirements; Its features are: In step 2), the strip copper material formed by extrusion process, the left part of the raised and thinned area on the lower surface of the copper strip is used to make the heat sink base of the power device, which is responsible for connecting the device and the heat sink and conducting the heat of the power chip to the heat sink. The right side of the raised and thinned area on its lower surface is used to make electrode pins, which bear the electrical connection between each electrode of the power device and the application circuit. The upward-protruding part on the upper surface of the middle area is used to process the copper frame and the chip source metal welding area, and the copper frame and the chip gate metal welding area, which are respectively welded to the source and gate electrodes of the chip to realize the connection between the source and gate of the power device. In step 5), a dedicated chip-mounting device is used to flip the power chip over and attach it to the copper frame, aligning the source and gate on the front of the chip with the source and gate on the raised area of ​​the frame.

Images