Semiconductor device and method of manufacturing the same

Abstract

Provided are a semiconductor device and a method for manufacturing the same. The method includes: sequentially forming a first oxide layer, a memory layer, a second oxide layer, a control gate layer, and a hard mask layer on a substrate; etching the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer to form a gate stack; forming a first gate spacer and a second gate spacer on opposite sides of the gate stack, respectively; forming a first select gate on a side of the first gate spacer opposite the gate stack, and forming a second select gate on a side of the second gate spacer opposite the gate stack; etching the gate stack to form a first opening; forming a source region in a portion of the substrate below the first opening; and forming a first drain region in the substrate on a side of the first select gate opposite the first opening, and forming a second drain region in the substrate on a side of the second select gate opposite the first opening.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In electronic devices, memory is needed to read and store data. Therefore, as the demand for electronic devices continues to grow, the requirements for memory technology are also getting higher and higher.

[0003] Flash memory is a non-volatile computer storage medium that is electrically erasable and reprogrammable, retaining information even after the power is turned off. Flash memory is easy to use, offers read and write flexibility, fast access speeds, and maintains information after a power outage. Consequently, flash memory technology is developing rapidly.

[0004] Flash memory includes an array of addressable memory cells, wherein each memory cell includes a floating gate transistor for storing corresponding information.Therefore, it is desirable to improve methods of manufacturing flash memory, and particularly memory cells in flash memory. Summary of the Invention

[0005] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: sequentially forming a first oxide layer, a storage layer, a second oxide layer, a control gate layer, and a hard mask layer on a substrate; etching the hard mask layer, the control gate layer, the second oxide layer, the storage layer, and the first oxide layer to form a gate stack consisting of the hard mask layer, the control gate layer, the second oxide layer, the storage layer, and the remaining portion of the first oxide layer; forming a first gate spacer and a second gate spacer on both sides of the gate stack, respectively, and forming a first select gate oxide structure and a second select gate oxide structure on a first region and a second region of the substrate, respectively, wherein: The first region and the second region are located on both sides of the gate stack; a first selection gate is formed on a side of the first gate spacer opposite to the gate stack, and a second selection gate is formed on a side of the second gate spacer opposite to the gate stack; the gate stack is etched to form a first opening through the hard mask layer, the control gate layer, the second oxide layer and the storage layer; a source region is formed in a portion of the substrate located below the first opening; and a first drain region is formed in the substrate on a side of the first selection gate opposite to the first opening, and a second drain region is formed in the substrate on a side of the second selection gate opposite to the first opening.

[0006] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: sequentially forming a first oxide layer, a selection gate layer, and a hard mask layer on a substrate; etching the hard mask layer and the selection gate layer to form a gate stack consisting of the remaining portions of the hard mask layer and the selection gate layer; forming a first storage structure on a first side surface and a first gate region of the gate stack, and forming a second storage structure on a second side surface and a second gate region of the gate stack, wherein the first gate region is located on one side of the first side surface of the gate stack and the second gate region is located on one side of the second side surface of the gate stack; forming a first control gate on the first storage structure, and forming a second control gate on the second storage structure; etching the gate stack to form a first opening passing through the hard mask layer and the selection gate layer; forming a drain region in a portion of the substrate below the first opening; and forming a first source region in the substrate on a side of the first control gate opposite to the first opening, and forming a second source region in the substrate on a side of the second control gate opposite to the first opening.

[0007] According to some embodiments of the present disclosure, a semiconductor device is provided. The semiconductor device is manufactured by the method described in the present disclosure.

[0008] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0011] Figures 2A-2G is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0012] Figures 3A-3M is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0013] Figures 4A-4B is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0014] Figure 5 is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0015] Figure 6 is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0016] Figure 7 is a schematic cross-sectional structural diagram of a semiconductor device according to some embodiments of the present disclosure;

[0017] Figure 8 is a circuit diagram of a memory cell array according to some embodiments of the present disclosure;

[0018] Figures 9A-9B is a top plan view of a memory cell array according to some embodiments of the present disclosure;

[0019] Figure 10 is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0020] Figures 11A-11G is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0021] Figures 12A-12N is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0022] Figures 13A-13B is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0023] Figure 14 is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0024] Figure 15 is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0025] Figure 16 is a schematic cross-sectional structural diagram of a semiconductor device according to some embodiments of the present disclosure;

[0026] Figure 17 is a circuit diagram of a memory cell array according to some embodiments of the present disclosure;

[0027] Figures 18A-18B is a top plan view of a memory cell array according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, the first element, component, area, layer or part discussed below may be referred to as the second element, component, area, layer or part without departing from the teachings of the present disclosure.

[0029] Spatially relative terms such as "below," "beneath," "lower," "beneath," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below" or "beneath" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" may encompass both orientations of "above" and "beneath." Terms such as "before" or "before" and "after" or "followed by" may similarly be used, for example, to indicate the order in which light passes through the elements. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0030] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" specify the presence of the features, wholes, steps, operations, elements and / or parts when used in this specification, but do not exclude the presence of one or more other features, wholes, steps, operations, elements, parts and / or their groups or add one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" refers to only A, only B, or both A and B.

[0031] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “directly adjacent to” another element or layer, no intervening elements or layers are present. However, in no case should “on” or “directly on” be interpreted as requiring that one layer completely cover the underlying layer.

[0032] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. Because of this, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the regions illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0034] As used herein, the term "substrate" may refer to a substrate of a sawed wafer, or may refer to a substrate of an unsawed wafer. Similarly, the terms chip and die may be used interchangeably unless such interchange would cause a conflict.

[0035] In the prior art, common types of flash memory cells include stacked gate memory cells and split gate memory cells. Compared with stacked gate memory cells, split gate memory cells have technical advantages such as lower power consumption and higher injection efficiency. For a flash memory with a split gate memory cell, the present disclosure provides a method for manufacturing a semiconductor device, comprising: sequentially forming a first oxide layer, a storage layer, a second oxide layer, a control gate layer, and a hard mask layer on a substrate; etching the hard mask layer, the control gate layer, the second oxide layer, the storage layer, and the first oxide layer to form a gate stack consisting of the hard mask layer, the control gate layer, the second oxide layer, the storage layer, and the remaining portion of the first oxide layer; forming a first gate spacer and a second gate spacer on both sides of the gate stack, respectively, and forming a first selection gate oxide structure and a second selection gate on the first region and the second region of the substrate, respectively. A gate oxide structure is provided, wherein the first region and the second region are located on both sides of the gate stack; a first selection gate is formed on a side of the first gate spacer opposite to the gate stack, and a second selection gate is formed on a side of the second gate spacer opposite to the gate stack; the gate stack is etched to form a first opening through the hard mask layer, the control gate layer, the second oxide layer and the storage layer; a source region is formed in a portion of the substrate located below the first opening; and a first drain region is formed in the substrate on a side of the first selection gate opposite to the first opening, and a second drain region is formed in the substrate on a side of the second selection gate opposite to the first opening.

[0036] Figure 1 is a schematic flowchart of a method 100 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0037] In step S101 , a first oxide layer, a storage layer, a second oxide layer, a control gate layer, and a hard mask layer are sequentially formed on a substrate.

[0038] According to some embodiments, the manufacturing method 100 further includes: forming shallow trench isolation in the substrate before forming the first oxide layer on the substrate. According to some embodiments, the manufacturing method 100 further includes: implanting memory cell wells in the substrate before forming the first oxide layer on the substrate.

[0039] According to some embodiments, a process of forming shallow trench isolation may include but is not limited to the following steps: forming a liner oxide, depositing silicon nitride, exposing an active area, etching shallow insulating trenches, filling shallow insulating trenches, planarizing shallow insulating trenches, and removing silicon nitride.

[0040] According to some embodiments, step S101 includes: forming a first oxide layer on a substrate; forming a storage layer on the first oxide layer; forming a second oxide layer on the storage layer; forming a control gate layer on the second oxide layer; and forming a hard mask layer on the control gate layer.

[0041] According to some embodiments, the material of the storage layer may be silicon nitride (SiN), or a high-K material such as HfO 2 , HfSiON, Ta 2 O 5 , Al 2 O 3 , TiO 2 , ZrO 2 , etc.

[0042] According to some embodiments, an ONO (oxygen-nitride-oxygen) material is grown on the upper surface of the substrate to form a first oxide layer, a storage layer, and a second oxide; a control gate polysilicon is deposited on the upper surface of the ONO (oxygen-nitride-oxygen) material to form a control gate layer; and a hard mask material (e.g., a silicon nitride material) is deposited on the control gate layer to form a hard mask layer.

[0043] Figure 2A FIG shows a cross-sectional view of an exemplary structure formed after step S101. Figure 2A As shown, the semiconductor structure 200 includes, from bottom to top, a substrate 210 , a first oxide layer 220 , a storage layer 230 , a second oxide layer 240 , a control gate layer 250 and a hard mask layer 260 .

[0044] At step S102 , the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer are etched to form a gate stack consisting of the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and remaining portions of the first oxide layer.

[0045] According to some embodiments, first, a photolithography process is performed on the upper surface of the hard mask layer to form a photoresist pattern; then, the hard mask layer, the control gate layer, the second oxide layer, the memory layer and the first oxide layer are etched using the formed photoresist pattern as a mask.

[0046] Figure 2B FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S102. Figure 2B As shown, the semiconductor structure 200 includes, from bottom to top, a substrate 210 and a gate stack 270, wherein the gate stack 270 includes, from bottom to top, a first oxide layer 220, a storage layer 230, a second oxide layer 240, a control gate layer 250 and the remaining portion of the hard mask layer 260.

[0047] At step S103, a first gate spacer and a second gate spacer are formed on both sides of the gate stack, and a first selection gate oxide structure and a second selection gate oxide structure are formed on a first region and a second region of the substrate, respectively, wherein the first region and the second region are located on both sides of the gate stack.

[0048] According to some embodiments, a first gate spacer and a second gate spacer are formed on both sides of a gate stack, and a first selection gate oxide structure and a second selection gate oxide structure are formed on a first region and a second region of a substrate, respectively, including: forming a control gate spacer on both sides of the gate stack; depositing a first gate oxide film on the side and upper surface of the gate stack, and on the first region and the second region of the substrate; removing portions of the first gate oxide film on the upper surface of the gate stack, and on the first region and the second region of the substrate to form a first gate spacer and a second gate spacer; and forming a first selection gate oxide structure and a second selection gate oxide structure on the first region and the second region of the substrate, respectively.

[0049] According to some embodiments, after etching the hard mask layer, the control gate layer, the second oxide layer, the storage layer and the first oxide layer, a control gate spacer is formed on both sides of the hard mask layer, the control gate layer, the second oxide layer, the storage layer and the remaining portion of the first oxide layer, for example, a control gate oxide (e.g., silicon oxide) is deposited on both sides of the hard mask layer, the control gate layer, the second oxide layer, the storage layer and the remaining portion of the first oxide layer, and the deposited control gate oxide is etched to form the control gate spacer.

[0050] According to some embodiments, depositing a first gate oxide film on the side and upper surface of the gate stack, and the first and second regions of the substrate includes: depositing the first gate oxide film on the side and upper surface of the gate stack, and the first, second and high-voltage tube regions of the substrate.

[0051] According to some embodiments, the first gate oxide film is etched (e.g., dry etching and wet etching) to retain a portion of the first gate oxide film on the sidewalls of the gate stack. According to some embodiments, after etching the first gate oxide film, a high-temperature rapid thermal process is performed to enhance the quality of the oxide on the sidewalls.

[0052] In the embodiments described in the present disclosure, a high-voltage tube oxide structure having a thickness different from that of the selection gate oxide structure is formed on the high-voltage tube region by depositing an oxide film and removing excess oxide during deposition, so as to facilitate the subsequent formation of corresponding high-voltage logic devices (for example, high-voltage devices powered by 11V) on the high-voltage tube region.

[0053] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure also includes performing selective gate channel ion (e.g., boron or BF2) implantation in the first and second regions of the substrate before depositing a first gate oxide film on the side and upper surfaces of the gate stack, and the first and second regions of the substrate.

[0054] According to some embodiments, performing select gate channel ion implantation in the first and second regions of the substrate includes: performing select gate channel photolithography to form a photoresist pattern to protect regions where ion implantation is not required; and performing select gate channel ion implantation using the formed photoresist pattern as a mask.

[0055] Figure 2C FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S103. Figure 2C As shown, the semiconductor structure 200 includes, from bottom to top, a substrate 210 and a gate stack 270. The gate stack 270 includes, from bottom to top, a first oxide layer 220, a memory layer 230, a second oxide layer 240, a control gate layer 250, and the remaining portion of the hard mask layer 260. The semiconductor structure 200 also includes first and second gate spacers 271a and 271b formed on both sides of the gate stack 270, and first and second select gate oxide structures 222a and 222b formed on the first and second regions of the substrate 210, respectively.

[0056] It should be understood that although the first selection gate oxide structure 222a and the first gate spacer 271a are shown as two separate parts, and the second selection gate oxide structure 222b and the second gate spacer 271b are shown as two separate parts, the first selection gate oxide structure 222a and the first gate spacer 271a can actually be continuous oxides but with different thicknesses, and the second selection gate oxide structure 222b and the second gate spacer 271b can actually be continuous oxides but with different thicknesses, for example, formed by the above-mentioned oxide film deposition step.

[0057] According to the embodiments described above, by retaining or additionally forming an oxide structure on the side of the gate stack before depositing the first gate oxide film on the first and second regions of the substrate, as well as on the side and upper surface of the gate stack, the gate oxide structure can be selected to have a different thickness from the gate spacer structure. For example, a thicker gate spacer structure is beneficial for data storage, and a thinner selection gate oxide structure is beneficial for improving the performance of the memory device (for example, providing a larger read current).

[0058] At step S104 , a first select gate is formed on a side of the first gate spacer opposite to the gate stack, and a second select gate is formed on a side of the second gate spacer opposite to the gate stack.

[0059] According to some embodiments, a logic well implant is performed in the substrate before forming a first select gate on a side of the first gate spacer opposite the gate stack and forming a second select gate on a side of the second gate spacer opposite the gate stack; forming a logic IO gate oxide structure on the substrate; and forming a logic core gate oxide structure on the substrate.

[0060] According to some embodiments, forming a first selection gate oxide structure and a second selection gate oxide structure on a first region and a second region of the substrate, respectively, includes forming the first selection gate oxide structure and the second selection gate oxide structure on the first region and the second region of the substrate, respectively, while forming a logic IO gate oxide structure or a logic core gate oxide structure.

[0061] According to some embodiments, forming a first selection gate on a side of the first gate spacer opposite to the gate stack, and forming a second selection gate on a side of the second gate spacer opposite to the gate stack includes: depositing selection gate polysilicon on the first selection gate oxide structure and the second selection gate oxide structure, and on the gate stack; and removing a portion of the deposited selection gate polysilicon to form the first selection gate and the second selection gate.

[0062] According to some embodiments, the deposited select gate polysilicon has the same coverage on the first select gate oxide structure, the second select gate oxide structure, and the surface of the gate stack, so that the deposited select gate polysilicon presents a "convex" shape. For example, as described below with reference to Figure 3G Described in detail.

[0063] According to some embodiments, removing portions of the deposited selection gate polysilicon to form a first selection gate and a second selection gate includes: planarizing the deposited selection gate polysilicon; etching the planarized selection gate polysilicon to form a first polysilicon structure and a second polysilicon structure located on a first region and a second region of the substrate, respectively; and etching the first polysilicon structure and the second polysilicon structure to form a first selection gate and a second selection gate, respectively.

[0064] According to some embodiments, the deposited select gate polysilicon is planarized to remove the select gate polysilicon deposited above the gate stack. According to some embodiments, during the planarization of the deposited select gate polysilicon, oxide deposited above the gate stack in a previous step may also be removed.

[0065] According to some embodiments, etching the planarized select gate polysilicon to form a first polysilicon structure and a second polysilicon structure respectively located on a first region and a second region of the substrate includes etching shoulders of the "L"-shaped select gate polysilicon on both sides of the gate stack to form a first polysilicon structure and a second polysilicon structure respectively located on the first region and the second region of the substrate in a rectangular shape, so as to facilitate subsequent etching using a photoresist or a hard mask spacer as a mask to form the first select gate and the second select gate. For example, as described below with reference to Figure 3H Described in detail.

[0066] According to some embodiments, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, includes: performing a first photolithography process on the first polysilicon structure and the second polysilicon structure; etching the first polysilicon structure and the second polysilicon structure using the photoresist pattern formed by the first photolithography process as a mask to form the first select gate and the second select gate, respectively; and removing the photoresist pattern formed by the first photolithography process. For example, as described below with reference to Figures 3I-3J Described in detail.

[0067] According to some embodiments, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, includes: forming a first hard mask spacer and a second hard mask spacer on both sides of the gate stack, respectively, the first hard mask spacer being located on the first polysilicon structure, and the second hard mask spacer being located on the second polysilicon structure; and etching the first polysilicon structure and the second polysilicon structure using the first hard mask spacer and the second hard mask spacer as masks to form the first select gate and the second select gate, respectively. For example, as described below with reference to Figures 4A-4B Described in detail.

[0068] According to some embodiments, removing portions of the deposited select gate polysilicon to form the first select gate and the second select gate includes self-aligned etching of the deposited select gate polysilicon to form the first select gate and the second select gate, respectively. For example, as described below with reference to Figure 5 Described in detail.

[0069] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure also includes: depositing logic gate polysilicon on the logic gate region of the substrate while depositing selection gate polysilicon on the first selection gate oxide structure and the second selection gate oxide structure and on the gate stack; and removing part of the deposited selection gate polysilicon to form the first selection gate and the second selection gate while removing part of the logic gate polysilicon to form the logic gate.

[0070] According to some other embodiments, logic gate polysilicon is deposited on the logic gate region of the substrate while select gate polysilicon is deposited on the first select gate oxide structure and the second select gate oxide structure and on the gate stack; and, in a processing step different from removing the portion of the deposited select gate polysilicon, a portion of the logic gate polysilicon is removed to form a logic gate.

[0071] Figure 2D FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S104. Figure 2D As shown, the semiconductor structure 200 includes, in addition to the substrate 210, the gate stack 270, the first selection gate oxide structure 222a, the first gate spacer 271a, the second selection gate oxide structure 222b and the second gate spacer 271b, a first selection gate 280a formed on the side of the first gate spacer 271a opposite to the gate stack 270, and a second selection gate 280b formed on the side of the second gate spacer 271b opposite to the gate stack 270.

[0072] At step S105 , the gate stack is etched to form a first opening passing through the hard mask layer, the control gate layer, the second oxide layer, and the memory layer.

[0073] According to some embodiments, etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the second oxide layer and the remaining portion of the storage layer includes: performing source photolithography to form a photoresist pattern; and etching the gate stack using the formed photoresist pattern as a mask to form the first opening.

[0074] Figure 2E FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S105. Figure 2E As shown, Figure 2DIn comparison, the first opening 272 passes through the hard mask layer, the control gate layer, the second oxide layer and the remaining portion of the storage layer, wherein the hard mask layer, the control gate layer, the second oxide layer and the remaining portion of the storage layer include gate structures of the memory cells respectively belonging to both sides, i.e., the gate structure located on the left side composed of the first storage layer 230a, the second oxide structure 240a on the left side, the first control gate 250a and the first hard mask 260a and the gate structure located on the right side composed of the second storage layer 230b, the second oxide structure 240b on the right side, the second control gate 250b and the second hard mask 260b.

[0075] At step S106 , a source region is formed in a portion of the substrate below the first opening.

[0076] According to some embodiments, the source region is formed by source ion implantation (e.g., arsenic and phosphorus), thereby forming a graded junction in the substrate. That is, in the source region, the source ion doping concentration gradually decreases from the first oxide layer to the substrate, thereby improving the stress-bearing capability of the semiconductor device. In the embodiments described in the present disclosure, because the gate structures and oxide structures of the memory cells on both sides are formed first, and the source region implantation is performed later, the performance of the source region is avoided by the thermal deposition step of forming the gate and oxide structures.

[0077] Figure 2F FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S106. Figure 2F As shown, Figure 2E In contrast, the semiconductor device 200 includes a source region 212 in the substrate 210 below the first opening 272 .

[0078] At step S107 , a first drain region is formed in the substrate on a side of the first select gate opposite to the first opening, and a second drain region is formed in the substrate on a side of the second select gate opposite to the first opening.

[0079] According to some embodiments, forming a first drain region in the substrate on a side of the first selection gate opposite to the first opening, and forming a second drain region in the substrate on a side of the second selection gate opposite to the first opening includes: performing lightly doped drain implantation in the substrate on a side of the first selection gate opposite to the first opening and in the substrate on a side of the second selection gate opposite to the first opening to form a first lightly doped drain region located on one side of the first selection gate and a second lightly doped drain region located on one side of the second selection gate; forming a first drain spacer on a side of the first selection gate opposite to the first opening, and forming a second drain spacer on a side of the second selection gate opposite to the first opening; forming a first source spacer on a side of the first selection gate facing the first opening, and forming a second source spacer on a side of the second selection gate facing the first opening; and performing heavily doped drain implantation in the substrate on a side of the first drain spacer opposite to the first opening and in the substrate on a side of the second drain spacer opposite to the first opening to form a first heavily doped drain region located on one side of the first drain spacer and a second heavily doped drain region located on one side of the second drain spacer.

[0080] Figure 2G FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S107. Figure 2G As shown, Figure 2F In contrast, the semiconductor device 200 includes a first drain region 211a formed in the substrate 210 on a side of the first selection gate 280a opposite the first opening 272 and a second drain region 211b formed in the substrate 210 on a side of the second selection gate 280b opposite the first opening 272.

[0081] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure further includes: forming a silicide structure on the first select gate, the first drain region, the source region, the second select gate, and the second drain region.

[0082] In existing semiconductor device manufacturing methods, an opening between two adjacent memory cells and a source region below the opening are first formed, and then a select gate is formed on one side of each memory cell. This results in excess select gate material being deposited in the opening between the two adjacent memory cells when the select gate material is deposited to form the select gate. In the semiconductor device manufacturing method disclosed herein, since select gates are first formed on both sides of the gate stack, and then an opening through the gate stack and a source region below the opening are formed, excess select gate material is not deposited in the opening as described above with reference to the existing manufacturing method. This reduces the number of steps for removing excess select gate material, lowering production costs. Furthermore, by avoiding depositing conductive polysilicon in more trench areas and removing the deposited polysilicon using methods such as dry etching, the process risks increased during etching and the probability of defects on the wafer surface after etching are reduced, thereby improving chip yield.

[0083] In addition, in existing semiconductor device manufacturing methods, since the source region located below the opening between two adjacent memory cells is first formed, and then deposition is performed to form the remaining structure of the memory cell, the deposition process performed after the source region is formed will affect the performance of the source region (for example, causing the source region to further expand), thereby placing high requirements on the process of forming the source region (that is, maintaining the desired performance after undergoing heat treatment in subsequent multiple process steps (for example, deposition). In the semiconductor device manufacturing method described in the present disclosure, since various deposition processes are performed before forming the source region, the formed source region is prevented from being affected by the subsequent deposition process, thereby reducing the process requirements for the source region.

[0084] Figures 3A-3M is a schematic cross-sectional view illustrating steps of a method for manufacturing a semiconductor device 300 according to some embodiments of the present disclosure.

[0085] According to some embodiments, Figure 3A As shown, and reference Figure 2A Similar to the description, the semiconductor structure 300 includes, from bottom to top, a substrate 210 , a first oxide layer 220 , a storage layer 230 , a second oxide layer 240 , a control gate layer 250 , and a hard mask layer 260 .

[0086] According to some embodiments, Figure 3BAs shown, photoresist is coated on the upper surface of the hard mask layer 260 and photolithography is performed to form a photoresist pattern 290, and the photoresist pattern 290 is used as a mask to etch the hard mask layer 260, the control gate layer 250, the second oxide layer 240, the storage layer 230 and the first oxide layer 220 to form a gate stack including the first oxide layer 220, the storage layer 230, the second oxide layer 240, the control gate layer 250 and the hard mask layer 260.

[0087] According to some embodiments, Figure 3C As shown, remove Figure 3B The photoresist pattern shown forms a first control gate spacer 273a and a second control gate spacer 273b on both sides of the hard mask layer 260, the control gate layer 250, the second oxide layer 240, the storage layer 230 and the remaining portion of the first oxide layer 220, for example, by depositing a control gate oxide and etching the deposited control gate oxide to form the control gate spacers.

[0088] According to some embodiments, Figure 3D As shown, performing selection gate channel ion implantation in the first and second regions of the substrate 210 includes: performing selection gate channel photolithography to form a photoresist pattern to protect the region where ion implantation is not required; and performing selection gate channel ion implantation using the formed photoresist pattern as a mask.

[0089] According to some embodiments, Figure 3E As shown, a first gate oxide film 291 covering the semiconductor device 300 is formed on the first and second regions of the substrate 210 and the side surfaces and upper surface of the gate stack.

[0090] According to some embodiments, although Figure 3E Not shown, a first gate oxide film 291 covering the semiconductor device 300 is formed on the first and second regions of the substrate 210 , the side surfaces and upper surface of the gate stack, and the upper surface of the high-voltage tube region.

[0091] According to some embodiments, Figure 3F As shown, the first gate oxide film 291 located in the first region and the second region, as well as the upper surface of the gate stack, is removed to obtain the first gate spacer 271a and the second gate spacer 271b. It should be understood that, although not shown, the portion of the first gate oxide film 291 located on the high-voltage tube region of the substrate 210 is retained for subsequent formation of an oxide structure corresponding to the high-voltage tube region.

[0092] According to some embodiments, although Figure 3FNot shown, but a logic well implant may be performed in the substrate 210 , a logic IO gate oxide structure may be formed on the substrate 210 , and a logic core gate oxide structure may be formed on the substrate 210 .

[0093] According to some embodiments, the entire thickness of the first gate oxide film 291 located on the first and second regions is removed, thereby redepositing oxide on the first and second regions of the substrate to form a first selection gate oxide structure 222a and a second selection gate oxide structure 222b of a predetermined thickness.

[0094] According to some embodiments, first and second select gate oxide structures 222 a and 222 b may be formed on the first and second regions of the substrate, respectively, while forming a logic IO gate oxide structure or a logic core gate oxide structure.

[0095] According to some embodiments, Figure 3G As shown, a select gate silicide 280 is deposited on the first select gate oxide structure 222a and the second select gate oxide structure 222b and on the gate stack, wherein the select gate silicide 280 has a substantially uniform coverage. Figure 3G Together with the select gate silicide 280 in the CMOS process, logic gate polysilicon for subsequent formation of logic gates is deposited.

[0096] According to some embodiments, Figure 3H As shown, the semiconductor structure 300 is planarized and polysilicon etched to remove a portion of the select gate silicide 280 to form a first polysilicon structure 281 a located on the first region and a second polysilicon structure 281 b located on the second region.

[0097] According to some embodiments, Figure 3I As shown, the first polysilicon structure 281a and the second polysilicon structure 281b are subjected to a photolithography process; the photoresist pattern 293 formed by the photolithography process is used as a mask to etch the first polysilicon structure 281a and the second polysilicon structure 281b to form a first selection gate 280a and a second selection gate 280b respectively. According to some embodiments, Figure 3I The steps shown are taken together to form the logic gate.

[0098] According to some embodiments, Figure 3J As shown, the source region is photolithographically processed (eg, corresponding to Figure 3JThe photoresist patterns 294a and 294b are shown and etched accordingly to form a first opening 272, and a source ion implantation is performed in a portion of the substrate 210 below the first opening 272 to form a source region 212. According to some embodiments, the source ion implantation may be an N-type ion implantation. According to other embodiments, in addition to the N-type ion implantation, the source ion implantation may further include an appropriately increased P-type ion implantation to adjust the floating gate channel threshold voltage.

[0099] According to some embodiments, Figure 3K As shown, a lightly doped drain (LDD) implantation lithography is performed (eg, corresponding to Figure 3K A photoresist pattern 295 is formed in the substrate 210 on the side of the first select gate 280a opposite the first opening 272 and a lightly doped drain implant (e.g., arsenic) is performed in the substrate 210 on the side of the second select gate 280b opposite the first opening 272 to form a first lightly doped drain region 2111a on one side of the first select gate 280a and a second lightly doped drain region 2111b on one side of the second select gate 280b. According to some embodiments, after the lightly doped drain implant is performed, processes related to forming logic IO / core devices may be performed. According to some embodiments, after the lightly doped drain implant is performed, the photoresist pattern 295 may be removed.

[0100] According to some embodiments, Figure 3L As shown, first, a first drain spacer 274a is formed on a side of the first selection gate 280a opposite to the first opening 272, and a second drain spacer 274b is formed on a side of the second selection gate 280b opposite to the first opening 272, a first source spacer 275a is formed on a side of the first selection gate 280a facing the first opening 272, and a second source spacer 275b is formed on a side of the second selection gate 280b facing the first opening 272; then, a heavily doped drain implantation lithography is performed (for example, corresponding to Figure 3L A photoresist pattern 296 is formed, and a heavily doped drain implant is performed in the substrate 210 on a side of the first drain spacer 274a opposite the first opening 272 and in the substrate 210 on a side of the second drain spacer 274b opposite the first opening 272 to form a first heavily doped drain region 2112a on one side of the first drain spacer 274a and a second heavily doped drain region 2112b on one side of the second drain spacer 274b. According to some embodiments, a baseline logic process may be performed after performing the heavily doped drain implant.

[0101] According to some embodiments, a silicide structure is formed on the first select gate, the first drain region, the source region, the second select gate, and the second drain region. Figure 3M As shown, silicide structures 223a-223e are formed on the first selection gate 280a, the first heavily doped drain region 2112a, the source region 212, the second selection gate 280b, and the second heavily doped drain region 2112b. Figure 3M As shown, the oxide layer 222 on the first heavily doped drain region 2112a and the second heavily doped drain region 2112b is removed, and part of the oxide layer 220 on the source region 212 is removed, and silicide structures 223a and 223e are formed on the substrate 210 exposed by removing the oxide layer 222, and a silicide structure 223c is formed on the substrate 210 exposed by removing the oxide layer 220.

[0102] Figures 4A-4B is a schematic cross-sectional view illustrating steps of a method for manufacturing a semiconductor device 400 according to some embodiments of the present disclosure.

[0103] According to some embodiments, Figure 3H After forming the first polysilicon structure 281a located on the first region and the second polysilicon structure 281b located on the second region, as shown in FIG. Figure 4A As shown, a first hard mask spacer 282a and a second hard mask spacer 282b are respectively formed on both sides of the semiconductor device 200, wherein the first hard mask spacer 282a is located on the first polysilicon structure 281a, and the second hard mask spacer 282b is located on the second polysilicon structure 281b, for example, by depositing a hard mask material and etching the hard mask material to form the first hard mask spacer 282a and the second hard mask spacer 282b.

[0104] According to some embodiments, Figure 4B As shown, the first and second hard mask spacers 282a and 282b are used as masks to etch the first and second polysilicon structures 281a and 281b to form the first and second select gates 280a and 280b, respectively.

[0105] According to some embodiments, in forming Figure 4B After the semiconductor structure 400 is shown, the above reference Figures 3J-3M The process steps are described to form a flash memory semiconductor device.

[0106] Figure 5 Schematic cross-sectional views of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0107] According to some embodiments, Figure 3H After forming the first polysilicon structure 281a located on the first region and the second polysilicon structure 281b located on the second region, as shown in FIG. Figure 5 As shown, the deposited select gate polysilicon is self-alignedly etched to form a first select gate 280a and a second select gate 280b, respectively.

[0108] According to some embodiments, in forming Figure 5 After the semiconductor structure 500 is formed, the above-mentioned steps may be performed. Figures 3J-3M The process steps are described to form a flash memory semiconductor device.

[0109] Figure 6 Schematic cross-sectional views of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0110] According to some embodiments, Figure 3E After forming the first gate oxide film 291 covering the semiconductor device 300, as shown in FIG. Figure 6 As shown, a select gate channel ion implantation is performed in the first and second regions of the substrate 210, including: performing select gate channel lithography to form a photoresist pattern to protect the region where ion implantation is not required; performing select gate channel ion implantation using the formed photoresist pattern as a mask; then removing the portion of the first gate oxide film 291 located in the first and second regions and on the upper surface of the gate stack to form gate oxide structures 271a and 271b on both sides of the gate stack. According to some embodiments, the first gate oxide film 291 is etched (e.g., dry etching and wet etching) to retain the portion of the first gate oxide film 291 on the sidewalls of the gate stack. According to other embodiments, instead of partially removing the first gate oxide film 291 on the side of the gate stack, the first gate oxide film 291 on the side of the gate stack is first completely removed, and then a certain thickness of oxide is formed on the sidewalls of the floating gate by, for example, polysilicon oxidation.

[0111] According to some embodiments, in forming Figure 6 After the semiconductor structure 600 is shown, the above reference Figures 3F-3M The process steps are described to form a flash memory semiconductor device.

[0112] According to an embodiment of the present disclosure, a semiconductor device is further provided, which is manufactured by the method for manufacturing the semiconductor device according to the present disclosure.

[0113] Figure 7 is a schematic cross-sectional structural diagram of a semiconductor device 700 according to some embodiments of the present disclosure.

[0114] According to some embodiments, the semiconductor device 700 includes a substrate 210, a gate stack 270a and 270b formed above the substrate 210, a first selection gate 280a, a second selection gate 280b, a first drain region 211a, a second drain region 211b and a source region 212 located in the substrate 210, wherein the first gate stack 270a includes a portion of the first oxide layer 220, the first storage layer 230a, the second oxide layer 240a, the first control gate 250a and the first hard mask 260a, and the second gate stack 270b includes a portion of the first oxide layer 220, the second storage layer 230b, the second oxide layer 240b, the second control gate 250b and the second hard mask 260b.

[0115] According to some embodiments, the semiconductor device 700 also includes a first gate spacer 271a located between the first selection gate 280a and the first gate stack 270a, a second gate spacer 271b located between the second selection gate 280b and the second gate stack 270b, a first selection gate oxide structure 222a located below the first selection gate 280a, and a second selection gate oxide structure 222b located below the second selection gate 280b.

[0116] According to some embodiments, semiconductor device 700 includes two memory cells sharing a source region 212. According to some embodiments, semiconductor device 700 includes a first programming channel 213a, a second programming channel 213b, and a first erasure channel 214a corresponding to the memory cell on the left, and a second programming channel 213c, a second programming channel 213d, and a second erasure channel 214b corresponding to the memory cell on the right. According to some embodiments, a first programming channel 213a extends from the first drain region 211a to the edge of the first storage layer 230a facing the first select gate 280a, a second programming channel 213b extends from the first drain region 211a to the source region 212, a first erase channel 214a extends from the source region 212 to the first storage layer 230a, a third programming channel 213b extends from the second drain region 211b to the edge of the second storage layer 230b facing the second select gate 280b, a fourth programming channel 213b extends from the second drain region 211b to the source region 212, and a second erase channel 214b extends from the source region 212 to the second storage layer 230b. The processes for programming, erasing, and reading the memory cells on the left and right are similar. The following uses the memory cell on the left as an example to illustrate programming, erasing, and reading operations.

[0117] According to some embodiments, when a programming operation is performed, a positive voltage higher than the threshold voltage (e.g., 0.9 to 1.6 V) is applied to the first selection gate 280 a, and a positive voltage (e.g., 4.5 to 7 V) is applied to the source terminal (i.e., the source region 212 ) to provide a strong lateral electric field, and a negative current (e.g., 1 μA) is injected into the first drain region 211 a. At this time, due to the electron source injection effect, a portion of hot electrons are injected into the first storage layer 230 a through the first programming channel 213 a, while a portion of hot electrons migrate to the source terminal through the second programming channel 213 b.

[0118] According to some embodiments, when an erase operation is performed, a higher negative voltage (e.g., -5V to 10V) is applied to the first control gate 250a, and a higher positive voltage (e.g., 5V to 10V) is applied to the source region 212 to form a voltage difference between the first control gate 250a and the source region 212 and the first storage layer 230a, and the first drain region 211a is set to 0V or floating. At this time, due to the BTBT (Band to Band Tunneling) effect, holes are injected into the first storage layer 230a.

[0119] According to some embodiments, when performing a read operation, a positive voltage (e.g., 1.8V) is applied to the first selection gate 280a, a positive voltage (e.g., 0-1.8V) is applied to the first control gate 250a, a lower positive voltage (e.g., 0.6V) is applied to the first drain region 211a, and the source region 212 is set to 0V. At this time, the state of the memory cell is determined by the current value between the source and drain terminals.

[0120] Figure 8 is a circuit diagram of a memory cell array 800 according to some embodiments of the present disclosure. It should be understood that Figure 8 The numbers of memory cells, word lines, bit lines, source lines and erase lines are only illustrative, and any of the above numbers can be adjusted according to actual application requirements to achieve a larger or smaller scale memory cell array.

[0121] like Figure 8 As shown, the memory cell array 800 includes a plurality of memory cells (eg, Figure 8 Memory cell 810 shown). According to some embodiments, each memory cell includes a selection transistor and a storage transistor connected in series, e.g., Figure 8 The memory cell 810 includes a selection transistor 811 and a storage transistor 812 , wherein the selection transistor 811 can select a memory cell of a fixed address for operation, and the storage transistor 812 can store information.

[0122] According to some embodiments, each row of memory cells corresponds to a word line, e.g. Figure 8 In FIG, the memory cells in the upper row correspond to word line WLn-1, the memory cells in the lower row correspond to word line WLn, and each word line is connected to the gate of the selection transistor in the corresponding memory cell. According to some embodiments, each column of memory cells corresponds to a bit line, for example, Figure 8 , the memory cells in the left column correspond to the bit line BLn-1, the memory cells in the middle column correspond to the bit line BLn, and the memory cells in the right column correspond to the bit line BLn+1, and each bit line is connected to the drain of the selection transistor in the corresponding memory cell. According to some embodiments, the memory cells in two adjacent rows correspond to one source line, for example, Figure 8 In the memory cell array 800, the memory cells in the upper and lower rows correspond to source lines SL, and each source line is connected to the source of the storage transistor in the corresponding memory cell. According to some embodiments, the source lines of all memory cells in each sector of the memory are electrically connected together. According to some embodiments, in the memory cell array 800, each row of memory cells corresponds to a control line, for example, Figure 8 , the memory cells in the upper row correspond to the control line CGn-1, the memory cells in the lower row correspond to the control line CGn, and each control line is connected to the control gate of the storage transistor in the corresponding memory cell;

[0123] According to some embodiments, the drain of the select transistor in the memory cell corresponds to, for example Figure 7 In the semiconductor device 700 shown, the first drain region 211a, the gate of the select transistor in the memory cell corresponds to, for example, Figure 7 The first selection gate 280a in the semiconductor device 700 shown in FIG. Figure 7 In the semiconductor device 700 shown in FIG. 1 , the control gate of the storage transistor in the memory cell corresponds to the first storage layer 230a. Figure 7 The first control gate 230a in the semiconductor device 700 shown in FIG. 1 corresponds to the source of the storage transistor in the memory cell. Figure 7 The source region 212 in the semiconductor device 700 is shown.

[0124] Figures 9A-9B is a top plan view of a memory cell array according to some embodiments of the present disclosure. Figure 9A As shown, the memory cell array 900 includes a plurality of bit lines BLn-1, BLn, and BLn+1, a plurality of word lines WLn-1 and WLn, and a source line SL.

[0125] According to some embodiments, each column of memory cells corresponds to the same bit line, e.g. Figure 9A As shown, the two memory cells in the left column both correspond to the bit line BLn-1. It should be understood that, although not shown, the bit line structures of the memory cells in the same column are electrically connected.

[0126] According to some embodiments, each row of memory cells corresponds to the same word line, e.g. Figure 9A As shown, the three memory cells in the upper row all correspond to word line WLn-1. Figure 9A As shown, each word line extends through multiple memory cells in the same row.

[0127] According to some embodiments, each row of memory cells corresponds to a control line, e.g. Figure 9A In the example, the memory cells in the upper row correspond to the control line CGn-1, the memory cells in the lower row correspond to the control line CGn, and each control line is connected to the storage layer in the corresponding memory cell.

[0128] According to some embodiments, adjacent rows of memory cells correspond to the same source line, e.g. Figure 9A As shown, the six memory cells in the upper and lower rows all correspond to the source line SL. Figure 9A As shown, a source line SL extends through adjacent rows of memory cells in the substrate, wherein the source line connects source regions in a plurality of bit lines.

[0129] Such as 9B Figure 9B The memory cell array 900 is shown with Figure 9A The difference of the memory cell array 900 shown is that instead of the source line SL extending through the multiple bit lines in the substrate, a corresponding tungsten plug is set on each bit line (for example, the corresponding tungsten plug Wn-1 of the bit line BLn-1), and the respective tungsten plugs are connected by metal lines to connect the source regions in the multiple bit lines.

[0130] The present disclosure also provides a method for manufacturing a semiconductor device, comprising: forming a first oxide layer, a selection gate layer and a hard mask layer on a substrate in sequence; etching the hard mask layer and the selection gate layer to form a gate stack consisting of the remaining portion of the hard mask layer and the selection gate layer; forming a first storage structure on a first side surface and a first gate region of the gate stack, and forming a second storage structure on a second side surface and a second gate region of the gate stack, wherein the first gate region is located on one side of the first side surface of the gate stack and the second gate region is located on one side of the second side surface of the gate stack; forming a first control gate on the first storage structure, and forming a second control gate on the second storage structure; etching the gate stack to form a first opening through the hard mask layer and the selection gate layer; forming a drain region in a portion of the substrate located below the first opening; and forming a first source region in the substrate on a side of the first control gate opposite to the first opening, and forming a second source region in the substrate on a side of the second control gate opposite to the first opening.

[0131] Figure 10 is a schematic flowchart of a method 1000 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0132] In step S1001 , a first oxide layer, a select gate layer, and a hard mask layer are sequentially formed on a substrate.

[0133] According to some embodiments, the manufacturing method 1000 further includes: forming shallow trench isolation in the substrate before forming the first oxide layer on the substrate. According to some embodiments, the manufacturing method 1000 further includes: implanting memory cell wells in the substrate before forming the first oxide layer on the substrate.

[0134] According to some embodiments, a process of forming shallow trench isolation may include but is not limited to the following steps: forming a liner oxide, depositing silicon nitride, exposing an active area, etching shallow insulating trenches, filling shallow insulating trenches, planarizing shallow insulating trenches, and removing silicon nitride.

[0135] According to some embodiments, step S1001 includes: forming a first oxide layer on a substrate; forming a select gate layer on the first oxide layer; and forming a hard mask layer on the select gate layer.

[0136] Figure 11A FIG shows a cross-sectional view of an exemplary structure formed after step S1001. Figure 11A As shown, the semiconductor structure 200 includes, from bottom to top, a substrate 1110 , a first oxide layer 1120 , a selection gate layer 1130 , and a hard mask layer 1140 .

[0137] At step S1002 , the hard mask layer and the select gate layer are etched to form a gate stack consisting of the remaining portion of the hard mask layer and the select gate layer.

[0138] According to some embodiments, first, a photolithography process is performed on an upper surface of the hard mask layer to form a photoresist pattern; then, the hard mask layer and the select gate layer are etched using the formed photoresist pattern as a mask.

[0139] Figure 11B FIG shows a cross-sectional view of an exemplary structure formed after steps S1001 to S1002. Figure 11B As shown, the semiconductor structure 1100 includes, from bottom to top, a substrate 1110 , a first oxide layer 1120 , and a gate stack 1170 , wherein the gate stack 1170 includes, from bottom to top, a gate layer 1130 and the remaining portion of the hard mask layer 1140 .

[0140] At step S1003, a first storage structure is formed on the first side of the gate stack and the first gate region, and a second storage structure is formed on the second side of the gate stack and the second gate region, wherein the first gate region is located on one side of the first side of the gate stack and the second gate region is located on one side of the second side of the gate stack.

[0141] According to some embodiments, a first storage structure is formed on a first side surface and a first gate region of a gate stack, and a second storage structure is formed on a second side surface and a second gate region of the gate stack, including: forming selection gate spacers on both sides of the gate stack; depositing a first gate oxide film on the side surface and the upper surface of the gate stack, and the first region and the second region of the substrate, wherein the first region and the second region are located on both sides of the gate stack, the first region includes the first gate region, and the second region includes the second gate region; removing portions of the first gate oxide film on the upper surface of the gate stack, and the first region and the second region of the substrate; depositing a first storage oxide layer, a storage layer, and a second storage oxide layer in sequence on the side surface and the upper surface of the gate stack, and the first region and the second region of the substrate; and removing portions of the first storage oxide layer, the storage layer, and the second storage oxide layer on the non-gate region of the substrate and on the upper surface of the gate stack to form the first storage structure and the second storage structure, wherein the non-gate region includes a portion of the first region that is not included in the first gate region and a portion of the second region that is not included in the second gate region.

[0142] According to some embodiments, after etching the hard mask layer and the select gate layer, select gate spacers are formed on both sides of the remaining portions of the hard mask layer and the select gate layer, for example, a select gate oxide (e.g., silicon oxide) is deposited on both sides of the remaining portions of the hard mask layer and the select gate layer, and the deposited select gate oxide is etched to form the select gate spacers.

[0143] According to some embodiments, the first gate oxide film is etched (e.g., dry etching and wet etching) to retain a portion of the first gate oxide film on the sidewalls of the gate stack. According to some embodiments, after etching the first gate oxide film, a high-temperature rapid thermal process is performed to enhance the quality of the oxide on the sidewalls.

[0144] In the embodiments described in the present disclosure, a high-voltage tube oxide structure having a thickness different from that of the selection gate oxide structure is formed on the high-voltage tube region by depositing an oxide film and removing excess oxide during deposition, so as to facilitate the subsequent formation of corresponding high-voltage logic devices (for example, high-voltage devices powered by 11V) on the high-voltage tube region.

[0145] According to some embodiments, before depositing the first gate oxide film on the side and upper surfaces of the gate stack and the first and second regions of the substrate, storage channel ion (eg, boron or BF2) implantation is performed in the first and second regions of the substrate.

[0146] According to some embodiments, the material of the storage layer may be silicon nitride (SiN), or a high-K material such as HfO 2 , HfSiON, Ta 2 O 5 , Al 2 O 3 , TiO 2 , ZrO 2 , etc.

[0147] According to some embodiments, sequentially depositing a first storage oxide layer, a storage layer, and a second storage oxide layer on the side surfaces and upper surface of the gate stack and the first and second regions of the substrate includes depositing an ONO (oxygen-nitrogen-oxygen) material on the side surfaces and upper surface of the gate stack and the first and second regions of the substrate, and removing portions of the ONO (oxygen-nitrogen-oxygen) material on non-gate regions of the substrate and on the upper surface of the gate stack to form the first storage structure and the second storage structure.

[0148] According to some embodiments, performing storage channel ion implantation in the first and second regions of the substrate includes: performing storage channel photolithography to form a photoresist pattern to protect regions where ion implantation is not required; and performing storage channel ion implantation using the formed photoresist pattern as a mask.

[0149] According to some embodiments, when performing storage channel ion implantation in the first and second regions of the substrate, a predetermined angle is tilted to adjust a channel of the select gate.

[0150] Figure 11C FIG shows a cross-sectional view of an exemplary structure formed after steps S1001 to S1003. Figure 11C As shown, the semiconductor structure 1100 includes, from bottom to top, a substrate 1110, a first oxide layer 1120, and a gate stack 1170. The gate stack 1170 includes, from bottom to top, a control gate layer 1130 and the remaining portion of the hard mask layer 1140. The semiconductor structure 1100 also includes a first storage structure 1122a formed on a first side surface of the gate stack 1170 and a first gate region 1113a, and a second storage structure 1122b formed on a second side surface of the gate stack 1170 and a second gate region 1113b.

[0151] According to the embodiments described above, by retaining or additionally forming an oxide structure on the side of the gate stack before depositing the first gate oxide film on the first and second regions of the substrate, as well as on the side and upper surface of the gate stack, the gate oxide structure can be selected to have a different thickness from the gate spacer structure. For example, a thicker gate spacer structure is beneficial for data storage, and a thinner selection gate oxide structure is beneficial for improving the performance of the memory device (for example, providing a larger read current).

[0152] In step S1004 , a first control gate is formed on the first memory structure, and a second control gate is formed on the second memory structure.

[0153] According to some embodiments, forming a first control gate on a first storage structure and forming a second control gate on a second storage structure include: depositing a first storage oxide layer, a storage layer, and a second storage oxide layer on the side and upper surface of a gate stack, and a first region and a second region of a substrate, and then depositing a control gate polysilicon on the second storage oxide layer; and removing portions of the deposited control gate polysilicon while removing portions of the first storage oxide layer, the storage layer, and the second storage oxide layer on the non-gate region of the substrate and on the upper surface of the gate stack to form a first control gate and a second control gate.

[0154] According to some embodiments, the deposited first storage oxide layer, the storage layer, the second storage oxide layer, and the control gate polysilicon have the same coverage, so that the deposited first storage oxide layer, the storage layer, the second storage oxide layer, and the control gate polysilicon present a "convex" shape. For example, as described below with reference to Figure 12H Described in detail.

[0155] According to some embodiments, removing portions of the deposited control gate polysilicon to form a first control gate and a second control gate includes: planarizing the deposited control gate polysilicon; etching the planarized control gate polysilicon to form a first polysilicon structure and a second polysilicon structure located on a first region and a second region of the substrate, respectively; and etching the first polysilicon structure and the second polysilicon structure to form a first control gate and a second control gate, respectively.

[0156] According to some embodiments, the deposited control gate polysilicon is planarized to remove the control gate polysilicon deposited above the gate stack. According to some embodiments, during the planarization of the deposited control gate polysilicon, the first storage oxide layer, the storage layer, and the second storage oxide layer deposited above the gate stack in the previous step may also be removed.

[0157] According to some embodiments, etching the planarized control gate polysilicon to form a first polysilicon structure and a second polysilicon structure respectively located on a first region and a second region of the substrate includes etching shoulders of an L-shaped select gate polysilicon on both sides of the gate stack to form a first polysilicon structure and a second polysilicon structure respectively located on the first region and the second region of the substrate in a rectangular shape, so as to facilitate subsequent etching using a photoresist or a hard mask spacer as a mask to form the first control gate and the second control gate. For example, as described below with reference to Figure 12I Described in detail.

[0158] According to some embodiments, etching the first polysilicon structure and the second polysilicon structure to form the first control gate and the second control gate, respectively, includes: performing a first photolithography process on the first polysilicon structure and the second polysilicon structure; etching the first polysilicon structure and the second polysilicon structure using the photoresist pattern formed by the first photolithography process as a mask to form the first control gate and the second control gate, respectively; and removing the photoresist pattern formed by the first photolithography process. For example, as described below with reference to Figures 12I-12J Described in detail.

[0159] According to some embodiments, a first control gate is formed on the first memory structure, and a logic well implant is performed in the substrate before forming a second control gate on the second memory structure; a logic IO gate oxide structure is formed on the substrate; and a logic core gate oxide structure is formed on the substrate.

[0160] According to some embodiments, etching the first polysilicon structure and the second polysilicon structure to form the first control gate and the second control gate, respectively, includes: forming a first hard mask spacer and a second hard mask spacer on both sides of the gate stack, respectively, the first hard mask spacer being located on the first polysilicon structure, and the second hard mask spacer being located on the second polysilicon structure; and etching the first polysilicon structure and the second polysilicon structure using the first hard mask spacer and the second hard mask spacer as masks to form the first control gate and the second control gate, respectively. For example, as described below with reference to Figures 13A-13B Described in detail.

[0161] According to some embodiments, removing a portion of the deposited control gate polysilicon to form the first control gate and the second control gate includes self-aligned etching of the deposited control gate polysilicon to form the first control gate and the second control gate, respectively. For example, as described below with reference to Figure 14 Described in detail.

[0162] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure also includes: depositing logic gate polysilicon on the logic gate region of the substrate while depositing control gate polysilicon on the second storage oxide layer; and removing part of the deposited control gate polysilicon to form a first control gate and a second control gate while removing part of the logic gate polysilicon to form a logic gate.

[0163] According to some other embodiments, logic gate polysilicon is deposited on the logic gate region of the substrate while control gate polysilicon is deposited on the second storage oxide layer; and, in a processing step different from removing a portion of the deposited control gate polysilicon, a portion of the logic gate polysilicon is removed to form a logic gate.

[0164] Figure 11D FIG shows a cross-sectional view of an exemplary structure formed after steps S1001 to S1004. Figure 11D As shown, the semiconductor structure 1100 includes, in addition to the substrate 1110, the first oxide layer 1120 and the gate stack 1170, and the first storage structure 1122a formed on the first side surface of the gate stack 1170 and the first gate region 1113a, and the second storage structure 1122b formed on the second side surface of the gate stack 1170 and the second gate region 1113b, the first control gate 1180a formed on the first storage structure 1122a and the second control gate 1180b formed on the second storage structure 1122b.

[0165] At step S1005 , the gate stack is etched to form a first opening through the hard mask layer and the select gate layer.

[0166] According to some embodiments, etching the gate stack to form a first opening through the hard mask layer and the remaining portion of the select gate layer includes: performing drain photolithography to form a photoresist pattern; and etching the gate stack using the formed photoresist pattern as a mask to form the first opening.

[0167] Figure 11E FIG shows a cross-sectional view of an exemplary structure formed after steps S1001 to S1005. Figure 11E As shown, Figure 11D In comparison, the first opening 1172 passes through the remaining portions of the hard mask layer and the selection gate layer, wherein the remaining portions of the hard mask layer and the selection gate layer include gate structures belonging to the memory cells on both sides, respectively, i.e., the gate structure located on the left side composed of the first selection gate 1130a and the first hard mask 1140a and the gate structure located on the right side composed of the second selection gate 1130b and the second hard mask 1140b.

[0168] At step S1006 , a drain region is formed in a portion of the substrate below the first opening.

[0169] According to some embodiments, forming a drain region in a portion of the substrate located below the first opening includes: performing a lightly doped drain implantation in the substrate below the first opening to form a lightly doped drain region in the substrate located below the first opening; forming a first drain spacer and a second drain spacer on the side of the gate stack in the first opening; and performing a heavily doped source implantation in the substrate below the first opening between the first drain spacer and the second drain spacer to form a heavily doped drain region located between the first drain spacer and the second drain spacer.

[0170] Figure 11F FIG shows a cross-sectional view of an exemplary structure formed after steps S1001 to S1006. Figure 11F As shown, Figure 11E In contrast, the semiconductor device 1100 includes a drain region 1112 in the substrate 1110 below the first opening 1172 .

[0171] In step S107 , a first source region is formed in the substrate on a side of the first control gate opposite to the first opening, and a second source region is formed in the substrate on a side of the second control gate opposite to the first opening.

[0172] According to some embodiments, the source region is formed by source ion implantation (e.g., arsenic and phosphorus), thereby forming a graded junction in the substrate. That is, in the source region, the source ion doping concentration gradually decreases from the first oxide layer to the substrate, thereby improving the stress-bearing capability of the semiconductor device. In the embodiments described in the present disclosure, because the gate structures and oxide structures of the memory cells on both sides are formed first, and the source region implantation is performed later, the performance of the source region is avoided by the thermal deposition step of forming the gate and oxide structures.

[0173] Figure 11G FIG shows a cross-sectional view of an exemplary structure formed after steps S1001 to S1007. Figure 11G As shown, Figure 11F In contrast, the semiconductor device 1100 includes a first source region 1111a formed in the substrate 1110 on a side of the first control gate 1180a opposite the first opening 1172 and a second source region 1111b formed in the substrate 1110 on a side of the second control gate 1180b opposite the first opening 1172.

[0174] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure further includes: forming a silicide structure on the first control gate, the first source region, the drain region, the second control gate, and the second source region.

[0175] In existing semiconductor device manufacturing methods, an opening between two adjacent memory cells and a source region below the opening are first formed, and then a control gate is formed on one side of each memory cell. This results in excess control gate material being deposited in the opening between the two adjacent memory cells when the control gate material is deposited to form the control gate. In the semiconductor device manufacturing method disclosed herein, since the control gates on both sides of the gate stack are first formed, and then the source regions are formed below both sides of the gate stack, excess control gate material is not deposited in the opening as described above with reference to the existing manufacturing method. This reduces the number of steps for removing excess control gate material, thereby lowering production costs. Furthermore, by avoiding depositing conductive polysilicon in more trench areas and removing the deposited polysilicon using methods such as dry etching, the process risks during etching and the probability of defects on the wafer surface after etching are reduced, thereby improving chip yield.

[0176] In addition, in existing semiconductor device manufacturing methods, since the source region located below the opening between two adjacent memory cells is first formed, and then deposition is performed to form the remaining structure of the memory cell, the deposition process performed after the source region is formed will affect the performance of the source region (for example, causing the source region to further expand), thereby placing high requirements on the process of forming the source region (that is, maintaining the desired performance after undergoing heat treatment in subsequent multiple process steps (for example, deposition). In the semiconductor device manufacturing method described in the present disclosure, since each deposition process is performed before the source region is formed, the formed source region is prevented from being affected by the subsequent deposition process, thereby reducing the process requirements for the source region.

[0177] Figures 12A-12N is a schematic cross-sectional view illustrating steps of a method for manufacturing a semiconductor device 1200 according to some embodiments of the present disclosure.

[0178] According to some embodiments, Figure 12A As shown, and reference Figure 11A Similar to the description, the semiconductor structure 1200 includes, from bottom to top, a substrate 1110 , a first oxide layer 1120 , a selection gate layer 1130 , and a hard mask layer 1140 .

[0179] According to some embodiments, Figure 12B As shown, photoresist is coated on the upper surface of the hard mask layer 1140 and photolithography is performed to form a photoresist pattern 1150, and the hard mask layer 1140 and the selection gate layer 1130 are etched using the photoresist pattern 1150 as a mask to form a gate stack including the hard mask layer 1140 and the selection gate layer 1130.

[0180] According to some embodiments, Figure 12C As shown, remove Figure 12B The photoresist pattern is shown, and a first select gate spacer 1173a and a second select gate spacer 1173b are formed on both sides of the hard mask layer 1140 and the remaining portion of the select gate layer 1130, for example, a select gate oxide is deposited, and the deposited select gate oxide is etched to form the select gate spacers.

[0181] According to some embodiments, Figure 12D As shown, performing storage channel ion implantation in the first and second regions of the substrate 1110 includes: performing storage channel photolithography to form a photoresist pattern to protect regions where ion implantation is not required; and performing storage channel ion implantation using the formed photoresist pattern as a mask.

[0182] According to some embodiments, Figure 12EAs shown, a first gate oxide film 1191 is deposited on the side and upper surface of the gate stack, and the first and second regions of the substrate.

[0183] According to some embodiments, although Figure 12E Not shown, a first gate oxide film 1191 covering the semiconductor device 1200 is formed on the first and second regions of the substrate 1110 , the side surfaces and upper surface of the gate stack, and the upper surface of the high-voltage tube region.

[0184] According to some embodiments, Figure 12F As shown, the first gate oxide film 291 located in the first region and the second region, as well as the upper surface of the gate stack, is removed to obtain a first gate spacer 1171a and a second gate spacer 1171b. It should be understood that, although not shown, the portion of the first gate oxide film 1191 located on the high-voltage tube region of the substrate 1110 is retained for subsequent formation of an oxide structure corresponding to the high-voltage tube region.

[0185] According to some embodiments, Figure 12G As shown, a first storage oxide layer 1161 , a storage layer 1162 , and a second storage oxide layer 1163 are sequentially deposited on the side and upper surface of the gate stack, and the first and second regions of the substrate.

[0186] According to some embodiments, although Figure 12G Not shown, but a logic well implant may be performed in the substrate 1110 , a logic IO gate oxide structure may be formed on the substrate 1110 , and a logic core gate oxide structure may be formed on the substrate 1110 .

[0187] According to some embodiments, Figure 12H As shown, a control gate silicide 1180 is formed on the upper surface of the second storage oxide layer 1163. The control gate silicide 1180 has a substantially uniform coverage. According to some embodiments, Figure 12H Together with the control gate silicide 1180 in the CMOS process, logic gate polysilicon for subsequent formation of logic gates is deposited.

[0188] According to some embodiments, Figure 12I As shown, the semiconductor structure 1200 is planarized and polysilicon etched to remove a portion of the control gate silicide 1180 to form a first polysilicon structure 1181a located on the first region and a second polysilicon structure 1181b located on the second region, and to remove portions of the first storage oxide layer 1161, the storage layer 1162, and the second storage oxide layer 1163 located on the hard mask layer 1140.

[0189] According to some embodiments, Figure 12JAs shown, the first polysilicon structure 1181a and the second polysilicon structure 1181b are subjected to a photolithography process; the photoresist pattern 1193 formed by the photolithography process is used as a mask to etch the first polysilicon structure 1181a and the second polysilicon structure 1181b to form a first control gate 1180a and a second control gate 1180b, respectively. According to some embodiments, the first storage oxide layer 1161, the storage layer 1162, and the second storage oxide layer 1163 are etched using the photoresist pattern 1193 formed by the photolithography process as a mask to form a first storage structure 1122a and a second storage structure 1122b. According to some embodiments, Figure 12J The steps shown are taken together to form the logic gate.

[0190] According to some embodiments, Figure 12K As shown, a lightly doped drain (LDD) implantation lithography is performed (eg, corresponding to Figure 12K 1194b), and a lightly doped drain implant (e.g., arsenic) is performed in the substrate 1110 below the first opening 1172 to form a lightly doped drain region 1112. According to some embodiments, after the lightly doped drain implant is performed, related processes for forming logic IO / core devices can be performed. According to some embodiments, after the lightly doped drain implant is performed, the photoresist patterns 1194a and 1194b can be removed.

[0191] According to some embodiments, when performing P-type drain ion implantation in the substrate region, a predetermined angle is tilted to adjust a channel of the select gate.

[0192] According to some embodiments, Figure 12L As shown, the source region is photolithographically processed (eg, corresponding to Figure 12L 1172 ), and source ion implantation is performed in the substrate 1110 on the side of the first control gate 1180a opposite the first opening 1172 and in the substrate 1110 on the side of the second control gate 1180b opposite the first opening 1172 to form a first source region 1211a located on one side of the first control gate 1180a and a second source region 1211b located on one side of the second control gate 1180b. According to some embodiments, the source ion implantation may be an N-type ion implantation. According to other embodiments, in addition to the N-type ion implantation, the source ion implantation may also include an appropriately increased amount of P-type ion implantation to adjust the floating gate channel threshold voltage.

[0193] According to some embodiments, Figure 12MAs shown, first, a first source spacer 1174a is formed on a side of the first control gate 1180a opposite to the first opening 1172, and a second source spacer 1174b is formed on a side of the second control gate 1180b opposite to the first opening 1172, a first drain spacer 1175a is formed on a side of the first control gate 1180a facing the first opening 1172, and a second drain spacer 1175b is formed on a side of the second control gate 1180b facing the first opening 1172; then, a heavily doped drain implantation lithography process is performed (e.g., corresponding to FIG. 1 ). Figure 12M A heavily doped source implant is performed in the substrate 1110 between the first drain spacer 1175a and the second drain spacer 1175b to form a second heavily doped drain region 1113 between the first drain spacer 1175a and the second drain spacer 1175b. According to some embodiments, a baseline logic process may be performed after performing the heavily doped drain implant.

[0194] According to some embodiments, a silicide structure is formed on the first control gate, the first source region, the drain region, the second control gate, and the second source region. Figure 12N As shown, silicide structures 1123a-1123e are formed on the first control gate 1180a, the first source region 1211a, the heavily doped drain region 1113, the second control gate 1180b and the second source region 1211b.

[0195] Figures 13A-13B is a schematic cross-sectional view illustrating steps of a method for fabricating a semiconductor device 1300 according to some embodiments of the present disclosure.

[0196] According to some embodiments, Figure 12I After forming the first polysilicon structure 1181a located on the first region and the second polysilicon structure 1181b located on the second region, as shown in FIG. Figure 13A As shown, a first hard mask spacer 1182a and a second hard mask spacer 1182b are respectively formed on both sides of the semiconductor device 1300, wherein the first hard mask spacer 1182a is located on the first polysilicon structure 1181a, and the second hard mask spacer 1182b is located on the second polysilicon structure 1181b, for example, by depositing a hard mask material and etching the hard mask material to form the first hard mask spacer 1182a and the second hard mask spacer 1182b.

[0197] According to some embodiments, Figure 13BAs shown, the first and second hard mask spacers 1182a and 1182b are used as masks to etch the first and second polysilicon structures 1181a and 1181b to form a first control gate 1180a and a second control gate 1180b, respectively.

[0198] According to some embodiments, in forming Figure 13B After the semiconductor structure 1300 is shown, the above reference Figures 12K-12N The process steps are described to form a flash memory semiconductor device.

[0199] Figure 14 Schematic cross-sectional views of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0200] According to some embodiments, Figure 12I After forming the first polysilicon structure 1181a located on the first region and the second polysilicon structure 1181b located on the second region, as shown in FIG. Figure 14 As shown, the deposited select gate polysilicon is self-alignedly etched to form a first control gate 1180a and a second control gate 1180b, respectively.

[0201] According to some embodiments, in forming Figure 14 After the semiconductor structure 1400 is shown, the above reference Figures 12K-12N The process steps are described to form a flash memory semiconductor device.

[0202] Figure 15 Schematic cross-sectional views of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0203] According to some embodiments, Figure 12E After forming the first gate oxide film 1191 covering the semiconductor device 1100, as shown in FIG. Figure 15As shown, a storage channel ion implantation is performed in the first and second regions of the substrate 1110, including: performing storage channel photolithography to form a photoresist pattern to protect the region where the ion implantation is not required; performing storage channel ion implantation using the formed photoresist pattern as a mask; then removing the portion of the first gate oxide film 1191 located in the first and second regions and on the upper surface of the gate stack, and removing a portion of the first gate oxide film 291 on the side surfaces of the gate stack to form gate oxide structures 1171a and 1171b on both sides of the gate spacer. According to some embodiments, the first gate oxide film 1191 is etched (e.g., dry etching and wet etching) to retain a portion of the first gate oxide film 1191 on the sidewalls of the gate stack. According to other embodiments, instead of partially removing the first gate oxide film 1191 on the side surfaces of the gate stack, the first gate oxide film 1191 on the side surfaces of the gate stack is first completely removed, and then a certain thickness of oxide is formed on the floating gate sidewalls by, for example, polysilicon oxidation.

[0204] According to some embodiments, in forming Figure 15 After the semiconductor structure 1500 is shown, the above reference Figures 12G-12N The process steps are described to form a flash memory semiconductor device.

[0205] According to an embodiment of the present disclosure, a semiconductor device is further provided, which is manufactured by the method for manufacturing the semiconductor device according to the present disclosure.

[0206] Figure 16 is a schematic cross-sectional structural diagram of a semiconductor device 1600 according to some embodiments of the present disclosure.

[0207] According to some embodiments, the semiconductor device 1600 includes a substrate 1110, a first oxide layer 1120a and 1120b formed above the substrate 1110, a first selection gate 1130a, a first hard mask layer 1140a, a second selection gate 1130b, a second hard mask layer 1140b, a first storage structure 1122a, a second storage structure 1122b, a first control gate 1180a, a second control gate 1180b, a first drain region 1211a, a second drain region 1211b and a source region 1112 located in the substrate 1110.

[0208] According to some embodiments, the first storage structure 1122a includes a first storage oxide layer 1161a, a storage layer 1162a on the first storage oxide layer 1161a, and a second storage oxide layer 1163a on the storage layer 1162a. The second storage structure 1122b includes a first storage oxide layer 1161b, a storage layer 1162b on the first storage oxide layer 1161b, and a second storage oxide layer 1163b on the storage layer 1162b.

[0209] According to some embodiments, semiconductor device 1600 includes two memory cells sharing a drain region 1112. According to some embodiments, semiconductor device 1600 includes a first programming channel 1113a, a second programming channel 1113b, and a first erase channel 1114a corresponding to the memory cell on the left, and a second programming channel 1113c, a second programming channel 1113d, and a second erase channel 1114b corresponding to the memory cell on the right. According to some embodiments, a first programming channel 1113a extends from the drain region 1112 to an edge of the memory layer 1162a facing the first storage oxide layer 1161a, a second programming channel 1113b extends from the source region 1112 to the first source region 1211a, a first erase channel 1114a extends from the first source region 1211a to the memory layer 1162a, a third programming channel 1113c extends from the drain region 1112 to an edge of the memory layer 1162b facing the first storage oxide layer 1161b, a fourth programming channel 1113d extends from the drain region 1112 to the second source region 1211b, and a second erase channel 1114b extends from the second source region 1211b to the memory layer 1162b. The processes for programming, erasing, and reading the memory cells on the left and right are similar. The following uses the memory cell on the left as an example to describe programming, erasing, and reading operations.

[0210] According to some embodiments, when a programming operation is performed, a positive voltage higher than the threshold voltage (for example, 0.9 to 1.6 V) is applied to the first selection gate 1130a, and a positive voltage (for example, 4.5 to 7 V) is applied to the first source region 1211a to provide a strong lateral electric field, and a negative current (for example, 1 μA) is injected into the drain region 1112. At this time, due to the electron source injection effect, a portion of hot electrons are injected into the storage layer 1162a through the first programming channel 1113a, while a portion of hot electrons migrate to the first source region 1211a through the second programming channel 1113b.

[0211] According to some embodiments, when an erase operation is performed, a higher negative voltage (e.g., -5V to 10V) is applied to the first control gate 1180a, and a higher positive voltage (e.g., 5V to 10V) is applied to the first source region 1211a to form a voltage difference between the first control gate 1180a and the first source region 1211a, and the drain region 1112 is set to 0V or floating. At this time, due to the BTBT (Band to Band Tunneling) effect, holes are injected into the first storage layer 1162a.

[0212] According to some embodiments, when performing a read operation, a positive voltage (e.g., 1.8V) is applied to the first control gate 1180a, a positive voltage (e.g., 1.8V) is applied to the first selection gate 1130a, a lower positive voltage (e.g., 0.6V) is applied to the drain region 1112, and the first source region 1211a is set to 0V. At this time, the state of the memory cell is determined by the current value between the source and drain terminals.

[0213] Figure 17 is a circuit diagram of a memory cell array 1700 according to some embodiments of the present disclosure. It should be understood that Figure 17 The numbers of memory cells, word lines, bit lines, source lines and erase lines are only illustrative, and any of the above numbers can be adjusted according to actual application requirements to achieve a larger or smaller scale memory cell array.

[0214] like Figure 17 As shown, the memory cell array 1700 includes a plurality of memory cells (eg, Figure 17 Memory cell 1710 shown). According to some embodiments, each memory cell includes a selection transistor and a storage transistor connected in series, e.g., Figure 17 The memory cell 1710 includes a selection transistor 1711 and a storage transistor 1712 , wherein the selection transistor 1711 can select a memory cell of a fixed address for operation, and the storage transistor 1712 can store information.

[0215] According to some embodiments, each row of memory cells corresponds to a word line, e.g. Figure 17 In FIG, the memory cells in the upper row correspond to word line WLn-1, the memory cells in the lower row correspond to word line WLn, and each word line is connected to the gate of the selection transistor in the corresponding memory cell. According to some embodiments, each column of memory cells corresponds to a bit line, for example, Figure 17, the memory cells in the left column correspond to the bit line BLn-1, the memory cells in the middle column correspond to the bit line BLn, and the memory cells in the right column correspond to the bit line BLn+1, and each bit line is connected to the drain of the selection transistor in the corresponding memory cell. According to some embodiments, the memory cells in two adjacent rows correspond to one source line, for example, Figure 17 In the memory cell array 1700, the memory cells in the upper and lower rows correspond to source lines SL, and each source line is connected to the source of the storage transistor in the corresponding memory cell. According to some embodiments, the source lines of all memory cells in each sector in the memory are electrically connected together. According to some embodiments, in the memory cell array 1700, each row of memory cells corresponds to a control line, for example, Figure 17 , the memory cells in the upper row correspond to the control line CGn-1, the memory cells in the lower row correspond to the control line CGn, and each control line is connected to the control gate of the storage transistor in the corresponding memory cell;

[0216] According to some embodiments, the drain of the select transistor in the memory cell corresponds to, for example Figure 16 The drain region 1112 in the semiconductor device 1600 shown, the gate of the select transistor in the memory cell corresponds to, for example, Figure 16 The first selection gate 1130a in the semiconductor device 1600 shown in FIG. 1 corresponds to the storage layer of the storage transistor in the memory cell. Figure 16 In the semiconductor device 1600 shown in FIG. 1 , the control gate of the storage transistor in the memory cell corresponds to the storage layer 1162a. Figure 16 The first control gate 1180a in the semiconductor device 1600 shown in FIG. 1 corresponds to the source of the storage transistor in the memory cell. Figure 16 The first source region 1211 a in the semiconductor device 1600 is shown.

[0217] Figures 18A-18B is a top plan view of a memory cell array according to some embodiments of the present disclosure. Figure 18A As shown, the memory cell array 1800 includes a plurality of bit lines BLn-1, BLn, and BLn+1, a plurality of word lines WLn-1 and WLn, and a source line SL.

[0218] According to some embodiments, each column of memory cells corresponds to the same bit line, e.g. Figure 18A As shown, the two memory cells in the left column both correspond to the bit line BLn-1. It should be understood that, although not shown, the bit line structures of the memory cells in the same column are electrically connected.

[0219] According to some embodiments, each row of memory cells corresponds to the same word line, e.g. Figure 18AAs shown, the three memory cells in the upper row all correspond to word line WLn-1. Figure 18A As shown, each word line extends through multiple memory cells in the same row.

[0220] According to some embodiments, each row of memory cells corresponds to a control line, e.g. Figure 18A In the example, the memory cells in the upper row correspond to the control line CGn-1, the memory cells in the lower row correspond to the control line CGn, and each control line is connected to the storage layer in the corresponding memory cell.

[0221] According to some embodiments, adjacent rows of memory cells correspond to the same source line, e.g. Figure 18A As shown, the six memory cells in the upper and lower rows all correspond to the source line SL. Figure 18A As shown, a source line SL extends through adjacent rows of memory cells in the substrate, wherein the source line connects source regions in a plurality of bit lines.

[0222] Such as 18B Figure 18B The memory cell array 1800 is shown with Figure 18A The difference of the memory cell array 1800 shown is that instead of the source line SL extending through multiple bit lines in the substrate, a corresponding tungsten plug is set on each bit line (for example, the corresponding tungsten plug Wn-1 of the bit line BLn-1), and the individual tungsten plugs are connected by metal lines to connect the source regions in the multiple bit lines.

[0223] Some exemplary aspects of the disclosure are described below.

[0224] Aspect 1. A method for manufacturing a semiconductor device, comprising:

[0225] forming a first oxide layer, a storage layer, a second oxide layer, a control gate layer and a hard mask layer in sequence on the substrate;

[0226] Etching the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer to form a gate stack consisting of the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and a remaining portion of the first oxide layer;

[0227] forming a first gate spacer and a second gate spacer on opposite sides of the gate stack, respectively, and forming a first select gate oxide structure and a second select gate oxide structure on a first region and a second region of the substrate, respectively, wherein the first region and the second region are located on opposite sides of the gate stack;

[0228] forming a first select gate on a side of the first gate spacer opposite the gate stack, and forming a second select gate on a side of the second gate spacer opposite the gate stack;

[0229] etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the second oxide layer, and the memory layer;

[0230] forming a source region in a portion of the substrate below the first opening; and

[0231] A first drain region is formed in the substrate on a side of the first select gate opposite to the first opening, and a second drain region is formed in the substrate on a side of the second select gate opposite to the first opening.

[0232] Aspect 2. The method according to aspect 1, wherein forming a first gate spacer and a second gate spacer on both sides of the gate stack, respectively, and forming a first select gate oxide structure and a second select gate oxide structure on the first region and the second region of the substrate, respectively, comprises:

[0233] forming control gate spacers on both sides of the gate stack;

[0234] Depositing a first gate oxide film on the side surfaces and upper surface of the gate stack, and the first and second regions of the substrate;

[0235] removing portions of the first gate oxide film on the upper surface of the gate stack and the first and second regions of the substrate to form the first and second gate spacers; and

[0236] A first select gate oxide structure and a second select gate oxide structure are formed on the first region and the second region of the substrate, respectively.

[0237] Aspect 3. The method according to aspect 2, wherein depositing a first gate oxide film on the side surface and upper surface of the gate stack and the first and second regions of the substrate comprises:

[0238] A first gate oxide film is deposited on the side surfaces and the upper surface of the gate stack, and the first region, the second region, and the high-voltage tube region of the substrate.

[0239] Aspect 4. The method according to aspect 1, further comprising forming a first select gate on a side of the first gate spacer opposite to the gate stack, and before forming a second select gate on a side of the second gate spacer opposite to the gate stack:

[0240] implanting a logic well in the substrate;

[0241] forming a logic IO gate oxide structure on the substrate; and

[0242] A logic core gate oxide structure is formed on the substrate.

[0243] Aspect 5. The method according to aspect 4, wherein forming a first select gate oxide structure and a second select gate oxide structure on the first region and the second region of the substrate, respectively, comprises:

[0244] The first select gate oxide structure and the second select gate oxide structure are formed on the first region and the second region of the substrate respectively while the logic IO gate oxide structure or the logic core gate oxide structure is formed.

[0245] Aspect 6. The method according to aspect 2, further comprising, before depositing a first gate oxide film on the side surface and the upper surface of the gate stack, and the first and second regions of the substrate:

[0246] Select gate channel ion implantation is performed in the first and second regions of the substrate.

[0247] Aspect 7. The method according to any one of aspects 1 to 6, wherein forming a first select gate on a side of the first gate spacer opposite to the gate stack, and forming a second select gate on a side of the second gate spacer opposite to the gate stack comprises:

[0248] depositing select gate polysilicon over the first select gate oxide structure and the second select gate oxide structure and over the gate stack; and

[0249] Portions of the deposited select gate polysilicon are removed to form the first select gate and the second select gate.

[0250] Aspect 8. The method according to aspect 7, wherein removing a portion of the deposited select gate polysilicon to form the first select gate and the second select gate comprises:

[0251] performing a planarization process on the deposited select gate polysilicon;

[0252] Etching the planarized select gate polysilicon to form a first polysilicon structure and a second polysilicon structure respectively located on the first region and the second region of the substrate; and

[0253] The first and second polysilicon structures are etched to form the first and second select gates, respectively.

[0254] Aspect 9. The method according to aspect 8, wherein etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, comprises:

[0255] performing a first photolithography process on the first polysilicon structure and the second polysilicon structure;

[0256] using the photoresist pattern formed by the first photolithography process as a mask, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively; and

[0257] The photoresist pattern formed by the first photolithography process is removed.

[0258] Aspect 10. The method according to aspect 8, wherein etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, comprises:

[0259] forming a first hard mask spacer and a second hard mask spacer on both sides of the gate stack, respectively, wherein the first hard mask spacer is located on the first polysilicon structure and the second hard mask spacer is located on the second polysilicon structure; and

[0260] The first and second polysilicon structures are etched using the first and second hard mask spacers as masks to form the first and second select gates, respectively.

[0261] Aspect 11. The method according to any one of aspects 1 to 6, wherein forming a first drain region in the substrate on a side of the first select gate opposite to the first opening, and forming a second drain region in the substrate on a side of the second select gate opposite to the first opening comprises:

[0262] performing a lightly doped drain implantation in the substrate on a side of the first select gate opposite to the first opening and in the substrate on a side of the second select gate opposite to the first opening to form a first lightly doped drain region located on one side of the first select gate and a second lightly doped drain region located on one side of the second select gate;

[0263] forming a first drain spacer on a side of the first select gate opposite the first opening, and forming a second drain spacer on a side of the second select gate opposite the first opening;

[0264] forming a first source spacer on a side of the first select gate facing the first opening, and forming a second source spacer on a side of the second select gate facing the first opening; and

[0265] A heavily doped drain implant is performed in the substrate on a side of the first drain spacer opposite the first opening and in the substrate on a side of the second drain spacer opposite the first opening to form a first heavily doped drain region located on one side of the first drain spacer and a second heavily doped drain region located on one side of the second drain spacer.

[0266] Aspect 12. The method according to any one of aspects 1 to 6, further comprising:

[0267] A silicide structure is formed on the first select gate, the first drain region, the source region, the second select gate, and the second drain region.

[0268] Aspect 13. A method for manufacturing a semiconductor device, comprising:

[0269] forming a first oxide layer, a select gate layer, and a hard mask layer in sequence on the substrate;

[0270] etching the hard mask layer and the select gate layer to form a gate stack consisting of the hard mask layer and a remaining portion of the select gate layer;

[0271] forming a first storage structure on the first side of the gate stack and the first gate region, and forming a second storage structure on the second side of the gate stack and the second gate region, wherein the first gate region is located on one side of the first side of the gate stack and the second gate region is located on one side of the second side of the gate stack;

[0272] forming a first control gate on the first storage structure, and forming a second control gate on the second storage structure;

[0273] etching the gate stack to form a first opening through the hard mask layer and the select gate layer;

[0274] forming a drain region in a portion of the substrate below the first opening; and

[0275] A first source region is formed in the substrate on a side of the first control gate opposite to the first opening, and a second source region is formed in the substrate on a side of the second control gate opposite to the first opening.

[0276] Aspect 14. The method according to aspect 13, wherein forming a first storage structure on the first side surface of the gate stack and the first gate region, and forming a second storage structure on the second side surface of the gate stack and the second gate region comprises:

[0277] forming select gate spacers on both sides of the gate stack;

[0278] Depositing a first gate oxide film on the side and upper surface of the gate stack, and on a first region and a second region of the substrate, wherein the first region and the second region are located on both sides of the gate stack, the first region includes the first gate region, and the second region includes the second gate region;

[0279] removing portions of the first gate oxide film on the upper surface of the gate stack and the first and second regions of the substrate;

[0280] Depositing a first storage oxide layer, a storage layer, and a second storage oxide layer in sequence on the side surfaces and the upper surface of the gate stack, and the first and second regions of the substrate; and

[0281] Portions of the first storage oxide layer, the storage layer, and the second storage oxide layer on the non-gate region of the substrate and on the upper surface of the gate stack are removed to form the first storage structure and the second storage structure, wherein the non-gate region includes a portion of the first region that is not included in the first gate region and a portion of the second region that is not included in the second gate region.

[0282] Aspect 15. The method according to aspect 14, wherein forming a first control gate on the first memory structure and forming a second control gate on the second memory structure comprises:

[0283] After sequentially depositing a first storage oxide layer, a storage layer, and a second storage oxide layer on the side surfaces and upper surface of the gate stack and the first and second regions of the substrate, depositing control gate polysilicon on the second storage oxide layer; and

[0284] While removing portions of the first storage oxide layer, storage layer, and second storage oxide layer on the non-gate region of the substrate and on the upper surface of the gate stack, portions of the deposited control gate polysilicon are removed to form the first control gate and the second control gate.

[0285] Aspect 16. The method according to aspect 15, wherein removing a portion of the deposited control gate polysilicon to form the first control gate and the second control gate comprises:

[0286] performing a planarization process on the deposited control gate polysilicon;

[0287] Etching the planarized control gate polysilicon to form a first polysilicon structure and a second polysilicon structure respectively located on the first region and the second region of the substrate; and

[0288] The first and second polysilicon structures are etched to form the first and second control gates, respectively.

[0289] Aspect 17. The method according to aspect 16, wherein etching the first polysilicon structure and the second polysilicon structure to form the first control gate and the second control gate, respectively, comprises:

[0290] performing a first photolithography process on the first polysilicon structure and the second polysilicon structure;

[0291] Using the photoresist pattern formed by the first photolithography process as a mask, etching the first polysilicon structure and the second polysilicon structure to form the first control gate and the second control gate, respectively; and

[0292] The photoresist pattern formed by the first photolithography process is removed.

[0293] Aspect 18. The method according to aspect 13, further comprising forming a first control gate on the first memory structure, and before forming a second control gate on the second memory structure:

[0294] implanting a logic well in the substrate;

[0295] forming a logic IO gate oxide structure on the substrate; and

[0296] A logic core gate oxide structure is formed on the substrate.

[0297] Aspect 19. The method according to aspect 14, further comprising, before depositing a first gate oxide film on the side surface and the upper surface of the gate stack, and the first and second regions of the substrate:

[0298] Storage channel ion implantation is performed in the first and second regions of the substrate.

[0299] Aspect 20. The method according to any one of aspects 13 to 19, wherein forming a drain region in a portion of the substrate below the first opening comprises:

[0300] performing a lightly doped drain implantation in the substrate below the first opening to form a lightly doped drain region in the substrate below the first opening;

[0301] forming first and second drain spacers on sides of the gate stack in the first opening; and

[0302] A heavily doped source implant is performed in the substrate below the first opening between the first drain spacer and the second drain spacer to form a heavily doped drain region between the first drain spacer and the second drain spacer.

[0303] Aspect 21. The method according to any one of aspects 13-19, further comprising:

[0304] A silicide structure is formed on the first control gate, the first source region, the drain region, the second control gate, and the second source region.

[0305] Aspect 22. A semiconductor device manufactured by the method according to any one of aspects 1 to 21.

[0306] Although the present disclosure has been illustrated and described in detail in the drawings and in the foregoing description, such illustration and description are to be considered illustrative and exemplary and not restrictive; the disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments will be understood and effected by those skilled in the art in practicing the claimed subject matter by studying the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps that are not listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first oxide layer, a storage layer, a second oxide layer, a control gate layer and a hard mask layer in sequence on the substrate; Etching the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer to form a gate stack consisting of the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and a remaining portion of the first oxide layer; A first gate spacer and a second gate spacer are formed on both sides of the gate stack, respectively, and a first select gate oxide structure and a second select gate oxide structure are formed on the first region and the second region of the substrate, respectively, wherein: forming control gate spacers on both sides of the gate stack; Depositing a first gate oxide film on the side surfaces and upper surface of the gate stack, and the first and second regions of the substrate; performing select gate channel ion implantation in the first and second regions of the substrate; removing portions of the first gate oxide film on the upper surface of the gate stack and the first and second regions of the substrate to form the first and second gate spacers; and Depositing an oxide of a predetermined thickness on a first region and a second region of the substrate to form a first select gate oxide structure and a second select gate oxide structure, respectively, wherein the first region and the second region are located on both sides of the gate stack, wherein the thickness of the first gate spacer is greater than the thickness of the first select gate oxide structure, and the thickness of the second gate spacer is greater than the thickness of the second select gate oxide structure; forming a first select gate on a side of the first gate spacer opposite the gate stack, and forming a second select gate on a side of the second gate spacer opposite the gate stack; etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the second oxide layer, and the memory layer; forming a source region in a portion of the substrate below the first opening; and A first drain region is formed in the substrate on a side of the first select gate opposite to the first opening, and a second drain region is formed in the substrate on a side of the second select gate opposite to the first opening.

2. The method according to claim 1, wherein Depositing a first gate oxide film on the side surface and the upper surface of the gate stack and the first region and the second region of the substrate comprises: A first gate oxide film is deposited on the side surfaces and the upper surface of the gate stack, and the first region, the second region, and the high-voltage tube region of the substrate.

3. The method of claim 1 , further comprising forming a first select gate on a side of the first gate spacer opposite the gate stack, and before forming a second select gate on a side of the second gate spacer opposite the gate stack: implanting a logic well in the substrate; forming a logic IO gate oxide structure on the substrate; and A logic core gate oxide structure is formed on the substrate.

4. The method according to claim 3, wherein: Forming a first select gate oxide structure and a second select gate oxide structure on the first region and the second region of the substrate, respectively, comprises: The first select gate oxide structure and the second select gate oxide structure are formed on the first region and the second region of the substrate respectively while the logic IO gate oxide structure or the logic core gate oxide structure is formed.

5. The method according to any one of claims 1 to 4, wherein forming a first select gate on a side of the first gate spacer opposite to the gate stack, and forming a second select gate on a side of the second gate spacer opposite to the gate stack comprises: depositing select gate polysilicon on the first select gate oxide structure and the second select gate oxide structure and on the gate stack; as well as Portions of the deposited select gate polysilicon are removed to form the first select gate and the second select gate.

6. The method according to claim 5, wherein: The removing a portion of the deposited select gate polysilicon to form the first select gate and the second select gate includes: performing a planarization process on the deposited select gate polysilicon; Etching the planarized select gate polysilicon to form a first polysilicon structure and a second polysilicon structure respectively located on the first region and the second region of the substrate; and The first and second polysilicon structures are etched to form the first and second select gates, respectively.

7. The method according to claim 6, wherein: The etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, comprises: performing a first photolithography process on the first polysilicon structure and the second polysilicon structure; using the photoresist pattern formed by the first photolithography process as a mask, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively; and The photoresist pattern formed by the first photolithography process is removed.

8. The method according to claim 6, wherein: The etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, comprises: forming a first hard mask spacer and a second hard mask spacer on both sides of the gate stack, respectively, wherein the first hard mask spacer is located on the first polysilicon structure and the second hard mask spacer is located on the second polysilicon structure; and The first and second polysilicon structures are etched using the first and second hard mask spacers as masks to form the first and second select gates, respectively.

9. The method according to any one of claims 1 to 4, wherein: The forming of a first drain region in the substrate on a side of the first selection gate opposite to the first opening, and the forming of a second drain region in the substrate on a side of the second selection gate opposite to the first opening comprises: performing a lightly doped drain implantation in the substrate on a side of the first select gate opposite to the first opening and in the substrate on a side of the second select gate opposite to the first opening to form a first lightly doped drain region on one side of the first select gate and a second lightly doped drain region on one side of the second select gate; forming a first drain spacer on a side of the first select gate opposite the first opening, and forming a second drain spacer on a side of the second select gate opposite the first opening; forming a first source spacer on a side of the first select gate facing the first opening, and forming a second source spacer on a side of the second select gate facing the first opening; and A heavily doped drain implant is performed in the substrate on a side of the first drain spacer opposite the first opening and in the substrate on a side of the second drain spacer opposite the first opening to form a first heavily doped drain region located on one side of the first drain spacer and a second heavily doped drain region located on one side of the second drain spacer.

10. The method according to any one of claims 1 to 4, further comprising: A silicide structure is formed on the first select gate, the first drain region, the source region, the second select gate, and the second drain region.

11. A method for manufacturing a semiconductor device, comprising: forming a first oxide layer, a select gate layer, and a hard mask layer in sequence on the substrate; etching the hard mask layer and the select gate layer to form a gate stack consisting of the hard mask layer and a remaining portion of the select gate layer; A first storage structure is formed on a first side surface of the gate stack and a first gate region, and a second storage structure is formed on a second side surface of the gate stack and the second gate region, wherein: forming select gate spacers on both sides of the gate stack; Depositing a first gate oxide film on the side and upper surface of the gate stack, and on a first region and a second region of the substrate, wherein the first region and the second region are located on both sides of the gate stack, the first region includes the first gate region, and the second region includes the second gate region, wherein the first gate region is located on one side of the first side of the gate stack, and the second gate region is located on one side of the second side of the gate stack; performing storage channel ion implantation in the first and second regions of the substrate; removing portions of the first gate oxide film on the upper surface of the gate stack and the first and second regions of the substrate; Depositing a first storage oxide layer, a storage layer, and a second storage oxide layer in sequence on the side surfaces and the upper surface of the gate stack, and the first and second regions of the substrate; and Removing portions of the first storage oxide layer, the storage layer, and the second storage oxide layer on the non-gate region of the substrate and on the upper surface of the gate stack to form the first storage structure and the second storage structure, wherein the non-gate region includes a portion of the first region that is not included in the first gate region and a portion of the second region that is not included in the second gate region; forming a first control gate on the first storage structure, and forming a second control gate on the second storage structure; etching the gate stack to form a first opening through the hard mask layer and the select gate layer; forming a drain region in a portion of the substrate below the first opening; and A first source region is formed in the substrate on a side of the first control gate opposite to the first opening, and a second source region is formed in the substrate on a side of the second control gate opposite to the first opening.

12. The method according to claim 11, wherein The forming of a first control gate on the first storage structure and a second control gate on the second storage structure comprises: After sequentially depositing a first storage oxide layer, a storage layer, and a second storage oxide layer on the side surfaces and upper surface of the gate stack and the first and second regions of the substrate, depositing control gate polysilicon on the second storage oxide layer; and While removing portions of the first storage oxide layer, storage layer, and second storage oxide layer on the non-gate region of the substrate and on the upper surface of the gate stack, portions of the deposited control gate polysilicon are removed to form the first control gate and the second control gate.

13. The method of claim 12, wherein removing the portion of the deposited control gate polysilicon to form the first control gate and the second control gate comprises: performing a planarization process on the deposited control gate polysilicon; Etching the planarized control gate polysilicon to form a first polysilicon structure and a second polysilicon structure respectively located on the first region and the second region of the substrate; as well as The first and second polysilicon structures are etched to form the first and second control gates, respectively.

14. The method according to claim 13, wherein The etching the first polysilicon structure and the second polysilicon structure to form the first control gate and the second control gate respectively comprises: performing a first photolithography process on the first polysilicon structure and the second polysilicon structure; Using the photoresist pattern formed by the first photolithography process as a mask, etching the first polysilicon structure and the second polysilicon structure to form the first control gate and the second control gate, respectively; and The photoresist pattern formed by the first photolithography process is removed.

15. The method according to claim 11, further comprising forming a first control gate on the first memory structure, and before forming a second control gate on the second memory structure: implanting a logic well in the substrate; forming a logic IO gate oxide structure on the substrate; and A logic core gate oxide structure is formed on the substrate.

16. The method according to any one of claims 11 to 15, wherein: The forming of a drain region in a portion of the substrate below the first opening comprises: performing a lightly doped drain implantation in the substrate below the first opening to form a lightly doped drain region in the substrate below the first opening; forming first and second drain spacers on sides of the gate stack in the first opening; and A heavily doped source implant is performed in the substrate below the first opening between the first drain spacer and the second drain spacer to form a heavily doped drain region between the first drain spacer and the second drain spacer.

17. The method according to any one of claims 11 to 15, further comprising: A silicide structure is formed on the first control gate, the first source region, the drain region, the second control gate, and the second source region.

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