A low-noise ultra-wideband active balun

Abstract

The present invention discloses a low-noise, ultra-wideband active balun, constructed using a current-reuse amplifier and a differential pair active balun in series. The current-reuse structure improves voltage gain, reduces power consumption and noise figure, and achieves 50Ω input impedance matching within an ultra-wideband through a broadband matching structure. The differential pair active balun introduces a phase compensation inductor to reduce phase error, uses a parallel compensation structure as a load to increase bandwidth, and uses diode biasing to reduce the impact of temperature on the operating state, thereby reducing phase and amplitude errors.

Description

Technical Field

[0001] The invention belongs to the technical field of microelectronics, and in particular relates to an active balun for C-Kμ bands in the technical field of radio frequency integrated circuits. Background Art

[0002] With the rapid development of wireless communication technology, the performance requirements for wireless communication systems are becoming increasingly demanding. Differential systems, with their advantages of high linearity and strong anti-interference capabilities, have significantly improved the performance of RF transceiver systems. However, the feed port of traditional antennas is single-ended, necessitating a balun converter between the RF front-end and the antenna to convert between single-ended and differential signals.

[0003] Balun amplifiers, which convert single-ended to differential signals, are widely used in circuits such as phase shifters, low-noise amplifiers, and mixers. Baluns come in two types: passive and active. Passive baluns not only occupy a large area and suffer from high insertion loss, but are also difficult to integrate. Common active balun structures include unipolar inverters, cross-cascade inverters, CG / CS structures, and differential pair structures. These structures not only occupy a small area and facilitate on-chip integration, but also provide a certain amount of gain while converting signals, making it easier to achieve wideband and impedance matching.

[0004] Existing active baluns are usually unipolar structures with small gain, resulting in a large noise figure, and cannot take into account both phase, gain balance and high bandwidth. When the frequency is low, the parasitic effect is weak. Traditional active baluns can convert single-ended signals into a pair of differential signals. However, when the operating frequency approaches millimeter waves, the parasitic effect is enhanced. The output end of the existing balun structure has large amplitude and phase errors, which in turn affects the performance of subsequent circuits. Therefore, its operating bandwidth is narrow. Summary of the Invention

[0005] To address the above-mentioned problems in the prior art, the present invention provides a low-noise ultra-wideband active balun. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] A low-noise ultra-wideband active balun provided by the present invention includes: a first-stage amplifier and a second-stage amplifier, wherein the first-stage amplifier and the second-stage amplifier are connected in series using a DC blocking capacitor C4 and an inter-stage matching inductor L5, the first-stage amplifier includes a matching network circuit, the first-stage amplifier has a current multiplexing structure, and is composed of two common-source amplifier circuits cascaded together and sharing a bias current, the second-stage amplifier has a differential pair balun structure, the first-stage amplifier is used to perform bandwidth matching and gain compensation on an input signal within an input frequency variation range, and to compensate for the attenuation of the gain of the second-stage amplifier, and the second-stage amplifier is used to convert a single-ended signal output by the first-stage amplifier into a differential signal.

[0007] Optionally, the first-stage amplifier includes a matching network, which includes a negative feedback resistor R1, a gate series inductor L1, a source degeneracy inductor L2, and a MOS transistor M1. One end of the gate series inductor L1 is connected to the DC blocking capacitor C1, and the other end is connected to the gate of the MOS transistor M1. The negative feedback resistor R1 is connected between the gate and drain of the MOS transistor M1. The matching network matches the input impedance to near a fixed ohm value.

[0008] Optionally, the two common-source amplifier circuits are a first-stage common-source amplifier circuit formed by a MOS tube M1, a negative feedback resistor R1, a source degenerate inductor L2, and a load resistor R3. One end of the gate series inductor L1 is connected to the DC blocking capacitor C1, and the other end is connected to the gate of the first MOS tube M1. The negative feedback resistor R1 is connected between the gate and drain of the MOS tube M1. The drain of the MOS tube M1 is connected to the resistor R3 as the load of the common-source amplifier, and self-bias is achieved through the negative feedback resistor R1.

[0009] MOS transistor M2, negative feedback resistor R2, negative feedback resistor R4, and resistor R5 form a second-stage common-source amplifier circuit. The source of MOS transistor M2 is connected to the source of MOS transistor M1, sharing a DC path. The drain of MOS transistor M2 is connected to resistor R5. The other end of resistor R5 is connected to power supply VDD, serving as the load of the second-stage common-source amplifier circuit. Resistors R2 and R4 are cascaded between the power supply and ground to provide a DC bias for MOS transistor M2. The other end of capacitor C3 is connected to the source of MOS M2, and one end is grounded. The two-stage common-source amplifier circuits are coupled via the cascade connection of capacitor C2 and inductor L3.

[0010] Optionally, both the MOS transistor M1 and the MOS transistor M2 operate in a saturation region, the power supply VDD is 2.5 V, the resistor R3 and the resistor R5 have a value range of [50, 100] ohms, the negative feedback resistor R2 and the negative feedback resistor R4 have resistance values in the kilohm range, the MOS transistor M2 is biased at approximately 1.5 V, and the inductor L3 is approximately 1 nH.

[0011] Optionally, self-biasing is achieved through a negative feedback resistor R1 , which is connected between the gate and drain of the MOS tube M1 , and the drain voltage of M1 is used as the bias voltage of the gate. The value range of the negative feedback resistor R1 is [300, 500]Ω.

[0012] Optionally, the MOS transistors M3 and M5, and the MOS transistors M4 and M6 in the differential pair structure are cascaded to form a cascode structure as the main structure. One path in the main structure includes a phase compensation inductor L4, while the other does not. The drain of the MOS transistor M3 and the source of the MOS transistor M5 are connected via the phase compensation inductor L4, the drain of the MOS transistor M4 and the source of the MOS transistor M6 are directly connected, the load resistor R8 and the load inductor L6 are connected in series between the drain of the MOS transistor M5 and the power supply VDD, and the load resistor R9 and the load inductor L7 are connected in series between the drain of the MOS transistor M6 and the power supply VDD, thereby increasing the bandwidth through the parallel compensation structure. The MOS transistor M3 inverts the gate input signal and transmits it from the drain to the gate of the MOSM4 via the capacitor C5 to achieve differential input. The gate and drain of the MOSM7 and the MOS transistor M8 are connected to form a diode structure, respectively connected to the resistor R 10 , resistor R 11 The voltage is divided and then passed through the resistor R 12 , resistor R 13 Provide bias voltage for MOS transistors M3 and MOS transistors M4; resistors R6 and R7 provide bias voltage for MOS transistors M5 and MOS transistors M6; grounding capacitor C6 is connected to the gate of MOS transistor M5, and grounding capacitor C7 is connected to the gate of MOS transistor M6 as decoupling capacitors to reduce the phase and amplitude errors of the output signal.

[0013] Optionally, the bias voltage Vbias of the MOS transistor M5 and the MOS transistor M6 is approximately 1.5V; the MOS transistor M3 and the MOS transistor M4 have the same size, and the MOS transistor M5 and the MOS transistor M6 have the same size, and both operate in the saturation region.

[0014] Optionally, the diode voltage divider structure refers to a diode structure in which the gate and drain of the MOS tube M7 and the MOS tube M8 are connected to each other and connected to the resistor R 10 、R 11 The voltage is divided and then passed through the resistor R 12 、R 13 Provides bias voltage for M3 and M4, R 10 and R 11 The value of R is the same 12 and R 13 The values are the same, the resistance values are all in the kilo-ohm range, and the sizes of M7 and M8 are the same.

[0015] Optionally, the phase compensation inductor means that the drain of the MOS transistor M3 and the source of the MOS transistor M5 are connected via a phase compensation inductor L4 to reduce the phase error. The phase compensation inductor L4 has a value of approximately 300 pH.

[0016] Optionally, the parallel compensation structure means that the load resistor R8 and the load inductor L6 are connected in series between the drain of M5 and the power supply VDD, the load resistor R9 and the load inductor L7 are connected in series between the drain of M6 and the power supply VDD, the load resistors R8 and R9 are around [50, 100]Ω, and the load inductors L6 and L7 are around 300pH.

[0017] Beneficial effects:

[0018] 1. A low-noise, ultra-wideband active balun, provided by embodiments of the present invention, employs a two-stage amplifier circuit structure. The first stage achieves broadband matching, reduces noise figure, increases gain, and compensates for gain loss in subsequent stages. The second stage converts single-ended signals to differential signals. As a result, the active balun's noise performance, gain characteristics, and differential output balance are relatively independent, facilitating design optimization.

[0019] 2. The first-stage amplifier circuit of the present invention adopts a current multiplexing structure, allowing the two-stage amplifier circuits to use one bias static current at the same time. Compared with the common-source amplifier structure, the gain is improved without changing the current. Compared with the traditional cascode structure, its voltage swing is larger and the linearity is higher.

[0020] 3. The present invention uses series inductor L4 for phase compensation. Due to the influence of the parasitic capacitance of the MOS transistor, the output signal of M3 is not in an ideal differential relationship with the input signal, resulting in a significant phase deviation between the signal input to M4 and the ideal signal. In addition, the parasitic capacitance of M4 also causes a significant phase shift in its output signal. Series inductor L4 can resonate with the parasitic capacitance of M3, reducing the offset of M3's output signal. It can also adjust the phase of M3's output signal to achieve an ideal differential signal with the output signal of M4.

[0021] 4. M7 and R of the present invention 10 、R 12 and M8, R 11 、R 13 The diode voltage divider structure provides bias for MOS transistors M3 and M4, replacing the traditional resistor voltage divider bias. The resulting bias is insensitive to temperature changes, making the static operating point of MOS transistors M3 and M4 more stable, and reducing the influence of temperature and power supply voltage on the output signal phase.

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 1 is a schematic structural diagram of a low-noise ultra-wideband active balun provided by an embodiment of the present invention;

[0024] Figure 2This is the input return loss simulation diagram of the active balun in simulation experiment 1;

[0025] Figure 3 1 is a simulation curve diagram of the phase-frequency characteristics of the active balun amplifier in simulation experiment 2 of the present invention;

[0026] Figure 4 This is a simulation curve diagram of the gain characteristics of the active balun amplifier in simulation experiment 3 of the present invention;

[0027] Figure 5 This is a phase error simulation curve diagram of simulation experiment 4 of the present invention;

[0028] Figure 6 This is a gain error simulation curve diagram of simulation experiment 5 of the present invention;

[0029] Figure 7 This is a noise coefficient simulation curve diagram of simulation experiment 6 of the present invention. DETAILED DESCRIPTION

[0030] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0031] like Figure 1 As shown, a low-noise ultra-wideband active balun provided by the present invention includes: a first-stage amplifier and a second-stage amplifier, the first-stage amplifier and the second-stage amplifier are connected in series using a DC blocking capacitor C4 and an inter-stage matching inductor L5, the first-stage amplifier includes a matching network circuit, the first-stage amplifier is a current multiplexing structure, and is composed of two common-source amplifier circuits cascaded with a common bias current, the second-stage amplifier is a differential pair balun structure, the first-stage amplifier is used to perform bandwidth matching and gain compensation on the input signal within the input frequency variation range, and compensate for the attenuation of the gain of the second-stage amplifier, and the second-stage amplifier is used to convert the single-ended signal output by the first-stage amplifier into a differential signal.

[0032] It's worth noting that the key specifications of an active balun include operating bandwidth, gain, output signal phase and amplitude imbalance, input-output matching, and noise figure. A low-noise active balun can reduce the system's noise figure. Ultra-wideband communication systems require an active balun with a wide operating bandwidth and good phase and amplitude balance in the output signal. This invention can be used in the front end of wireless communication receivers to convert between single-ended and differential signals, providing a certain voltage gain and a low noise figure.

[0033] The first-stage amplifier includes a matching network, which includes a negative feedback resistor R1, a gate series inductor L1, a source degenerate inductor L2, and a MOS transistor M1. One end of the gate series inductor L1 is connected to a DC blocking capacitor C1, and the other end is connected to the gate of MOS transistor M1. The negative feedback resistor R1 is connected between the gate and drain of MOS transistor M1. The matching network matches the input impedance to a near-fixed ohmic value. The two common-source amplifier circuits comprise the first-stage common-source amplifier circuit, which is composed of the MOS transistor M1, the negative feedback resistor R1, the source degenerate inductor L2, and the load resistor R3. One end of the gate series inductor L1 is connected to the DC blocking capacitor C1, and the other end is connected to the gate of the first MOS transistor M1. The negative feedback resistor R1 is connected between the gate and drain of MOS transistor M1. The drain of MOS transistor M1 is connected to resistor R3, which serves as the load of the common-source amplifier. Self-biasing is achieved through the negative feedback resistor R1.

[0034] MOS transistor M2, negative feedback resistor R2, negative feedback resistor R4, and resistor R5 form a second-stage common-source amplifier circuit. The source of MOS transistor M2 is connected to the source of MOS transistor M1, sharing a DC path. The drain of MOS transistor M2 is connected to resistor R5. The other end of resistor R5 is connected to power supply VDD, serving as the load of the second-stage common-source amplifier circuit. Resistors R2 and R4 are cascaded between the power supply and ground to provide a DC bias for MOS transistor M2. The other end of capacitor C3 is connected to the source of MOS M2, and one end is grounded. The two-stage common-source amplifier circuits are coupled via the cascade connection of capacitor C2 and inductor L3.

[0035] In the second-stage differential pair amplifier structure, MOS transistors M3 and M5, MOS transistors M4 and MOS transistors M6 are cascaded to form a cascode structure as the main structure. One path in the main structure includes a phase compensation inductor L4, while the other does not. The drain of MOS transistor M3 and the source of MOS transistor M5 are connected via the phase compensation inductor L4, the drain of MOS transistor M4 and the source of MOS transistor M6 are directly connected, the load resistor R8 and the load inductor L6 are connected in series between the drain of MOS transistor M5 and the power supply VDD, and the load resistor R9 and the load inductor L7 are connected in series between the drain of MOS transistor M6 and the power supply VDD. The bandwidth is increased by the parallel compensation structure. After the gate input signal is inverted, MOS transistor M3 transmits it from the drain to the gate of MOS transistor M4 through capacitor C5 to achieve differential input. The gate and drain of MOS transistor M7 and MOS transistor M8 are connected to form a diode structure, respectively connected to resistor R 10 , resistor R 11 The voltage is divided and then passed through the resistor R 12 , resistor R 13Provide bias voltage for MOS transistors M3 and MOS transistors M4; resistors R6 and R7 provide bias voltage for MOS transistors M5 and MOS transistors M6; grounding capacitor C6 is connected to the gate of MOS transistor M5, and grounding capacitor C7 is connected to the gate of MOS transistor M6 as decoupling capacitors to reduce the phase and amplitude errors of the output signal.

[0036] MOS transistors M1 and M2 both operate in the saturation region. The power supply VDD is 2.5V. The resistors R3 and R5 have values in the range of [50, 100] ohms. The negative feedback resistors R2 and R4 have resistances in the kilohm range, biasing MOS transistor M2 at approximately 1.5V. The inductor L3 is approximately 1nH. Self-biasing is achieved through negative feedback resistor R1, which is connected between the gate and drain of MOS transistor M1, with the drain voltage of M1 serving as the gate bias voltage. The negative feedback resistor R1 has a value in the range of [300, 500] Ω. The bias voltage Vbias of MOS transistors M5 and M6 is approximately 1.5V. MOS transistors M3 and M4 have the same dimensions, and MOS transistors M5 and M6 have the same dimensions, and both operate in the saturation region. The diode voltage divider structure involves connecting the gates and drains of MOS transistors M7 and M8 to form a diode structure, respectively connected to resistors R 10 、R 11 The voltage is divided and then passed through the resistor R 12 、R 13 Provides bias voltage for M3 and M4, R 10 and R 11 The value of R is the same 12 and R 13 The values of M7 and M8 are the same, with resistance values in the kilo-ohm range. The phase compensation inductor, L4, connects the drain of MOS transistor M3 and the source of MOS transistor M5 to reduce phase error. The phase compensation inductor L4 is set at approximately 300 pH. The parallel compensation structure connects load resistor R8 and load inductor L6 in series between the drain of M5 and power supply VDD, while load resistor R9 and load inductor L7 are connected in series between the drain of M6 and power supply VDD. The values of load resistors R8 and R9 are approximately [50, 100] Ω, and the values of load inductors L6 and L7 are approximately 300 pH.

[0037] The present invention discloses a low-noise, ultra-wideband active balun, constructed by serially connecting a current-reuse amplifier and a differential pair active balun. This low-noise, ultra-wideband active balun utilizes the current-reuse structure to increase voltage gain, reduce power consumption and noise figure, and achieve 50Ω input impedance matching within an ultra-wideband through a broadband matching structure. The differential pair active balun introduces a phase compensation inductor to reduce phase error, employs a parallel compensation structure as a load to increase bandwidth, and utilizes diode biasing to mitigate the effects of temperature and power supply voltage on operating conditions, thereby reducing phase and amplitude errors.

[0038] The following combination Figure 1 The structure of the present invention is introduced as follows:

[0039] refer to Figure 1 The broadband matching network consists of a negative feedback resistor R1, a gate series inductor L1, and a source degeneration inductor L2. One end of the inductor L1 is connected to the DC blocking capacitor C1, and the other end is connected to the gate of M1. The negative feedback resistor R1 is connected between the gate and drain of the MOS transistor M1, providing negative feedback and self-bias for the MOS transistor. By adjusting the values of these three components, the parasitic capacitance of the MOS transistor is offset and the input impedance is matched to approximately 50Ω. The negative feedback resistor R1 has a value range of [300, 500]Ω, the gate series inductor L1 is adjusted to approximately 1nH, and the source degeneration inductor L2 is adjusted to approximately 100pH.

[0040] The first-stage amplifier adopts a current-multiplexing structure, consisting of two cascaded common-source amplifiers. MOS transistor M1, negative feedback resistor R1, source degeneration inductor L2, and load resistor R3 together form the first-stage common-source amplifier circuit. MOS transistor M1's drain is connected to resistor R3, serving as the load for the common-source amplifier. MOS transistor M2, along with resistors R2, R4, and R5, forms the second-stage common-source amplifier circuit. MOS transistor M2's source is connected to the source of M1, sharing a DC path. Its drain is connected to resistor R5, whose other end is connected to power supply VDD, serving as the load for the second-stage common-source amplifier circuit. Resistors R2 and R4, connected in cascade between the power supply and ground, provide a DC bias for M2. Capacitor C3, with its other end connected to the source of M2, provides an AC ground. The two common-source amplifier circuits are coupled via a cascade connection of capacitor C2 and inductor L3. Inductor L3 provides inter-stage matching to enhance the gain of the high-frequency amplifier. Both MOS tubes work in the saturation region. R3 and R5 provide gain and have values of [50, 100]Ω. The power supply VDD is 2.5V. The negative feedback resistor bias resistors R2 and R4 are in the kilohm range. M2 is biased at around 1.5V, and the inductor L3 is adjusted to be determined around 1nH.

[0041] The second-stage amplifier is an active balun with a differential pair structure. MOS tubes M3 and M5, M4 and M6 respectively form a cascode structure as the main structure. The drain of M3 and the source of M5 are connected through the phase compensation inductor L4, and the drain of M4 and the source of M6 are directly connected. The load resistor R8 and the load inductor L6 are connected in series between the drain of M5 and the power supply VDD, and the load resistor R9 and the load inductor L7 are connected in series between the drain of M6 and the power supply VDD. The bandwidth is increased by the parallel compensation structure. After M3 inverts the gate input signal, it is transmitted from the drain to the gate of M4 through the capacitor C5 to achieve differential input. The gate and drain of M7 and M8 are connected to form a diode structure, respectively connected to R 10 、R 11 The voltage is divided and then passed through R 12 、R 13 Provide bias voltage for M3 and M4. Resistors R6 and R7 provide bias voltage for M5 and M6. Ground capacitors C6 and C7 are connected to the gates of M5 and M6 respectively as decoupling capacitors. To reduce the phase and amplitude errors of the output signal, the sizes of MOS tubes M3 and M4, and the sizes of M5 and M6 should be the same and all work in the saturation region. By adjusting the sizes of M7 and M8 and R 10 、R 11 The bias voltage of M3 and M4 is determined to be around 900mV. The bias voltage Vbias of M5 and M6 is around 1.5V, the phase compensation inductor L4 is around 300pH, and the resistors R6, R7, and R 12 、R 13 Both are in the kilo-ohm range, the load resistors R8 and R9 are around [50, 100]Ω, and the load inductors L6 and L7 are adjusted around 300pH.

[0042] The DC blocking capacitor C4 and the inductor L5 are connected in series between the first-stage amplifier and the second-stage active balun. L5 is used for inter-stage matching to improve gain, and its value is around 800pH.

[0043] The working principle of the present invention is as follows:

[0044] The current multiplexing amplifier receives the input RF in Input signals in the C to Kμ frequency band provide bias voltage for M1 via negative feedback resistor R1, while resistors R2 and R4 provide bias voltage for M2 via cascade voltage divider. Load resistors R3 and R5 and the interstage matching inductor L3 are adjusted to achieve the appropriate gain for the current multiplexing amplifier. The signal is amplified by the two common-source amplifiers where M1 and M2 reside before being transmitted to the next stage.

[0045] The MOS transistor in the amplifier circuit converts the input voltage into current. If the channel length modulation effect and body effect of the MOS transistor are ignored, the input impedance of the amplifier circuit is:

[0046]

[0047] where Z in represents the input impedance of the current multiplexing amplifier, C gs1 is the gate-source parasitic capacitance of M1, g m1 is the transconductance of M1, which is expressed as μ, C ox 、 I D They represent the carrier mobility, gate oxide capacitance, aspect ratio and leakage current of M1, R m =R1(1-A V1o )(A V1o is the open-loop gain of the first-stage common-source amplifier) is the Miller equivalent impedance of R1, It is the characteristic frequency of MOS tube M1.

[0048] By adjusting L2 and R m , so that the real part of the input impedance is 50Ω, and adjust L1 and L2 to make the imaginary part of the input impedance 0, achieving ultra-wideband input matching.

[0049] Assuming good matching, the gain of the current multiplexing amplifier is:

[0050] A V1 =A V11 ·A V12 =g m1,eff R3·g m2 R5

[0051] Among them A V11 =g m1,eff R3 is the gain of the first stage common source amplifier, g m1,eff is the equivalent transconductance of the first-stage common-source amplifier under ideal matching, A V12 =g m2 R5 is the gain of the second-stage common-source amplifier, g m2 is the transconductance of M2.

[0052] The MOS tube M3 of the differential pair active balun receives the output signal from the current multiplexing amplifier, inverts the signal through M3 and transmits it to M4, and then amplifies it by the common gate tubes M5 and M6 to produce differential output. The gate and drain of M7 and M8 are connected to form a diode structure, respectively connected to R 10 、R 11The voltage divider provides bias voltage for M3 and M4. Resistors R6 and R7 provide bias voltage for M5 and M6. Adjusting the phase compensation inductor L4 reduces the output signal phase error, and adjusting the MOS transistor size reduces the output signal amplitude error. Decoupling capacitors C6 and C7 are added to the gates of M5 and M6 to filter out coupling from the source signal and improve gain. Good gain flatness is achieved by adjusting the load resistors R8 and R9 and the load inductors L6 and L7.

[0053] An inductor is connected in series at the load to form a parallel compensation structure. The load impedance is:

[0054]

[0055] Where L=L6=L7, R=R8=R9, and C is the parasitic capacitance at the output end.

[0056] Adding an inductor in series with the load resistor adds a component whose impedance increases with frequency, which helps to compensate for the decrease in capacitor impedance and can keep the total impedance unchanged over a wider frequency range, thus having good broadband characteristics.

[0057] In order to ensure that the amplitude error of the two output signals is as small as possible, the amplitude of the gate input signal of the common source tubes M3 and M4 should be the same and the size should be consistent, so the gain of the two common source tubes is

[0058] Ignoring the body effect, the differential pair active balun gain is:

[0059]

[0060] where g m3,4 is the transconductance of M3 and M4, g m5,6 is the transconductance of M5 and M6, r o3,4 ( λ is the channel length modulation coefficient, I D is the leakage current) is the output impedance of M3 and M4, r o5,6 is the output impedance of M5 and M6.

[0061] The total gain of the active balun is:

[0062]

[0063] The overall gain of the active balun is:

[0064]

[0065] Where NF1 is the noise of the current multiplexing amplifier and NF2 is the noise of the differential pair active balun.

[0066] It can be seen from the above formula that the greater the gain of the current multiplexing amplifier, the smaller the impact of the differential pair active balun on the overall noise, and the smaller the overall noise. Therefore, the high gain of the current multiplexing amplifier can reduce the noise of the active balun.

[0067] The effects of the present invention are further described below in conjunction with simulation experiments.

[0068] 1. Simulation experiment conditions:

[0069] The hardware platform of the simulation experiment of the present invention is: the processor is Intel(R) Core(TM) i5-10400CPU, the main frequency is 2.9GHz, and the memory is 8GB.

[0070] The software platforms for the simulation experiment of the present invention are: Linux operating system and IC617.

[0071] The present invention uses the Spectre RF simulation tool to simulate the circuit of the present invention, adopts the SMIC40nm CMOS process, gives the power supply voltage VDD as 2.5V, the operating temperature as 27°C, the bias voltage and Vbias as 2.5V, the operating frequency as 13GHz, and the scanning range of the input RF signal frequency as [6G, 20G]Hz.

[0072] 2. Simulation content and results analysis:

[0073] In the Cadence software experimental platform, six simulation experiments were conducted on the characteristics of the second-order active balun amplifier of the present invention, including input return loss, phase-frequency characteristics, gain characteristics, phase error and gain error, and noise figure.

[0074] Figure 2 This is the input return loss simulation of the active balun in simulation experiment 1. Figure 2 The horizontal axis in represents the frequency scanning range, in GHz. Figure 2 The vertical axis in represents the input return loss S11 value, in dB. By changing the operating frequency of the circuit and measuring the S11 value, the input return loss simulation curve of the active balun circuit of the present invention is obtained. Figure 2 It can be seen from the figure that in the operating frequency range of 6-20 GHz, the input return loss of the active balun can be as low as -17 dB, and is less than -10 dB between 8.5 GHz and 19.9 GHz, meeting the input matching requirements.

[0075] Figure 3 This is a simulation curve diagram of the phase-frequency characteristics of the active balun amplifier in simulation experiment 2 of the present invention. Figure 3 The horizontal axis in represents the frequency scanning range, in GHz. Figure 3The vertical axis in represents the output signal phase value, in degrees. By changing the operating frequency of the circuit and measuring the phase size of the two output ports, the phase-frequency characteristic simulation curve of the broadband active balun circuit of the present invention is obtained. Figure 3 The curve S21 marked with a solid line represents the phase simulation curve of Vout1, and the curve S31 marked with a dotted line represents the phase simulation curve of Vout2. Figure 3 It can be seen that this design can maintain the phase difference of the output signal at about 180 degrees in the operating frequency range of 6-20GHz, which basically meets the design requirements.

[0076] Figure 4 This is a simulation curve diagram of the gain characteristics of the active balun amplifier in simulation experiment 3 of the present invention. Figure 4 The horizontal axis in represents the frequency scanning range, in GHz. Figure 4 The vertical axis in represents the output signal gain amplitude value, in dB. By changing the operating frequency of the circuit and measuring the gain of the two output ports, the gain characteristic simulation curve of the second-order active balun circuit of the present invention is obtained. Figure 4 The curve S21 indicated by a solid line represents the gain characteristic curve of Vout1, and the curve S31 indicated by a dotted line represents the gain characteristic curve of Vout2. Figure 3 It can be seen that in the operating frequency range of 6-20 GHz, the amplitudes of the output signals Vout1 and Vout2 are very close, and the S21 and S31 gain curves are maintained above 7.8 dB within the operating frequency range, meeting the design requirements.

[0077] Figure 5 This is a phase error simulation curve diagram of simulation experiment 4 of the present invention. Figure 5 The horizontal axis in represents the frequency scanning range, in GHz. Figure 5 The vertical axis represents the output signal phase error value, in degrees. In the simulation process, by setting the operating frequency of the active balun circuit to 6-20GHz, the phase of the two differential output ports is subtracted to obtain the phase error. Figure 5 It can be seen that the phase difference between the two output ports is close to 180 degrees, and the maximum deviation is 0.015 degrees.

[0078] Figure 6 This is a gain error simulation curve diagram of simulation experiment 5 of the present invention. Figure 6 The horizontal axis in represents the frequency scanning range, in GHz. Figure 6 The vertical axis represents the output signal gain error value in dB. In the simulation process, by setting the operating frequency of the active balun circuit to 6-20GHz, the gain error is obtained by subtracting the gains of the two differential output ports. Figure 6It can be seen that the gain error between the two output ports is less than 0.082dB.

[0079] Figure 5 and Figure 6 The simulation results show that the two output signals obtained by the active balun amplifier of the present invention have good differential performance, and the basic function of converting the signal from single-ended to dual-ended is well realized.

[0080] Figure 7 This is a noise coefficient simulation curve diagram of simulation experiment 6 of the present invention. Figure 7 The horizontal axis in represents the frequency scanning range, in GHz. Figure 7 The vertical axis represents the noise figure value in dB. By simulating the noise figure of the active balun input, the noise figure simulation curve is obtained. Figure 7 It can be seen that in the 6-20 GHz operating frequency band, the noise figure is less than 4.4 dB, and the noise performance is greatly improved.

[0081] The above simulation experiments demonstrate that the present invention has a 14 GHz bandwidth, good impedance matching at the input port, a gain of over 7.8 dB, and good noise performance. The present invention effectively implements the active balun circuit function of converting single-ended to differential, with extremely low phase and gain errors between the two output signals and good differential performance.

[0082] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A low-noise ultra-wideband active balun, characterized in that: include: The first stage amplifier and the second stage amplifier are connected by a DC blocking capacitor. and interstage matching inductors The first-stage amplifier comprises a matching network circuit, a current multiplexing structure, and a cascade connection of two common-source amplifier circuits sharing a bias current. The second-stage amplifier comprises a differential pair balun structure. The first-stage amplifier is configured to perform bandwidth matching and gain compensation on an input signal within a frequency range, and to compensate for attenuation of the gain of the second-stage amplifier. The second-stage amplifier is configured to convert a single-ended output signal of the first-stage amplifier into a differential signal. The two common source amplifier circuits are MOS tubes With negative feedback resistor , source degenerate inductance , load resistance Together they form the first-stage common-source amplifier circuit, with the gate connected in series with an inductor. One end is connected to the DC blocking capacitor , the other end is connected to the first MOS tube The gate, negative feedback resistor Connect to MOS tube Between the gate and drain, MOS tube Drain connected to resistor As the load of the common source amplifier, through the negative feedback resistor Achieve self-biasing; MOS tube With negative feedback resistor , negative feedback resistor ,resistance The second-stage common-source amplifier circuit is formed, and the MOS tube Source and MOS tube Drain through resistor connected and share a DC path; MOS tube Drain and resistor Connected, resistor The other end is connected to the power supply , as the load of the second-stage common-source amplifier circuit, the resistor ,resistance Cascade voltage divider is used between power supply and ground to form MOS tube Provides DC bias, capacitor The other end is connected to MOS The source, one end is grounded; the two-stage common source amplifier circuit is connected by a capacitor and inductance Cascade to couple the connection; MOS tube in differential pair structure and MOS tubes , MOS tube and MOS tubes They are cascaded to form a cascode structure as the main structure, one of which contains a phase compensation inductor. , the other one does not include; among them, MOS tube The drain and MOS tube The source of the phase compensation inductor Connected, MOS tube Drain and MOS tube The source is directly connected to the load resistor and load inductance In MOS tube Drain and Power Supply In series, the load resistor and load inductance In MOS tube Drain and Power Supply The MOS tube is connected in series to increase the bandwidth through the parallel compensation structure. After the gate input signal is inverted, it is sent from the drain through the capacitor Transfer to MOS Gate, to achieve differential input; MOS and MOS tubes The gate and drain of the diode are connected to form a diode structure, respectively ,resistance Voltage division, then through the resistor ,resistance For MOS tube and MOS tubes Provide bias voltage; resistor ,resistance For MOS tube , MOS tube Provide bias voltage; ground capacitor With MOS tube Gate and ground capacitance With MOS tube The gate is connected as a decoupling capacitor to reduce the phase and amplitude errors of the output signal.

2. The low-noise ultra-wideband active balun according to claim 1, characterized in that: The first stage amplifier includes a matching network, and the matching network includes a negative feedback resistor , Gate series inductance , source degenerate inductance and MOS tubes , gate series inductance One end is connected to the DC blocking capacitor , the other end is connected to the MOS tube The gate, negative feedback resistor Connect to MOS tube Between the gate and drain, the matching network matches the input impedance to a near fixed ohm value.

3. The low-noise ultra-wideband active balun according to claim 1, characterized in that: MOS tube and MOS tubes The tubes are working in the saturation region, the power supply is 2.5V, the resistor and resistors The value range is [50, 100] ohms, the negative feedback resistor and negative feedback resistors The resistance value of the MOS tube is in the kilo-ohm range. Biased around 1.5V, the inductor Around 1nH.

4. The low-noise ultra-wideband active balun according to claim 1, wherein: The negative feedback resistor The self-bias is achieved by the negative feedback resistor Connect to MOS tube Between the gate and drain, The drain voltage is used as the gate bias voltage, and the negative feedback resistor The value range is [300, 500]Ω.

5. The low-noise ultra-wideband active balun according to claim 1, characterized in that: The MOS tube , MOS tube The bias voltage Vbias is around 1.5V; the MOS tube and MOS tubes The same size, MOS tube and MOS tubes The sizes are the same and both operate in the saturation region.

6. The low-noise ultra-wideband active balun according to claim 1, characterized in that: The diode voltage divider structure refers to the MOS tube and MOS tubes The gate and drain of the diode are connected to form a diode structure, respectively 、 Voltage division, then through the resistor 、 for and Provide bias voltage, and The same value, and The values are the same, and the resistance values are all in the kilo-ohm range. and The same size.

7. The low-noise ultra-wideband active balun according to claim 1, characterized in that: The phase compensation inductor refers to the MOS tube The drain and MOS tube The source of the phase compensation inductor Connected to reduce phase error, phase compensation inductor The value is around 300pH.

8. The low-noise ultra-wideband active balun according to claim 1, wherein: The parallel compensation structure refers to the load resistance and load inductance exist Drain and Power Supply In series, the load resistor and load inductance exist Drain and Power Supply In series, the load resistor 、 In the vicinity of [50, 100]Ω, the load inductance 、 Around 300pH.

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