Superconducting q-capacitor and operating tuning frequency

Abstract

A method for adjusting a resonant frequency of a qubit (100) in a quantum mechanical device (500) includes providing a substrate (202) having a front side (202A) and a back side (202B), the front side having at least a qubit formed thereon, the at least a qubit including capacitor pads (104A and 104B), and removing substrate material from the back side of the substrate at a region opposite the at least one qubit to change a capacitance around the at least one qubit to adjust a resonant frequency of the at least one qubit.

Description

BACKGROUND

[0001] The presently claimed embodiments of the present invention relate to superconducting quantum mechanical devices, and more particularly to a method for adjusting the resonant frequency of a qubit in a quantum mechanical device and a quantum mechanical device having one or more frequency adjusted qubits.

[0002] In superconducting quantum computing systems, the operating frequency of individual qubits within the computing circuit is controlled or set for proper operation. Unfortunately, Josephson junction (JJ) resistance in superconducting qubits can be difficult to control precisely. Thus, there is an undesirable amount of variability in the qubit JJ resistance that manifests itself as variability in the resonant frequency of the operation in the individual qubits. The resonant frequency of a qubit depends on the impedance of the device, i.e., on both the capacitance and resistance of the device. Various methods have been developed to adjust the qubit frequency after chip fabrication through modification of the JJ resistance. However, for example, the accuracy of predicting what modification is needed to properly align or set the qubit frequency is not sufficient to consistently avoid all possible frequency collisions in larger systems. As a result, undesirable frequency collisions still occur in superconducting qubit systems after the chip has been packaged and / or flip-chip bump bonded for use.

[0003] Accordingly, providing a method of modifying the qubit operating frequency after the chip has been flip-chip bonded can yield significant advantages in the deployment of larger quantum computing systems, as the operating parameters can be brought to fine-tuned performance after implementation of the package. Conventionally, qubit performance specifications have been modified through front side etching. However, front side etching is undesirable because (i) it significantly disturbs the qubit in the case of very strong electromagnetic (e.g., microwave or radio frequency) fields, (ii) it cannot be performed once the chip has been flip-chip bump bonded without bumping the chip for further processing, and (iii) the bump bonding process itself can have an impact on the final qubit performance metrics. SUMMARY

[0004] An aspect of the present invention is to provide a method for adjusting the resonant frequency of a qubit in a quantum mechanical device. The method includes providing a substrate having a front side and a back side, the front side having at least one qubit formed thereon, the at least one qubit having a capacitor pad. The method further includes removing substrate material from the back side of the substrate at a region opposite the at least one qubit to change a capacitance around the at least one qubit to adjust the resonant frequency of the at least one qubit.

[0005] In embodiments, removing the substrate material from the backside of the substrate at the region opposite the at least one qubit comprises selectively chemically etching the backside of the substrate using a chemical etchant selected based on the substrate material.

[0006] In embodiments, prior to chemically etching the backside of the substrate, an initial cavity is formed in the backside of the substrate in the vicinity of the at least one qubit by mechanically removing material from the backside of the substrate and then chemically etching the backside of the substrate at the initial cavity formed. In embodiments, forming the initial cavity in the backside of the substrate comprises defining a face of the initial cavity having one or more first crystal planes and one or more second crystal planes such that the chemical etchant preferentially etches the substrate material from the one or more first crystal planes and substantially does not etch the substrate material from the one or more second crystal planes to form a final etched cavity in the vicinity of the at least one qubit. In embodiments, the substrate material is silicon and the one or more first crystal planes have a (111) plane and the one or more second crystal planes have a (100) plane.

[0007] In embodiments, the method further comprises controlling the amount of substrate material etched by selecting the size and shape of the initial cavity such that etching of the substrate material stops when the one or more first crystal planes are substantially eliminated, thereby forming a final self-limited etched cavity. In embodiments, controlling the amount of material etched comprises controlling the etch depth of the final cavity from the backside to the frontside.

[0008] In embodiments, removing the substrate material from the backside of the substrate at the region opposite the at least one qubit comprises: applying an etch mask film to the backside of the substrate; and etching the selected region at the backside of the substrate opposite the at least one qubit. In embodiments, after applying the etch film mask to the backside of the substrate and prior to etching the selected region at the backside of the substrate, one or more openings are formed in the etch film mask at the selected region. In embodiments, forming the one or more openings in the etch film mask comprises using focused ion beam etching, laser ablation, or mechanical milling, or any combination thereof to form the one or more openings.

[0009] In embodiments, the method further comprises disposing a chemical etchant container to define a region around the one or more openings in the etch film mask, and providing a wet or dry etch chemistry to remove the substrate material from the defined region at the one or more openings in the etch film mask to form one or more cavities at the backside of the substrate.

[0010] In embodiments, removing the substrate material from the backside of the substrate at the region opposite the at least one qubit comprises using laser ablation, mechanical milling, focused ion beam, or any combination thereof to remove material.

[0011] In embodiments, removing substrate material from the backside of the substrate at a region opposite the at least one qubit includes removing the substrate material from the backside of the substrate at multiple regions opposite multiple qubits to form multiple cavities on the backside of the substrate. In embodiments, removing the substrate material from the backside of the substrate at the multiple regions opposite the multiple qubits includes removing the substrate material from the backside of the substrate at the multiple regions opposite the multiple qubits substantially simultaneously using a global substrate etch process. In embodiments, the global etch process includes applying a chemical etch process.

[0012] In embodiments, the method further includes controlling the amount of material etched by selecting a size and shape of the initial cavity formed for each of the multiple regions such that etching of the substrate material stops at different times depending on the selected geometry or shape of the initial opening. In embodiments, forming the initial cavity includes defining a face of the initial cavity in the substrate material having one or more first crystal planes and one or more second crystal planes such that the substrate material is etched from the one or more first crystal planes and substantially not etched from the one or more second crystal planes.

[0013] Another aspect of the present invention is to provide a quantum mechanical device, the device including a substrate having a frontside and a backside; and a plurality of qubits formed on the frontside of the substrate, the plurality of qubits including a plurality of capacitor pads. The substrate includes one or more cavities formed on the backside of the substrate opposite one or more qubits of the plurality of qubits. A size or shape, or both, of the one or more cavities are selected to change a capacitance around the one or more qubits in order to adjust a resonant frequency of the one or more qubits.

[0014] In embodiments, the substrate can be made of, for example, silicon, high resistivity silicon, or sapphire. In embodiments, the plurality of capacitor pads are made of a superconducting material. In embodiments, the superconducting material can be aluminum (Al) or niobium (Nb). In embodiments, the resonant frequency of the one or more qubits is adjusted by 0.2% to 20%. In embodiments, the resonant frequency of each of the one or more qubits is adjusted by a different amount depending on the size or shape, or both, of the one or more cavities.

[0015] The above method provides an alternative solution to mitigate frequency collisions in superconducting qubit systems by etching the substrate from the backside of the device. Backside etching of the qubit not only provides an alternative method to tune the qubit operating frequency, but it also enables frequency tuning of a qubit chip that has already been flip-chip bonded without having to de-bond the qubit sub-system to fine-tune the chip for proper operation. Backside etching of the qubit also allows wafer / substrate scale processing while minimally disturbing the qubit environment and junction inductance by making substrate modifications in areas where the radio frequency (RF) field is weakest, but can still have a proper and desired impact on device performance. BRIEF DESCRIPTION OF DRAWINGS

[0016] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

[0017] The present disclosure, as well as the methods of operation and functions of the related elements of structure and the combination of parts and economies of manufacture, will become more apparent upon consideration of the following description and the appended claims with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate similar parts in the various figures. It is to be expressly understood, however, that the drawings are for purposes of illustration only and are not intended as a definition of the limits of the application. As such, the

[0018] Figure 1A is a schematic cross-sectional view of a qubit device according to an embodiment of the present application;

[0019] Figure 1B is an electron microscope (EM) image of a Josephson junction according to an embodiment of the present application;

[0020] Figure 1C is an electronic circuit diagram of a qubit device coupled to an electromagnetic signal line through a capacitor according to an embodiment of the present application;

[0021] Figure 2 is a contour plot of the simulated two-dimensional electric field generated by a plurality of capacitor pads connected to the Josephson junction according to an embodiment of the present application;

[0022] Figures 3A to 3C is a contour plot of the potential distribution around a capacitor pad according to an embodiment of the present application;

[0023] Figure 4 is a plot of capacitance (in %) versus etch depth (in pm) corresponding to the amount of substrate material removed from the backside of the substrate according to an embodiment of the present application;

[0024] Figure 5schematically depicts the concept of changing the capacitance of multiple qubits by varying the shape and / or depth of the trenches or cavities on the backside of the substrate according to embodiments of the present application;

[0025] Figure 6 is a flowchart of a method for adjusting the resonant frequency of a qubit (e.g., qubit 1, qubit 2, qubit 3) in a quantum mechanical device according to embodiments of the present application;

[0026] Figure 7 is a schematic of an initial cavity formed on the backside of a substrate that leads to self-limiting anisotropic etching according to embodiments of the present application;

[0027] Figure 8 depicts the backside of a substrate having multiple cavities according to embodiments of the present application;

[0028] Figure 9 shows a three-dimensional illustration of an etch mask film applied to the backside of a substrate according to embodiments of the present application;

[0029] Figure 10 shows an example micrograph of a qubit chip having four qubits (qubit 1, qubit 2, qubit 3, and qubit 4) according to embodiments of the present application, for example, on the frontside of the substrate of the qubit chip;

[0030] Figure 11 is a schematic of a qubit chip bonded to an interposer substrate with bumps according to embodiments of the present disclosure;

[0031] Figure 12 is a schematic of a qubit chip bonded to an interposer substrate having one or more openings formed on the backside of the substrate according to embodiments of the present disclosure;

[0032] Figure 13A is a schematic three-dimensional representation of a container deposited on the backside of a substrate to define an area surrounding one or more openings in an etch film mask according to embodiments of the present application;

[0033] Figure 13B is a schematic top view within the container showing the relative positions of the qubit chip and the one or more openings according to embodiments of the present application; and

[0034] Figure 13C is a schematic showing the position of a qubit chip relative to the container according to embodiments of the present application, the chip being on the frontside of the substrate. DETAILED DESCRIPTION

[0035] Figure 1Ais a schematic cross-sectional view of a qubit device 100 according to embodiments of the present invention. As shown, the qubit device 100 includes a Josephson junction 102 and capacitor pads 104A and 104B. The Josephson junction 102 is connected to the capacitor pads 104A and 104B. The capacitor pads 104A and 104B can in turn be capacitively coupled to electromagnetic (e.g., microwave or radio frequency) signal lines 106A, 106B, and 106C through, for example, capacitors 108A, 108B, and 108C. Figure 1A

[0036] Figure 1B is an electron microscope (EM) image of a Josephson junction according to embodiments of the present invention. In embodiments, the Josephson junction can have a size of about 100 nm 2 by 100 nm 2 . Figure 1C is an electrical diagram of a qubit device 100 coupled to electromagnetic signal lines through capacitors 108A, 108B, and 108C according to embodiments of the present invention. The Josephson junction 102 has an internal capacitance C j and an internal inductance L j (e.g., L j is about 20 nH and C j is about 1 fF). However, as must be appreciated, the internal inductance L j and the internal capacitance C j of the Josephson junction 102 can have other values depending on the construction of the Josephson junction 102. In addition to the Josephson junction internal capacitance C j , the qubit 100 also has a coupling or signal capacitance C s due to the capacitor pads 104A and 104B. In embodiments, the capacitance C s (from the capacitor pads 104A and 104B) can be about 60 fF. However, depending on the size, geometry, or shape of the capacitor pads 104A and 104B, the capacitance C s may also have other values.

[0037] In embodiments, the resonant frequency is determined by the capacitive and resistive contributions from both the Josephson junction (including the internal capacitance C j and inductance L j ) and the associated capacitors C s from the capacitor pads 104A and 104B. Thus, for example, a first resonant frequency f 01 of the qubit depends on the device capacitance and can be mathematically expressed by the following equation (1). For example, the "0" in the index indicates the ground state of the Josephson junction 102 and the "1" in the index indicates the first excited state of the Josephson junction 102.

[0038] ​ (1)

[0039] where the energy E j and E c can be expressed by the following two equations (2) and (3).

[0040] (2)

[0041] (3)

[0042] where e is the electron charge, h is the Planck constant, is the sum of all capacitances, and I c is the critical current (Ambegaokar-Baratoff), given by the following equation (4).

[0043] (4)

[0044] where R n is the resistance of the Josephson junction (JJ), and is the superconducting energy gap, which is a material property independent of the material geometry, where the size of the superconducting energy gap indicates the energy gain of two electrons when they form a Cooper pair. The energy gap depends on the temperature and increases as the temperature decreases.

[0045] Thus, by changing the capacitance C s that includes the contribution of these capacitances it is possible to change or alter the resonance frequency (e.g., the first resonance frequency f 01 ) of the qubit.

[0046] Figure 2 is a contour plot of an analog two-dimensional electric field produced by the capacitor pads 104A and 104B connected to the Josephson junction 102 according to an embodiment of the invention. The two capacitor pads 104A and 104B of the qubit 100 are represented as bars in Figure 2 . The Josephson junction 102 (not shown) is located between the two bars 104A and 104B. For example, the left bar corresponding to the capacitor pad 104A can be connected to zero potential, while the right bar corresponding to the capacitor pad 104B can be connected to a higher potential (e.g., about 7 10 3 V / m). In Figure 2 , the electron contour plot is superimposed on the representation of the capacitor pads 104A, 104B that are part of the quantum mechanical device 200. The qubit 100 is also part of the quantum mechanical device 200, which further includes a substrate 202. The substrate 202 has a front side 202A and a back side 202B. In Figure 2The capacitor pads 104A and 104B, shown as bars, and the Josephson junction 102 located between the two capacitor pads 104A and 104B of the qubit 100 are located on the front side 200A of the substrate 202 of the quantum mechanical device 200.

[0047] The change in the electric field distribution indicates a change in the effective dielectric constant of the substrate 202. The capacitance of the quantum mechanical device 200 is related to the effective dielectric constant of the substrate 202. The change in the electric field distribution can be achieved by changing the thickness of the substrate 200 at a particular location in the substrate 202. This can be performed, for example, by etching the substrate 202 from the back side 202B (i.e., removing substrate material from the back side 202B). The change in the electric field distribution due to the etching of the substrate 202 at the back side 202B indicates a change in the quantum mechanical device capacitance.

[0048] Figures 3A to 3C is a contour plot of the electric potential distribution around the capacitor pads 104A and 104B according to an embodiment of the present invention. The electric potential contours 300 are drawn around the ends of the capacitor pads 104A and 104B. Figure 3A The distribution of the electric potential around the Josephson junction 102 is shown, where the back side 202B of the substrate 202 of the device 200 is not etched. The ends of the capacitor pads 104A, 104B can be identified by the presence of a higher concentration of electric potential (typically shown as dots) 300. The Josephson junction 102 is located between the end of the capacitor pad 104A and the end of the capacitor pad 104B.

[0049] Figure 3B The distribution of the electric potential around the Josephson junction 102 is shown. The Josephson junction 102 is also located between the end of the capacitor pad 104A and the end of the capacitor pad 104B. However, as Figure 3B shown, the back side 202B of the substrate 202 is etched near the Josephson junction 102. The profile of the etched material of the substrate 202 is shown as a trapezoidal shape 302, where more material is removed near the Josephson junction 102 than further away from the Josephson junction 102. The removal of material at the back side 202B of the substrate 202 changes the shape of the electric potential contours 300, and thus the distribution of the electric potential around or near the Josephson junction 102. Thus, this indicates that the Josephson junction 102, and thus the capacitance of the qubit 100 around the capacitor pads 104A and 104B, is changed.

[0050] Figure 3C The distribution of the electric potential around the Josephson junction 102 is shown. The Josephson junction 102 is also located between the end of the capacitor pad 104A and the end of the capacitor pad 104B. As Figure 3C shown, the back side 202B of the substrate 202 is etched near the Josephson junction 102. The profile of the etched material of the substrate 202 is shown as a trapezoidal shape 302, where more material is removed near the Josephson junction 102 than further away from the Josephson junction 102. The removal of material at the back side 202B of the substrate 202 changes the shape of the electric potential contours 300, and thus the distribution of the electric potential around or near the Josephson junction 102. Thus, this indicates that the Josephson junction 102, and thus the capacitance of the qubit 100 around the capacitor pads 104A and 104B, is changed. Figure 3BThe etch profile shown is compared to the etch profile shown in FIG. 3. The backside 202B of the substrate 202 is etched further near the Josephson junction 102. The profile of the etched material of the substrate 202 is shown as a trapezoidal shape 304, where more material is removed near the Josephson junction 102 than Figure 3B the trapezoidal profile 302 shown in FIG. 3. The removal of material at the backside 202B of the substrate 202 changes the shape of the potential contour 300 and, thus, the distribution of the potential around or near the Josephson junction 102. Thus, this indicates that the capacitance of the quantum bit around the Josephson junction 102, as well as the capacitor pads 104A and 104B, is changed even further compared to Figure 3B the trapezoidal profile 302 shown in FIG. 3.

[0051] Figure 4 is a plot of capacitance (in %) versus etch depth (in pm) for the amount of substrate material removed at the backside 202B of the substrate 202 according to embodiments of the present application. The etch depth point 400 at approximately 0 pm corresponds to the zero etch depth shown in FIG. 3. Figure 3A The etch depth point 402 at approximately 70 pm corresponds to the etch depth shown in FIG. 3. Figure 3B The etch depth point 404 at approximately 100 pm corresponds to the etch depth shown in FIG. 4. Figure 3C The etch depth point 404 at approximately 100 pm corresponds to the etch depth shown in FIG. 4. At the etch depth point 400, the capacitance is 100% corresponding to the full value capacitance. At the etch depth point 402, the capacitance is approximately 80%. At the etch depth point 404, the capacitance is approximately 20%. The capacitance decreases as the etch depth increases. At the etch depth point 402, the remaining or residual thickness of the substrate material is approximately 30 pm. In embodiments, the useful tuning range of the frequency of the quantum bit is provided by the capacitance between approximately 100% and approximately 80% (e.g., a capacitance change between approximately 0.2% and approximately 20%). However, it is also contemplated to provide a wider range of frequency tuning by allowing a wider range of capacitance change (e.g., between 0.1% and 50%) where the substrate material is removed at depths in a range of, for example, between approximately 10 pm and approximately 90 pm. Figure 4 The plot shown in FIG. 4 is provided for a specific type of substrate material of silicon in this case. Thus, similar plots can also be provided for other types of substrate materials such as sapphire, etc. The curve capacitance versus etch depth for silicon can be different than the curve capacitance versus etch depth for sapphire. For example, the etch depth for sapphire. Thus, the numbers above for capacitance and for etch depth are provided for illustrative purposes only to show the change in capacitance as a function of etch depth.

[0052] Figure 5 The concept of changing the capacitance of multiple quantum bits by different amounts by changing the shape and / or depth of the trench or cavity at the backside of the substrate according to embodiments of the present application is schematically depicted. Figure 5Cross-sections of three of the multiple cavities formed by etching the back side 202B of the substrate 202 of the quantum mechanical device 500 are also depicted. (See diagram for example.) Figure 8 As shown, take a section along line 5-5. For example, as... Figure 5 As shown, the capacitance of the first qubit (qubit 1) of the quantum mechanical device 500 changes by approximately 1%, the capacitance of the second qubit (qubit 2) of the quantum mechanical device 500 changes by approximately 20%, and the capacitance of the third qubit (qubit 3) of the quantum mechanical device 500 changes by approximately 3%. Figure 5 As shown, by forming a trench or cavity 501 (e.g., a triangular trench) on the back side 202B of substrate 202 opposite to qubit 1 on the front side 202A of substrate 202, the capacitance of qubit 1 changes by approximately 1%. Similarly, by forming a wider trench or cavity 503 (e.g., a wider triangular trench), the capacitance of qubit 3 changes by approximately 3%, wherein more substrate material is removed or etched on the back side 202B of substrate 202 opposite to qubit 3 on the front side 202A of substrate 202. By forming even wider trenches or cavities 502 (e.g., wider trapezoidal trenches), the capacitance of qubit 2 changes by approximately 20%, wherein even more substrate material is removed or etched on the back side 202B of substrate 202 opposite to qubit 2 on the front side 202A of substrate 202.

[0053] Therefore, as can be understood from the preceding paragraphs, a quantum mechanical device 500 is provided having a plurality of qubits (qubit 1, qubit 2, qubit 3) formed on the front side 202A of a substrate 202. The plurality of qubits (qubit 1, qubit 2, qubit 3) includes a plurality of capacitor pads 104A, 104B. The substrate 202 has one or more cavities 501, 502, 503 formed on the back side 202B of the substrate 202 opposite to one or more of the plurality of qubits (qubit 1, qubit 2, qubit 3). The size or shape, or both, of the one or more cavities 501, 502, 503 are selected to change the capacitance around the one or more qubits (qubit 1, qubit 2, qubit 3) in order to adjust the resonant frequency of the one or more qubits (qubit 1, qubit 2, qubit 3).

[0054] In one embodiment, the substrate 202 may be, for example, silicon, high-resistivity silicon, or sapphire. In another embodiment, the plurality of capacitor pads 104A, 104B are made of a superconducting material. The superconducting material may be, for example, aluminum (Al), niobium (Nb), etc.

[0055] In embodiments, the resonant frequency of the one or more qubits (qubit 1, qubit 2, qubit 3) can be adjusted by 0.2% to 20%. For example, the resonant frequency of qubit 1 can be adjusted by about 2% by changing the capacitance by about 1%. The resonant frequency of qubit 2 can be adjusted by about 40% by changing the capacitance by about 20%. The resonant frequency of qubit 3 can be adjusted by about 6% by changing the capacitance by about 3%. Thus, in embodiments, the resonant frequency of each of the one or more qubits (qubit 1, qubit 2, qubit 3) can be adjusted by a different amount depending on the size or shape, or both, of the one or more cavities 501, 502, and 503.

[0056] As can be appreciated from the above paragraphs, there is also provided a method for adjusting a resonant frequency of a qubit (e.g., qubit 1, qubit 2, qubit 3) in a quantum mechanical device (e.g., quantum mechanical device 500). Figure 6 is a flowchart of a method for adjusting a resonant frequency of a qubit (e.g., qubit 1, qubit 2, qubit 3) in a quantum mechanical device (e.g., quantum mechanical device 500) in accordance with embodiments of the present application. The method includes providing a substrate 202 having a front side 202A and a back side 202B at step S602. Formed on the front side 202A is at least one qubit (qubit 1, qubit 2, qubit 3). The at least one qubit (qubit 1, qubit 2, qubit 3) includes a capacitor pad 104A, 104B. At step S604, the method further includes removing substrate material from the back side 202B of the substrate 202 at a region opposite the at least one qubit (qubit 1, qubit 2, qubit 3) so as to change a capacitance around the at least one qubit (qubit 1, qubit 2, qubit 3) so as to adjust a resonant frequency of the at least one qubit (qubit 1, qubit 2, qubit 3).

[0057] In embodiments, removing substrate material from the back side 202B of the substrate 202 at a region opposite the at least one qubit (qubit 1, qubit 2, qubit 3) includes selectively chemically etching the back side 202B of the substrate 202 using a chemical etchant selected according to the substrate material (e.g., silicon, sapphire, etc.). In embodiments, prior to chemically etching the back side 202B of the substrate 202, an initial cavity is formed in the back side 202B of the substrate 202 in the vicinity of the at least one qubit (e.g., qubit 1, qubit 2, qubit 3) by mechanically removing material from the back side 202B of the substrate 202 and then chemically etching the back side 202B of the substrate 202 at the initial cavity formed.

[0058] Figure 7is a schematic of an initial cavity 602 formed on the backside 202B of a substrate 202 resulting in a self-limited anisotropic etch according to embodiments of the application. In embodiments, forming the initial cavity 602 in the backside 202B of the substrate 202 includes defining a facet 604 of the initial cavity 602 having one or more first crystal planes 604A (e.g., crystal planes (111)) and one or more second crystal planes 604B (e.g., crystal planes (100)) such that a chemical etchant preferentially etches the substrate material from the one or more first crystal planes 604A (e.g., crystal planes (111)) and substantially not from the one or more second crystal planes 604B (e.g., crystal planes (100)) to form an etched final cavity 606 (not shown in Figure 7 ) in the vicinity of at least one qubit. In this way, the etching is anisotropic because it preferentially etches one crystal plane over another, and is self-limiting because the etching automatically stops when the etchant reaches the less etched crystal plane (second crystal plane).

[0059] In embodiments, the substrate material can be, for example, silicon, in which case the one or more first crystal planes include (111) silicon crystal planes and the one or more second crystal planes include (100) silicon crystal planes. However, other crystal planes can be selected depending on the type of substrate material.

[0060] In embodiments, the method includes controlling the amount of etched substrate material by selecting the size and shape of the initial cavity (e.g., cavity 602) such that etching of the substrate material is stopped when the one or more first crystal planes 604A (e.g., (111)-planes) are substantially eliminated in order to form a final cavity of a size self-limited etch. In embodiments, controlling the amount of etched material includes controlling the etch depth of the final cavity from the backside 202B to the frontside 202A of the substrate 202.

[0061] Figure 8 A backside 202B of a substrate 202 having a plurality of cavities 800 according to embodiments of the application is shown. For example, by selecting an appropriate shape for the initial cavity 602 (shown in Figure 7 ), the size and / or shape of the cavities can be controlled. In this way, etching of the substrate material is stopped when the one or more first crystal planes 604A (e.g., (111)-planes) are substantially eliminated in order to form a final cavity 800 of a size self-limited etch. Figure 5 A cross-section along line 5-5 of the three cavities formed is shown.

[0062] In an embodiment, removing substrate material from the backside 202B of the substrate 202 at regions opposite the at least one qubit 100 (e.g., qubit 1, qubit 2, qubit 3) includes applying one etch mask film 900 to the backside 202B of the substrate 202 and etching selected regions on the backside 202B of the substrate 202 opposite the at least one qubit 100. Figure 9 A three-dimensional illustration of an etch mask film 900 applied to the backside 202B of a substrate according to an embodiment of the present disclosure is shown. In an embodiment, applying the etch mask film 900 to the backside 202B of the substrate 202 includes depositing niobium (Nb) on the backside 202B of the substrate 202. In another embodiment, applying the etch mask film 900 to the backside 202B of the substrate 202 includes depositing an oxide or silicon nitride (SiN) on the backside 202B of the substrate 202. In yet another embodiment, creating the etch mask involves oxidizing the silicon substrate 202 and removing the oxide layer on the frontside 202A of the silicon substrate 202.

[0063] In an embodiment, after applying or creating the etch mask film 900 on the substrate 202, the substrate is processed to create capacitor pads, Josephson junctions, etc. by performing aluminum evaporation on the frontside 202A of the substrate 202. The backside-coated processed substrate is then diced to produce a plurality of chips 1002. A microscopic image is then taken of the frontside 202A of the diced qubit chip 1002 in order to record the positions of the qubits 100 (e.g., qubit 1, qubit 2, qubit 3) relative to the edges of the dice. Figure 10 An example microscopic image of a qubit chip 1002 having four qubits (qubit 1, qubit 2, qubit 3, and qubit 4) on the frontside 1004A of a substrate 1004 of the qubit chip 1002, according to an embodiment of the present disclosure, is shown.

[0064] The method further includes bump bonding the substrate 1004 of the qubit chip 1002 having the qubits (qubit 1, qubit 2, qubit 3, and qubit 4) to an interposer substrate 1102. Figure 11 A schematic diagram of a qubit chip 1002 bonded to an interposer substrate 1102 with bump bonding 1006 according to an embodiment of the present disclosure. The frontside 1004A of the substrate 1004 of the qubit chip 1002 having the qubits disposed thereon faces the interposer substrate 1102, while the backside 1004B of the substrate 1004 of the qubit chip 1002 faces away from or is opposite the interposer substrate 1102.

[0065] In an embodiment, the method further comprises forming one or more openings 1202 in the etch film mask thin film 900 at selected regions after applying the etch film mask thin film 900 to the backside 1004B of the substrate 1004 and prior to etching the selected regions at the backside 1004B of the substrate 1004. Figure 12 is a schematic illustration of a quantum bit chip 1002 bonded to an interposer substrate 1102 having one or more openings 1202 formed on the backside 1004B of the substrate 1004 in accordance with an embodiment of the present disclosure. In an embodiment, the one or more openings 1202 can be formed, for example, by using focused ion beam (FIB) etching, laser ablation, mechanical milling, or any combination thereof, or other etching methods.

[0066] In an embodiment, the method further comprises disposing a chemical etchant container 1302 to define a region 1304 around the one or more openings 1202 in the etch mask thin film 900 and providing a wet or dry etch chemistry to remove substrate material from the defined region 1304 at the one or more openings 1202 in the etch mask thin film 900 to form one or more cavities (such as cavities 501, 502, 503 shown) at the backside 1004B of the substrate 1004. Figure 5 Figure 13A is a schematic three-dimensional representation of a container 1302 deposited on the backside 1004B of the substrate 1004 to define a region 1304 around the one or more openings 1202 in the etch mask thin film 900 in accordance with an embodiment of the present disclosure. Figure 13B is a schematic top view of the interior of the container 1302 showing the relative positions of the quantum bit chip 1002 and the one or more openings 1202 in accordance with an embodiment of the present disclosure. Figure 13C is a schematic illustration showing the position of the quantum bit chip 1002 relative to the container 1302 in accordance with an embodiment of the present disclosure, the quantum bit chip positioned on the frontside 1004A of the substrate 1004.

[0067] ​In embodiments, removing substrate material from the backside 1004B of the substrate 1004 at the region 1304 opposite the at least one qubit (qubit 1, qubit 2,...) includes removing substrate material from the backside 1004B of the substrate 1004 at a plurality of regions 1304 opposite a plurality of qubits to form a plurality of cavities on the backside 1004B of the substrate 1004. In embodiments, removing the substrate material from the backside 1004B of the substrate 1004 at the plurality of regions opposite the plurality of qubits includes removing the substrate material from the backside 1004B of the substrate 1004 at the plurality of regions 1304 opposite the plurality of qubits substantially simultaneously using a global substrate etching process. In embodiments, the global etching process includes applying a chemical etching process. For example, a chemical etchant can be poured into a chemical etchant container 1302 to etch the substrate at the one or more openings 1202.

[0068] In embodiments, the method further includes controlling the amount of material etched by selecting a size and shape of the initial cavity formed for each of the plurality of regions so as to stop etching of the substrate material at different times depending on the geometry or shape of the initial opening selected (e.g., as shown in Figure 7 In embodiments, forming the initial cavity includes defining a face of the initial cavity in the substrate material having one or more first crystal planes and one or more second crystal planes such that the substrate material is etched from the one or more first crystal planes and substantially not etched from the one or more second crystal planes, as described in the paragraphs above.

[0069] The backside etching method above has a number of benefits, including: 1) individual qubits can be independently frequency tuned, e.g., by using different degrees of backside substrate removal at the vicinity of each qubit, thereby changing the qubit capacitance by different amounts; 2) individual qubits can be independently frequency tuned using a global substrate etching process; 3) backside etching enables qubit operation specifications to be modified with substantially less or minimal perturbation to the qubit’s environment; 4) qubit frequency tuning after die bumping or packaging of the chip is enabled, allowing fine tuning of qubit specifications after packaging has occurred, which enables a more reliable and controllable end product to achieve optimal device performance.

[0070] The description of various embodiments of the application has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technology found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for tuning a resonant frequency of a qubit in a quantum mechanical device, comprising: providing a substrate having a front side and a back side, the front side having at least one qubit formed thereon, the at least one qubit including a first capacitor pad and a second capacitor pad with a gap retained therebetween; and removing substrate material from the back side of the substrate at least at an area located below the gap to form a trench to change a capacitance around the at least one qubit to tune a resonant frequency of the at least one qubit, wherein a base of the trench is wider than the gap and extends under the entire gap.

2. The method of claim 1, wherein, Removing the substrate material from the back side of the substrate at the area located below the gap includes selectively chemically etching the back side of the substrate using a chemical etchant selected according to the substrate material.

3. The method of claim 2, wherein, Prior to chemically etching the back side of the substrate, forming an initial cavity in the back side of the substrate below the gap in a vicinity of the at least one qubit by mechanically removing material from the back side of the substrate, and then chemically etching the back side of the substrate at the formed initial cavity.

4. The method of claim 3, wherein, Forming the initial cavity in the back side of the substrate includes defining a face of the initial cavity having one or more first crystal planes and one or more second crystal planes such that the chemical etchant preferentially etches the substrate material from the one or more first crystal planes without substantially etching substrate material from the one or more second crystal planes to form an etched final cavity of the trench below the gap in a vicinity of the at least one qubit.

5. The method of claim 4, wherein, The substrate material is silicon and the one or more first crystal planes include (111) planes and the one or more second crystal planes include (100) planes.

6. The method of claim 4, further comprising controlling an amount of the substrate material etched by selecting a size and shape of the initial cavity such that etching of the substrate material stops when the one or more first crystal planes are substantially eliminated, thereby forming a self-limited etched final cavity.

7. The method of claim 5, further comprising controlling an amount of the substrate material etched by selecting a size and shape of the initial cavity such that etching of the substrate material stops when the one or more first crystal planes are substantially eliminated, thereby forming a self-limited etched final cavity.

8. The method of claim 6 or 7, wherein, Controlling an amount of the substrate material etched includes controlling an etch depth of the etched final cavity from the back side to the front side.

9. The method of any one of claims 1-7, wherein, Removing the substrate material from the back side of the substrate at the area located below the gap includes applying an etch mask film to the back side of the substrate and etching a selected area at the back side of the substrate opposite the at least one qubit.

10. The method of claim 9, further comprising: forming one or more openings in the etch mask thin film at the selected regions after applying the etch mask thin film to the backside of the substrate and prior to etching the selected regions at the backside of the substrate.

11. The method of claim 10, wherein, forming the one or more openings in the etch mask thin film includes using focused ion beam etching, laser ablation, or mechanical milling, or any combination thereof to form the one or more openings.

12. The method of any one of claims 10-11, further comprising disposing a chemical etchant container to define an area around the one or more openings in the etch mask thin film and providing a wet or dry etch chemistry to remove substrate material from the defined area at the one or more openings in the etch mask thin film to form one or more cavities at the backside of the substrate.

13. The method of any one of claims 1-7, wherein, removing the substrate material from the backside of the substrate at the regions located below the gaps includes removing material using laser ablation, mechanical milling, focused ion beam, or any combination thereof.

14. The method of any one of claims 1-7, wherein, removing the substrate material from the backside of the substrate includes removing the substrate material from the backside of the substrate at a plurality of regions opposite a plurality of qubits to form a plurality of cavities on the backside of the substrate.

15. The method of claim 14, wherein the removing the substrate material from the backside of the substrate at the plurality of regions opposite the plurality of qubits includes removing the substrate material from the backside of the substrate at the plurality of regions opposite the plurality of qubits substantially simultaneously using a global substrate etch process.

16. The method of claim 15, wherein, the global substrate etch process includes applying a chemical etch process.

17. The method of any one of claims 15-16, further comprising controlling an amount of etched material by selecting a size and shape of an initial cavity formed for each of the plurality of regions such that removal of the substrate material stops at different times depending on the selected geometry or shape of the initial cavity.

18. The method of claim 17, wherein, forming the initial cavity includes defining a face of the initial cavity in the substrate material having one or more first crystal planes and one or more second crystal planes such that the substrate material is etched from the one or more first crystal planes and substantially not etched from the one or more second crystal planes.

19. A quantum mechanical device, comprising: a substrate having a frontside and a backside, the frontside having at least one qubit formed thereon, the at least one qubit including a first capacitor pad and a second capacitor pad with a gap remaining between the first capacitor pad and the second capacitor pad; and wherein the substrate includes a region located below the respective gap for forming a trench to change a capacitance around the at least one qubit to adjust a resonant frequency of the at least one qubit, wherein a base of the trench is wider than the gap and extends under the entire gap.

20. The quantum mechanical device of claim 19, wherein, the substrate is selected from the group consisting of silicon, high resistivity silicon, and sapphire.

21. The quantum mechanical device of claim 19, wherein, the first capacitor pad and the second capacitor pad are made of a superconducting material.

22. The quantum-mechanical device of claim 20, wherein, The first and second capacitor pads are made of a superconducting material.

23. The quantum-mechanical device of claim 21 or 22, wherein, The superconducting material is selected from the group consisting of aluminum (Al) and niobium (Nb).

24. The quantum-mechanical device of any one of claims 19 to 22, wherein, The resonance frequency of the at least one qubit is adjusted by 0.2% to 20%.

25. The quantum-mechanical device of any one of claims 19 to 22, wherein, The resonance frequency of each of the at least one qubit is adjusted by a different amount depending on the size or shape of the trench, or both.

26. A quantum mechanical device comprising: a substrate having a front side and a back side, the front side having a plurality of qubits formed thereon, each qubit of the plurality of qubits including a respective capacitor pad of a plurality of capacitor pads, a respective gap being preserved between adjacent ones of the respective capacitor pads; wherein the substrate includes an area beneath the respective gap for forming a trench to change a capacitance around the plurality of qubits to adjust a resonance frequency of the plurality of qubits, wherein a base of the trench is wider than the gap and extends beneath the entire gap.

27. The quantum-mechanical device of claim 26, wherein, The dimensions of the trench include a size and a shape, and wherein the resonance frequency of the plurality of qubits is adjusted based on changing the size of the trench, changing the shape of the trench, or both changing the size and shape of the trench.

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