Display panel and display device

Abstract

The embodiment of the present invention provides a display panel and a display device, which relates to the field of display technology and is used to improve the working reliability of a light-emitting shift circuit. The display panel includes a substrate and a circuit layer located on one side of the substrate, the circuit layer includes a light-emitting shift circuit; the light-emitting shift circuit includes: a first output module, the first output module is electrically connected to a first node, a first fixed potential signal line and a light-emitting control signal line respectively, the first output module is used to respond to the voltage of the first node, and transmit the light-emitting enable voltage provided by the first fixed potential signal line to the light-emitting control signal line; at least one control module electrically connected to the first node, the control module includes one or more control transistors; the display panel also includes a top shading layer, the top shading layer is located on the side of the control transistor facing away from the substrate, in a direction perpendicular to the plane where the substrate is located, the top shading layer overlaps with the channel of at least one control transistor, and the top shading layer receives a voltage signal.

Description

[Technical field]

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. [Background technology]

[0002] The display panel includes a light emitting shift circuit, which is electrically connected to the sub-pixel through a light emitting control signal line and is used to provide a light emitting control signal to the sub-pixel to control the light emitting state of the sub-pixel.

[0003] As is known to all, the light-emitting shift circuit includes a plurality of transistors. However, when the transistor is affected by external factors such as light, its threshold voltage is prone to drift, thereby affecting the working reliability of the light-emitting shift circuit. For example, due to the influence of the characteristics of the transistor device, the light-emitting shift circuit may have voltage instability when outputting the light-emitting enable level, causing the output signal to have steps, thereby affecting the light-emitting state of the sub-pixel, and even causing the light-emitting shift circuit to fail to function so that the sub-pixel cannot emit light normally, which seriously affects the display performance. [Summary of the invention]

[0004] In view of this, an embodiment of the present invention provides a display panel and a display device to improve the working reliability of a light emitting shift circuit.

[0005] On the one hand, an embodiment of the present invention provides a display panel, comprising a substrate and a circuit layer located on one side of the substrate, wherein the circuit layer comprises a light emitting shift circuit;

[0006] The light emitting shift circuit comprises:

[0007] a first output module, the first output module being electrically connected to the first node, the first fixed potential signal line and the light-emitting control signal line respectively, and the first output module being used for transmitting the light-emitting enable voltage provided by the first fixed potential signal line to the light-emitting control signal line in response to the voltage of the first node;

[0008] at least one control module electrically connected to the first node, the control module comprising one or more control transistors;

[0009] The display panel also includes a top shading layer, which is located on the side of the control transistor facing away from the substrate. In a direction perpendicular to the plane where the substrate is located, the top shading layer overlaps with a channel of at least one of the control transistors, and the top shading layer receives a voltage signal.

[0010] On the other hand, an embodiment of the present invention provides a display device, including the above-mentioned display panel.

[0011] One of the above technical solutions has the following beneficial effects:

[0012] The embodiment of the present invention sets a top light shielding layer. On the one hand, the top light shielding layer can shield the external ambient light incident from the top of the display panel, preventing this part of the external ambient light from irradiating the channel of the control transistor, thereby reducing the influence of light on the threshold voltage of this part of the control transistor, and preventing the threshold of this part of the control transistor from being positively biased. In this way, the reliability of the working state of the control transistor in the control module can be improved, avoiding the influence on the voltage of the first node, enabling the light-emitting shift circuit to output a stable low level during the light-emitting period, and improving the accuracy of the light-emitting brightness of the light-emitting element.

[0013] On the other hand, a large number of metal traces for forming transistors or signal lines are arranged in the circuit layer. When the top light-shielding layer is located on the side of the control transistor facing away from the substrate, the top light-shielding layer is equivalent to being arranged inside the film layer of the display panel. By making the top light-shielding layer receive a voltage signal, signal transmission can be enabled on the top light-shielding layer, thereby avoiding the large area of ​​metal layer without signal addition affecting the device electrical properties of the transistor in the circuit layer.

Brief Description of the Drawings

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 A top view of a display panel provided by an embodiment of the present invention;

[0016] Figure 2 A cross-sectional view of a display panel provided by an embodiment of the present invention;

[0017] Figure 3 A schematic diagram of a circuit structure of a light emitting shift circuit provided in an embodiment of the present invention;

[0018] Figure 4 Another circuit structure schematic diagram of the light emitting shift circuit provided in an embodiment of the present invention;

[0019] Figure 5 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention;

[0020] Figure 6 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention;

[0021] Figure 7 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention;

[0022] Figure 8 for Figure 7 A cross-sectional view along the A1-A2 direction;

[0023] Fig. 9 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0024] Fig.10 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0025] Fig.11 A schematic diagram of another membrane layer structure provided by an embodiment of the present invention;

[0026] Fig.12 Another top view of the display panel provided by the embodiment of the present invention;

[0027] Fig.13 for Fig.12 A cross-sectional view along the B1-B2 direction;

[0028] Fig.14 for Fig.12 Another cross-sectional view along the B1-B2 direction;

[0029] Fig.15 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0030] Fig.16 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0031] Fig.17 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0032] Fig.18 Another partial cross-sectional view of a display panel provided by an embodiment of the present invention;

[0033] Fig.19 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0034] Fig. 20 Another partial cross-sectional view of a display panel provided by an embodiment of the present invention;

[0035] Fig.21 A timing diagram provided by an embodiment of the present invention;

[0036] Fig. 22 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. [Specific implementation method]

[0037] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] It should be clear that the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0040] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0041] An embodiment of the present invention provides a display panel, such as Figure 1 and Figure 2 As shown, Figure 1 A top view of a display panel provided by an embodiment of the present invention, Figure 2 A cross-sectional view of a display panel provided in an embodiment of the present invention, the display panel includes a substrate 1 and a circuit layer 2 located on one side of the substrate 1, the circuit layer 2 includes a light emitting shift circuit 3 and a pixel circuit 4, wherein the light emitting shift circuit 3 is electrically connected to the pixel circuit 4 through a light emitting control signal line Emit, for providing a light emitting control signal to the pixel circuit 4, and the pixel circuit 4 is further electrically connected to the light emitting element 10, for responding to the light emitting control signal to drive the light emitting element 10 to emit light.

[0042] like Figure 3 and Figure 4 As shown, Figure 3 A schematic diagram of a circuit structure of the light emitting shift circuit 3 provided in an embodiment of the present invention is shown in FIG. Figure 4Another circuit structure diagram of the light emitting shift circuit 3 provided in an embodiment of the present invention is shown. The light emitting shift circuit 3 includes a first output module 5, and the first output module 5 is electrically connected to the first node N1, the first fixed potential signal line VGL and the light emitting control signal line Emit respectively. The first output module 5 is used to respond to the voltage of the first node N1 and transmit the light emitting enable voltage provided by the first fixed potential signal line VGL to the light emitting control signal line Emit. In addition, the light emitting shift circuit 3 also includes at least one control module 6 electrically connected to the first node N1, and the control module 6 includes one or more control transistors M0.

[0043] See also Figure 2 The display panel also includes a top light-shielding layer 7, which is located on the side of the control transistor M0 facing away from the substrate 1. In a direction perpendicular to the plane of the substrate 1, the top light-shielding layer 7 overlaps with a channel of at least one control transistor M0, and the top light-shielding layer 7 receives a voltage signal.

[0044] It should be noted that, combined with Figure 2 , the control transistor M0 includes an active layer p, a gate g, a first electrode s and a second electrode d, wherein the active layer p includes a first doping region m1 electrically connected to the first electrode s, a second doping region m2 electrically connected to the second electrode d, and a channel c located between the first doping region m1 and the second doping region m2. The top light shielding layer 7 overlaps with the channel of the control transistor M0, which means that the top light shielding layer 7 overlaps with the channel c of the active layer p in the control transistor M0.

[0045] According to the specific structure of the light-emitting shift circuit 3, the first output module 5 outputs the light-emitting enable voltage (low level) by responding to the voltage of the first node N1. If the potential of the first node N1 is unstable, the conduction degree of the transistor in the first output module 5 will change, making the signal output by the first output module 5 unstable and unable to maintain a constant low potential, thereby affecting the light-emitting state of the light-emitting element 10. The control module 6 is directly connected to the first node N1, so the device characteristics of the control transistor M0 in the control module 6 will affect the potential of the first node N1, thereby greatly affecting the stability of the light-emitting enable voltage output by the first output module 5.

[0046] The embodiment of the present invention provides a top light shielding layer 7. On the one hand, the top light shielding layer 7 can shield the external ambient light incident from the top of the display panel, and prevent this part of the external ambient light from irradiating the channel of the control transistor M0, thereby reducing the influence of the light on the threshold voltage of this part of the control transistor M0, and preventing the threshold of this part of the control transistor M0 from being positively biased. In this way, the reliability of the working state of the control transistor M0 in the control module 6 can be improved, and the influence on the voltage of the first node N1 can be avoided, so that the light-emitting shift circuit 3 can output a stable low level during the light-emitting period, and the accuracy of the light-emitting brightness of the light-emitting element 10 can be improved.

[0047] On the other hand, a large number of metal traces for forming transistors or signal lines are arranged in the circuit layer 2. When the top light-shielding layer 7 is located on the side of the control transistor M0 facing away from the substrate 1, the top light-shielding layer 7 is equivalent to being arranged inside the film layer of the display panel. By making the top light-shielding layer 7 receive a voltage signal, signal transmission can be enabled on the top light-shielding layer 7, thereby avoiding the large area of ​​metal layer without signal added to affect the device electrical properties of the transistor in the circuit layer 2.

[0048] In one possible implementation, see Figure 3 The control module 6 includes a first control module 61, and the control transistor M0 in the first control module 61 includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is electrically connected to the first clock signal line CK, the first electrode of the first transistor M1 is electrically connected to the shift control signal line IN, and the second electrode of the first transistor M1 is electrically connected to the second node N2; the gate and the first electrode of the second transistor M2 are electrically connected to the second node N2 respectively, and the second electrode of the second transistor M2 is electrically connected to the first node N1.

[0049] like Figure 5 As shown, Figure 5 A schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention, the top light shielding layer 7 includes a first top light shielding layer 71, and in a direction perpendicular to the plane where the substrate 1 is located, the first top light shielding layer 71 overlaps with the channel of the second transistor M2.

[0050] The inventors found in the research process that the device performance of the second transistor M2 in the light-emitting shift circuit 3 directly affects the stability of the signal output by the light-emitting shift circuit 3. In combination with the above circuit structure, it can be seen that the gate of the second transistor M2 is electrically connected to the first pole, and at this time, the second transistor M2 is equivalent to a unidirectionally conducting diode. Under ideal conditions, in the light-emitting stage, the shift control signal line IN provides a low potential, the second transistor M2 is normally turned on, and the second transistor M2 transmits the low potential provided by the shift control signal line IN to the first node N1, thereby controlling the first output module 5 to transmit the light-emitting enable voltage (low level) transmitted by the first fixed potential signal line VGL to the light-emitting control signal line Emit.

[0051] However, if the second transistor M2 is affected by the external environment such as light and causes the threshold voltage of the second transistor M2 to drift positively, it will affect the potential written to the first node N1 via the second transistor M2, so that the potential of the first node N1 is raised. After the potential of the first node N1 is raised, the ability of the first output module 5 to output a low level is weakened. At this time, the signal transmitted to the light control signal line Emit by the light-emitting shift circuit 3 generates a small step, so that the output potential is raised to the ideal light-emitting enable voltage. In this way, the light-emitting brightness of the light-emitting element 10 becomes low, or even cannot emit light normally, resulting in the failure of the light-emitting shift circuit 3.

[0052] To this end, in an embodiment of the present invention, by utilizing the first top light-shielding layer 71 to shield the channel of the second transistor M2, the influence of light on the threshold voltage of the second transistor M2 can be reduced, and the threshold of the second transistor M2 can be prevented from being positively biased. In this way, it can be ensured to a greater extent that the light-emitting shift circuit 3 outputs a stable light-emitting enable voltage during the light-emitting period, thereby ensuring the accuracy of the light-emitting brightness of the light-emitting element 10.

[0053] Further, see again Figure 3 and Figure 4 The control transistor M0 in the first control module 61 further includes a third transistor M3, a gate of the third transistor M3 is electrically connected to the second node N2, and a first electrode of the third transistor M3 is electrically connected to the second clock signal line XCK. The first control module 61 further includes a first capacitor C1, a first plate of the first capacitor C1 is electrically connected to the second node N2, and a second plate of the first capacitor C1 is electrically connected to the second electrode of the third transistor M3.

[0054] like Figure 6 As shown, Figure 6 This is a schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention. In a direction perpendicular to the plane where the substrate 1 is located, the first top light shielding layer 71 also overlaps with the channel of the third transistor M3.

[0055] In a conventional light-emitting shift circuit, a voltage-stabilizing capacitor is usually electrically connected directly to the first node N1 to stabilize the voltage of the first node N1. However, in the embodiment of the present invention, the first capacitor C1 is not directly connected to the first node N1, but the overall structure formed by the third transistor M3 and the first capacitor C1 is used to couple the potential of the first node N1 to a lower level during the light-emitting stage, so that the light-emitting enable voltage (low level) transmitted by the first fixed potential signal line VGL has a smaller loss when transmitted through the first output module 5, thereby outputting a lower low potential to the light-emitting control signal line Emit.

[0056] Specifically, the gate of the second transistor M2 is short-circuited with the first electrode, which is equivalent to a unidirectional conducting diode. Due to the presence of the third transistor M3 and the first capacitor C1, the potential of the second node N2 is coupled by the second clock signal. When the potential of the second node N2 is greater than the potential of the first node N1, the second transistor M2 is turned off, and the potential change of the second node N2 will not affect the potential of the first node N1. When the potential of the second node N2 is less than the potential of the first node N1, the second transistor M2 is gradually turned on, and the potential of the first node N1 tends to V N1 +|Vth|, the second transistor M2 keeps the first node N1 at a relatively stable voltage most of the time, but compared with the traditional voltage stabilizing capacitor, the voltage stabilizing ability of the second transistor M2 is not so strong, so when the signal output by the light emitting shift circuit jumps low, the potential of the first node N1 will be coupled to a lower level, and the degree of conduction of the first output module 5 becomes larger, so that the potential output by the light emitting shift circuit to the light emitting control signal line Emit is lower, and the light emitting brightness of the light emitting element 10 is more stable. In the embodiment of the present invention, by making the first top light shielding layer 71 block the channel of the third transistor M3, the device performance of the third transistor M3 can be made more stable, so that when the second clock signal jumps high and low, the potential of the second node N2 will also change accordingly, thereby regulating the conduction state of the second transistor M2.

[0057] In a possible implementation, Figure 7 and Figure 8 As shown, Figure 7 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention is shown in FIG. Figure 8 for Figure 7 In the cross-sectional view along the A1 - A2 direction, the first top light shielding layer 71 is reused as the first electrode plate C11 or the second electrode plate C12 of the first capacitor C1 .

[0058] In combination with the circuit structure of the light-emitting shift circuit 3, it can be known that the second transistor M2 and the first capacitor C1 are connected to each other, and in the layout design of the circuit, the second transistor M2 is also close to the first capacitor C1. In the embodiment of the present invention, while using the first top light-shielding layer 71 to block the external ambient light, by further making the first top light-shielding layer 71 multiplexed as the first electrode plate C11 or the second electrode plate C12 of the first capacitor C1, the lateral space occupied by the first capacitor C1 on one side of the horizontal direction of the second transistor M2 can be reduced, and the layout design can be optimized; or, without increasing the lateral space occupied by the first capacitor C1 on one side of the horizontal direction of the second transistor M2, the area directly facing each other between the two electrodes in the first capacitor C1 can be increased, thereby improving the design flexibility of the capacitance value of the first capacitor C1.

[0059] In a feasible implementation, the first top light shielding layer 71 is electrically connected to the second plate of the first capacitor C1. In the layout design of the circuit, the second transistor M2 is close to the first capacitor C1, and accordingly, the first top light shielding layer 71 is also close to the second plate of the first capacitor C1. Therefore, the first top light shielding layer 71 is electrically connected to the second plate of the first capacitor C1, while ensuring that the voltage signal is transmitted on the first top light shielding layer 71, the length of the connection line electrically connected to the first top light shielding layer 71 can be reduced.

[0060] Alternatively, the first top light shielding layer 71 may also be electrically connected to the second node N2. In the layout design of the circuit, the second transistor M2 is close to the second node N2, and accordingly, the first top light shielding layer 71 is also close to the second node N2, so that the first top light shielding layer 71 is electrically connected to the second node N2 to optimize the layout design. In addition, when the first top light shielding layer 71 is electrically connected to the second node N2, the potential of the first top light shielding layer 71 and the first electrode and gate of the second transistor M2 change synchronously, thereby reducing the influence of the potential jump on the first top light shielding layer 71 on the potential on the first electrode and gate of the second transistor M2.

[0061] In one possible implementation, see Figure 3 and Figure 4 The control module 6 includes a second control module 62, and the control transistor M0 in the second control module 62 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the first clock signal line CK, a first electrode of the fourth transistor M4 is electrically connected to the shift control signal line IN, and a second electrode of the fourth transistor M4 is electrically connected to the first node N1.

[0062] It should be noted that the embodiments of the present invention illustrate Figure 3 and Figure 4 The two structures of the light-emitting shift circuit 3 are compared with Figure 3 The light emitting shift circuit 3 shown, Figure 4 The light-emitting shift circuit 3 shown in the figure adds several normally-on transistors, such as the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16, which are used to stabilize the node voltage. Since these transistors are continuously turned on, they can also be regarded as connecting wiring in structure. In this regard, in the embodiment of the present invention, the second electrode of the fourth transistor M4 is electrically connected to the first node N1, which can be understood as Figure 3 The second electrode of the fourth transistor M4 is directly connected to the first node N1, which can also be understood as Figure 4 A second electrode of the illustrated fourth transistor M4 is connected to the first node N1 via a normally-on sixteenth transistor M16.

[0063] like Fig. 9 As shown, Fig. 9 This is another schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention. The top light shielding layer 7 includes a second top light shielding layer 72. In a direction perpendicular to the plane where the substrate 1 is located, the second top light shielding layer 72 overlaps with a channel of the fourth transistor M4.

[0064] When the shift control signal line IN provides a low level (light-emitting enable level) and the first clock signal line CK provides a low level, the fourth transistor M4 is turned on, and the low level provided by the shift control signal line IN is transmitted to the first node N1, thereby controlling the first output module 5 to output a light-emitting enable voltage. It can be seen that the device performance of the fourth transistor M4 will directly affect the potential of the first node N1, thereby affecting the stability of the light-emitting enable voltage output by the first output module 5. In the embodiment of the present invention, by shielding the channel of the fourth transistor M4 with the second top light-shielding layer 72, the influence of light on the threshold voltage of the fourth transistor M4 can be reduced, and then when the first clock signal line CK provides a low level, the fourth transistor M4 can be turned on to a greater extent, thereby ensuring that the potential of the first node N1 is consistent with the low level provided by the shift control signal line IN.

[0065] It should be noted that see Fig. 9 In the layout design of the light-emitting shift circuit 3, the fourth transistor M4 is close to a first fixed voltage signal line VGL. In the embodiment of the present invention, the second top light-shielding layer 72 can be arranged on the same layer as the first fixed voltage signal line VGL and be interconnected, so that the light-emitting enable voltage (low level) provided by the first fixed voltage signal line VGL is transmitted on the second top light-shielding layer 72.

[0066] In one possible implementation, see Figure 3 and Figure 4The control module 6 includes a third control module 63, and the control transistor M0 in the third control module 63 includes a fifth transistor M5, a gate of the fifth transistor M5 is electrically connected to the first control signal line RST, a first electrode of the fifth transistor M5 is electrically connected to the second fixed potential signal line, and a second electrode of the fifth transistor M5 is electrically connected to the first node N1.

[0067] like Fig.10 As shown, Fig.10 This is another schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention. The top light-shielding layer 7 includes a third top light-shielding layer 73. In a direction perpendicular to the plane where the substrate 1 is located, the third top light-shielding layer 73 overlaps with a channel of the fifth transistor M5.

[0068] In the light-emitting shift circuit 3, the fifth transistor M5 is a transistor for preventing abnormal power failure. Generally, the first control signal line RST continuously provides a high level, the fifth transistor M5 remains cut off, and the high level provided by the second fixed potential signal line charges the parasitic capacitance in the fifth transistor M5. In the event of an abnormal power failure, the fifth transistor M5 can transmit its own storage to the first node N1 to ensure that the first output module 5 cannot output the light-emitting enable level, thereby preventing the light-emitting element 10 from emitting light abnormally. By using the third top light-shielding layer 73 to block the channel of the fifth transistor M5 to prevent the threshold of the fifth transistor M5 from being positively biased, the stability of the working state of the fifth transistor M5 can be ensured, thereby enabling it to play a more reliable anti-power failure function in the light-emitting shift circuit 3.

[0069] It should be noted that see Fig.10 In the layout design of the light-emitting shift circuit 3, the fifth transistor M5 is close to the first control signal line RST. In the embodiment of the present invention, the third top light-shielding layer 73 can be arranged on the same layer as the first control signal line RST and be interconnected, so that the high level provided by the first control signal line RST is transmitted on the third top light-shielding layer 73.

[0070] In one possible implementation, see Figure 3 and Figure 4 The light-emitting shift circuit 3 further includes a first driving module 8, which includes a sixth transistor M6, a seventh transistor M7, and a second capacitor C2. The gate of the sixth transistor M6 and the first electrode plate of the second capacitor C2 are electrically connected to the fourth node N4, respectively, the first electrode of the sixth transistor M6 is electrically connected to the second clock signal line XCK, the second electrode of the sixth transistor M6 is electrically connected to the second electrode plate of the second capacitor C2, the gate of the seventh transistor M7 is electrically connected to the second clock signal line XCK, the first electrode of the seventh transistor M7 is electrically connected to the second electrode of the sixth transistor M6, and the second electrode of the seventh transistor M7 is electrically connected to the third node N3.

[0071] It should be noted that, as mentioned above, Figure 4 The fifteenth transistor M15 shown in the figure is a normally-on transistor, which can also be regarded as a connecting line in structure. Therefore, in the embodiment of the present invention, the gate of the sixth transistor M6 and the first plate of the second capacitor C2 are respectively electrically connected to the fourth node N4, which can be understood as Figure 3 The gate of the sixth transistor M6 and the first plate of the second capacitor C2 are directly connected to the fourth node N4, which can also be understood as Figure 4 The gate of the sixth transistor M6 and the first plate of the second capacitor C2 are connected to the fourth node N4 through the fifteenth transistor M15, respectively.

[0072] The control module 6 includes a fourth control module 64, and the control transistor M0 in the fourth control module 64 includes an eighth transistor M8, a gate of the eighth transistor M8 is electrically connected to the first node N1, a first electrode of the eighth transistor M8 is electrically connected to the first clock signal line CK, and a second electrode of the eighth transistor M8 is electrically connected to the fourth node N4.

[0073] like Fig.11 As shown, Fig.11 This is another schematic diagram of a film layer structure provided by an embodiment of the present invention. The top light shielding layer 7 includes a fourth top light shielding layer 74. In a direction perpendicular to the plane where the substrate 1 is located, the fourth top light shielding layer 74 overlaps with the channel of the eighth transistor M8.

[0074] In order to reduce leakage current, the eighth transistor M8 in the light-emitting shift circuit 3 can be designed as a dual-gate transistor. Since the channel length of the dual-gate transistor is longer, it is more affected by light. In the embodiment of the present invention, by providing the fourth top light-shielding layer 74 to shield the channel of the eighth transistor M8, the stability of the conduction state of the eighth transistor M8 can be improved, thereby improving the stability of the potential of the fourth node N4, and then when the voltage of the fourth node N4 is used to drive the first driving module 8, the stability of the potential output by the first driving module 8 is guaranteed.

[0075] It should be noted that see Fig.11 In the layout design of the light-emitting shift circuit 3, the eighth transistor M8 is close to a first fixed voltage signal line VGL. In the embodiment of the present invention, the fourth top light-shielding layer 74 can be arranged on the same layer as the first fixed voltage signal line VGL and be interconnected, so that the light-emitting enable voltage (low level) provided by the first fixed voltage signal line VGL is transmitted on the fourth top light-shielding layer 74.

[0076] In a feasible implementation, the top shading layer 7 receives a constant voltage signal. At this time, a stable potential is continuously transmitted on the top shading layer 7, which can prevent the potential jump coupling on the top shading layer 7 from affecting the node potential in the light-emitting shift circuit 3.

[0077] For example, see Fig. 9 and Fig.11 The second top light shielding layer 72 and the fourth top light shielding layer 74 are respectively connected to the first fixed voltage signal line VGL, and the second top light shielding layer 72 and the fourth top light shielding layer 74 respectively receive a constant low level.

[0078] In a feasible implementation, the top light shielding layer 7 is electrically connected to the first node N1. In the layout design of the circuit, the portion of the control transistor M0 electrically connected to the first node N1 is relatively close to the first node N1. When the top light shielding layer 7 blocks the channel of the control transistor M0, the top light shielding layer 7 is also relatively close to the first node N1. Therefore, electrically connecting the top light shielding layer 7 to the first node N1 can optimize the layout design. On the other hand, when the top light shielding layer 7 is electrically connected to the first node N1, the potential on the second pole of the top light shielding layer 7 and the first pole or the second pole of the part of the control transistor M0 changes synchronously. For example, the first top light shielding layer 71 is electrically connected to the first node N1, which can also reduce the influence of the potential jump on the first top light shielding layer 71 on the potential on the second pole of the second transistor M2.

[0079] In a possible implementation, Fig.12 and Fig.13 As shown, Fig.12 Another top view of a display panel provided by an embodiment of the present invention, Fig.13 for Fig.12 A cross-sectional view along the B1-B2 direction, the display panel also includes a light-emitting device layer 9, the light-emitting device layer 9 is located on the side of the circuit layer 2 facing away from the substrate 1, the light-emitting device layer 9 includes a plurality of light-emitting elements 10, the light-emitting elements 10 include an anode 11, a light-emitting layer 12 located on the side of the anode 11 facing away from the substrate 1, and a cathode 13 located on the side of the light-emitting layer 12 facing away from the substrate 1. The cathode 13 is electrically connected to the negative power bus PVEE through an auxiliary connection portion 14, and the top light-shielding layer 7 is located between the control transistor M0 and the auxiliary connection portion 14.

[0080] If the top light shielding layer 7 is set on the same layer as the first and second electrodes of the control transistor M0, due to the limitation of the layout space, the horizontal gap between the top metal layer and the first and second electrodes of the control transistor M0 will be very small. At this time, when the external environment enters through the gap between the top metal layer and the first and second electrodes of the control transistor M0, it will cause greater interference. Especially for display panels with camera functions and fingerprint recognition functions, when the top light shielding layer 7 is located in the optical component setting area, the interference caused by the top light shielding layer 7 and other metal wiring will greatly affect the imaging quality and fingerprint recognition accuracy. In the embodiment of the present invention, by setting the top light shielding layer 7 between the control transistor M0 and the auxiliary connection part 14, the top light shielding layer 7 will not be set on the same layer as the metal wiring used to form each transistor in the light-emitting shift circuit 3, thereby effectively improving the interference phenomenon between the metals on the same layer.

[0081] Or, in another feasible implementation, as Fig.14 As shown, Fig.14 for Fig.12 In another cross-sectional view along the B1-B2 direction, the display panel further includes a light-emitting device layer 9, which is located on the side of the circuit layer 2 facing away from the substrate 1. The light-emitting device layer 9 includes a plurality of light-emitting elements 10, and the light-emitting elements 10 include an anode 11, a light-emitting layer 12 located on the side of the anode 11 facing away from the substrate 1, and a cathode 13 located on the side of the light-emitting layer 12 facing away from the substrate 1. The top light-shielding layer 7 is provided on the same layer as the anode 11. At this time, the top light-shielding layer 7 and the anode 11 are formed by the same patterning process, which saves the process flow.

[0082] Furthermore, combined with Fig.12 and Fig.14 The cathode 13 is electrically connected to the negative power bus PVEE through an auxiliary connecting portion 14 , and the top light shielding layer 7 is reused with the auxiliary connecting portion 14 .

[0083] It should be noted that the display panel includes a display area and a non-display area, and the light-emitting shift circuit 3, the negative power bus PVEE and the auxiliary connection part 14 are all arranged in the non-display area. When the top light-shielding layer 7 is reused with the auxiliary connection part 14, at least part of the light-emitting shift circuit 3 overlaps with the auxiliary connection part 14. At this time, the lateral width occupied by the light-emitting shift circuit 3 and the auxiliary connection part 14 in the non-display area can be reduced, which helps to reduce the border width of the non-display area. Moreover, the auxiliary connection part 14 is relatively wide, and can also block the channel of the control transistor M0 to a greater extent.

[0084] Furthermore, if Fig.15 and Fig.16 As shown, Fig.15 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.16A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, wherein the top light-shielding layer 7 includes a plurality of openings 15, and in a direction perpendicular to the plane where the substrate 1 is located, the openings 15 do not overlap with the channel of the control transistor M0, that is, the openings 15 in the top light-shielding layer 7 are arranged so as to avoid the channel of the control transistor M0.

[0085] See also Fig.14 , below the top light-shielding layer 7 is usually a planarization layer 16 formed of an organic material. In the process of the display panel, the planarization layer 16 will decompose water vapor by itself or absorb part of the water vapor. When other film layers are subsequently formed on the planarization layer 16, this part of the water vapor will be released, causing the upper film layer to bulge, and then the problem of film layer detachment occurs. In the embodiment of the present invention, by setting a plurality of openings 15 in the top light-shielding layer 7, these openings 15 can be used to achieve an exhaust effect, so that the water vapor in the planarization layer 16 is effectively released, thereby avoiding the water vapor remaining in the planarization layer 16 and causing subsequent problems such as film layer deformation. At the same time, by making the opening 15 not overlap with the channel of the control transistor M0, the top light-shielding layer 7 can cover the channel of the control transistor M0 to achieve a greater degree of shielding of the channel of the control transistor M0.

[0086] In one possible implementation, see again Figure 3 and Figure 4 The first output module 5 includes a ninth transistor M9, a gate of the ninth transistor M9 is electrically connected to the first node N1, a first electrode of the ninth transistor M9 is electrically connected to the first fixed potential signal line VGL, and a second electrode of the ninth transistor M9 is electrically connected to the light emitting control signal line Emit.

[0087] like Fig.17 As shown, Fig.17 This is a schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention. In a direction perpendicular to the plane where the substrate 1 is located, the top light shielding layer 7 also overlaps with the channel of the ninth transistor M9.

[0088] If the threshold voltage of the ninth transistor M9 drifts, it will affect the conduction degree of the ninth transistor M9, so that the voltage transmitted by the light-emitting shift circuit 3 to the light-emitting control signal line Emit cannot reach the light-emitting enable voltage provided by the first fixed potential signal line VGL, thereby affecting the light-emitting accuracy of the light-emitting element 10. By using the top light-shielding layer 7 to also shield the channel of the ninth transistor M9, the influence of light on the threshold voltage of the ninth transistor M9 can be reduced, and its threshold can be prevented from shifting.

[0089] In one possible implementation, see again Figure 3 and Figure 4The light-emitting shift circuit also includes a second output module 17, which includes a tenth transistor M10, a gate of which is electrically connected to the third node N3, a first electrode of which is electrically connected to the second fixed potential signal line, and a second electrode of which is electrically connected to the light-emitting control signal line Emit.

[0090] See again Fig.17 In a direction perpendicular to the plane where the substrate 1 is located, the top light shielding layer 7 also overlaps with the channel of the tenth transistor M10.

[0091] Among them, the tenth transistor M10 is used to transmit the light-emitting non-enable voltage provided by the second fixed potential signal line to the light-emitting control signal line Emit. If the threshold voltage of the tenth transistor M10 drifts under the influence of light, the tenth transistor M10 will have a reduced degree of conduction or a poor off-state, which will affect the stability of the potential output by the tenth transistor M10. For example, when the light-emitting shift circuit 3 needs to transmit the light-emitting enable voltage to the light-emitting control signal line Emit, if the tenth transistor M10 is not in a good off-state, the second fixed potential signal line will leak to the light-emitting control signal line Emit through the tenth transistor M10, thereby causing the light-emitting shift circuit 3 to be unable to output a stable low level. To this end, the embodiment of the present invention uses the top light-shielding layer 7 to also shield the channel of the tenth transistor M10, thereby reducing the influence of light on the threshold voltage of the tenth transistor M10, thereby preventing its threshold from shifting, and improving the reliability of the working state of the tenth transistor M10.

[0092] It should be noted that see Fig.18 In the layout design of the light-emitting shift circuit 3, the ninth transistor M9 and the tenth transistor M10 are relatively close to a first fixed voltage signal line VGL, and are also relatively close to a second fixed potential signal line VGH. In the embodiment of the present invention, the portion of the top light shielding layer 7 that shields the channels of the ninth transistor M9 and the tenth transistor M10 can be arranged at the same layer as the first fixed voltage signal line VGL or the second fixed potential signal line VGH and are interconnected, so that a low level or a high level is transmitted on this portion of the top light shielding layer 7.

[0093] In a possible implementation, Fig.18 and Fig.19 As shown, Fig.18 is another partial cross-sectional view of a display panel provided by an embodiment of the present invention, Fig.19The present invention is another schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention. The display panel also includes a bottom light-shielding layer 18. The bottom light-shielding layer 18 is located on the side of the control transistor M0 facing the substrate 1. In a direction perpendicular to the plane where the substrate 1 is located, the bottom light-shielding layer 18 overlaps with a channel of at least one control transistor M0. The bottom light-shielding layer 18 is used to block external ambient light incident through the bottom of the display panel, thereby preventing this part of the external ambient light from affecting the threshold voltage of the control transistor M0.

[0094] In one possible implementation, see Figure 3 and Figure 4 The first output module 5 includes a ninth transistor M9, a gate of the ninth transistor M9 is electrically connected to the first node N1, a first electrode of the ninth transistor M9 is electrically connected to the first fixed potential signal line VGL, and a second electrode of the ninth transistor M9 is electrically connected to the light emitting control signal line Emit.

[0095] The light-emitting shift circuit 3 also includes a second output module 17, which includes a tenth transistor M10, a gate of which is electrically connected to the third node N3, a first electrode of which is electrically connected to the second fixed potential signal line, and a second electrode of which is electrically connected to the light-emitting control signal line Emit.

[0096] like Fig. 20 As shown, Fig. 20 This is another partial cross-sectional view of the display panel provided by the embodiment of the present invention. In the direction perpendicular to the plane where the substrate 1 is located, the bottom light shielding layer 18 at least overlaps with the channel of the ninth transistor M9 and / or the tenth transistor M10.

[0097] For the two output tubes, the ninth transistor M9 and the tenth transistor M10, their threshold voltage directly affects the conduction degree of the two transistors when they are turned on, and further affects the stability of the low level or high level output by the light-emitting shift circuit 3. It can be seen from the film structure of the circuit that the area of ​​the ninth transistor M9 and the tenth transistor M10 is relatively large, and its area is much larger than the area of ​​other control transistors. To this end, by setting a bottom light shielding layer 18 under the ninth transistor M9 and the tenth transistor M10, while preferentially using the bottom light shielding layer 18 to reduce the influence of the external ambient light on the device characteristics of the two output tubes, the bottom light shielding layer 18 is far away from other metal wires in the circuit layer 2, so the coupling between the bottom light shielding layer 18 and other signal wires is also small, even after setting a large area of ​​the bottom light shielding layer 18, it will not have a significant impact on the parasitic capacitance.

[0098] Furthermore, the bottom light shielding layer 18 receives a power supply voltage or a ground voltage.

[0099] In addition to being affected by light, the threshold voltage of the transistor is also affected by the friction of the copper rod. The friction of the copper rod causes the substrate 1 to accumulate negative charges, which increases the channel carriers of the transistor, thereby causing the transfer characteristic curve of the transistor to shift and the threshold voltage to be positively biased. By setting the bottom shading layer 18 as a metal shading layer and making it receive the power supply voltage or the ground voltage, the bottom shading layer 18 can also be used to shield the influence of the friction charge on the channel of the control transistor M0, thereby avoiding the positive bias of the threshold voltage of the control transistor M0 to a greater extent.

[0100] In addition, it should be noted that, again, Figure 3 and Figure 4 In the embodiment of the present invention, the light emitting shift circuit may further include an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13.

[0101] The gate of the eleventh transistor M11 is electrically connected to the first clock signal line CK, the first electrode of the eleventh transistor M11 is electrically connected to the first fixed potential signal line VGL, and the second electrode of the eleventh transistor M11 is electrically connected to the second electrode of the eighth transistor M8. The gate of the twelfth transistor M12 is electrically connected to the second electrode of the eleventh transistor M11, the first electrode of the twelfth transistor M12 is electrically connected to the second fixed potential signal line, and the second electrode of the twelfth transistor M12 is electrically connected to the second electrode of the third transistor M3. The gate of the thirteenth transistor M13 is connected to the first node N1, the first electrode of the thirteenth transistor M13 is electrically connected to the second fixed potential signal line, and the second electrode of the thirteenth transistor M13 is electrically connected to the third node N3.

[0102] Combination Figure 3 and Figure 4 ,like Fig.21 As shown, Fig.21 A timing diagram is provided in an embodiment of the present invention. The working process of the light-emitting shift circuit 3 includes a first time period t1 to a fifth time period t5.

[0103] In the first period t1, the shift control signal line IN provides a high level, the first clock signal line CK provides a low level, the second clock signal line XCK provides a high level, the eleventh transistor M11 writes the low level provided by the first fixed potential signal line VGL into the fourth node N4, controls the sixth transistor M6 to be turned on, and the sixth transistor M6 writes the high level provided by the second clock signal line XCK into the gate of the seventh transistor M7, controls the seventh transistor M7 to be turned off, at this time, the third node N3 is at the high level in the previous driving cycle, and controls the tenth transistor M10 to be turned off. The fourth transistor M4 writes the high level provided by the shift control signal line IN into the first node N1, controls the ninth transistor M9 to be turned off, and at this time, the light-emitting shift circuit 3 maintains the high level outputted in the previous driving cycle.

[0104] In the second time period t2, the shift control signal line IN provides a high level, the first clock signal line CK provides a high level, the second clock signal line XCK provides a low level, the seventh transistor M7 is turned on, and the low level of the fourth node N4 is transmitted to the third node N3, and the tenth transistor M10 is controlled to be turned on, and the high level provided by the second fixed potential signal line is transmitted to the light-emitting control signal line Emit.

[0105] In the third period t3, the shift control signal line IN provides a high level, the first clock signal line CK provides a low level, the second clock signal line XCK provides a high level, and the light emitting shift circuit 3 continuously outputs a high level.

[0106] In the fourth period t4, the shift control signal line IN provides a low level, the first clock signal line CK provides a high level, and the second clock signal line XCK provides a low level. Similar to the third period, the light emitting shift circuit 3 continues to be at a high level.

[0107] In the fifth period t5, the shift control signal line IN provides a low level, the first clock signal line CK provides a low level, the second clock signal line XCK provides a high level, the eighth transistor M8 is turned on, writes a level to the fourth node N4, controls the sixth transistor M6 to be turned on, and the sixth transistor M6 writes the high level provided by the second clock signal line XCK into the gate of the seventh transistor M7, and controls the seventh transistor M7 to be turned off. The fourth transistor M4 is turned on, writes the low level provided by the shift control signal line IN into the first node N1, controls the ninth transistor M9 to be turned on, and transmits the low level provided by the first fixed potential signal line VGL to the light emitting control signal line Emit. At the same time, when the output end of the light emitting shift circuit 3 jumps from high to low, the potential of the first node N1 will be pulled lower due to coupling, the ninth transistor M9 will be turned on more completely, and the voltage drop when the low level provided by the first fixed potential signal line VGL is transmitted to the light emitting control signal line Emit via the ninth transistor M9 is smaller, so that the voltage on the light emitting control signal line Emit is closer to the low level provided by the first fixed potential signal line VGL.

[0108] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig. 22 As shown, Fig. 22 1 is a schematic diagram of a structure of a display device provided in an embodiment of the present invention, and the display device includes the above-mentioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above-mentioned embodiment, and will not be repeated here. Fig. 22 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0109] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: It includes a substrate and a circuit layer located on one side of the substrate, wherein the circuit layer includes a light-emitting shift circuit; The light emitting shift circuit comprises: a first output module, the first output module being electrically connected to the first node, the first fixed potential signal line and the light-emitting control signal line respectively, and the first output module being used for transmitting the light-emitting enable voltage provided by the first fixed potential signal line to the light-emitting control signal line in response to the voltage of the first node; at least one control module electrically connected to the first node, the control module comprising one or more control transistors; The display panel also includes a top shading layer, which is located on the side of the control transistor facing away from the substrate. In a direction perpendicular to the plane where the substrate is located, the top shading layer overlaps with a channel of at least one of the control transistors, and the top shading layer receives a voltage signal.

2. The display panel according to claim 1, characterized in that: The control module comprises a first control module, and the control transistor in the first control module comprises a first transistor and a second transistor; wherein the gate of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the shift control signal line, the second electrode of the first transistor is electrically connected to the second node, the gate and the first electrode of the second transistor are electrically connected to the second node respectively, and the second electrode of the second transistor is electrically connected to the first node; The top light shielding layer includes a first top light shielding layer, and in a direction perpendicular to the plane where the substrate is located, the first top light shielding layer overlaps with a channel of the second transistor.

3. The display panel according to claim 2, characterized in that: The control transistor in the first control module further includes a third transistor, a gate of the third transistor is electrically connected to the second node, and a first electrode of the third transistor is electrically connected to the second clock signal line; The first control module further includes a first capacitor, a first plate of the first capacitor is electrically connected to the second node, and a second plate of the first capacitor is electrically connected to the second electrode of the third transistor; In a direction perpendicular to the plane where the substrate is located, the first top light shielding layer also overlaps with the channel of the third transistor.

4. The display panel according to claim 3, characterized in that: The first top light shielding layer is reused as the first plate or the second plate of the first capacitor.

5. The display panel according to claim 3, characterized in that: The first top light shielding layer is electrically connected to the second plate of the first capacitor, or the first top light shielding layer is electrically connected to the second node.

6. The display panel according to claim 1, characterized in that: The control module includes a second control module, the control transistor in the second control module includes a fourth transistor, a gate of the fourth transistor is electrically connected to the first clock signal line, a first electrode of the fourth transistor is electrically connected to the shift control signal line, and a second electrode of the fourth transistor is electrically connected to the first node; The top light-shielding layer includes a second top light-shielding layer, and in a direction perpendicular to the plane where the substrate is located, the second top light-shielding layer overlaps with a channel of the fourth transistor.

7. The display panel according to claim 1, characterized in that: The control module includes a third control module, the control transistor in the third control module includes a fifth transistor, the gate of the fifth transistor is electrically connected to the first control signal line, the first electrode of the fifth transistor is electrically connected to the second fixed potential signal line, and the second electrode of the fifth transistor is electrically connected to the first node; The top light-shielding layer includes a third top light-shielding layer, and in a direction perpendicular to the plane where the substrate is located, the third top light-shielding layer overlaps with a channel of the fifth transistor.

8. The display panel according to claim 1, characterized in that: The light-emitting shift circuit further includes a first driving module, the first driving module includes a sixth transistor, a seventh transistor and a second capacitor, wherein a gate of the sixth transistor and a first plate of the second capacitor are electrically connected to a fourth node respectively, a first electrode of the sixth transistor is electrically connected to a second clock signal line, a second electrode of the sixth transistor is electrically connected to a second plate of the second capacitor, a gate of the seventh transistor is electrically connected to the second clock signal line, a first electrode of the seventh transistor is electrically connected to a second electrode of the sixth transistor, and a second electrode of the seventh transistor is electrically connected to a third node; The control module includes a fourth control module, the control transistor in the fourth control module includes an eighth transistor, the gate of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the first clock signal line, and the second electrode of the eighth transistor is electrically connected to the fourth node; The top light-shielding layer includes a fourth top light-shielding layer, and in a direction perpendicular to the plane where the substrate is located, the fourth top light-shielding layer overlaps with the channel of the eighth transistor.

9. The display panel according to claim 1, characterized in that: The top light shielding layer receives a constant voltage signal.

10. The display panel according to claim 1, characterized in that: The top light shielding layer is electrically connected to the first node.

11. The display panel according to claim 1, characterized in that: The display panel further comprises a light emitting device layer, the light emitting device layer is located on a side of the circuit layer facing away from the substrate, the light emitting device layer comprises an anode, a light emitting layer located on a side of the anode facing away from the substrate, and a cathode located on a side of the light emitting layer facing away from the substrate; The cathode is electrically connected to the negative power bus through an auxiliary connection portion, and the top light shielding layer is located between the control transistor and the auxiliary connection portion.

12. The display panel according to claim 1, characterized in that: The display panel further comprises a light emitting device layer, the light emitting device layer is located on a side of the circuit layer facing away from the substrate, the light emitting device layer comprises an anode, a light emitting layer located on a side of the anode facing away from the substrate, and a cathode located on a side of the light emitting layer facing away from the substrate; The top light shielding layer is arranged on the same layer as the anode.

13. The display panel according to claim 12, characterized in that: The cathode is electrically connected to the negative power bus through an auxiliary connection portion, and the top light shielding layer is reused with the auxiliary connection portion.

14. The display panel according to claim 13, characterized in that: The top light shielding layer includes a plurality of openings, and in a direction perpendicular to the plane where the substrate is located, the openings do not overlap with the channel of the control transistor.

15. The display panel according to claim 1, characterized in that: The first output module includes a ninth transistor, a gate of the ninth transistor is electrically connected to the first node, a first electrode of the ninth transistor is electrically connected to the first fixed potential signal line, and a second electrode of the ninth transistor is electrically connected to the light emitting control signal line; In a direction perpendicular to the plane where the substrate is located, the top light shielding layer also overlaps with the channel of the ninth transistor.

16. The display panel according to claim 1, characterized in that: The light-emitting shift circuit further includes a second output module, the second output module includes a tenth transistor, a gate of the tenth transistor is electrically connected to the third node, a first electrode of the tenth transistor is electrically connected to the second fixed potential signal line, and a second electrode of the tenth transistor is electrically connected to the light-emitting control signal line; In a direction perpendicular to the plane where the substrate is located, the top light shielding layer also overlaps with the channel of the tenth transistor.

17. The display panel according to claim 1, characterized in that: The display panel further includes a bottom light shielding layer, which is located on a side of the control transistor facing the substrate, and overlaps with a channel of at least one of the control transistors in a direction perpendicular to a plane where the substrate is located.

18. The display panel according to claim 17, characterized in that: The first output module includes a ninth transistor, a gate of the ninth transistor is electrically connected to the first node, a first electrode of the ninth transistor is electrically connected to the first fixed potential signal line, and a second electrode of the ninth transistor is electrically connected to the light emitting control signal line; The light-emitting shift circuit further includes a second output module, the second output module includes a tenth transistor, a gate of the tenth transistor is electrically connected to the third node, a first electrode of the tenth transistor is electrically connected to the second fixed potential signal line, and a second electrode of the tenth transistor is electrically connected to the light-emitting control signal line; In a direction perpendicular to the plane where the substrate is located, the bottom light shielding layer also overlaps with a channel of the ninth transistor and / or the tenth transistor.

19. The display panel according to claim 17, characterized in that: The bottom light shielding layer receives a power supply voltage or a ground voltage.

20. A display device, characterized in that: It comprises the display panel as claimed in any one of claims 1 to 19.

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