Devices and methods for error protection in delay control

Abstract

This application relates to apparatus and methods for delay control error protection. Apparatus and methods for correcting codes used for delay adjustment are disclosed. An example method includes providing a bit of a thermometer code in response to at least a shift direction signal; and adjusting the amount of delay in response to the thermometer code. Providing the bit includes correcting the bit using one or more adjacent bits on one side of the bit in the thermometer code and one or more adjacent bits on the other side of the bit in the thermometer code.

Description

Technical Field

[0001] This application relates to an apparatus and method for delay control error protection. Background Technology

[0002] High data reliability, high-speed memory access, low power consumption, and reduced chip size are the characteristics required for semiconductor memories. To achieve high memory access speeds, a clock signal is used as a reference signal to adjust the timing of operations within the semiconductor memory.

[0003] When an external clock signal enters the circuit, the clock phase of the internal clock signal, based on the external clock signal, may be delayed due to the inherent delays of the circuit components. At high operating speeds, distortion of the clock signal duty cycle can adversely affect circuit operation. To accommodate these delay and distortion effects, the clock path may include delay circuitry. Delay circuitry, such as a delay-locked loop (“DLL”), can be used to adjust the clock phase to match the phase of the external clock. A typical DLL may include a coarse delay line providing coarser resolution for delay adjustment and a fine delay line providing finer resolution for delay adjustment. The coarse delay line includes shift register circuitry providing thermometer code representing the delay adjustment. In the thermometer code Q<0:N>, integers from zero to N can be represented by the rightmost bit Q, which is a “1”. <k:n>And (if present) other bit representations as "0", where k is another integer from zero to N. Recently, soft errors, such as bit flips in thermometer codes due to neutron impacts caused by cosmic rays, have been observed. As a countermeasure, a simple thermometer protection has been implemented by flipping the bit representing "0" to the right of the bit representing "1". However, this type of countermeasure is fragile when the bit representing "1" is faulty. To mitigate bit flips, the Double Interlocked Memory Cell Latch (DICE latch) has been introduced. However, the DICE latch has the disadvantages of low speed and weak robustness in terms of metastability. Because operations in coarse delay lines are time-sensitive, the low-speed DICE latch is not suitable for countermeasures in coarse delay lines. Therefore, another countermeasure that can efficiently correct multiple bit flips at high speeds suitable for coarse delay lines is desired. Summary of the Invention

[0004] One aspect of this application relates to a device comprising: an adjustable delay line configured to adjust the amount of delay in response to a thermometer code; and a shift register circuit comprising: a first shift register configured to provide a first bit of the thermometer code; a second shift register configured to provide a second bit of the thermometer code; a third shift register configured to provide a third bit of the thermometer code; and a fourth shift register configured to provide a fourth bit of the thermometer code, wherein the second shift register is configured to receive complementary bits of the first and third bits, and is further configured to provide, based on the shift direction, a second shift register during shift register operation. The first or third bit is used as the second bit, wherein the third shift register is configured to receive the complementary bit of the second and fourth bits, and is further configured to provide the second or fourth bit as the third bit based on the shift direction during shift register operation, wherein the third shift register is further configured to receive the complementary bit of the first bit, wherein the third shift register is configured to provide the first value as the third bit if the first, second and fourth bits are first values ​​during the correction operation, and wherein the third shift register is configured to provide the second value as the third bit if the first, second and fourth bits are second values ​​during the correction operation.

[0005] Another aspect of this application relates to a device comprising: an adjustable delay line configured to adjust the amount of delay in response to a thermometer code; and a shift register configured to provide a bit of a thermometer code in response to two adjacent higher significant bits comprising an immediately adjacent higher significant bit relative to a bit in the thermometer code and an immediately adjacent lower significant bit relative to said bit, wherein the shift register is configured to provide one of the adjacent bits as said bit based on a shift direction in response to a signal being active, wherein the shift register is configured to provide a value in response to a signal being inactive if the two adjacent higher significant bits and the immediately adjacent lower significant bit have the same value.

[0006] Another aspect of this application relates to a method comprising: providing a bit of a thermometer code in response to at least a shift direction signal; and adjusting an amount of delay in response to the thermometer code, wherein providing the bit comprises: correcting the bit using one or more adjacent higher significant bits and one or more adjacent lower significant bits relative to the bit in the thermometer code.

[0007] Another aspect of this application relates to a method comprising: correcting the bit value of a bit included in a thermometer code, the thermometer code further including a more significant bit and a less significant bit relative to the bit, wherein the bit value of the bit is corrected based on at least one more significant bit and at least one less significant bit; providing the thermometer code including the bit with the corrected bit value to an adjustable delay line; and adjusting the delay of the adjustable delay line based on the thermometer code. Attached Figure Description

[0008] Figure 1 This is a schematic block diagram of a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2A This is a block diagram of a DLL circuit in a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2B This is a block diagram of a CDL in a DLL circuit according to an embodiment of the present disclosure.

[0011] Figure 3 This is a flowchart of the calibration operation of the thermometer code according to an embodiment of the present disclosure.

[0012] Figure 4 This is a diagram illustrating the calibration operation of a thermometer code in a DLL circuit according to an embodiment of the present disclosure.

[0013] Figure 5 This is a schematic diagram of a shift register circuit in a DLL circuit according to an embodiment of the present disclosure.

[0014] Figure 6 This is a schematic diagram of a shift register according to an embodiment of the present disclosure.

[0015] Figure 7A This is a schematic diagram of most circuits according to embodiments of the present disclosure.

[0016] Figure 7B This is a schematic diagram of an overwrite latch according to an embodiment of the present disclosure.

[0017] Figure 8A This is a schematic diagram of most circuits according to embodiments of the present disclosure.

[0018] Figure 8B This is a schematic diagram of an overwrite latch according to an embodiment of the present disclosure.

[0019] Figure 9 This is a flowchart of the calibration operation of the thermometer code in the DLL circuit according to an embodiment of the present disclosure.

[0020] Figure 10 This is a diagram illustrating the calibration operation of a thermometer code in a DLL circuit according to an embodiment of the present disclosure.

[0021] Figure 11 This is a schematic diagram of a shift register circuit in a DLL circuit according to an embodiment of the present disclosure.

[0022] Figure 12 This is a schematic diagram of a shift register according to an embodiment of the present disclosure.

[0023] Figure 13A This is a schematic diagram of most circuits according to embodiments of the present disclosure.

[0024] Figure 13B This is a schematic diagram of an overwrite latch according to an embodiment of the present disclosure. Detailed Implementation

[0025] Various embodiments of this disclosure will be explained in detail below with reference to the accompanying drawings. The detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments of this disclosure by means of description. The detailed description is detailed enough to enable those skilled in the art to practice the embodiments of this disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0026] Figure 1 This is a schematic block diagram of a chip 101 of a semiconductor memory device 10 according to an embodiment of the present disclosure. In some embodiments, the semiconductor memory device 10 is a device that may include multiple chips (including chip 101). Chip 101 may include a clock input circuit 105, an internal clock generator 107, a command and address input circuit 11, an address decoder 12, a command decoder 125, multiple row decoders 13, a memory cell array 15 including a sense amplifier 151 and a transmission gate 152, multiple column decoders 14, multiple read / write amplifiers 16, input / output (I / O) circuitry 17, and a voltage generator circuit 19. The semiconductor memory device 10 may include multiple external terminals, including address and command terminals coupled to a command / address bus, clock terminals CK and / or CK, a data terminal DQ, a data strobe terminal DQS, and a data mask terminal DM, and power supply terminals VDD, VSS, VDDQ, and VSSQ.

[0027] The memory cell array 15 includes multiple rows (e.g., rows 0 to 7), each row including multiple word lines WL, multiple bit lines BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. The selection of the word lines WL for each row is performed by the corresponding row decoder 13, and the selection of the bit lines BL is performed by the corresponding column decoder 14. Multiple sense amplifiers SAMP 151 are positioned for their corresponding bit lines BL and coupled to at least one corresponding local I / O line (e.g., LIOT / B), which is further coupled to one of at least two main I / O line pairs (e.g., MIOT / B) via a transmission gate TG 152, which acts as a switch.

[0028] Command and address input circuit 11 can receive address signals and row group address signals from external sources at the command / address terminal via the command / address bus (C / A), and transmit the address signals and row group address signals to address decoder 12. Address decoder 12 can decode the address signals received from command and address input circuit 11 and provide address signal ADD. Address signal ADD may include row address signals to row decoder 13 and column address signals to column decoder 14. Address decoder 12 can also receive row group address signals and provide row group address signals to row decoder 13 and column decoder 14.

[0029] Command and address input circuitry 11 can receive command signals from external sources via the command / address bus at the command / address terminal and provide the command signals to command decoder 125. Command decoder 125 can decode the command signals and generate various internal command signals. For example, internal command signals may include row command signals for selecting word lines and column command signals for selecting bit lines, such as read or write commands.

[0030] Therefore, when an activation command is issued and an activation command is promptly supplied to the row address, and a read command is issued and a read command is promptly supplied to the column address, read data is read from the memory cell specified by the row address and column address in the memory cell array 15. The read / write amplifier 16 can receive the read data and provide it to the I / O circuit 17. The I / O circuit 17 can provide the read data, the data strobe signal at the data strobe terminal DQS, and the data mask signal at the data mask terminal DM to the outside via the data terminal DQ. Similarly, when an activation command is issued and an activation command is promptly supplied to the row address, and a write command is issued and a write command is promptly supplied to the column address, the I / O circuit 17 can receive the write data at the data terminals DQ, DQS, and DM, the data strobe signal at DQS, and the data mask signal at DM, and provide the write data to the memory cell array 15 via the read / write amplifier 16. Therefore, write data can be written to the memory cell specified by the row address and column address.

[0031] Turning to the explanation of external terminals included in semiconductor device 10, clock terminals CK and CKB can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be supplied to clock input circuit 105. Clock input circuit 105 can receive the external clock signal and generate an internal clock signal ICLK. Clock input circuit 105 can provide the internal clock signal ICLK to internal clock generator 107. Internal clock generator 107 can generate a phase-controlled internal clock signal LCLK based on the received internal clock signal ICLK. In some embodiments, DLL circuitry can be used as internal clock generator 107. Internal clock generator 107 can provide the phase-controlled internal clock signal LCLK to IO circuit 17. IO circuit 17 can use the phase-controlled internal clock signal LCLK as a timing signal for determining the output timing of read data.

[0032] The power supply terminals can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be supplied to voltage generator circuit 19. Voltage generator circuit 19 can generate various internal voltages VKK, VARY, VPERI, and the like based on the power supply voltages VDD and VSS. The internal voltage VKK can be used in the line decoder 13, the internal voltage VARY can be used in the sense amplifier 151 included in the memory cell array 15, and the internal voltage VPERI is used in many other circuit blocks. The power supply terminals can also receive power supply voltages VDDQ and VSSQ. I / O circuit 17 can receive power supply voltages VDDQ and VSSQ. For example, power supply voltages VDDQ and VSSQ can be the same voltages as power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used in I / O circuit 17.

[0033] Figure 2A This is a block diagram of a DLL circuit 200 according to an embodiment of the present disclosure. The DLL circuit 200 may be a DLL circuit serving as an internal clock generator 107. The DLL circuit 200 may include a delay line 210 that can generate an internal clock signal LCLK by delaying an internal clock signal PCLK. Here, the internal clock signal PCLK is the output signal of a duty cycle corrector (DCC) 270. The DCC 270 may receive the internal clock signal ICLK from a clock input circuit 105 after receiving external clock signals CK and CKB, and may further receive duty cycle information from a duty cycle detector 250, which detects and corrects the duty cycle of the internal clock LCLK and provides the internal clock signal PCLK. The delay line 210 includes a coarse delay line (CDL) 211 with a coarse (e.g., large) step size for delay adjustment and a fine delay line (FDL) 212 with a fine (e.g., small) step size for delay adjustment and a low resolution, connected in series. The output signal of delay line 210 is provided as an internal clock LCLK. The internal clock LCLK can, for example, be provided to IO circuit 17. The internal clock signal LCLK can be used as... Figure 1 The reference signal is used to control the timing of providing the read data DQ and the data strobe signal DQS.

[0034] The output signal of delay line 210 can also be supplied to replication circuit 220. Replication circuit 220 can represent a delay equivalent to the sum of delays on the clock path, including but not limited to the delay of IO circuit 17 and the delay of clock input circuit 105. The output signal of replication circuit 220 can be provided to phase detector 230 as replication clock signal RCLK. The internal clock signal ICLK from clock input circuit 105 can also be provided to phase detector 230. In semiconductor devices with high-speed memory access, the read data to be provided on data terminal DQ and the data strobe signal at data strobe terminal DQS need to be synchronized with external clock signals CK and CKB. Phase detector 230 can detect the phase difference between replication clock signal RCLK and internal clock signal ICLK reflecting external clock signals CK and CKB, and provide a phase shift signal to delay line control circuit 240. In response to the phase shift signal, delay line control circuit 240 can provide control signals including shift direction control signal, set signal and reset signal to CDL 211 to control the delay of delay line 210. When the phase of the replica clock signal RCLK lags behind the phase of the internal clock signal ICLK, the delay of delay line 210 can be reduced. Conversely, if the phase of the replica clock signal RCLK leads the phase of the internal clock signal ICLK, the delay of delay line 210 can be increased. The delay of delay line 210, such as CDL 211 and FDL 212, can be controlled to lock the phase of the replica clock signal RCLK in sync with the phase of the internal clock signal ICLK. Figure 2B This is a block diagram of CDL 211 in DLL circuit 200 according to an embodiment of the present disclosure. CDL 211 may include shift register circuit 2111 and adjustable delay line 2112. Shift register circuit 2111 may receive shift direction control signals, set signals, and reset signals from delay line control circuit 240. Shift register circuit 2111 may provide coarse delay control code Q<0:N> to adjustable delay line 2112. Coarse delay control code Q<0:N> may be thermometer code. Adjustable delay line 2112 may include a plurality of delay units (not shown) coupled in series. Each of the plurality of delay units may each receive a corresponding bit of the coarse delay control code and may provide an even / odd input clock signal to CDL 212. Here, an odd clock signal may be provided from one of the selected odd numbers of the plurality of delay units, and an even clock signal may be provided from one of the selected even numbers of the plurality of delay units. The odd and even numbers are adjacent numbers. Even / odd input clock signals can have a phase difference relative to each other. The FDL 212 can further receive a set of fine control signals and clock signals in response to the phase shift. The FDL 212 can provide a latching clock signal as an internal clock signal LCLK in response to the even / odd input clock signals and fine control signals. Therefore, the read data and data strobe signals DQS can be synchronized with the external clock signals CK and CKB.

[0035] Figure 3 This is a flowchart of a thermometer code calibration operation 30 according to an embodiment of the present disclosure. In some embodiments, the calibration operation 30 for the thermometer code Q<0:N> (e.g., N is a natural number) can be performed in... Figure 2B In the shift register circuit 2111, the thermometer code Q<0:N> can represent a natural number, where the thermometer code includes one or more rightmost bits with "1" and zero or more leftmost bits with "0". Figure 3 The calibration operation 30 can be performed in the calibration thermometer code Q<0:N> bit Q. <k>The bit value is used relative to bit Q in the thermometer code. <k>(For example, in Q) <k>One or more adjacent higher significant bits (on one side) and bit Q relative to the thermometer code. <k>(For example, in Q) <k>On the other side) one or more lower effective neighboring bits, where k is a natural number less than N. In some embodiments, if three neighboring bits Q<k+2> Q<k+1> and Q <k-1>If it is available, then Figure 3 The calibration operation 30 can use bit Q in the thermometer code. <k>Two adjacent higher significant bits Q on one side<k+2> and Q<k+1> and position Q <k>A neighboring lower significant bit Q on the other side <k-1>If three adjacent bits Q<k+2> Q<k+1> and Q <k-1>If they have the same value (e.g., "1" or "0"), then the same value can be set to bit Q. <k>The correction bit value. In some embodiments, Figure 3 The correction operation 30 in the thermometer code weights one or more adjacent higher significant bits more than one or more adjacent lower significant bits in the thermometer code.

[0036] For example, Figure 3 The correction operation 30 can be performed at the correction bit Q. <k>When using the thermometer code Q<0:N>, the Q value is... <k>The two adjacent bits Q on the right side<k+1> and Q<k+2> (therefore, the more significant bit) and Q <k>The neighboring bit Q on the left <k-1>(Therefore, the lower significant bits). Q <k-1>and Q<k+1> It can be bit Q <k>The adjacent bit. In operation box 31, for each bit Q of the thermometer code Q<0:N>. <k>For each k less than (N-1), a correction operation can be initiated. In operation block 32, neighboring bits, such as Q, can be received and checked. <k-1>Q<k+1> and Q<k+2> If three adjacent bits Q <k-1>Q<k+1> and Q<k+2> If the same value x (e.g., "1" or "0") ("Yes") is present in operation box 33, then bit Q <k>The same value x can be set in operation box 34. Then the operation proceeds from box 34 to operation box 35. If three adjacent bits Q... <k-1>Q<k+1> and Q<k+2> If any of the bits in operation box 33 has a different value ("No"), then the operation proceeds to operation box 35. In operation box 35, the natural number k is decremented by one and the operation proceeds to operation box 36. If the natural number k is not equal to zero, then the operation proceeds to operation box 32, the next lower bit of the thermometer code Q<0:N>. In this example, the next lower bit could be Q.<k'> And the three nearest neighbors are Q.<k'-1> Q<k'+1> and Q<k'+2> In operation box 32, check the three adjacent bits Q.<k'-1> Q<k'+1> and Q<k'+2> And if three adjacent bits Q<k'-1> Q<k'+1> and Q<k'+2> If the values ​​in operation box 33 are the same, then bit Q<k'> In operation box 34, the same value is set. This recursive process is repeated in operation box 36 until the natural number k equals zero. After the natural number k becomes equal to zero in operation box 36, the correction operation for Q<0:N> is complete and a new correction operation for the next thermometer code Q<0:N> can be performed. The iteration of the correction operation continues until Q<0:N> becomes a thermometer code that does not have the bit sequence "10" in the thermometer code. In some embodiments described above, the correction operation 30 is performed from the higher bit to the lower bit (e.g., from Q... <n-2>To Q <1> Bit correction. In other embodiments, it can be performed from the lower bit to the higher bit (e.g., from Q). <1> To Q <n-2>Perform a similar correction operation.

[0037] Figure 4 This is a diagram illustrating the calibration operation of a thermometer code in a DLL circuit according to an embodiment of the present disclosure. In some embodiments, a calibration operation 30 using the thermometer code Q<0:N> (e.g., N is a natural number) can be used, and the natural number N can be seven. Q <0> yes Figure 4 The leftmost bit of the thermometer code instance and Q <n>It is the rightmost position.

[0038] In conversion 41, Q in the thermometer code Q<0:N> <3> The "1" can be converted to "0". When the natural number k equals 3, in Figure 3 Check bit Q in operation box 32 <3> neighboring Q <2> Q <4> and Q <5> Because Q <2> Q <4> and Q <5> All values ​​in operation box 33 are "0", therefore Q <3> You can set it to "0" in operation box 34, regardless of Q. <3> The current value of Q. In another transformation 42, Q <3> The "0" can be converted to "1". When the natural number k equals 3, in Figure 3 Check bit Q in operation box 32 <3> neighboring Q <2> Q <4> and Q <5> Because the neighboring bit Q <2> Q <4> and Q <5> In operation box 33, all values ​​are "1", therefore Q <3> It can be set to "1" in operation box 34, regardless of Q. <3> The current value. In conversion 42, because Q <4> It is "1", therefore Q of conversion 42 is maintained. <2> Instead of setting it to "0", it is set to "1". In another conversion 43, similar to conversion 42, because the adjacent bit Q... <2> Q <4> and Q <5> Both are "1", therefore Q <3> The "0" can be converted to "1" regardless of Q. <3> The current value.

[0039] In another transformation 44, Q <3> The "1" can be converted to "0" in the correction operation of operation box 31. When the natural number k equals 3, in Figure 3 Checking adjacent bits Q in operation box 32 <2> Q <4> and Q <5> Because the neighboring bit Q <2> Q <4> and Q <5> All values ​​in operation box 33 are "0", therefore Q <3> You can set it to "0" in operation box 34, regardless of Q. <3> The current value of Q. The correction operation continues and Q... <1> The "1" can be converted to "0". When the natural number k equals 1, in Figure 3 Checking adjacent bits Q in operation box 32 <0> Q <2> and Q <3> Because the neighboring bit Q <0> Q <2> and Q <3> All values ​​in operation box 33 are "0", therefore Q <1> You can set it to "0" in operation box 34, regardless of Q. <1> The current value.

[0040] In another transformation 45, Q <4> The "0" can be converted to "1" in the correction operation of operation box 31. When the natural number k equals 4, in Figure 3 Checking adjacent bits Q in operation box 32 <3> Q <5> and Q <6> Because the neighboring bit Q <3> Q <5> and Q <6> In operation box 33, all values ​​are "1", Q <4> It can be set to "1" in operation box 34, regardless of Q. <4> The current value of Q. The correction operation continues, and Q... <2> The "0" can be converted to "1". When the natural number k equals 2, in Figure 3 Checking adjacent bits Q in operation box 32 <1> Q <3> and Q <4> Because the neighboring bit Q <1> Q <3> and Q <4> In operation box 33, all values ​​are "1", Q <2> It can be set to "1" in operation box 34, regardless of Q. <2> The current value. As shown in transformations 44 and 45, the correction operation is performed in the iteration until Q<0:N> becomes a thermometer code that does not have the bit sequence "10".

[0041] Figure 5 This is a schematic diagram of a shift register circuit 50 in a DLL circuit according to an embodiment of the present disclosure. In some embodiments, the shift register circuit 50 may include... Figure 2B In the shift register circuit 2111. It should be noted that... Figure 2B The structure of shift register circuit 2111 is not limited to this shift register circuit 50 (51). Shift register circuit 50 may include shift registers 51 (0) to 51 (N). Shift registers 51 (0) to 51 (N) may be coupled in series and receive various control and clock signals. After initialization, shift registers 51 (0) to 51 (N) may be preset to provide all bits of thermometer code Q<0:N>, which are respectively set to "1". In normal operation as a shift register, depending on the direction of shift, shift register 51 (k) may receive as Q from shift register 51 (k-1). <k-1>QF in opposite phase <k-1>The complementary bit and received from shift register 51(k+1) as Q<k+1> QF in opposite phase<k+1> Depending on the shift direction, shift register 51(k) can be used in QF.<k+1> or QF <k-1>After the inversion, Q is provided<k+1> Or Q <k-1>.

[0042] In some embodiments, shift register 51(k) may also receive complementary bit QF from shift register 51(k+2).<k+2> Shift register 51(k) can provide bit Q <k>Q <k>This is a bit of the thermometer code Q<0:N>. Shift register 51(k) can also transfer the complementary bit QF. <k>Shift registers 51(k+1) and 51(k-1) and shifter register 51(k-2) (not shown) are provided. In some embodiments, each of shift registers 51(0) to 51(N) is operable. Figure 3 The correction operation 30. For example, shift register 51(k) can check bit Q in operation block 32. <k-1>Q<k+1> and Q<k+2> Does operation box 33 have the same value x (e.g., "1" or "0")? If bit Q <k-1>Q<k+1> and Q<k+2> If the values ​​are the same, then shift register 51(k) can provide bits Q representing the same value x. <k>.like Figure 5 As shown, these correction operations in the cascaded shift registers 51(0) to 51(N) can be performed continuously and in parallel.

[0043] Figure 6 This is a block diagram of a shift register 60 according to an embodiment of the present disclosure. In some embodiments, shift register 60 may be a shift register 51 of a plurality of shift registers 50. Shift register 60 may include a selector 61, a shift latch 62, a majority circuit 63, and an overwrite latch 64. Selector 61 may begin operation in response to an initialization signal Init. Selector 61 may receive a shift direction control signal indicating the shift direction of bits in thermometer code Q<0:N>. In some embodiments, the shift direction control signal may be generated by... Figure 2A The delay line control circuit 240 is provided. Selector 61 can further receive bits QF from the adjacent shift register. <k-1>and QF<k+1> The adjacent shift register can shift the adjacent bit Q. <k-1>and Q<k+1> Provide the bits Q to the thermometer code Q<0:N> <k>。QF <k-1>and QF<k+1> After each inversion, the next adjacent bit is Q. <k-1>and Q<k+1> The complementary bit. In response to the shift direction control signal, selector 61 can select QF <k-1>or QF<k+1> Provided to shift latch 62. When Q... <k-1>and Q<k+1> When Q is "0" and "1" respectively, <k>It can be set to "0" or "1" depending on the shift direction. For example, if the shift direction is set to the left to increase the thermometer code Q<0:N>, then Q <k>It can be set to Q<k+1> The "1". If the shift direction is set to the right to reduce the thermometer code Q<0:N>, then Q <k>It can be set to Q <k-1>The "0". Shift latch 62 provides normal shift register operation. Shift latch 62 can receive as QF from selector 61. <k-1>or QF<k+1> The shift latch 62 can receive a clock signal CLK and its complementary clock signal CLKF. In response to the clock signal CLK being active, the shift latch 62 can latch bit QF from the selector 61. <k-1>or QF<k+1> The shift latch 62 can latch bit Q after inversion. <k-1>Or Q<k+1> Provided to the overwrite latch 64.

[0044] Most circuits 63 can be derived from a nearby shift register (e.g., Figure 5 The shift registers 51(k-1) and 51(k+1) receive the complementary bit QF. <k-1>and QF<k+1> Most circuits 63 can also draw from another shift register (e.g., Figure 5 The shift register 51(k+2) receives the complementary bit QF.<k+2> Response to complementary bit QF <k-1>QF<k+1> and QF<k+2> Most circuits 63 can provide intermediate signals IntA and IntB.

[0045] The overwrite latch 64 can receive a clock signal CLK and its complementary clock signal CLKF. The overwrite latch 64 can also receive adjacent bits Q from the shift latch 62. <k-1>Or Q<k+1> The overwrite latch 64 can also receive intermediate signals IntA and IntB from the majority circuitry 63. In some embodiments, the overwrite latch 64 can provide Q from the shift latch 62. <k-1>Or Q<k+1> The shift latch 62 performs normal shift register operation in response to the clock signal CLK being active. In some embodiments, the clock signal CLK may be a single-trigger pulse signal. The overwrite latch 64 can perform a correction operation in response to the clock signal CLK being inactive and the complementary clock signal CLKF being active. In some embodiments, in response to the clock signal CLK being inactive and the complementary clock signal CLKF being active, the overwrite latch 64 can provide a correction bit as Q based on intermediate signals IntA and IntB. <k>When QF <k-1>QF<k+1> and QF<k+2> When it is "0", the correction bit Q <k>It can be set to "1". When QF <k-1>QF<k+1> and QF<k+2> When it is "1", the correction bit Q <k>It can be set to "0". When QF <k-1>QF<k+1> and QF<k+2> At the same time, the overwrite latch 64 can provide Q <k>Without correction.

[0046] Figure 7A This is a schematic diagram of a majority circuit 70 according to an embodiment of the present disclosure. In some embodiments, the majority circuit 70 may be... Figure 6 The majority circuit 63. The majority circuit 70 may be a logic circuit. In some embodiments, a logic high ("1") level may be represented by a relatively high voltage (e.g., a positive supply voltage VDD) and a logic low ("0") level may be represented by a relatively low voltage (e.g., a negative supply voltage VSS or ground voltage). For example, the majority circuit 70 may include an inverted logic NOR gate 71 that performs a logical disjunction (e.g., a logic NOR operation) of input signals and an inverted logic NAND gate 72 that performs a logical conjunction (e.g., a logic NAND operation) of input signals. The logic NOR gate 71 and the logic NAND gate 72 may receive complementary bits QF. <k-1>QF<k+1> and QF<k+2> As input signals, logic NOR gate 71 can provide an intermediate signal IntA, and logic NAND gate 72 can provide an intermediate signal IntB. In some embodiments, the intermediate signals IntA and IntB can be... Figure 6 The intermediate signals IntA and IntB are in QF. <k-1>QF<k+1> and QF<k+2> When it is "1", logic NOR gate 71 and logic NAND gate 72 can provide "0" as intermediate signals IntA and IntB. When QF <k-1>QF<k+1> and QF<k+2> When it is "0", logic NOR gate 71 and logic NAND gate 72 can provide "1" as intermediate signals IntA and IntB. If QF <k-1>QF<k+1> and QF<k+2> If any one of them is different from the other two, then logic NOR gate 71 can provide "0" as the intermediate signal IntA and logic NAND gate 72 can provide "1" as the intermediate signal IntB.

[0047] Figure 7B This is a schematic diagram of an overwrite latch 73 according to an embodiment of the present disclosure. In some embodiments, the overwrite latch 73 may be... Figure 6 The overwrite latch 64. The overwrite latch 73 can be a logic circuit. In some embodiments, a logic high ("1") level can be represented by a relatively high voltage (e.g., a positive supply voltage VDD) and a logic low ("0") level can be represented by a relatively low voltage (e.g., a negative supply voltage VSS or ground voltage).

[0048] The overwrite latch 73 may include an inverter 74. In some embodiments, the inverter 74 may be a tri-state (high Z) inverter. The inverter 74 may receive a latch bit Q. <k-1>Or Q<k+1> Inverter 74 can further receive clock signal CLK and its complementary clock signal CLKF. In response to clock signal CLK being active, inverter 74 can provide latch bit Q. <k-1>Or Q<k+1> When the clock signal CLK is inactive and the complementary clock signal CLKF is active, the inverter 74 may not provide any level due to its high impedance state.

[0049] The overwrite latch 73 may include logic circuitry 75. Logic circuitry 75 can perform logic operations in response to the complementary clock signal CLKF being active and the clock signal CLK being inactive. In other words, logic circuitry 75 can be enabled when inverter 74 is disabled, and logic circuitry 75 can be disabled when inverter 74 is enabled. Logic circuitry 75 can receive the output bit Q of the overwrite latch 73. <k>And intermediate signals IntA and IntB. In some embodiments, intermediate signals IntA and IntB may be intermediate signals IntA and IntB from majority circuit 63. In some embodiments, intermediate signals IntA and IntB may be intermediate signals IntA and IntB from majority circuit 70. Logic circuit 75 may include a logic OR gate. The logic OR gate may receive intermediate signal IntA and output bit Q. <k>It can also perform a logical OR operation on the two received signals (e.g., a logical OR operation). Therefore, if the intermediate signal IntA is "1", the logical OR gate can provide "1". If the intermediate signal IntA is "0", the logical OR gate can provide the output bit Q. <k>The logic circuit 75 may further include a logic NAND gate. The logic NAND gate can receive the intermediate signal IntB and the output of the logic OR gate, and can perform a logic NAND operation on these two received signals. Therefore, if the intermediate signal IntA is "1" and the intermediate signal IntB is also "1", then the logic NAND gate can provide "0". If the intermediate signal IntB is "0", then the logic NAND gate can provide "1". If the intermediate signal IntA is "0" and the intermediate signal IntB is "1", then the logic AND gate can provide an inverted output bit QF. <k>The logic circuit 75 may further include an inverter that inverts the output signal of the logic AND gate. Therefore, when the logic circuit is enabled, if Q... <k-1>Q<k+1> and Q<k+2> If it is "1", then logic circuit 75 can provide "1", and if Q <k-1>Q<k+1> and Q<k+2> If Q is "0", then "0" can be provided. <k-1>Q<k+1> and Q<k+2> If any one of the bits differs from the other two, then logic circuit 75 can provide an output bit Q. <k>.

[0050] The overwrite latch 73 may include a logic NAND gate 77. The logic NAND gate 77 may receive a set signal after being inverted by the inverter 76. The logic NAND gate 77 may also receive the output signal of the inverter 74 or the output signal of the logic circuit 75, depending on the state of the clock signal CLK. The logic NAND gate 77 may provide an output bit Q of "1" in response to the set signal being in a state for preset operation. <k>The logic NAND gate 77 can provide Q in response to the clock signal CLK being active.<k+1> Or Q <k-1>When Q is in position <k-1>Q<k+1> and Q<k+2> When the value x is the same, logic NAND gate 77 can provide the same value as Q. <k>The same value x (e.g., "1" or "0"). If bit Q <k-1>Q<k+1> and Q<k+2> If any one of the bits differs from the other two, then logic NAND gate 77 can provide output bit Q as is. <k>The overwrite latch 73 may also include an output bit Q that can be enabled. <k>Inverted and provides complementary bit QF <k>Inverter 78.

[0051] Figure 8A This is a schematic diagram of a majority circuit 80 according to an embodiment of the present disclosure. In some embodiments, the majority circuit 80 may be... Figure 6 The majority circuit 63. The majority circuit 80 may be a logic circuit. In some embodiments, a logic high ("1") level may be represented by a relatively high voltage (e.g., a positive supply voltage VDD) and a logic low ("0") level may be represented by a relatively low voltage (e.g., a negative supply voltage VSS or ground voltage). For example, the majority circuit 80 may include a series-coupled logic NOR gate 81 and an inverter 83, and a series-coupled logic NAND gate 82 and a logic NOR gate 84. The logic NOR gate 81 and the logic NAND gate 82 may receive complementary bits QF. <k-1>QF<k+1> and QF<k+2> 81-bit NOR gate with executable complementary bit QF <k-1>QF<k+1> and QF<k+2> The logic NOR gate 81 can perform a logic NOR operation and provide an output signal. Inverter 83 can receive the output signal from logic NOR gate 81 and invert the output signal to form an intermediate signal IntA. Logic NAND gate 82 can perform complementary bit QF. <k-1>QF<k+1> and QF<k+2> The logic NAND gate 84 can receive a set signal and other output signals as input signals from the logic NAND gate 82. The logic NOR gate 84 can perform a logic NOR operation on the input signals and provide an intermediate signal IntB. In some embodiments, the intermediate signals IntA and IntB can be... Figure 6 The intermediate signals IntA and IntB are in QF. <k-1>QF<k+1> and QF<k+2> When it is "0", most circuits 80 can provide "0" as the intermediate signal IntA and provide the inverted signal of "0" or the set signal as the intermediate signal IntB. When QF <k-1>QF<k+1> and QF<k+2> When it is "1", most circuits 80 can provide "1" as the intermediate signal IntA and provide "1" or the inverted signal of the set signal as the intermediate signal IntB. If QF <k-1>QF<k+1> and QF<k+2> If any one of them is different from the other two, then the majority circuit 80 can provide "1" as the intermediate signal IntA and provide "0" or the inverted signal of the set signal as the intermediate signal IntB.

[0052] Figure 8B This is a schematic diagram of an overwrite latch 85 according to an embodiment of the present disclosure. In some embodiments, the overwrite latch 85 may be... Figure 6 The overwrite latch 64. The overwrite latch 85 may be a logic circuit. In some embodiments, a logic high ("1") level may be represented by a relatively high voltage (e.g., a positive supply voltage VDD) and a logic low ("0") level may be represented by a relatively low voltage (e.g., a negative supply voltage VSS or ground voltage).

[0053] The overwrite latch 85 may include an inverter 86. In some embodiments, the inverter 86 may be a tri-state (high Z) inverter. The inverter 86 may receive a latch bit Q. <k-1>Or Q<k+1> Inverter 86 can further receive clock signal CLK and its complementary clock signal CLKF. In response to clock signal CLK being active, inverter 86 can provide latch bit Q. <k-1>Or Q<k+1> When the clock signal CLK is inactive and the complementary clock signal CLKF is active, the inverter 86 may not provide any level due to its high impedance state.

[0054] The overwrite latch 85 may include logic circuitry 87. Logic circuitry 87 can perform logic operations in response to the complementary clock signal CLKF being active and the clock signal CLK being inactive. In other words, logic circuitry 87 can be enabled when inverter 86 is disabled, and logic circuitry 87 can be disabled when inverter 86 is enabled. Logic circuitry 87 can receive the output bit Q of the overwrite latch 85. <k>And intermediate signals IntA and IntB. In some embodiments, intermediate signals IntA and IntB may be intermediate signals IntA and IntB from majority circuit 63. In some embodiments, intermediate signals IntA and IntB may be intermediate signals IntA and IntB from majority circuit 80. Logic circuit 87 may include a logic OR gate. The logic OR gate may receive a set signal and output bit Q. <k>It can also perform a logical OR operation on these two received signals. Therefore, if a set signal is enabled, the logical OR gate can provide "0". If no set signal is enabled, the logical OR gate can provide an inverted output bit QF. <k>The logic circuit 87 may further include an inverter that inverts the output signal of the logic OR gate. Therefore, when the logic circuit is enabled, if a set signal is activated, the logic circuit 87 can provide a "1", and if no set signal is activated, it can provide a Q. <k>.

[0055] The overwrite latch 85 may include another logic circuit 88. The logic circuit 88 may include a logic AND gate that can receive an intermediate signal IntA and the output signal of the logic circuit 87 and provide an output signal for a logic NAND operation. The logic circuit 88 may provide an output bit Q that is "1" in response to a set signal being in an active state for a preset operation. <k>The logic circuit 88 can provide Q in response to the clock signal CLK being active.<k+1> Or Q <k-1>When Q is in position <k-1>Q<k+1> and Q<k+2> When representing the same value x, logic circuit 88 can provide the same value x (e.g., "1" or "0") as Q. <k>If bit Q <k-1>Q<k+1> and Q<k+2> If any one of the bits differs from the other two and no set signal is activated, then logic circuit 88 can provide output bit Q. <k>There is no change. When the set signal is activated, logic circuit 88 can provide a Q signal set to "1". <k>The overwrite latch 85 may also include an output bit Q that can be enabled. <k>Inverted and provides complementary bit QF <k>The inverter 88.

[0056] Figure 9 This is a flowchart of a thermometer code calibration operation 90 according to an embodiment of the present disclosure. In some embodiments, the calibration operation 90 for the thermometer code Q<0:N> (e.g., N is a natural number) can be performed in... Figure 2B In the shift register circuit 2111, the thermometer code Q<0:N> can represent a natural number, where the thermometer code includes one or more rightmost bits with "1" and zero or more leftmost bits with "0". Figure 9 The calibration operation 90 can be performed in the calibration thermometer code Q<0:N> bit Q. <k>The bit value is used relative to bit Q in the thermometer code. <k>The nearest higher significant bit (e.g., bit Q) <k>(the higher bit on one side) and the bit Q relative to the thermometer code <k>The nearest lower significant bit (e.g., bit Q) <k>The lower digit on the other side), where k is a natural number less than N. For example, Figure 9 The correction operation 90 in the correction bit Q <k>Use the Q in the thermometer code. <k>The two adjacent bits Q on the right side<k+1> and Q<k+2> and Q <k>The two adjacent bits Q on the left <k-1>WaQ <k-2>, where k is a natural number less than (N-1).

[0057] In some embodiments, the correction operation 90 may include two iterations. If two adjacent bits Q <k-1>WaQ <k-2>If it is available, then Figure 9 The first iteration of the correction operation 90 can use bit Q. <k>Two adjacent lower effective (e.g., lower) bits Q <k-1>WaQ <k-2>If four neighboring bits Q <k-1>WaQ <k-2>If two adjacent bits Q have the same predetermined value (e.g., "1"), then... <k-1>WaQ <k-2>The predetermined value can be set to bit Q. <k>The correction bit value. If three adjacent bits Q<k+2> Q<k+1> and Q <k-1>Available, then in Figure 9 In the second iteration of the correction operation 90, bit Q in the thermometer code can be used. <k>Two adjacent higher significant bits Q on one side<k+2> and Q<k+1> and position Q <k>A neighboring lower significant bit Q on the other side <k-1>If three adjacent bits Q<k+2> Q<k+1> and Q <k-1>If they have the same value (e.g., "1" or "0"), then the same value can be set to bit Q. <k>The correction bit value. The above operations are merely examples; in some embodiments, the correction operation may weight one or more adjacent higher significant bits in the thermometer code more than one or more adjacent lower significant bits in the thermometer code, and in another embodiment, the correction operation may weight one or more adjacent lower significant bits in the thermometer code more than one or more adjacent higher significant bits in the thermometer code.

[0058] For example, the first iteration may include Figure 9 Operation boxes 91 to 95. In operation box 91, a calibration operation can be initiated to perform Q for the thermometer code Q<0:N>. <k>Each bit and operation is performed for each natural number k that is equal to or less than (N). In operation box 92, two adjacent data Q are examined. <k-2>WaQ <k-1>If two neighboring data Q <k-2>WaQ <k-1>If they have the same predetermined value, such as "1" in operation box 93 ("Yes"), then Q <k>In operation box 93', set the value to the same predetermined value "1", then proceed to operation box 94. If two adjacent data Q <k-2>WaQ <k-1>If any of the values ​​in the array has a value that is not the predetermined value in operation box 93 ("No"), then the operation proceeds to operation box 94. In either case, k is incremented in operation box 94. In operation box 94, k is incremented by one and the operation proceeds to operation box 95. If k is not less than (N-1) in operation box 95, then the operation returns to operation box 92. Therefore, this recursive process in the first iteration is repeated until the natural number k is equal to the natural number (N-1) in operation box 95. After the natural number k becomes equal to the natural number (N-1) in operation box 95, the correction operation for Q<0:N> proceeds to the second iteration starting from operation box 96.

[0059] The second iteration may include Figure 9 Operation boxes 96 to 100. In operation box 96, a calibration operation can be initiated to perform Q for the thermometer code Q<0:N>. <k>Each bit of the sum is used for operations on each natural number k. In operation box 97, neighboring data, such as Q, can be received and examined. <k-1>Q<k+1> and Q<k+2> If three neighboring data Q <k-1>Q<k+1> and Q<k+2> If the same value x (e.g., "1" or "0") is present in operation box 98 ("Yes"), then the data Q... <k>In operation box 98', the value x can be set to the same value, and then the operation proceeds to operation box 99. If three adjacent data Q... <k-1>Q<k+1> and Q<k+2> If any of the elements in the code has a different value in operation box 98 ("No"), then the operation proceeds to operation box 99. In operation box 99, k is decremented by one and the operation proceeds to operation box 100. If k is greater than zero in operation box ("Yes"), then the operation proceeds to operation box 97. If k is greater than one in operation box 100 ("Yes"), then the operation proceeds to operation box 90. Therefore, this recursive process in the second iteration is repeated until the natural number k equals zero in operation box 100. After the natural number k becomes equal to zero in operation box 100, the correction operation for Q<0:N> has been completed and a new correction operation for the next thermometer code Q<0:N> can be performed by proceeding to operation box 90. This iteration of the correction operation continues until Q<0:N> no longer has the value of Q.<k,k+1> The temperature code continues up to the bit sequence "10". In some embodiments described above, the correction operation 90 is performed from the lower significant (e.g., lower) bit to the higher significant (e.g., higher) bit (e.g., from Q). <2> To Q <n-2>Bit correction. In other embodiments, it can be performed from the higher significant bit to the lower significant bit (e.g., from Q). <n-2>To Q <2> Perform a similar correction operation.

[0060] Figure 10 This is a diagram illustrating the calibration operation of a thermometer code in a DLL circuit according to an embodiment of the present disclosure. In some embodiments, a calibration operation 90 of thermometer code Q<0:N> can be used (e.g., N is a natural number), and the natural number N can be seven. Q <0> yes Figure 10 The leftmost bit of the thermometer code instance and Q <n>It is the rightmost position.

[0061] In conversion 101, Q <3> The "1" can be converted to "0". When the natural number k equals 3, in Figure 9 Check bit Q in operation box 92 <3> neighboring Q <2> Q <4> and Q <5> Because the neighboring bit Q <2> Q <4> and Q <5> All values ​​in operation box 93 are "0", therefore Q <3> You can set it to "0" in operation box 94, regardless of Q. <3> The current value of Q. In other transformations 102 and 103, Q... <3> The "0" can be converted to "1". When the natural number k equals 3, in Figure 9 In operation box 92, check the adjacent bit Q. <2> Q <4> and Q <5> Because Q <2> Q <4> and Q <5> In operation box 93, all values ​​are "1", therefore Q <3> It can be set to "1" in operation box 94, regardless of Q. <3> and Q <1> The current value of Q. In conversion 102, because Q... <4> It is "1", therefore Q of conversion 102 is maintained. <2> The "1".

[0062] In another conversion 104, because the neighboring bit Q <2> Q <4> and Q <5> Both are "0", therefore Q <3> The "1" can be converted to "0" in the first correction operation of operation box 91. When the natural number k equals 3, in Figure 9 In operation box 92, check the adjacent bit Q. <2> Q <4> and Q <5> Because the neighboring bit Q <2> Q <4> and Q <5> In operation box 93, it is "0", therefore Q <3> It can be set to "0" in operation box 93', regardless of Q. <3> The current value of Q. After this correction operation has been performed iteratively in operation box 98 ("Yes") for all natural numbers k in the range between 1 and (N-2), a second correction operation in operation box 91 for the next Q<0:N> of transformation 104 can be performed. In the second correction operation of operation box 91 of transformation 104, Q <1> The "1" can be converted to "0". When the natural number k equals 1, in Figure 9 In operation box 92, check the adjacent bit Q. <0> Q <2> and Q <3> Because Q <0> Q <2> and Q <3> All values ​​in operation box 93 are "0", therefore Q <1> It can be set to "0" in operation box 93', regardless of Q. <1> The current value.

[0063] In another transformation 105, Q <4> The "0" can be converted to "1" in the first correction operation of operation box 91. When the natural number k equals 4, in Figure 9 In operation box 92, check the adjacent bit Q. <3> Q <5> and Q <6> And because of the neighboring Q position <3> Q <5> and Q <6> In operation box 93, all values ​​are "1", therefore Q <4> It can be set to "1" in operation box 93', regardless of Q. <4> The current value of Q. After this correction operation has been performed iteratively in operation box 98 ("Yes") for all natural numbers k in the range between 1 and (N-2), a second correction operation in operation box 91 for the next Q<0:N> of conversion 105 can be performed. In the second correction operation of operation box 91 of conversion 105, Q <2> The "0" can be converted to "1". When the natural number k equals 2 in the second correction operation, in Figure 9 In operation box 92, check the adjacent bit Q. <1> Q <3> and Q <4> Because Q <1> Q <3> and Q <4> In operation box 93, all values ​​are "1", therefore Q <2> It can be set to "1" in operation box 93', regardless of Q. <2> The current value. As shown in transformations 104 and 105, the correction operation is performed in the iteration until Q<0:N> becomes a thermometer code that does not have the bit sequence "10".

[0064] In another transformation 106, Q <4> The "0" can be converted to "1" in the first correction operation of operation box 91. When the natural number k equals 4, in Figure 9 Check Q in operation box 92 <3> Q <5> and Q <6> Because Q <3> and Q <6> It is "1" and Q <5> Since the value is "0", the operation proceeds to operation box 94. Because k equals 4 (greater than one), the operation further proceeds to operation box 95. Figure 9 Further check Q in operation box 95 <2> Because the neighboring bit Q <2> Q <3> Q <6> In operation box 96, all values ​​are "1", therefore Q <4> It can be set to "1" in operation box 96', regardless of Q. <4> The current value and Q <5> The "0". After incrementing k by one in operation box 97, the natural number k is five in operation box 98, which is not equal to six (N-1). Therefore, the operation proceeds to operation box 92, thereby checking bit Q. <5> The three neighboring bits Q <4> Q <6> and Q <7> Because Q <6> and Q <7> Q is "1" and when k is four. <4> Q was previously set to "1", therefore <4> Q <6> and Q <7> In operation box 93, all values ​​are the same, "1". Therefore, Q <5> This can also be set to "1" in operation box 93'. As shown in transformations 104 and 105, the correction operation is performed in the iteration until Q<0:N> becomes no longer a function of Q.<k,k+1> The temperature code ends at the bit sequence "10".

[0065] Figure 11 This is a schematic diagram of a shift register circuit 110 in a DLL circuit according to an embodiment of the present disclosure. In some embodiments, the shift register circuit 110 may include... Figure 2B In the shift register circuit 2111. It should be noted that... Figure 2B The structure of shift register circuit 2111 is not limited to this shift register circuit 110 (111). Shift register circuit 110 may include shift registers 111 (0) to 111 (N). Shift registers 111 (0) to 111 (N) may be coupled in series and receive various control and clock signals. After initialization, shift registers 111 (0) to 111 (N) may be preset to provide all bits of thermometer code Q<0:N> set to "1" respectively. In normal operation as a shift register, depending on the direction of shift, shift register 111 (k) may receive adjacent bits Q from shift register 51 (k-1). <k-1>QF in opposite phase <k-1>The complementary bit is received from shift register 111(k+1) as the adjacent bit Q.<k+1> QF in opposite phase<k+1> Depending on the shift direction, shift register 111(k) can be used in QF.<k+1> or QF <k-1>After the inversion, Q is provided<k+1> Or Q <k-1>.

[0066] In some embodiments, shift register 111(k) may also receive complementary bit QF from shift register 111(k+2).<k+2> And receive another complementary bit QF from shift register 111(k-2) <k-2>Shift register 111(k) can provide bits Q <k>Q <k>This is a bit of the thermometer code Q<0:N>. Shift register 111(k) can also move the complementary bit QF... <k>Provided to shift registers 111(k+2), 111(k+1), 111(k-1), and 111(k-2). In some embodiments, each shift register 51 of shift registers 111(0) to 111(N) is executable. Figure 9 The correction operation is performed at 90. For example, shift register 91(k) can check bit Q in operation block 92. <k-1>Q<k+1> and Q<k+2> Does operation box 93 have the same value x (e.g., "1" or "0")? If bit Q <k-1>Q<k+1> and Q<k+2> If the values ​​are the same, then shift register 111(k) can provide bits Q representing the same value x in operation block 93'. <k>If the neighboring bit Q <k-2> 、Q <k-1>Q<k+1> and Q<k+2> Since most bits are represented as "1" in operation box 96, shift register 111(k) can provide bits Q set to "1" in operation box 96'. <k>.like Figure 11 As shown, these correction operations in the cascaded shift registers 111(0) to 111(N) can be performed continuously and in parallel.

[0067] Figure 12 This is a block diagram of a shift register 120 according to an embodiment of the present disclosure. In some embodiments, shift register 120 may be a shift register 111 of a plurality of shift registers 120. Shift register 120 may include a selector 121, a shift latch 122, a majority circuit 123, and an overwrite latch 124. Selector 121 may begin operation in response to an initialization signal Init. Selector 121 may receive a shift direction control signal indicating the shift direction of bits in thermometer code Q<0:N>. In some embodiments, the shift direction control signal may be generated by... Figure 2A The delay line control circuit 240 is provided. Selector 121 can further receive bits QF from the adjacent shift register. <k-1>and QF<k+1> The adjacent shift register can shift the adjacent bit Q. <k-1>and Q<k+1> Provide the bits Q to the thermometer code Q<0:N> <k>。QF <k-1>and QF<k+1> After each inversion, the next adjacent bit is Q. <k-1>and Q<k+1> The complementary bit. In response to the shift direction control signal, selector 121 can select QF <k-1>or QF<k+1> Provided to shift latch 122. When Q... <k-1>and Q<k+1> When Q is "0" and "1" respectively, <k>It can be set to "0" or "1" depending on the shift direction. For example, if the shift direction is set to the left to increase the thermometer code Q<0:N>, then Q <k>It can be set to Q<k+1> The "1". If the shift direction is set to the right to reduce the thermometer code Q<0:N>, then Q <k>It can be set to Q <k-1>The "0". Shift latch 122 can perform normal shift register operations. Shift latch 122 can receive as QF from selector 121. <k-1>or QF<k+1> The shift latch 122 can receive a clock signal CLK and its complementary clock signal CLKF. In response to the clock signal CLK being active, the shift latch 122 can latch bit QF from the selector 121. <k-1>or QF<k+1> The shift latch 122 can latch bit Q after inversion. <k-1>Or Q<k+1> Provided to overwrite latch 124.

[0068] Most circuits 123 can be derived from a nearby shift register (e.g., Figure 11 The shift registers 111(k-2), 111(k-1), 111(k+1), and 111(k+2) receive complementary neighbor bits QF. <k-2>、QF <k-1>QF<k+1> and QF<k+2> Response to complementary bit QF <k-2>、QF <k-1>QF<k+1> and QF<k+2> Most circuits 123 can provide intermediate signals IntA and IntB.

[0069] The overwrite latch 124 can receive a clock signal CLK and its complementary clock signal CLKF. The overwrite latch 124 can also receive adjacent bits Q from the shift latch 122, which performs normal shift register operations. <k-1>Or Q<k+1> The overwrite latch 124 can also receive intermediate signals IntA and IntB from the majority circuitry 123. In some embodiments, the overwrite latch 124 can provide the adjacent bit Q from the shift latch 62 in response to the clock signal CLK being active. <k-1>Or Q<k+1> Therefore, Q <k>It can depend on the shift direction control signal rather than Q. <k-1>Or Q<k+1> In some embodiments, the clock signal CLK may be a single-trigger pulse signal. The overwrite latch 124 may perform a correction operation in response to the clock signal CLK being inactive and the complementary clock signal CLKF being active. In some embodiments, in response to the clock signal CLK being inactive and the complementary clock signal CLKF being active, the overwrite latch 124 may provide a correction bit as Q based on intermediate signals IntA and IntB. <k>When QF <k-1>QF<k+1> and QF<k+2> When it is "1", the correction bit Q <k>It can be set to "0". When QF <k-1>QF<k+1> and QF<k+2> When it is "0", the correction bit Q <k>It can be set to "1". When QF <k-1>QF<k+1> and QF<k+2> At the same time, if QF <k-2>、QF <k-1>QF<k+1> and QF<k+2> If most of the values ​​are "0", then the overwrite latch 124 can provide "1" as a correction bit Q. <k>Otherwise, the overwrite latch 124 can provide Q. <k>Without correction.

[0070] Figure 13A This is a schematic diagram of a majority circuit 130 according to an embodiment of the present disclosure. In some embodiments, the majority circuit 130 may be... Figure 12 The majority circuit 123. The majority circuit 130 may be a logic circuit. In some embodiments, a logic high ("1") level may be represented by a relatively high voltage (e.g., a positive supply voltage VDD) and a logic low ("0") level may be represented by a relatively low voltage (e.g., a negative supply voltage VSS or ground voltage). In some embodiments, the majority circuit 130 may include a logic NAND gate 131 that performs a logical AND (e.g., a logic NAND operation) on an input signal. The logic NAND gate 131 may receive a neighboring bit QF. <k-1>and QF<k+1> and position Q<k+2> The complementary bit is used as the input signal, and the logic NAND gate 131 can provide the intermediate signal IntA. For example, if the complementary bit QF <k-1>and QF<k+1> and position Q<k+2> If it is "1", then the intermediate signal IntA can be "0". Otherwise, the intermediate signal IntA can be "1".

[0071] In some embodiments, the majority circuit 130 may include logic circuit 133. Logic circuit 133 may receive complementary bit QF. <k-1>and QF<k+1> and position Q<k+2> As an input signal, logic circuit 133 may include logic OR gate 133A. Logic OR gate 133A can receive complementary bit QF. <k-1>and QF<k+1> and position Q<k+2> It can also perform a logical OR operation (e.g., a logical OR operation) on these three received signals. Therefore, if the complementary bit QF <k-1>and QF<k+1> and position Q<k+2> If any of the bits in the OR gate is "1", then the OR gate 133A can provide "1". If the complementary bit QF <k-1>and QF<k+1> and position Q<k+2> If the value is "0", then logic OR gate 133A can provide "0". Logic circuit 133 may further include logic NAND gate 133B. Logic NAND gate 133B can receive the output signal of logic OR gate 133A and provide bit Q. <k-1>WaQ <k-2>The output signal of another logic NAND gate 132 is used for the NAND operation. Logic NAND gate 133B can perform a logic NAND operation on these two received signals. Therefore, if the output signal of logic OR gate 133A is "1" and the output signal of logic NAND gate 132 is "1", then logic NAND gate 133B can provide "0". Otherwise, logic NAND gate 133B can provide "0".

[0072] Figure 13B This is a schematic diagram of an overwrite latch 139 according to an embodiment of the present disclosure. In some embodiments, the overwrite latch 139 may be... Figure 12 The overwrite latch 124. The overwrite latch 139 may be a logic circuit. In some embodiments, a logic high ("1") level may be represented by a relatively high voltage (e.g., a positive supply voltage VDD) and a logic low ("0") level may be represented by a relatively low voltage (e.g., a negative supply voltage VSS or ground voltage).

[0073] The overwrite latch 139 may include an inverter 134. In some embodiments, the inverter 134 may be a tri-state (high Z) inverter. The inverter 134 may receive a latch bit Q. <k-1>Or Q<k+1> Inverter 134 can further receive clock signal CLK and its complementary clock signal CLKF. In response to clock signal CLK being active, inverter 134 can provide latch bit Q. <k-1>Or Q<k+1> When the clock signal CLK is inactive and the complementary clock signal CLKF is active, the inverter 134 may not provide any level due to its high impedance state.

[0074] The overwrite latch 139 may include logic circuitry 135. Logic circuitry 135 can perform logic operations in response to the complementary clock signal CLKF being active and the clock signal CLK being inactive. In other words, logic circuitry 135 can be enabled when inverter 134 is disabled, and logic circuitry 135 can be disabled when inverter 134 is enabled. Logic circuitry 135 can receive the output bit Q of the overwrite latch 139. <k>And intermediate signals IntA and IntB. In some embodiments, intermediate signals IntA and IntB may be intermediate signals IntA and IntB from majority circuit 123. In some embodiments, intermediate signals IntA and IntB may be intermediate signals IntA and IntB from majority circuit 130. Logic circuit 135 may include a logic OR gate. The logic OR gate may receive intermediate signal IntA and output bit Q. <k>It can also perform a logical OR operation on the two received signals (e.g., a logical OR operation). Therefore, if the intermediate signal IntA is "1", the logical OR gate can provide "1". If the intermediate signal IntA is "0", the logical OR gate can provide the output bit Q. <k>The logic circuit 135 may further include a logic NAND gate. The logic NAND gate can receive an intermediate signal IntB and the output of a logic OR gate, and can perform a logic NAND operation on these two received signals. Therefore, if the intermediate signal IntA is "1" and the intermediate signal IntB is also "1", then the logic NAND gate can provide "0". If the intermediate signal IntB is "0", then the logic NAND gate can provide "1". If the intermediate signal IntA is "0" and the intermediate signal IntB is "1", then the logic AND gate can provide an inverted output bit QF. <k>The logic circuit 135 may further include an inverter that inverts the output signal of the logic AND gate. For example, when bit Q... <k-1>Q<k+1> and Q<k+2> When representing the same value x, logic circuit 135 can provide the same value x (e.g., "1" or "0") as Q. <k>Even if Q is a bit <k-1>Q<k+1> and Q<k+2> If any one of the bits in Q is different from the other two, then bit Q <k-2> 、Q <k-1>Q<k+1> and Q<k+2> If all three bits are "1", then logic circuit 135 can provide the value "1". Otherwise, logic circuit 135 can provide the output bit Q as is. <k>.

[0075] The overwrite latch 139 may include a logic NAND gate 137. The logic NAND gate 137 may receive a set signal after being inverted by the inverter 136. The logic NAND gate 137 may also receive the output signal of the inverter 134 or the output signal of the logic circuit 135, depending on the state of the clock signal CLK. The logic NAND gate 137 may provide an output bit Q of "1" in response to the set signal being in a state for preset operation. <k>The logic NAND gate 137 can provide Q in response to the clock signal CLK being active.<k+1> Or Q <k-1>When the set signal and clock signal CLK are inactive, logic NAND gate 137 can provide an output signal from logic circuit 135. For example, when bit Q... <k-1>Q<k+1> and Q<k+2> When representing the same value x, logic NAND gate 137 can provide the same value x (e.g., "1" or "0") as Q. <k>Even if Q is a bit <k-1>Q<k+1> and Q<k+2> If any one of the bits in Q is different from the other two, then bit Q <k-2> 、Q <k-1>Q<k+1> and Q<k+2> If all three bits are "1", then logic NAND gate 137 can provide the value "1". Otherwise, logic NAND gate 137 can provide the output bit Q as is. <k>The overwrite latch 139 may also include an output bit Q that can be enabled. <k>Inverted and provides complementary bit QF <k>Inverter 138.

[0076] Although various embodiments have been disclosed, those skilled in the art will understand that this disclosure extends beyond the specific disclosed embodiments to other alternative embodiments and / or uses of embodiments, as well as obvious modifications and equivalents thereof. Furthermore, other modifications within the scope of this disclosure will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also contemplated and still fall within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for each other to form different modes of the disclosed embodiments. Therefore, it is intended that the scope of at least some of this disclosure should not be limited to the specific disclosed embodiments described above.< / k> < / k> < / k> < / k-2> < / k> < / k> < / k> < / k-2> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k-2> < / k> < / k> < / k> < / k> < / n> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / n> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k:n>

Claims

1. A memory device comprising: An adjustable delay line is configured to receive thermometer codes output from a shift register circuit and adjust the amount of delay in response to the thermometer codes. and The shift register circuit, configured to generate the thermometer code and transmit the thermometer code to the adjustable delay line, includes: A first shift register is configured to provide the first bit of the thermometer code; A second shift register is configured to provide the second bit of the thermometer code; A third shift register, configured to provide the third bit of the thermometer code; and A fourth shift register, configured to provide the fourth bit of the thermometer code, The second shift register is configured to receive complementary bits of the first bit and the third bit, and is further configured to provide either the first bit or the third bit as the second bit based on the shift direction during shift register operation. The third shift register is configured to receive complementary bits of the second bit and the fourth bit, and is further configured to provide either the second bit or the fourth bit as the third bit based on the shift direction during shift register operation. The third shift register is further configured to receive the complementary bit of the first bit. The third shift register is configured to provide the first value as the third bit if the first, second, and fourth bits are first values ​​during the correction operation, and The third shift register is configured to provide the second value as the third bit if the first, second, and fourth bits are second values ​​during the correction operation.

2. The memory device of claim 1, wherein the first and second bits are higher significant bits relative to the third bit in the thermometer code, and The fourth bit is a less significant bit relative to the third bit in the thermometer code.

3. The memory device according to claim 2, The thermometer code represents a natural number containing one or more most significant bits having the first value and zero or more least significant bits having the second value.

4. The memory device of claim 1, wherein the second bit and the fourth bit are adjacent to the third bit, and the first bit is adjacent to the second bit in the thermometer code.

5. The memory device of claim 1, further comprising a fifth shift register configured to provide a fifth bit of the thermometer code. The fourth shift register is configured to receive complementary bits of the third and fifth bits, and is further configured to provide either the third or the fifth bit as the fourth bit during shift register operation. The third shift register is further configured to receive the complementary bit of the fifth bit, and configured to provide the predetermined value as the third bit during the correction operation if the majority of the first, second, fourth, and fifth bits are predetermined values.

6. The memory device according to claim 5, wherein the predetermined value is one.

7. The memory device of claim 5, wherein the first and second bits are higher significant bits relative to the third bit in the thermometer code, and The fourth and fifth bits are less significant bits relative to the third bit in the thermometer code.

8. A memory device comprising: An adjustable delay line is configured to receive thermometer codes provided by a shift register circuit and adjust the amount of delay in response to the thermometer codes. and The shift register circuit is configured to provide bits of the thermometer code in response to two adjacent higher significant bits, the two adjacent higher significant bits comprising the immediately adjacent higher significant bit relative to the bit in the thermometer code and the immediately adjacent lower significant bit relative to the bit. The shift register circuitry is configured to provide one of the immediately adjacent bits as the bit based on a shift direction valid in response to a clock signal. If the two adjacent higher significant bits and the immediately adjacent lower significant bit have the same value, the shift register circuit is configured to provide a value in response to the invalidation of the clock signal.

9. The memory device of claim 8, wherein the shift register circuitry comprises: Most circuits are configured to receive complementary bits of the two higher significant adjacent bits of the bit and complementary bits of the adjacent lower significant bits of the bit, and are further configured to provide first and second intermediate signals. and An overwrite latch is configured to receive the first and second intermediate signals and a complementary clock signal of the clock signal, and is further configured to provide the value in response to the complementary clock signal being active if the two higher significant adjacent bits and the immediately adjacent lower significant bit have the same value.

10. The memory device of claim 9, wherein the plurality of circuits comprises: A logic NOR gate configured to receive the complementary bit relative to the two adjacent higher significant bits of the bit and the complementary bit relative to the adjacent lower significant bit of the bit, configured to perform a logic NOR operation on the received bit and further configured to provide the result of the logic NOR operation as the first intermediate signal. and A logic NAND gate configured to receive the complementary bit relative to the two adjacent higher significant bits of the bit and the complementary bit relative to the adjacent lower significant bit of the bit, configured to perform a logic NAND operation on the received bit and further configured to provide the result of the logic NAND operation as a second intermediate signal.

11. The memory device of claim 10, wherein the write latch comprises: A tri-state inverter configured to receive one of the adjacent bits and further configured to provide a complementary signal of the one of the adjacent bits in response to the clock signal being active; A logic circuit configured to receive the first and second intermediate signals and the bit, and in response to the complementary clock signal being active, further configured to provide a complementary value of the value as an output signal when the two adjacent higher significant bits and the immediately adjacent lower significant bit have the same value, and further configured to provide a complementary bit of the bit as the output signal when any bit of the two adjacent higher significant bits and the immediately adjacent lower significant bit has a value different from the other adjacent bits; and A logic NAND gate configured to receive either the complementary signal of one of the adjacent bits from the tri-state inverter or the output signal from the logic circuit. The logic NAND gate is further configured to provide one of the immediately adjacent bits as the bit in response to the clock signal being active. The logic NAND gate is further configured to provide the value as the bit in response to the complementary clock signal being active when the two adjacent higher significant bits and the immediately adjacent lower significant bit have the same value. The logic NAND gate is further configured to provide the bit in response to the complementary clock signal being active when any one of the two adjacent higher significant bits and the immediately adjacent lower significant bit has a value different from the other adjacent bits.

12. The memory device of claim 10, wherein the majority circuitry further comprises: An inverter configured to receive the result of the logical NOR operation and further configured to provide the inverted version of the result as the first intermediate signal; and A logic NOR gate configured to receive a reset signal and the result of the logic NAND operation, configured to perform a logic NOR operation on the reset signal and the result of the logic NAND operation, and further configured to provide the result of the logic NOR operation on the reset signal and the result of the logic NAND operation as a second intermediate signal.

13. The memory device of claim 12, wherein the write latch comprises: A tri-state inverter configured to receive one of the adjacent bits and further configured to provide a complementary signal of the one of the adjacent bits in response to the clock signal being active; A first logic circuit is configured to receive the bit and the set signal, and is further configured to provide the result of a logic OR operation of the set signal or the bit as an output signal in response to the complementary clock signal being active. and A second logic circuit is configured to receive the first and second intermediate signals and is further configured to receive the complementary signal of one of the adjacent bits from the tri-state inverter or the output signal from the first logic circuit. The second logic circuit is further configured to provide one of the adjacent bits as the bit in response to the clock signal being active. The second logic circuit is further configured to provide the value as the bit in response to the complementary clock signal being active when the two adjacent higher significant bits and the immediately adjacent lower significant bit have the same value. The second logic circuit is further configured to provide the bit in response to the complementary clock signal being active when any one of the two adjacent higher significant bits and the immediately adjacent lower significant bit has a value different from the other adjacent bits.

14. The memory device of claim 9, wherein the shift register circuitry further comprises: A selector configured to receive a complementary bit of the adjacent bit and a shift direction control signal, and further configured to provide one of the complementary bits of the adjacent bit in response to the shift direction control signal; and A shift latch configured to receive one of the complementary bits of the adjacent bit and further configured to provide one of the adjacent bits in response to the clock signal being active.

15. The memory device of claim 9, wherein the shift register circuitry is configured to further provide the bit in response to another adjacent bit, the other adjacent bit being adjacent to the immediately following lower significant bit relative to the bit in the thermometer code. The shift register circuit is configured to provide the predetermined value in response to the signal being inactive, provided that a majority of the two adjacent higher significant bits and the two adjacent lower significant bits have predetermined values. The majority circuitry is further configured to receive the two adjacent higher significant bits and the two adjacent lower significant bits and is further configured to provide the first and second intermediate signals.

16. A method for error protection in delay control, comprising: At least one bit of the thermometer code is provided in response to the shift direction signal; and The amount of delay adjusted in response to the thermometer code. The bits provided include: The bit is corrected using one or more adjacent higher significant bits relative to the bit in the thermometer code and one or more adjacent lower significant bits relative to the bit in the thermometer code.

17. The method of claim 16, wherein correcting the bit comprises: The value is set to the bit if it contains two adjacent bits that have values ​​relative to the bit in the thermometer code, namely the immediately preceding higher significant bit and the immediately preceding lower significant bit.

18. The method of claim 16, wherein correcting the bit comprises: The value is set to the bit if a majority of the bits containing the two adjacent higher significant bits relative to the bit in the thermometer code and the two adjacent lower significant bits relative to the bit have values.

19. The method of claim 16, further comprising: When the clock signal is in the first state, one of the adjacent bits is provided as the bit based on the shift direction signal; and The correction bit is provided when the clock signal is in a second state different from the first state.

20. The method of claim 19, wherein the thermometer code represents a natural number comprising one or more most significant bits having a first value and zero or more least significant bits having a second value.

21. A method for error protection in delay control, comprising: The correction includes the bit value of a bit in a thermometer code, the thermometer code further including a more significant bit and a less significant bit relative to the bit, wherein the bit value of the bit is corrected based on at least one more significant bit and at least one less significant bit. The thermometer code, including the bit with the correction bit value, is provided to the adjustable delay line; and The delay of the adjustable delay line is adjusted based on the thermometer code.

22. The method of claim 21, wherein correcting the bit value of the bit comprises: The bit value is set to the value in response to the fact that the adjacent higher significant bit and the adjacent lower significant bit have values.

23. The method of claim 21, wherein correcting the bit value comprises: The value is set to the bit if a majority of the two adjacent higher significant bits and the two adjacent lower significant bits of the bit in the thermometer code have the value.

24. The method of claim 21, wherein the bit repeats in providing the thermometer code until the thermometer code represents a natural number comprising one or more most significant bits having a first value and zero or more least significant bits having a second value.

25. The method of claim 21, wherein correcting the bit value comprises: The predetermined value is set to the bit if two adjacent lower significant bits in the thermometer code have predetermined values.

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