Multilayer Ceramic Capacitors

Abstract

The laminated ceramic capacitor comprises: a laminated body, in which a plurality of dielectric layers and a plurality of internal electrode layers are laminated; and a pair of external electrodes, which are electrically connected to the internal electrode layers and are formed on two end surfaces of the laminated body. The laminated body comprises: an effective portion; a main surface side outer layer portion, which is located between two main surfaces and the outermost surfaces of the effective portions on the two main surface sides; and an end surface side outer layer portion, which is located between two end surfaces and the outermost surfaces of the effective portions on the two end surface sides. The main surface side outer layer portion comprises a glass layer arranged to be opposite to the effective portion. The glass layer is arranged to overlap with the front ends of the external electrodes arranged on a part of the two main surfaces and a part of the two side portions, and is arranged not to be exposed from the effective portion to the two end surfaces.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] In general, a laminated ceramic capacitor is formed using a ceramic sintered body made of a dielectric ceramic such as barium titanate, and internal electrodes are formed inside the ceramic sintered body so as to overlap each other via a dielectric layer. In addition, an external electrode is formed on one end surface of the ceramic sintered body so as to be electrically connected to the internal electrode, and an external electrode is formed on the other end surface so as to be electrically connected to the internal electrode (for example, refer to Japanese Patent Publication No. 08-306580).

[0003] However, in a laminated ceramic capacitor such as that described in Japanese Patent Publication No. 08-306580, when the laminated ceramic capacitor is mounted on a mounting substrate directly or using solder, the mounting substrate and the ceramic sintered body (laminated body) expand or contract based on their respective thermal expansion coefficients when the temperature changes. Here, due to the difference in thermal expansion coefficients between the two, stress is applied to the ceramic sintered body, and cracks may occur in the ceramic sintered body. In addition, when the crack reaches the internal electrode, a short circuit may occur.

[0004] Furthermore, for example, when a multilayer ceramic capacitor such as that disclosed in Japanese Patent Application Laid-Open No. 08-306580 is used in a mobile device such as a portable phone or a portable music player, there is a possibility that cracks may occur in the ceramic sintered body due to the impact (stress) when the mobile device is dropped, and a short circuit may also occur. Summary of the invention

[0005] Therefore, a main object of the present invention is to provide a multilayer ceramic capacitor that does not suffer from short-circuit failure even when cracks occur in the multilayer body.

[0006] The present invention relates to a laminated ceramic capacitor comprising: a laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and including a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; a first internal electrode layer arranged on the plurality of dielectric layers and exposed at the first end surface; a second internal electrode layer arranged on the plurality of dielectric layers and exposed at the second end surface; a first external electrode connected to the first internal electrode layer and arranged on the first end surface and a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface; and a second external electrode connected to the second internal electrode layer and arranged on the second end surface and a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, wherein the laminate comprises: an effective portion in which a plurality of internal electrode layers are opposite to each other; an outer layer portion on the first main surface side, The outer layer portion on the second main surface side is located on the second main surface side and is formed by a plurality of dielectric layers located between the first main surface and the outermost surface of the effective portion on the first main surface side and an extension line of the outermost surface; the outer layer portion on the first end surface side is located on the first end surface side and is formed by a plurality of dielectric layers located between the first end surface and the outermost surface of the effective portion on the first end surface side; and the outer layer portion on the second end surface side is located on the second end surface side. The present invention is formed of a plurality of dielectric layers located between the second end surface and the outermost surface of the effective portion on the second end surface side, and has, on the first main surface side outer layer portion and the second main surface side outer layer portion, a glass layer arranged on the dielectric layer and arranged to be opposite to the effective portion, the glass layer being arranged to overlap with the front end of the first external electrode and the front end of the second external electrode arranged on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface in a plan view, and the glass layer being arranged not to be exposed on the first end surface and the second end surface from the effective portion side.

[0007] In the multilayer ceramic capacitor according to the present invention, the outer layer portion on the first main surface side and the outer layer portion on the second main surface side have a glass layer disposed on the dielectric layer and disposed to face the effective portion, the glass layer being disposed to overlap with the front end of the first external electrode and the front end of the second external electrode disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface in a plan view, and the glass layer being disposed not to be exposed on the first end surface and the second end surface from the effective portion side, so that the extension of cracks to the effective portion can be suppressed. As a result, the moisture resistance reliability of the multilayer ceramic capacitor can be improved.

[0008] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is a perspective view showing an appearance of an example of a multilayer ceramic capacitor according to an embodiment of the present invention.

[0010] Figure 2 yes Figure 1 Cross-sectional view at line II-II.

[0011] Figure 3 yes Figure 1 Cross-sectional view at line III-III.

[0012] Figure 4A FIG. 1 is a diagram showing a structure in which the opposing electrode portion of the internal electrode layer of the multilayer ceramic capacitor according to the first embodiment of the present invention is divided into two. Figure 1 Cross-sectional view at line II-II.

[0013] Figure 4B The structure of the laminated ceramic capacitor according to the present invention in which the opposing electrode portion of the internal electrode layer is divided into three is shown. Figure 1 Cross-sectional view at line II-II.

[0014] Figure 4C The structure of the laminated ceramic capacitor according to the present invention in which the opposing electrode portion of the internal electrode layer is divided into four Figure 1 Cross-sectional view at line II-II. DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the embodiments described below, the same or common parts are denoted by the same reference numerals in the drawings, and their description will not be repeated.

[0016] 1. Multilayer ceramic capacitors

[0017] A multilayer ceramic capacitor according to a first embodiment of the present invention will be described. Figure 1 FIG. 1 is a perspective view showing an appearance of an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 yes Figure 1 Cross-sectional view at line II-II. Figure 3 yes Figure 1 Cross-sectional view at line III-III. FIG. 4A to FIG. 4C yes Figure 3 An enlarged cross-sectional view of the figure shown.

[0018] like Figures 1 to 3As shown, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped multilayer body 12 and external electrodes 30 disposed at both ends of the multilayer body 12. As described later, the external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0019] The laminate 12 has a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 stacked. Furthermore, the laminate 12 has a first main surface 12a and a second main surface 12b opposite to each other in the height direction x, a first side surface 12c and a second side surface 12d opposite to each other in the width direction y orthogonal to the height direction x, and a first end surface 12e and a second end surface 12f opposite to each other in the length direction z orthogonal to the height direction x and the width direction y. In the laminate 12, the corners and the ridges are rounded. In addition, the so-called corners are the parts where three adjacent faces of the laminate intersect, and the so-called ridges are the parts where two adjacent faces of the laminate intersect. In addition, the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f may be partially or entirely formed with projections and depressions.

[0020] The laminate 12 has an effective portion 18, and the effective portion 18 includes a single or multiple dielectric layers 14c and multiple internal electrode layers 16 arranged thereon. The internal electrode layer 16 includes a first internal electrode layer 16a extending to a first end face 12e and a second internal electrode layer 16b extending to a second end face 12f. In the effective portion 18, multiple first internal electrode layers 16a and second internal electrode layers 16b are opposed to each other via the dielectric layer 14c.

[0021] The stacked body 12 has a first main surface side outer layer portion 20a, which is located on the first main surface 12a side and is formed by a plurality of dielectric layers 14a located between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and a straight line on the outermost surface.

[0022] Similarly, the stack 12 has a second main surface side outer layer portion 20b, which is located on the second main surface 12b side and is formed by a plurality of dielectric layers 14b located between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and a straight line on the outermost surface.

[0023] The laminate 12 has a first side surface side outer layer portion 22a located on the first side surface 12c side and formed of a plurality of dielectric layers 14c located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side.

[0024] Similarly, the laminate 12 has a second side outer layer portion 22b located on the second side 12d side and formed of a plurality of dielectric layers 14c located between the second side 12d and the outermost surface of the inner layer portion 18 on the second side 12d side.

[0025] The laminate 12 has a first end surface side outer layer portion 24a located on the first end surface 12e side and formed of a plurality of dielectric layers 14c located between the first end surface 12e and the outermost surface of the inner layer portion 18 on the first end surface 12e side.

[0026] Similarly, the laminate 12 has a second end surface side outer layer portion 24b, which is located on the second end surface 12f side and is formed of a plurality of dielectric layers 14c located between the second end surface 12f and the outermost surface of the inner layer portion 18 on the second end surface 12f side.

[0027] The first principal surface side outer layer portion 20 a is located on the first principal surface 12 a side of the laminate 12 and is an aggregate of a plurality of dielectric layers 14 a located between the first principal surface 12 a and the internal electrode layer 16 closest to the first principal surface 12 a .

[0028] The second principal surface side outer layer portion 20 b is located on the second principal surface 12 b side of the laminate 12 and is an aggregate of a plurality of dielectric layers 14 b located between the second principal surface 12 b and the internal electrode layer 16 closest to the second principal surface 12 b .

[0029] The dimensions of the laminate 12 are not particularly limited, but preferably the dimension in the longitudinal direction z is 0.2 mm to 10 mm, the dimension in the width direction y is 0.1 mm to 10 mm, and the dimension in the height direction x is 0.1 mm to 5 mm.

[0030] The dielectric layer 14 can be formed of a dielectric material such as a ceramic material. As such a dielectric material, for example, a dielectric material containing BaTiO 3 、CaTiO 3 、SrTiO 3 or CaZrO 3 When the dielectric material mentioned above is included as the main component, a material containing a secondary component such as Mn compound, Fe compound, Cr compound, Co compound, Ni compound, etc. whose content is less than the main component may be used according to the desired properties of the laminate 12.

[0031] The thickness of dielectric layer 14 after firing is preferably 0.5 μm or more and 10 μm or less.

[0032] The glass layer 15 is disposed inside the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b. This will be described in more detail below.

[0033] The first main surface side outer layer portion 20a includes a glass layer 15a, which is disposed on the dielectric layer 14a and disposed opposite to the effective portion 18. The second main surface side outer layer portion 20b includes a glass layer 15b, which is disposed on the dielectric layer 14b and disposed opposite to the effective portion 18. Therefore, in the laminated ceramic capacitor 10 mounted on the mounting substrate, even if a temperature change occurs and stress is applied to the laminated body 12 due to the difference in thermal expansion coefficients between the mounting substrate and the laminated body 12, and cracks are generated in the laminated body 12 itself, the stress can be absorbed by the glass layers 15a and 15b, and the cracks can be suppressed from extending to the internal electrode layer 16 included in the effective portion 18. As a result, short circuit failure can be suppressed.

[0034] The glass layers 15a and 15b are arranged so as to overlap with the front end of the first external electrode 30a and the front end of the second external electrode 30b arranged on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d in a plan view. Therefore, even cracks from the front end of the external electrode 30 can be reliably guided to the glass layers 15a and 15b, wherein stress applied when the mounting substrate on which the multilayer ceramic capacitor 10 is mounted shrinks thermally or the mounting substrate is bent is easily concentrated on the front end of the external electrode 30. As a result, short circuit failure can be suppressed.

[0035] The glass layers 15a and 15b are preferably arranged inside the laminate 12 so that the dimension from the effective portion 18 side is 50% or less of the dimension in the length direction z of the first end surface side outer layer portion 24a and the second end surface side outer layer portion 24b connecting the first end surface 12e and the second end surface 12f. In addition, the length in the length direction z of the glass layers 15a and 15b is arranged inside the laminate 12 with a length equal to or greater than the length in the length direction z of the effective portion 18. In other words, the glass layers 15a and 15b are arranged so as not to be exposed at the first end surface 12e and the second end surface 12f of the laminate 12. Thus, even if cracks are generated and moisture infiltrates from the portion where the cracks are generated, the cracks can be retained inside the glass layers 15a and 15b, and not only that, the moisture can also be retained inside the glass layers 15a and 15b. Therefore, it is possible to suppress moisture from reaching the interface between the laminated body 12 and the external electrode 30, which is a path through which moisture easily penetrates into the effective portion 18. As a result, the moisture resistance reliability of the laminated ceramic capacitor 10 can be maintained.

[0036] Here, the ratio of the dimension of the glass layer 15 from the effective portion 18 side to the dimension of the first end surface side outer layer portion 24a and the second end surface side outer layer portion 24b in the length direction z connecting the first end surface 12e and the second end surface 12f is calculated by the method described below.

[0037] First, in the sample multilayer ceramic capacitor 10, a cross-section is polished along a plane direction parallel to the side surface of the multilayer body 12 to a position that is 1 / 2w of the dimension w in the width direction y of the multilayer body 12 to expose the LT surface of the multilayer ceramic capacitor.

[0038] Next, in the first end surface side outer layer portion 24a, the following points are taken, and their midlines are taken as the extension direction, such as Figure 2 The reference line A1 is drawn out as shown, wherein the above-mentioned points are: a point on the front end of the second internal electrode layer 16b on the side not exposed at the first end face 12e, which is located on the side closest to the first main face 12a; a point on the front end of the second internal electrode layer 16b on the side not exposed at the first end face 12e, which is located at a point 1 / 2t of the dimension t in the height direction x of the stack 12; and a point on the front end of the second internal electrode layer 16b on the side not exposed at the first end face 12e, which is located on the side closest to the second main face 12b.

[0039] Next, take the following points and take their midlines as the extension directions, such as Figure 2 The reference line A2 is drawn out as shown, wherein the above-mentioned points are: the point of the first internal electrode layer 16a exposed at the first end face 12e which is located closest to the first main surface 12a; the point of the first internal electrode layer 16a exposed at the first end face 12e which is located at 1 / 2t of the dimension t in the height direction x of the stack 12; and the point of the first internal electrode layer 16a exposed at the first end face 12e which is located closest to the second main surface 12b.

[0040] Then, the distance between the reference line A1 and the reference line A2 in the direction connecting the first end surface 12e and the second end surface 12f is defined as a distance L1.

[0041] Similarly, in the second end surface side outer layer portion 24b, the following points are taken, and their midlines are taken as the extension direction, such as Figure 2The reference line A3 is drawn out as shown, wherein the above-mentioned points are: a point on the front end of the first internal electrode layer 16a on the side not exposed at the second end face 12f, which is located on the side closest to the first main surface 12a; a point on the front end of the first internal electrode layer 16a on the side not exposed at the second end face 12f, which is located at a point 1 / 2t of the dimension t in the height direction x of the stack 12; and a point on the front end of the first internal electrode layer 16a on the side not exposed at the second end face 12f, which is located on the side closest to the second main surface 12b.

[0042] Next, take the following points and Figure 2 As shown, taking the midline as the extension direction, the reference line A4 is drawn, wherein the above-mentioned points are: the point of the second internal electrode layer 16b exposed on the second end face 12f which is located closest to the first main surface 12a; the point of the second internal electrode layer 16b exposed on the second end face 12f which is located at a position 1 / 2t of the dimension t in the height direction x of the stack 12; and the point of the second internal electrode layer 16b exposed on the second end face 12f which is located closest to the second main surface 12b.

[0043] Then, the distance between the reference line A3 and the reference line A4 in the direction connecting the first end surface 12e and the second end surface 12f is defined as a distance L2.

[0044] Then, L, which is an average value of the distance L1 and the distance L2 measured by the above-mentioned method, is defined as the distance of the first end surface side outer layer portion 24 a and the distance of the second end surface side outer layer portion 24 b , respectively.

[0045] Then, if Figure 2 As shown, in the glass layer 15a located in the outer layer portion 20a on the first main surface side, the distance B1 from the reference line A1 to the end of the glass layer 15a protruding toward the first end surface 12e and the distance B2 from the reference line A3 to the end of the glass layer 15a protruding toward the second end surface 12f are measured.

[0046] Likewise, if Figure 2 As shown, in the glass layer 15b located on the outer layer 20b on the second main surface side, the distance B3 from the reference line A1 to the end of the glass layer 15b protruding toward the first end surface 12e and the distance B4 from the reference line A3 to the end of the glass layer 15b protruding toward the second end surface 12f are measured.

[0047] Then, B, which is the average value of the distances B1 , B2 , B3 , and B4 , is defined as the length of the glass layer 15 protruding from the effective portion 18 .

[0048] Then, using L and B defined as described above, B / L is calculated as the ratio of the dimension of the glass layer 15 from the effective portion 18 side to the dimension of the first end face side outer layer portion 24a and the second end face side outer layer portion 24b in the length direction z connecting the first end face 12e and the second end face 12f, and the ratio is defined as the length ratio of the dimension of the glass layer 15 from the effective portion 18 side to the dimension of the first end face side outer layer portion 24a and the second end face side outer layer portion 24b in the length direction z connecting the first end face 12e and the second end face 12f, and the calculation is performed.

[0049] The glass layers 15a and 15b are arranged inside the laminate 12 so that the dimension from the effective portion 18 side of the first side outer layer portion 22a and the second side outer layer portion 22b does not exceed 50% of the dimension in the width direction y connecting the first side 12c and the second side 12d of the first side outer layer portion 22a and the second side outer layer portion 22b. In addition, the length in the width direction y of the glass layers 15a and 15b is arranged inside the laminate 12 to be equal to or greater than the length in the width direction y of the effective portion 18. In other words, the glass layers 15a and 15b are arranged so as not to be exposed on the first side 12c and the second side 12d of the laminate 12. Thus, even if cracks are generated and moisture infiltrates from the portion where the cracks are generated, the cracks can be retained in the glass layers 15a and 15b, and the moisture can also be retained in the glass layers 15a and 15b. Therefore, it is possible to suppress moisture from reaching the interface between the laminated body 12 and the external electrode 30, which is a path through which moisture easily penetrates into the effective portion 18. As a result, the moisture resistance reliability of the laminated ceramic capacitor 10 can be maintained.

[0050] The thickness of the glass layer 15 in the height direction x connecting the first main surface 12a and the second main surface 12b is preferably 0.2 μm or more and 13 μm or less. If the thickness of the glass layer 15 is in the range of 0.2 μm or more and 13 μm or less, cracks are guided to the glass layer 15 side, and the extension of cracks to the internal electrode layer 16 can be reliably prevented. As a result, short circuit failures inside the stack 12 can be suppressed, and the moisture resistance reliability of the stacked ceramic capacitor 10 can be maintained.

[0051] On the other hand, when the thickness of the glass layer 15 becomes less than 0.2 μm, the effect of absorbing stress (cracks) decreases, and the cracks may reach the internal electrode layer 16 as the effective part 18. In addition, when the thickness of the glass layer 15 becomes greater than 13 μm, the adhesion between the dielectric layers 14 decreases, and structural defects may be easily generated.

[0052] The thickness of the glass layers 15 a and 15 b was measured by the method described below.

[0053] That is, first, in the laminated ceramic capacitor 10, the cross-section is polished along the surface direction parallel to the side surface of the laminate 12 until the position becomes 1 / 2w of the dimension w in the width direction y of the laminate 12, so that the LT surface of the laminated ceramic capacitor 10 is exposed. Next, a SEM image is taken using a scanning electron microscope at the center of the glass layer 15a on the first main surface side outer layer 20a side in the polished cross section. The range of the image at this time is 20μm×15μm, and the magnification is set to 6000 times. The size of the glass layer 15a in the longitudinal direction z contained in this range is divided into 5 points at equal intervals, and the thickness of the glass layer 15a at the position of the 5 points is measured. Furthermore, a SEM image is taken using a scanning electron microscope at the center of the glass layer 15b on the second main surface side outer layer 20b side in the polished cross section. The range of the image at this time is 20μm×15μm, and the magnification is set to 6000 times. The dimension of the glass layer 15b in the longitudinal direction z accommodated in the range is divided into five points at equal intervals, and the thickness of the glass layer 15b at the positions of the five points is measured. Here, the average value of a total of 10 points, which is the five points of the glass layer 15a on the first main surface side outer layer portion 20a and the five points of the glass layer 15b on the second main surface side outer layer portion 20b, is calculated, and this value is used as the thickness of the glass layer 15 of the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b.

[0054] The Vickers hardness of the glass layer 15 is preferably lower than the Vickers hardness of the dielectric layer 14. This can completely suppress cracks from extending to the internal electrode layer 16 disposed in the effective portion 18. As a result, short circuit failures inside the laminate 12 can be suppressed, and the moisture resistance reliability of the laminated ceramic capacitor 10 can be maintained.

[0055] The Vickers hardness of the glass layer 15 is preferably lower than 8 GPa, which is the Vickers hardness of the dielectric layer 14. This can make the effect of the present invention more significant.

[0056] The Vickers hardness of the glass layer 15 is measured by the method described below.

[0057] That is, regarding the Vickers hardness of the glass layer 15, first, in the laminated ceramic capacitor 10, the cross-section is ground to a position that is 1 / 2w of the dimension w in the width direction y of the laminated body 12 along the plane direction parallel to the side surface of the laminated body 12, so that the LT surface of the laminated ceramic capacitor 10 is exposed. Next, a Vickers indenter is pressed against the glass layer 15a using a micro hardness meter at the center of the glass layer 15a on the first main surface side outer layer portion 20a side in the ground cross section, and the Vickers hardness of the glass layer 15a on the first main surface side outer layer portion 20a side is measured. Next, a Vickers indenter is pressed against the glass layer 15b using a micro hardness meter at the center of the glass layer 15b on the second main surface side outer layer portion 20b side in the ground cross section, and the Vickers hardness of the glass layer 15b on the second main surface side outer layer portion 20b side is measured. Here, the average value of the Vickers hardness of glass layer 15 a on the first principal surface side outer layer portion 20 a side and the Vickers hardness of glass layer 15 b on the second principal surface side outer layer portion 20 b side is calculated and this value is taken as the Vickers hardness of glass layer 15 of multilayer ceramic capacitor 10 .

[0058] On the other hand, the Vickers hardness of dielectric layer 14 was measured by the method described below.

[0059] That is, regarding the Vickers hardness of the dielectric layer 14, first, in the laminated ceramic capacitor 10, the cross-section is ground to a position that is 1 / 2w of the dimension w in the width direction y of the laminated body 12 along the plane direction parallel to the side surface of the laminated body 12, so that the LT surface of the laminated ceramic capacitor 10 is exposed. Next, at the center of the first main surface side outer layer portion 20a side in the ground section, a Vickers indenter is pressed against the dielectric layer 14a using a micro hardness tester, and the Vickers hardness of the dielectric layer 14a on the first main surface side outer layer portion 20a side is measured. Next, at the center of the second main surface side outer layer portion 20b side in the ground section, a Vickers indenter is pressed against the dielectric layer 14b using a micro hardness tester, and the Vickers hardness of the dielectric layer 14b on the second main surface side outer layer portion 20b side is measured. Here, the average value of the Vickers hardness of dielectric layer 14 a on the first main surface side outer layer portion 20 a side and the Vickers hardness of dielectric layer 14 b on the second main surface side outer layer portion 20 b side is calculated and this value is taken as the Vickers hardness of dielectric layer 14 of multilayer ceramic capacitor 10 .

[0060] As the glass used for the glass layer 15, any glass such as borosilicate glass, alkali silicate glass, and alkaline earth silicate glass can be used. Among them, glass having a low ion filling rate and containing an alkali metal is particularly preferred. This can reduce the strength of the glass and achieve an effect of easily guiding cracks.

[0061] The laminate 12 includes, for example, a plurality of substantially rectangular first internal electrode layers 16a and a plurality of second internal electrode layers 16b as the plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are buried and alternately arranged at equal intervals with the dielectric layer 14 sandwiched therebetween along the height direction x of the laminate 12.

[0062] The first internal electrode layer 16a includes a first opposing electrode portion 26a and a first lead electrode portion 28a. The first opposing electrode portion 26a is opposed to the second internal electrode layer 16b. The first lead electrode portion 28a is located on one end side of the first internal electrode layer 16a and extends from the first opposing electrode portion 26a to the first end surface 12e of the stacked body 12. The end of the first lead electrode portion 28a is led out to the first end surface 12e and exposed.

[0063] The shape of the first counter electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or may be formed to be inclined (tapered) in a plan view. In addition, the shape may be tapered in a plan view with an inclination toward a certain direction.

[0064] The shape of the first lead electrode portion 28a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or may be formed to be inclined (tapered) in a plan view. In addition, the shape may be tapered in a plan view with an inclination toward a certain direction.

[0065] The width of the first counter electrode portion 26a of the first internal electrode layer 16a and the width of the first lead electrode portion 28a of the first internal electrode layer 16a may be formed to have the same width, or the width of either one may be formed to be narrow.

[0066] The second internal electrode layer 16b includes a second opposing electrode portion 26b and a second lead electrode portion 28b, the second opposing electrode portion 26b being opposed to the first internal electrode layer 16a, and the second lead electrode portion 28b being located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 26b to the second end face 12f of the laminate 12. The end of the second lead electrode portion 28b is led out to the second end face 12f and exposed.

[0067] The shape of the second counter electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or the corners may be formed to be inclined (tapered) in a plan view. In addition, the shape may be tapered in a plan view with an inclination toward a certain direction.

[0068] The shape of the second lead electrode portion 28b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or may be formed to be inclined (tapered) in a plan view. In addition, the shape may be tapered in a plan view with an inclination toward a certain direction.

[0069] The width of the second counter electrode layer 26b of the second internal electrode layer 16b and the width of the second lead electrode portion 28b of the second internal electrode layer 16b may be formed to have the same width, or the width of either one may be formed to be narrow.

[0070] The first internal electrode layer 16 a and the second internal electrode layer 16 b can be formed of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals such as an Ag—Pd alloy.

[0071] The thickness of each of the internal electrode layers 16 , that is, the first internal electrode layer 16 a and the second internal electrode layer 16 b is preferably 0.2 μm or more and 2.0 μm or less.

[0072] Furthermore, the total number of the first internal electrode layers 16 a and the second internal electrode layers 16 b is preferably 15 or more and 200 or less.

[0073] like Figures 1 to 3 As shown in FIG. 1 , external electrodes 30 are arranged on the first end surface 12 e side and the second end surface 12 f side of the stacked body 12 .

[0074] The external electrode 30 includes a base electrode layer 32 and a plating layer 34 formed on the surface of the base electrode layer 32 , and the base electrode layer 32 includes a metal component and a glass component.

[0075] The external electrode 30 includes a first external electrode 30 a and a second external electrode 30 b .

[0076] The first external electrode 30a is connected to the first internal electrode layer 16a and is arranged on the surface of the first end surface 12e. In addition, the first external electrode 30a is also extended from the first end surface 12e and arranged on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead electrode portion 28a of the first internal electrode layer 16a.

[0077] The second external electrode 30b is connected to the second internal electrode layer 16b and is arranged on the surface of the second end surface 12f. In addition, the second external electrode 30b is also extended from the second end surface 12f and arranged on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead electrode portion 28b of the second internal electrode layer 16b.

[0078] In the laminate 12, the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b are opposed to each other via the dielectric layer 14c, thereby forming an electrostatic capacitor. Therefore, an electrostatic capacitor can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0079] In addition, if Figure 4A to Figure 4C As shown, Figure 1 The stacked body 12 shown may also be configured as follows: in addition to the first internal electrode layer 16a and the second internal electrode layer 16b, a floating internal electrode layer 16c not extended to either the first end face 12e or the second end face 12f is provided, and the opposing electrode portion 26c is divided into a plurality of portions by the floating internal electrode layer 16c. Figure 4A The 2 links shown, Figure 4B The 3-link shown, Figure 4C The 4-connected structure shown can of course be a structure with more than 4 connections. In this way, by dividing the opposing electrode portion 26c into a plurality of structures, a plurality of capacitance components are formed between the opposing internal electrode layers 16a, 16b, and 16c, and these capacitance components are connected in series. Therefore, the voltage applied to each capacitance component becomes lower, and the multilayer ceramic capacitor 10 can be made to have a higher withstand voltage.

[0080] The base electrode layer 32 includes at least one selected from a sintered layer and a thin film layer.

[0081] Hereinafter, each structure in the case where the base electrode layer 32 is set as the above-mentioned sintered layer and thin film layer will be described.

[0082] The foundation electrode layer 32 includes a first foundation electrode layer 32 a and a second foundation electrode layer 32 b .

[0083] The first foundation electrode layer 32a is connected to the first internal electrode layer 16a and is arranged on the surface of the first end surface 12e. In addition, the first foundation electrode layer 32a also extends from the first end surface 12e and is arranged on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first foundation electrode layer 32a is electrically connected to the first extraction electrode portion 28a of the first internal electrode layer 16a.

[0084] The second foundation electrode layer 32b is connected to the second internal electrode layer 16b and is arranged on the surface of the second end surface 12f. In addition, the second foundation electrode layer 32b also extends from the second end surface 12f and is arranged on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second foundation electrode layer 32b is electrically connected to the second extraction electrode portion 28b of the second internal electrode layer 16b.

[0085] (In the case of burnt layer)

[0086] The sintered layer contains a glass component and a metal component. The glass component of the sintered layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. As the metal component of the sintered layer, for example, it contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The sintered layer is obtained by applying a conductive paste containing a glass component and a metal component to the stacked body 12 and sintering it. It can be a sintered layer obtained by simultaneously sintering a stacked chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the stacked chip, or it can be a sintered layer obtained by applying a conductive paste to the stacked body 12 and sintering it after the stacked chip having the internal electrode layer 16 and the dielectric layer 14 is sintered to obtain the stacked body 12. In addition, when the laminated chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminated chip are simultaneously fired to obtain a sintered layer, the sintered layer is preferably formed by sintering a conductive paste to which a dielectric material is added instead of a glass component. The sintered layer may also be a plurality of layers.

[0087] The thickness of the first foundation electrode layer 32a located at the center of the first end face 12e in the height direction x in the longitudinal direction z connecting the first end face 12e and the second end face 12f is preferably about 3 μm or more and 160 μm or less, for example.

[0088] The thickness of the second foundation electrode layer 32b located at the center of the second end face 12f in the height direction x in the longitudinal direction z connecting the first end face 12e and the second end face 12f is preferably about 3 μm or more and 160 μm or less, for example.

[0089] In addition, the thickness of the first base electrode layer 32a located at a portion of the first principal surface 12a and the second principal surface 12b in the central portion in the longitudinal direction z connecting the first end surface 12e and the second end surface 12f and in the height direction x connecting the first principal surface 12a and the second principal surface 12b is preferably, for example, about 3 μm or more and 40 μm or less.

[0090] In addition, the thickness of the second base electrode layer 32b located at a portion of the first principal surface 12a and the second principal surface 12b in the central portion in the longitudinal direction z connecting the first end surface 12e and the second end surface 12f, in the height direction x connecting the first principal surface 12a and the second principal surface 12b is preferably, for example, about 3 μm or more and 40 μm or less.

[0091] In addition, the thickness of the first base electrode layer 32a located at a portion of the first side surface 12c and the second side surface 12d at the central portion in the longitudinal direction z connecting the first end surface 12e and the second end surface 12f, and in the width direction y connecting the first side surface 12c and the second side surface 12d is preferably, for example, greater than 3 μm and less than 40 μm.

[0092] In addition, the thickness of the second base electrode layer 32b located at a portion of the first side surface 12c and the second side surface 12d at the central portion in the longitudinal direction z connecting the first end surface 12e and the second end surface 12f, and in the width direction y connecting the first side surface 12c and the second side surface 12d is preferably, for example, greater than 3 μm and less than 40 μm.

[0093] (Thin film layer)

[0094] When the base electrode layer 32 is formed of a thin film layer, the thin film layer is formed by a thin film forming method such as a sputtering method or a vapor deposition method, and is formed by depositing metal particles.

[0095] The plating layer 34 includes a first plating layer 34 a and a second plating layer 34 b .

[0096] The first plating layer 34a and the second plating layer 34b may be formed of a plurality of layers.

[0097] The first plating layer 34a is arranged to cover the first foundation electrode layer 32a.

[0098] The second plating layer 34b is arranged to cover the second foundation electrode layer 32b.

[0099] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0100] The plating layer 34 may also be formed of a plurality of layers. Preferably, it is a two-layer structure of a lower plating layer and an upper plating layer. Preferably, the lower plating layer is formed of a Ni plating layer, and the upper plating layer is formed of a Sn plating layer. The Ni plating layer can prevent the base electrode layer 32 from being corroded by the solder when the multilayer ceramic capacitor 10 is mounted, and the Sn plating layer improves the wettability of the solder when the multilayer ceramic capacitor 10 is mounted, so that the multilayer ceramic capacitor 10 can be easily mounted on the mounting substrate.

[0101] The thickness of each plating layer 34 is preferably 1 μm or more and 15 μm or less.

[0102] Alternatively, the external electrode 30 may be formed only of a plating layer without providing the base electrode layer 32 .

[0103] Hereinafter, a structure in which the base electrode layer 32 is not provided but the plating layer is provided will be described.

[0104] The first external electrode 30a and the second external electrode 30b may each be provided with a plated layer directly formed on the surface of the laminate 12 without providing the base electrode layer 32. That is, the laminated ceramic capacitor 10 may also have a structure including a plated layer directly electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. In such a case, the plated layer may be formed after a catalyst is arranged on the surface of the laminate 12 as a pretreatment.

[0105] In addition, when the base electrode layer 32 is not provided and the plating layer is directly formed on the stack 12, the amount of reduction in the thickness of the base electrode layer 32 can be converted into a lower height, that is, thinning, or converted into the thickness of the stack 12, that is, the thickness of the effective part 18, thereby improving the design freedom of the thin chip.

[0106] The plating layer preferably includes a lower plating electrode formed on the surface of the laminate 12 and an upper plating electrode formed on the surface of the lower plating electrode.

[0107] The lower plated electrode and the upper plated electrode each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing the metal.

[0108] The lower-layer plated electrode is preferably formed using Ni having a solder barrier property, and the upper-layer plated electrode is preferably formed using Sn or Au having good solder wettability.

[0109] In addition, for example, when Ni is used to form the first internal electrode layer 16a and the second internal electrode layer 16b, the base plated electrode is preferably formed using Cu having good bonding properties with Ni. In addition, the upper plated electrode can be formed as needed, and the first external electrode 30a and the second external electrode 30b can each be composed of only the lower plated electrode.

[0110] The plating layer may have an upper plating electrode as the outermost layer, or another plating electrode may be further formed on the surface of the upper plating electrode.

[0111] The thickness of the plating is preferably 1 μm or more and 15 μm or less.

[0112] The plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99 volume % or more.

[0113] The dimension of the multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a and the second external electrode 30b in the length direction z is set to L dimension, the dimension of the multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a and the second external electrode 30b in the height direction x is set to T dimension, and the dimension of the multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a and the second external electrode 30b in the width direction y is set to W dimension.

[0114] Regarding the dimensions of the multilayer ceramic capacitor 10, the L dimension in the length direction z is greater than or equal to 0.2 mm and less than or equal to 10.0 mm, the W dimension in the width direction y is greater than or equal to 0.1 mm and less than or equal to 5.0 mm, and the T dimension in the height direction x is greater than or equal to 0.05 mm and less than or equal to 5.0 mm. In addition, the dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0115] exist Figure 1 In the illustrated multilayer ceramic capacitor 10, the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b have a glass layer 15, the glass layer 15 is disposed on the dielectric layer 14 and disposed so as to face the effective portion 18, the glass layer 15 is disposed so as to overlap with the front end of the first external electrode 30a and the front end of the second external electrode 30b disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d in a plan view, and is disposed so as not to be exposed from the effective portion 18 side to the first end surface 12e and the second end surface 12f, so that the extension of cracks to the effective portion 18 can be suppressed. As a result, the moisture resistance reliability of the multilayer ceramic capacitor 10 can be improved.

[0116] 2. Manufacturing method of multilayer ceramic capacitor

[0117] Next, a method for manufacturing a multilayer ceramic capacitor will be described.

[0118] First, a dielectric sheet for a dielectric layer and a conductive paste for an internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0119] Then, conductive paste for the internal electrode layer is printed in a predetermined pattern on the dielectric sheet by screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern of the first internal electrode layer and a dielectric sheet having a pattern of the second internal electrode layer are prepared.

[0120] In addition, a glass paste is printed on the dielectric sheet in a given pattern by, for example, screen printing or gravure printing. Thus, a dielectric sheet having a pattern of a glass layer is prepared. The thickness of the glass layer can be controlled by changing the thickness of the printing plate. In addition, the hardness of the glass layer can be controlled by changing the glass composition ratio. Furthermore, a dielectric sheet for an outer layer on which the pattern of the internal electrode layer is not printed is also prepared for the dielectric sheet.

[0121] Next, a portion of the second main surface side outer layer portion is formed by stacking a predetermined number of dielectric sheets for the outer layer on which the pattern of the internal electrode layer is not printed. Here, when forming the portion of the second main surface side outer layer portion, a dielectric sheet with a pattern of a glass layer is stacked at an arbitrary position where the glass layer is desired to be set, thereby forming a glass layer in the second main surface side outer layer portion. Then, a dielectric sheet with a pattern of the first internal electrode layer printed and a dielectric sheet with a pattern of the second internal electrode layer printed are sequentially stacked on the portion of the second main surface side outer layer portion to form the structure of the present invention, thereby forming a portion of the effective portion. A predetermined number of dielectric sheets for the outer layer on which the pattern of the internal electrode layer is not formed are stacked on the portion of the effective portion, thereby forming a portion of the first main surface side outer layer portion. Here, when forming the portion of the first main surface side outer layer portion, a dielectric sheet with a pattern of a glass layer is stacked at an arbitrary position where the glass layer is desired to be set, thereby forming a glass layer in the first main surface side outer layer portion. In this way, a laminated sheet having a glass layer was produced.

[0122] Next, the laminated sheets are pressed in the laminating direction by isostatic pressing or the like, thereby producing a laminated block.

[0123] Then, the stacked block is cut into a predetermined size to form stacked chips. At this time, the corners and ridges of the stacked chips may be rounded by barrel grinding or the like.

[0124] Next, the laminated chips are fired to produce the laminated body 12. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode layer 16, but is preferably 900°C or higher and 1400°C or lower.

[0125] Next, a conductive paste that becomes a base electrode layer is applied to both end faces of the laminate. In the present embodiment, the base electrode layer is a sintered layer. The conductive paste containing a glass component and a metal is applied to the laminate by, for example, a dipping method. Then, a sintering treatment is performed to form a base electrode layer. The temperature of the sintering treatment at this time is preferably above 700°C and below 900°C.

[0126] When the base electrode layer is formed of a thin film layer, the base electrode layer can be formed by a thin film forming method such as sputtering or vapor deposition. The base electrode layer formed of a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0127] Next, a plating layer is formed. In addition, the plating layer can be formed on the surface of the base electrode layer or directly on the laminate. In this embodiment, the plating layer is formed on the surface of the base electrode layer. In more detail, a Ni plating layer and a Sn plating layer are formed on the base electrode layer. The Ni plating layer and the Sn plating layer are sequentially formed, for example, by a drum plating method.

[0128] On the other hand, the base electrode layer may not be provided but the plating layer may be provided on the exposed portion of the internal electrode layer of the laminate. In this case, the plating layer can be formed by the following method.

[0129] That is, a plating process is applied to the first end face and the second end face of the laminate, thereby forming a lower layer plating electrode on the exposed portion of the internal electrode layer. When performing the plating process, either electrolytic plating or electroless plating can be used. However, electroless plating requires a pretreatment using a catalyst or the like in order to increase the plating deposition speed, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferably used. In addition, as required, an upper layer plating electrode formed on the surface of the lower layer plating electrode can also be formed in the same manner.

[0130] As described above, the multilayer ceramic capacitor 10 according to the present embodiment is manufactured.

[0131] 3. Experimental Example 1

[0132] The laminated ceramic capacitor was produced according to the above manufacturing method and evaluated by confirming the presence of cracks in the non-directional laminate and by humidity resistance reliability test. The evaluation based on the presence of cracks in the non-directional laminate was performed by confirming the presence of cracks in the internal direction of the non-directional laminate and the presence of cracks in the non-directional effective part.

[0133] (a) Specifications of samples of the embodiment

[0134] As an example, a laminated ceramic capacitor of the following specifications was prepared. The samples of Examples 1 to 8 prepared were samples in which the length of the glass layer in the longitudinal direction z was changed as shown in Table 1. More specifically, the length ratio of the dimension of the glass layer from the effective portion side to the dimension of the outer layer portion on the first end face side and the outer layer portion on the second end face side connecting the first end face and the second end face in the longitudinal direction z was changed.

[0135] Dimensions of multilayer ceramic capacitors (design values): L×W×T=1.0mm×0.5mm×0.5mm

[0136] Specifications of dielectric layer

[0137] Main component material of dielectric layer: BaTiO 3

[0138] · Layer thickness of dielectric layer: 1.5 μm

[0139] Vickers hardness of dielectric layer: 8.0 GPa

[0140] Specifications of glass layer

[0141] Type of glass in the glass layer 2 O-SiO 2 Glass-like, set to 40Na 2 O-60SiO 2 .

[0142] ·Thickness of glass layer: 5μm

[0143] · Setting range of glass layer: refer to Table 1

[0144] Vickers hardness of glass layer: 7.7GPa

[0145] Specifications of internal electrode layers

[0146] Internal electrode material: Ni

[0147] Specifications of external electrode layer

[0148] Specifications of base electrode layer

[0149] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0150] Thickness in the length direction z at the center of the sintered layer in the height direction x located at the first end surface and the second end surface: 30 μm

[0151] Thickness in the height direction x connecting the first and second main surfaces at the center of the sintered layer in the length direction z (thickness of the base electrode layer in the center of the e dimension): 10 μm

[0152] Thickness in the width direction y connecting the first side surface and the second side surface at the center of the sintered layer in the length direction z (thickness of the base electrode layer in the center of the e-inch): 10 μm

[0153] Specifications of lower plating layer

[0154] Lower plating layer: Ni plating layer

[0155] Thickness in the length direction z at the center of the lower plating layer in the height direction x at the first end face and the second end face: 3 μm

[0156] Thickness in the height direction x connecting the first and second main surfaces at the center of the lower plating layer in the length direction z of the first and second main surfaces (thickness of the base electrode layer in the center of the length): 3 μm

[0157] Thickness in the width direction y connecting the first side surface and the second side surface at the center of the lower plating layer in the length direction z of the first side surface and the second side surface (thickness of the base electrode layer in the center of the e-inch): 3 μm

[0158] Specifications of upper plating layer

[0159] Upper plating layer: Sn plating layer

[0160] Thickness in the length direction z at the center of the upper plating layer in the height direction x of the first end face and the second end face: 3 μm

[0161] Thickness in the height direction x connecting the first and second main surfaces at the center of the upper plating layer in the length direction z of the first and second main surfaces (thickness of the base electrode layer in the center of the length): 4 μm

[0162] Thickness in the width direction y connecting the first side surface and the second side surface at the center of the upper plating layer in the length direction z of the first side surface and the second side surface (thickness of the base electrode layer in the center of the e-inch): 4 μm

[0163] (b) Specifications of Comparative Example Samples

[0164] As a comparative example, a multilayer ceramic capacitor without a glass layer was prepared. In the comparative example, the same specifications as those of the example were used except that the glass layer was not provided.

[0165] (c) Measurement and test methods

[0166] (Calculation method of the ratio of the dimension of the glass layer from the effective portion side to the dimension of the first end surface side outer layer portion and the second end surface side outer layer portion in the length direction z connecting the first end surface and the second end surface)

[0167] First, in the multilayer ceramic capacitors serving as samples of the embodiments and comparative examples, cross-section grinding was performed along a surface direction parallel to the side surface of the multilayer body to a position that was 1 / 2w of the dimension w in the width direction y of the multilayer body, so that the LT surface of the multilayer ceramic capacitor was exposed.

[0168] Next, in the outer layer portion on the first end face side, take the following points, take the midline as the extension direction, and draw out the reference line A1, wherein the above-mentioned points are: a point on the front end of the second internal electrode layer on the side not exposed at the first end face, located on the first end face side closest to the first main face; a point on the front end of the second internal electrode layer on the side not exposed at the first end face, located at a point 1 / 2t of the dimension t in the height direction x of the stack; and a point on the front end of the second internal electrode layer on the side not exposed at the first end face, located on the first end face side closest to the second main face.

[0169] Next, take the following points and take their midpoints as the extension direction to draw out the reference line A2, wherein the above-mentioned points are: the point of the first internal electrode layer exposed at the first end face which is located closest to the first main surface; the point of the first internal electrode layer exposed at the first end face which is located at a position 1 / 2t of the dimension t in the height direction x of the stack; and the point of the first internal electrode layer exposed at the first end face which is located closest to the second main surface.

[0170] Here, the distance between the reference line A1 and the reference line A2 in the direction connecting the first end surface and the second end surface is referred to as the distance L1.

[0171] Similarly, in the outer layer portion on the second end face side, the following points are taken, and the midline thereof is taken as the extension direction to draw out the reference line A3, wherein the above-mentioned points are: a point on the front end of the second end face side of the first internal electrode layer on the side not exposed at the second end face that is located closest to the first main face side; a point on the front end of the second end face side of the first internal electrode layer on the side not exposed at the second end face that is located at a point 1 / 2t of the dimension t in the height direction x of the stack; and a point on the front end of the second end face side of the first internal electrode layer on the side not exposed at the second end face that is located closest to the second main face side.

[0172] Next, take the following points and take their midpoints as the extension direction to draw out the reference line A4, wherein the above-mentioned points are: the point of the second internal electrode layer exposed at the second end face which is located closest to the first main surface; the point of the second internal electrode layer exposed at the second end face which is located at a position 1 / 2t of the dimension t in the height direction x of the stack; and the point of the second internal electrode layer exposed at the second end face which is located closest to the second main surface.

[0173] Here, the distance between the reference line A3 and the reference line A4 in the direction connecting the first end surface and the second end surface is referred to as the distance L2.

[0174] Then, L, which is the average value of the distance L1 and the distance L2 measured by the above-mentioned method, is defined as the distance of the first end surface side outer layer portion and the distance of the second end surface side outer layer portion, respectively.

[0175] Next, in the glass layer located on the first main surface outer layer, a distance B1 from the reference line A1 to the end of the glass layer protruding toward the first end surface and a distance B2 from the reference line A3 to the end of the glass layer protruding toward the second end surface were measured.

[0176] Similarly, in the glass layer located on the outer layer portion on the second main surface side, a distance B3 from the reference line A1 to the end of the glass layer protruding toward the first end surface side and a distance B4 from the reference line A3 to the end of the glass layer protruding toward the second end surface side were measured.

[0177] Then, B, which is the average value of the distances B1, B2, B3, and B4, is defined as the length of the glass layer protruding from the effective portion.

[0178] Then, using L and B defined as described above, B / L is calculated as the ratio of the dimension of the glass layer from the effective portion side to the dimension of the outer layer portion on the first end face side and the outer layer portion on the second end face side in the length direction z connecting the first end face and the second end face, and the ratio is defined as the length ratio of the dimension of the glass layer from the effective portion side to the dimension of the outer layer portion on the first end face side and the outer layer portion on the second end face side in the length direction z connecting the first end face and the second end face, and the calculation is performed.

[0179] (Method for Confirming the Presence of Cracks in Irdirectional Laminated Body)

[0180] The presence or absence of cracks in the isotropic laminate was confirmed by the method described below.

[0181] That is, first, the multilayer ceramic capacitors as samples of each example and comparative example were mounted on a mounting substrate having a thickness of 1.6 mm using solder paste.

[0182] Then, a pressing rod with a diameter of 1 mm was used to bend the mounting substrate from the back side of the mounting substrate on which the multilayer ceramic capacitor was not mounted, thereby applying mechanical pressure. The holding time at this time was set to 60 seconds, and the bending amount was set to 8 mm. In addition, in this test, conditions that are more severe than normal conditions are set. After the substrate is bent, the multilayer ceramic capacitor as a sample is removed from the mounting substrate, cross-section grinding is performed, and the presence or absence of cracks is observed. Regarding the cross-section grinding, grinding is performed along the surface direction parallel to the side of the stacked body of the multilayer ceramic capacitor until it becomes a position of 1 / 2w of the dimension w in the width direction y of the stacked body, so that the LT surface of the multilayer ceramic capacitor is exposed. The observation magnification is set to 100 times. In the case where a crack is confirmed to start from the vicinity of the front end of the external electrode located on the first main surface and the second main surface and extend in the inner direction of the stacked body, it is judged that there is a crack toward the stacked body.

[0183] (Method for confirming the presence of cracks in the effective part)

[0184] The confirmation of cracks extending to the effective part is the same as the method of confirming the presence or absence of cracks extending to the laminated body described above, and therefore, when cracks extending to the effective part are confirmed, it is determined that cracks extending to the effective part exist.

[0185] (Method of moisture resistance reliability test)

[0186] The moisture resistance reliability test was performed by the method described below.

[0187] That is, first, the laminated ceramic capacitors as samples of each embodiment and comparative example were mounted on a glass epoxy substrate using solder. Then, each sample was subjected to a humidity accelerated test in a high temperature and high humidity tank at 85°C and 85% RH at 6.3V for 1000 hours, and the insulation resistance value was measured. At this time, samples with an insulation resistance value (IR value) less than 107Ω were judged as defective.

[0188] (d) Results

[0189] Table 1 shows the B / L, the presence of cracks in the isodirectional laminate, the presence of cracks in the isodirectional effective portion, and the test results of the moisture resistance reliability test for each sample of Examples 1 to 8.

[0190] [Table 1]

[0191]

[0192] According to Table 1, in the samples of Examples 1 to 8, the glass layer is arranged to overlap with the front end of the first external electrode and the front end of the second external electrode arranged on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface in a plan view, and the glass layer is arranged in the outer layer portion on the first main surface side and the outer layer portion on the second main surface side of the laminate so as not to be exposed from the effective portion side to the first end surface and the second end surface, so even if cracks are generated toward the laminate, cracks toward the effective portion are not confirmed. In addition, in Examples 1 to 8, regarding the results of the moisture resistance reliability test, less than 5 out of 10 results were obtained in all Examples.

[0193] In addition, in the samples of Examples 1 to 5, the ratio of the size of the glass layer from the effective portion side to the size of the outer layer portion on the first end face side and the outer layer portion on the second end face side in the length direction z connecting the first end face and the second end face, that is, B / L, was less than 50%. Therefore, the results of the moisture resistance reliability test were that there were no samples judged to be defective among the 10 samples, and good results were obtained.

[0194] On the other hand, in the samples of the comparative example, no glass layer was provided on the outer layer portion on the first main surface side and the outer layer portion on the second main surface side of the stack, and therefore cracks developed toward the effective portion in 6 out of 10 samples, and the cracks toward the effective portion could not be suppressed. Furthermore, the result of the moisture resistance reliability test was that 6 out of 10 samples were defective.

[0195] It is clear from the above results that because the glass layer is configured to overlap with the front end of the first external electrode and the front end of the second external electrode arranged on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface when viewed from above, and is configured not to be exposed from the effective portion side on the first end surface and the second end surface, the extension of cracks to the effective portion can be suppressed.

[0196] Furthermore, it was confirmed that if the glass layer is arranged inside the laminate so that the dimension from the effective portion side is less than 50% of the dimension in the length direction z of the first end face side outer layer portion and the second end face side outer layer portion connecting the first end face and the second end face, cracks to the effective portion can be suppressed, and a laminated ceramic capacitor with moisture-resistant reliability can be obtained. That is, in the samples of Examples 1 to 5, the glass layer is not arranged so that the dimension from the effective portion side exceeds 50% of the dimension in the length direction z of the first end face side outer layer portion and the second end face side outer layer portion connecting the first end face and the second end face, and the glass layer is arranged so that it does not expose the first end face and the second end face of the laminate. Thus, even if cracks occur in the laminate and moisture infiltrates from the cracked portion, the cracks can be stopped in the glass layer, and not only that, the moisture can also be stopped in the glass layer. This suggests that it is possible to suppress moisture from reaching the interface between the stacked body and the external electrode, which is a path for moisture to easily penetrate into the effective portion.

[0197] 4. Experimental Example 2

[0198] Next, according to the above-mentioned manufacturing method, a laminated ceramic capacitor was manufactured in which the thickness of the glass layer in the height direction x connecting the first main surface and the second main surface was changed in the design of Example 3 in Table 1, and was evaluated by confirming the presence of cracks in the laminate and moisture resistance reliability test. The evaluation based on the presence of cracks in the laminate was performed by confirming the presence of cracks in the internal direction of the laminate and confirming the presence of cracks in the effective part.

[0199] (a) Samples used in the experiment

[0200] Regarding the multilayer ceramic capacitors as samples in which the thickness of the glass layer in the height direction x connecting the first main surface and the second main surface was changed in the design of Example 3 in Table 1, samples No. 1 to No. 7 were prepared as shown in Table 2.

[0201] (b) Measurement and test methods

[0202] (Method for measuring the thickness of glass layer)

[0203] The thickness of the glass layer was measured by the method described below.

[0204] That is, first, in the laminated ceramic capacitors of the samples No. 1 to No. 7, the cross-section was ground along the surface direction parallel to the side of the laminate until the position of 1 / 2w of the dimension w in the width direction y of the laminate, so that the LT surface of the laminated ceramic capacitor was exposed. Next, a SEM image was taken using a scanning electron microscope at the center of the glass layer on the outer layer side of the first main surface side in the ground section. The shooting range at this time was set to 20μm×15μm, and the magnification was set to 6000 times. The size of the glass layer in the length direction z contained in this range was divided into 5 points at equal intervals, and the thickness of the glass layer at the position of the 5 points was measured. Furthermore, in the same manner, a SEM image was taken using a scanning electron microscope at the center of the glass layer on the outer layer side of the second main surface side in the ground section. The shooting range at this time was set to 20μm×15μm, and the magnification was set to 6000 times. The dimension of the glass layer in the longitudinal direction z accommodated in the range is divided into five points at equal intervals, and the thickness of the glass layer at the positions of the five points is measured. Here, the average value of a total of 10 points, including the five points of the glass layer on the first main surface side outer layer portion side and the five points of the glass layer on the second main surface side outer layer portion side, is calculated, and this value is used as the thickness of the glass layer on the first main surface side outer layer portion and the second main surface side outer layer portion.

[0205] The method for confirming the presence of cracks in the non-directional laminate and the method for confirming the presence of cracks in the non-directional effective portion were performed by the same method as in Experimental Example 1.

[0206] (c) Results

[0207] Table 2 shows the test results of the glass layer thickness, the presence of non-directional cracks in the laminate, the presence of non-directional cracks in the effective portion, and the moisture resistance reliability test for each sample number 1 to sample number 7 in which the thickness of the glass layer in the height direction connecting the first main surface and the second main surface is changed in the design of Example 3 of Experimental Example 1.

[0208] [Table 2]

[0209]

[0210] According to Table 2, in the samples with sample numbers 2 to 6, the thickness of the glass layer was greater than 0.2 μm and less than 13 μm, so even if cracks occurred in the laminate, cracks in the effective part were not confirmed. As for the results of the moisture resistance reliability test, there were no samples judged to be defective among the 10 samples, and good results were obtained.

[0211] On the other hand, in the sample No. 1, the thickness of the glass layer was 0.1 μm, so the effect of absorbing stress (cracks) was reduced, and 1 in 10 cracks were generated toward the effective part. As for the results of the moisture resistance reliability, 1 in 10 was judged as defective. Therefore, it can be confirmed that in the sample No. 1, there is a case where the crack reaches the internal electrode layer as the effective part. In addition, in the sample No. 7, the thickness of the glass layer was 15 μm, so although no cracks were confirmed toward the effective part, the results of the moisture resistance reliability test were that 1 in 10 was judged as defective, which can be confirmed that the adhesion between the dielectric layers is reduced, and there is a case where structural defects are easily generated.

[0212] According to the above results, as long as the thickness of the glass layer in the height direction x connecting the first main surface and the second main surface is within the range of 0.2 μm or more and 13 μm or less, the cracks will be guided to the glass layer, and the extension of the cracks to the internal electrode layer can be reliably suppressed. As a result, the following suggestion is given, that is, short circuit failure can be suppressed and the moisture resistance reliability of the laminated ceramic capacitor can be maintained.

[0213] 5. Experimental Example 3

[0214] Next, according to the above-mentioned manufacturing method, a laminated ceramic capacitor was produced in which the Vickers hardness of the glass layer and the Vickers hardness of the dielectric layer were changed in the sample No. 3 having the design of Example 3 in Table 1 and the thickness of the glass layer being 2 μm, and the evaluation was performed by confirming the presence of cracks in the laminated body. The evaluation based on the presence of cracks in the laminated body was performed by confirming the presence of cracks in the internal direction of the laminated body and the presence of cracks in the effective part.

[0215] (a) Samples used in the experiment

[0216] Regarding the multilayer ceramic capacitor, which is a sample in which the Vickers hardness of the glass layer and the Vickers hardness of the dielectric layer are changed in the sample No. 3 which is the design of Example 3 in Table 1 and the thickness of the glass layer is set to 2 μm, samples No. 8 to No. 12 were prepared as shown in Table 3.

[0217] The type of glass of sample No. 8 is Na 2 O-SiO 2 Glass-like, set to 43Na 2 O-57SiO 2 Glass.

[0218] The type of glass of sample No. 9 is Na 2 O-SiO 2 Glass-like, set to 40Na 2 O-60SiO 2 Glass.

[0219] The type of glass of sample No. 10 is Na 2 O-SiO 2 Glass-like, set to 40Na 2 O-60SiO 2 Glass.

[0220] The type of glass of the sample No. 11 is Na 2 O-SiO 2 Glass-like, set as 37Na 2 O-63SiO 2 Glass.

[0221] The type of glass of sample No. 12 is Na 2 O-SiO 2 Glass-like, set as 34Na 2 O-66SiO 2 Glass.

[0222] (b) Measurement and test methods

[0223] (Method for measuring Vickers hardness of glass layer)

[0224] The Vickers hardness of the glass layer was measured by the method described below.

[0225] That is, regarding the Vickers hardness of the glass layer, first, in the laminated ceramic capacitor, a section is ground along a surface direction parallel to the side of the laminate until a position that is 1 / 2w of the dimension w in the width direction y of the laminate is reached, so that the LT surface of the laminated ceramic capacitor is exposed. Next, a Vickers indenter is pressed on the glass layer at the center of the glass layer on the outer layer side of the first main surface side in the ground section using a micro hardness meter, and the Vickers hardness of the glass layer on the outer layer side of the first main surface side is measured. Next, a Vickers indenter is pressed on the glass layer at the center of the glass layer on the outer layer side of the second main surface side in the ground section using a micro hardness meter, and the Vickers hardness of the glass layer on the outer layer side of the second main surface side is measured. Here, the average value of the Vickers hardness of the glass layer on the outer layer side of the first main surface side and the Vickers hardness of the glass layer on the outer layer side of the second main surface side is calculated, and this value is used as the Vickers hardness of the glass layer of the laminated ceramic capacitor.

[0226] (Method for measuring Vickers hardness of dielectric layer)

[0227] The Vickers hardness of the dielectric layer was measured by the method described below.

[0228] That is, regarding the Vickers hardness of the dielectric layer, first, in the laminated ceramic capacitor, a cross-section grinding is performed until a position that becomes 1 / 2w of the dimension w in the width direction y of the laminated body along the surface direction parallel to the side of the laminated body, so that the LT surface of the laminated ceramic capacitor is exposed. Next, a Vickers indenter is pressed on the dielectric layer using a micro hardness tester at the center of the outer layer side of the first main surface side in the grinding section, and the Vickers hardness of the dielectric layer on the outer layer side of the first main surface side is measured. Next, a Vickers indenter is pressed on the dielectric layer using a micro hardness tester at the center of the outer layer side of the second main surface side in the grinding section, and the Vickers hardness of the dielectric layer on the outer layer side of the second main surface side is measured. Here, the average value of the Vickers hardness of the dielectric layer on the outer layer side of the first main surface side and the Vickers hardness of the dielectric layer on the outer layer side of the second main surface side is calculated, and this value is used as the Vickers hardness of the dielectric layer of the laminated ceramic capacitor.

[0229] The method for confirming the presence of cracks in the non-directional laminate and the method for confirming the presence of cracks in the non-directional effective portion were performed by the same method as in Experimental Example 1.

[0230] (c) Results

[0231] Table 3 shows the test results of the thickness of the glass layer, the presence of cracks in the non-directional laminate, and the presence of cracks in the non-directional effective part for each of the samples No. 8 to No. 12 in which the Vickers hardness of the glass layer and the Vickers hardness of the dielectric layer were changed in the sample No. 3 which is the design of Example 3 of Table 1 and the thickness of the glass layer is set to 2 μm.

[0232] [Table 3]

[0233]

[0234] According to Table 3, in Sample Nos. 8 and 9, the Vickers hardness of the glass layer was lower than the Vickers hardness of the dielectric layer. Therefore, even if cracks occurred in the laminate, cracks in the effective portion were not observed.

[0235] In addition, in Sample Nos. 8 and 9, since the Vickers hardness of the glass layer is lower than 8 GPa, which is the Vickers hardness of the dielectric layer, it was confirmed that cracking to the effective portion could be suppressed.

[0236] On the other hand, in samples No. 10 to No. 12, the Vickers hardness of the glass layer was higher than that of the dielectric layer, so it was confirmed that cracks occurred in the effective part, although only 4 out of 10 cracks occurred in any sample.

[0237] In the samples of sample numbers 10 to 12, the Vickers hardness of the glass layer was 8 GPa or more, which was the Vickers hardness of the dielectric layer. Therefore, it was confirmed that cracks were generated in the effective portion.

[0238] The above results show that when the Vickers hardness of the glass layer is lower than that of the dielectric layer, the extension of cracks to the internal electrode layer, which is the effective part, can be reliably suppressed. As a result, the following suggestion is given, that is, short circuit failure can be suppressed and the moisture resistance reliability of the laminated ceramic capacitor can be maintained.

[0239] Furthermore, as described above, the embodiments of the present invention have been disclosed through the above description, but the present invention is not limited thereto.

[0240] That is, various changes can be added to the above-described embodiments with respect to the structure, shape, material, number, position, or arrangement without departing from the scope of the technical idea and purpose of the present invention, and they are included in the present invention.

Claims

1. A laminated ceramic capacitor comprising: A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and including a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; a first internal electrode layer disposed on the plurality of dielectric layers and exposed at the first end surface; a second internal electrode layer disposed on the plurality of dielectric layers and exposed at the second end surface; a first external electrode connected to the first internal electrode layer and arranged on the first end surface and a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface; as well as The second external electrode is connected to the second internal electrode layer and is disposed on the second end surface and a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, wherein: The laminated body has: an effective portion in which the plurality of first internal electrode layers and the plurality of second internal electrode layers are opposed to each other via the dielectric layer; a first main surface side outer layer portion, located on the first main surface side, formed by the plurality of dielectric layers located between the first main surface and the outermost surface of the effective portion on the first main surface side and an extension of the outermost surface; A second main surface side outer layer portion, located on the second main surface side, formed by the plurality of dielectric layers located between the second main surface and the outermost surface of the effective portion on the second main surface side and an extension of the outermost surface; a first end surface side outer layer portion located on the first end surface side and formed by the plurality of dielectric layers located between the first end surface and the outermost surface of the effective portion on the first end surface side; and The second end surface side outer layer portion is located on the second end surface side and is formed by the plurality of dielectric layers located between the second end surface and the outermost surface of the effective portion on the second end surface side. The first main surface side outer layer portion and the second main surface side outer layer portion have a glass layer disposed on the dielectric layer and disposed to face the effective portion, The glass layer is arranged so as to overlap with the front end of the first external electrode and the front end of the second external electrode arranged on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface in a plan view, The glass layer is configured to protrude from the effective portion and not be exposed on the first end surface and the second end surface. The dielectric components of the first main surface side outer layer portion and the effective portion are made of the same dielectric component.

2. The multilayer ceramic capacitor according to claim 1, wherein The glass layer is arranged in the laminate so that the dimension from the effective portion side is 50% or less of the dimension of the first end surface side outer layer portion and the second end surface side outer layer portion in the longitudinal direction connecting the first end surface and the second end surface.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein: The thickness of the glass layer in the height direction connecting the first main surface and the second main surface is 0.2 μm or more and 13 μm or less.

4. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein: The glass layer has a lower Vickers hardness than the dielectric layer.

5. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein: The glass layer has a Vickers hardness of 8 GPa or less.

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