Nanosheet transistor with self-aligned dielectric pillar

Abstract

A semiconductor structure and a method for forming a semiconductor structure with a self-aligned dielectric pillar for reducing trench silicide to gate parasitic capacitance are provided. A nanosheet stack (206) is formed over a substrate (204). A dielectric pillar (402) is positioned adjacent to the nanosheet stack (206) and on a shallow trench isolation region (212) of the substrate (204). The nanosheet stack (206) is recessed to expose a surface of the shallow trench isolation region (212), and a source or drain (S / D) region (602) is formed on the exposed surface of the shallow trench isolation region (212). A contact trench (802) is formed that exposes a surface of the S / D region (602) and a surface of the dielectric pillar (402).

Description

BACKGROUND

[0001] The present invention relates generally to methods of fabrication and resulting structures for semiconductor devices, and more specifically, to nanosheet transistor architectures with self-aligned dielectric pillars for reducing parasitic capacitance.

[0002] Known metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication techniques include process flows for constructing planar field-effect transistors (FETs). A planar FET includes a substrate (also referred to as a silicon plate), a gate formed over the substrate, source and drain regions formed on opposite ends of the gate, and a channel region under the gate proximate to the surface of the substrate. The channel region electrically connects the source region to the drain region, while the gate controls the current in the channel. The gate voltage controls whether the path from the drain to the source is open (“off”) or a resistive path (“on”).

[0003] In recent years, research has been directed toward the development of non-planar transistor architectures. For example, nanosheet FETs offer increased device density and some increased performance over lateral devices. In nanosheet FETs, the channel is implemented as a stack of spaced-apart nanosheets, and the gate stack surrounds the entire perimeter of each nanosheet, making possible more complete depletion in the channel region and reducing short-channel effects due to steeper subthreshold swing (SS) and smaller drain-induced barrier lowering (DIBL). The surrounding gate structure and source / drain contacts used in nanosheet devices also enable better management of leakage current and parasitic capacitance in the active region, even as drive current increases. SUMMARY

[0004] Embodiments of the present invention relate to a method for forming a semiconductor structure with self-aligned dielectric pillars for reducing trench silicide-to-gate parasitic capacitance. A non-limiting example of the method includes forming a nanosheet stack over a substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. The nanosheet stack is recessed to expose a surface of the shallow trench isolation region, and a source or drain (S / D) region is formed on the exposed surface of the shallow trench isolation region. A contact trench is formed that exposes a surface of the S / D region and a surface of the dielectric pillar.

[0005] Embodiments of the present invention relate to a semiconductor structure. A non-limiting example of the semiconductor device includes a nanosheet stack positioned over a substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. A S / D region is positioned on a surface of the shallow trench isolation region, and a trench silicide is formed on a surface of the S / D region and a surface of the dielectric pillar.

[0006] Embodiments of the invention relate to a method for forming a semiconductor structure with a self-aligned dielectric pillar for reducing trench silicide to gate parasitic capacitance. A non-limiting example of the method includes forming a bottom isolation structure on a substrate and forming a nanosheet stack on the bottom isolation structure. The bottom isolation structure is between the nanosheet stack and the substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. A conformal liner is formed over the S / D regions and the dielectric pillar, and an interlayer dielectric is positioned over the conformal liner. Portions of the interlayer dielectric and portions of the conformal liner are removed to form a contact trench that exposes a surface of the S / D regions and a surface of the dielectric pillar. A trench silicide is formed in the contact trench.

[0007] Embodiments of the invention relate to a method for forming a semiconductor structure with a self-aligned dielectric pillar for reducing trench silicide to gate parasitic capacitance. A non-limiting example of the method includes forming a semiconductor fin on a substrate. A dielectric pillar is positioned adjacent to the semiconductor fin and on a shallow trench isolation region of the substrate. The semiconductor fin is recessed to expose a surface of the shallow trench isolation region, and an S / D region is formed on the exposed surface of the shallow trench isolation region. A contact trench is formed that exposes a surface of the S / D region and a surface of the dielectric pillar.

[0008] Embodiments of the invention relate to a semiconductor structure. A non-limiting example of the semiconductor device includes a semiconductor fin on a substrate. A dielectric pillar is positioned adjacent to the semiconductor fin and on a shallow trench isolation region of the substrate. An S / D region is on a surface of the shallow trench isolation region, and a trench silicide is formed on a surface of the S / D region and a surface of the dielectric pillar.

[0009] Additional technical features and benefits are realized through the techniques of the invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0010] The specifics of the exclusive right described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention will be apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A top view of a semiconductor structure after a processing operation is shown in accordance with one or more embodiments of the invention;

[0012] Figure 2A A cross-sectional view along line X of a semiconductor structure after a processing operation is described in accordance with one or more embodiments of the invention; Figure 1

[0013] Figure 2B ​A cross-sectional view along line Y of the semiconductor structure according to one or more embodiments of the application after a processing operation is described. Figure 1

[0014] Figure 3A A cross-sectional view along line X of the semiconductor structure according to one or more embodiments of the application after a processing operation is described. Figure 1

[0015] Figure 3B A cross-sectional view along line Y of the semiconductor structure according to one or more embodiments of the application after a processing operation is described. Figure 1

[0016] Figure 4A A cross-sectional view along line X of the semiconductor structure according to one or more embodiments of the application after a processing operation is described. Figure 1

[0017] Figure 4B A cross-sectional view along line Y of the semiconductor structure according to one or more embodiments of the application after a processing operation is described. Figure 1

[0018] Figure 5A A cross-sectional view along line X of the semiconductor structure according to one or more embodiments of the application after a processing operation is described. Figure 1

[0019] Figure 5B A cross-sectional view along line Y of the semiconductor structure according to one or more embodiments of the application after a processing operation is described. Figure 1

[0020] Figure 6A A cross-sectional view along line X of the semiconductor structure according to one or more embodiments of the application after a processing operation is described. Figure 1

[0021] Figure 6B A cross-sectional view along line Y of the semiconductor structure according to one or more embodiments of the application after a processing operation is described. Figure 1

[0022] Figure 7A A cross-sectional view along line X of the semiconductor structure according to one or more embodiments of the application after a processing operation is described. Figure 1

[0023] Figure 7B A cross-sectional view along line Y of the semiconductor structure according to one or more embodiments of the application after a processing operation is described. Figure 1

[0024] Figure 8A ​​​​​​​​​​​The semiconductor structure shown according to one or more embodiments of the present invention is along the processing operation. Figure 1 A cross-sectional view of line X;

[0025] Figure 8B The semiconductor structure described according to one or more embodiments of the present invention is along the processing operation. Figure 1 A cross-sectional view of line Y;

[0026] Figure 9A The semiconductor structure shown according to one or more embodiments of the present invention is along the processing operation. Figure 1 A cross-sectional view of line X;

[0027] Figure 9B The semiconductor structure described according to one or more embodiments of the present invention is along the processing operation. Figure 1 A cross-sectional view of line Y;

[0028] Figure 10A The following is illustrated after the processing operation according to one or more embodiments of the present invention. Figure 1 A cross-sectional view of the X-shaped fin semiconductor structure;

[0029] Figure 10B The following describes the process after the processing operation according to one or more embodiments of the present invention. Figure 1 A cross-sectional view of a Y-shaped finned semiconductor structure;

[0030] Figure 11 A flowchart illustrating a method according to one or more embodiments of the present invention is described;

[0031] Figure 12 A flowchart illustrating a method according to one or more embodiments of the present invention is described; and

[0032] Figure 13 A flowchart illustrating a method according to one or more embodiments of the present invention is described.

[0033] The figures described herein are illustrative. Many variations may be made to the figures or operations described herein without departing from the scope of the invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified.

[0034] In the accompanying drawings and the following detailed description of the embodiments of the invention, the various elements shown in the drawings have two or three reference numerals. With minor exceptions, the leftmost digit of each reference numeral corresponds to the figure in which its element is first shown. Detailed Implementation

[0035] It is to be understood that, while example embodiments of the present application are described in connection with a particular transistor architecture (nanosheet transistor), embodiments of the present application are not limited to the particular transistor architecture or materials described in this specification. Rather, embodiments of the present application can be implemented in connection with any other type of transistor architecture (e.g., finFET) or materials now known or later developed.

[0036] For the sake of brevity, conventional techniques related to semiconductor devices and integrated circuit (IC) fabrication can or can not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well-known and so do not need to be described in detail here. Instead, additional details regarding making and using these devices are described in a number of

[0037] Turning now to a more specific overview of the technology with which aspects of the present application are more directly related, continued scaling of FETs is currently limited due to an increase in parasitic capacitance associated with a reduction in gate pitch. For example, in a conventional nanosheet process flow (process on record, or POR), source / drain trench contacts (sometimes referred to as TS or trench silicide) are formed by etching an interlayer dielectric (ILD). While landing the source / drain trench contacts on the source / drain region(s) is beneficial because such an arrangement reduces contact resistance in the device, landing the source / drain trench contacts on the isolation (e.g., shallow trench isolation, also referred to as STI) between nanosheets in a nanosheet transistor region undesirably increases the TS to gate capacitance. The increase in parasitic capacitance not only slows the circuit speed of the final device, but also increases power consumption.

[0038] Turning now to an overview of aspects of the present application, one or more embodiments of the present application address the aforementioned shortcomings of the prior art by providing a new semiconductor structure and method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide to gate parasitic capacitance. In aspects of the present application, the method includes forming a buried dielectric pillar that is self-aligned to a nanosheet structure. In some embodiments of the present application, the dielectric pillar is located between source / drain regions of adjacent nanosheet stacks. The dielectric pillar extends upward from the substrate and serves as an etch stop for source / drain trench contact trench patterning. As a result, the vertical depth of the source / drain trench contact on the STI is reduced. As a result, the TS to gate capacitance is reduced. Advantageously, the dielectric pillar can be similarly incorporated into other transistor structures, such as a FinFET, to achieve an equivalent reduction in parasitic capacitance.

[0039] Turning now to a more detailed description of aspects of the present application, Figure 1A top view of a semiconductor structure 100 after a set of initial fabrication operations have been applied as part of a method for fabricating a final semiconductor device is described. In some embodiments of the invention, the final semiconductor device may include one or more gates 102 formed on one or more nanosheet stacks 104 (or fins in a FinFET implementation). In some embodiments of the invention, gate spacers 106 are located on the sidewalls of one or more gates 102. In some embodiments of the invention, the final semiconductor device may include source / drain trench contacts 108 located between adjacent nanosheet stacks of one or more nanosheet stacks 104 relative to line X (across the nanosheets in the source / drain regions). In some embodiments of the invention, the final semiconductor device may include dielectric pillars 110 located between adjacent nanosheet stacks of one or more nanosheet stacks 104 relative to line Y (across the gates in the fin regions). The final semiconductor device may be various types of MOSFETs, including, for example, n-type nanosheet field-effect transistors (NS NFETs), p-type nanosheet field-effect transistors (NS PFETs), n-type FinFETs, and p-type FinFETs.

[0040] Figure 2A and Figure 2B The description describes a process according to one or more embodiments of the present invention, following a set of initial manufacturing operations applied as part of a method for manufacturing a final semiconductor device, along... Figure 1 A cross-sectional view of the semiconductor structure 100 taken by lines X (across the nanosheets in the source / drain regions) and Y (across the gate in the fin regions). In some embodiments of the invention, a bottom isolation structure 202 is formed on the substrate 204. In some embodiments of the invention, a nanosheet stack 206 is formed on the bottom isolation structure 202.

[0041] The bottom isolation structure 202 can be made of any suitable dielectric material, such as, for example, low-k dielectrics, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the invention, the bottom isolation structure 202 is a single-layer isolation structure. In some embodiments of the invention, the bottom isolation structure 202 is a multilayer isolation structure. For example, the bottom isolation structure 202 may include a nitride-oxide-nitride Tr layer stack (e.g., SiN / SiO2 / SiN).

[0042] The substrate 204 can be made of any suitable substrate material, such as, for example, monocrystalline Si, silicon germanium (SiGe), III-V compound semiconductors, II- VI compound semiconductors, or semiconductor-on-insulator (SOI). For example, III-V compound semiconductors include materials having at least one Group III element and at least one Group V element, such as one or more of aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), aluminum indium arsenide (AlInAs), aluminum nitride (AIN), gallium antimonide (GaSb), gallium aluminum antimonide (GaAlSb), gallium arsenide (GaAs), gallium arsenic antimonide (GaAsSb), gallium nitride (GaN), indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium gallium arsenic phosphide (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphide (InP), and alloy combinations including at least one of the foregoing materials. Alloy combinations can include binary (two elements, e.g., gallium arsenide (III)), ternary (three elements, e.g., InGaAs), and quaternary (four elements, e.g., aluminum gallium indium phosphide (AlInGaP)) alloys.

[0043] In some embodiments of the application, the substrate 204 can include a buried oxide layer (not shown). The buried oxide layer can be made of any suitable dielectric material, such as, for example, silicon oxide. In some embodiments of the application, the buried oxide layer is formed to a thickness of about 145 nm, although other thicknesses are within the contemplation of the application.

[0044] In some embodiments of the application, the nanosheet stack 206 can include one or more semiconductor layers 208 alternating with one or more sacrificial layers 210. In some embodiments of the application, the semiconductor layers 208 and the sacrificial layers 210 are epitaxially grown layers. For ease of discussion, reference is made to operations performed on a nanosheet stack 206 having three nanosheets (e.g., semiconductor layers 208) alternating with three sacrificial layers (e.g., sacrificial layers 210). However, it should be understood that the nanosheet stack 206 can include any number of nanosheets alternating with a corresponding number of sacrificial layers. For example, the nanosheet stack 206 can include a single nanosheet, two nanosheets, five nanosheets, eight nanosheets, or any number of nanosheets, and a corresponding number of sacrificial layers (i.e., as appropriate to form a nanosheet stack having a bottommost sacrificial layer under a bottommost nanosheet and a sacrificial layer between each pair of adjacent nanosheets).

[0045] Semiconductor layer 208 can be made of any suitable material, such as, for example, single-crystal silicon or silicon germanium. In some embodiments of the invention, semiconductor layer 208 is an nFET nanosheet. In some embodiments of the invention, the nFET nanosheet is a silicon nFET nanosheet. In some embodiments of the invention, semiconductor layer 208 has a thickness of about 4 nm to about 10 nm, for example, 6 nm, but other thicknesses are also within the scope of the invention. In some embodiments of the invention, substrate 204 and semiconductor layer 208 can be made of the same semiconductor material. In other embodiments of the invention, substrate 204 can be made of a first semiconductor material, while semiconductor layer 208 can be made of a second semiconductor material.

[0046] The sacrificial layer 210 may be a silicon or silicon-germanium layer, depending on the material of the semiconductor layer 208. For example, in embodiments where the semiconductor layer 208 is a silicon nanosheet, the sacrificial layer 210 may be a silicon-germanium layer. In some embodiments of the invention, the sacrificial layer 210 is a silicon-germanium layer with a germanium concentration of about 25% (sometimes referred to as SiGe25), although other germanium concentrations are also within the scope of the invention. In some embodiments of the invention, the sacrificial layer 210 has a thickness of about 12 nm to about 15 nm, for example, 10 nm, although other thicknesses are also within the scope of the invention. In some embodiments of the invention, the sacrificial layer 210 is made of the same material as the intermediate sacrificial layer 210 in the bottom isolation structure 202.

[0047] like Figure 2A As shown, the shallow trench isolation region 212 (also referred to as the STI region) can be formed adjacent to the nanosheet stack 206 and the bottom isolation structure 202. In some embodiments of the invention, the trench is formed by removing a portion of the nanosheet stack 206 and the bottom isolation structure 202, thus recessing the exposed surface of the substrate 204. The trench can then be filled with a dielectric material, such as a low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. The shallow trench isolation region 212 provides electrical isolation between the nanosheet stack 206 and other adjacent devices on the substrate 204 (e.g., other nanosheet stacks or any other active devices).

[0048] like Figure 2B As shown, one or more sacrificial gates 214 (sometimes referred to as dummy gates) are formed on the nanosheet stack 206. The portion of the nanosheet stack on which the gates are formed is called the channel region. The sacrificial gates 214 can be made of any suitable material, such as, for example, amorphous silicon or polycrystalline silicon. Any known method for patterning sacrificial gates can be used, such as, for example, wet etching, dry etching, or a combination of sequential wet and / or dry etching.

[0049] In some embodiments of the invention, a hard mask 216 is formed on the sacrificial gate 214. In some embodiments of the invention, the sacrificial gate 214 is formed by patterning the hard mask 216 and selectively removing portions of the sacrificial gate 214 not covered by the patterned hard mask 216 using a wet or dry etching process. In some embodiments of the invention, a thin oxide layer (not shown) is formed between the nanosheet stack 206 and the sacrificial gate 214.

[0050] The hard mask 216 can be made of any suitable material, such as, for example, silicon nitride. In some embodiments of the invention, a second hard mask (not shown) is formed on the hard mask 216 to form a double-layer hard mask. In some embodiments, the second hard mask comprises an oxide, such as, for example, silicon dioxide.

[0051] like Figure 2B As further shown, in some embodiments of the invention, spacers 218 (also referred to as sidewall spacers or gate spacers) are formed on the sidewalls of the sacrificial gate 214. In some embodiments of the invention, spacers 218 are formed using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), finite reaction process CVD (LRPCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical solution deposition, molecular beam epitaxy (MBE), or other similar processes combined with wet or dry etching processes. For example, spacer material may be conformally deposited on the semiconductor structure 100 and selectively removed using RIE to form spacers 218.

[0052] The spacer 218 can be made of any suitable material, such as, for example, a low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the invention, the spacer 218 comprises silicon nitride. The spacer 218 can be formed to a thickness of about 5 to 40 nm, although other thicknesses are also within the scope of the invention.

[0053] Figure 3A and Figure 3B Describing one or more embodiments of the present invention after the processing operation along Figure 1 The cross-sectional view of the semiconductor structure 100 obtained by lines X and Y. In some embodiments of the present invention, the sacrificial region 302 is formed on the nanosheet stack 206, the bottom isolation structure 202, and the shallow trench isolation region 212.

[0054] In some embodiments of the invention, the sacrificial region 302 comprises a silicon-germanium layer having a germanium concentration selected to provide etch selectivity relative to the nanosheet stack 206. For example, in some embodiments of the invention, the sacrificial layer 210 is a silicon-germanium layer with a germanium concentration of about 25%, and the sacrificial region 302 is made of silicon-germanium (sometimes referred to as SiGe60) with a germanium concentration of about 60%.

[0055] Sacrificial region 302 provides a widening of the source / drain regions in the final device (e.g., Figure 5A and Figure 5B (As shown). In some embodiments of the invention, the sacrificial region 302 is optional. Widening of the source / drain is advantageous for FinFETs because the fins are typically narrow and the gaps between the fins are large. For relatively wide nanosheets with a width greater than about 20 nm, widening of the source / drain of the nanosheet is optional because the gaps between the nanosheets are already small; however, widening is useful for narrow fins with a width less than about 20 nm.

[0056] Figure 4A and Figure 4B Describing one or more embodiments of the present invention after the processing operation along Figure 1 The cross-sectional view of the semiconductor structure 100 obtained by lines X and Y. In some embodiments of the invention, dielectric pillars 402 are formed between the nanosheet stack 106 and adjacent nanosheet stacks.

[0057] In some embodiments of the invention, the dielectric pillar 402 comprises silicon carbide (SiC), although other dielectric materials are also within the scope of the invention. In some embodiments of the invention, the dielectric pillar 402 is formed by conformal deposition of the dielectric material followed by etch-back to fill the gaps between the sacrificial regions 302 (e.g., between enlarged source / drain regions).

[0058] Figure 5A and Figure 5B Describing one or more embodiments of the present invention after the processing operation along Figure 1The cross-sectional views of the semiconductor structure 100 obtained by lines X and Y are shown. In some embodiments of the invention, the sacrificial region 302 may be removed, and the nanosheet stack 206 may be recessed to expose the surfaces of the bottom isolation structure 202 and the shallow trench isolation region 212. The sacrificial region 302 may be removed using wet etching, dry etching, or a combination of wet and / or dry etching, and the nanosheet stack 206 may be recessed. In some embodiments of the invention, the sacrificial region 302 is removed, and the nanosheet stack is recessed using one or more selective etchings of the bottom isolation structure 202. For example, among other options, vapor-phase HCl or vapor-phase ClF3 may be used to selectively remove silicon, SiGe25, and SiGe60 relative to silicon nitride.

[0059] like Figure 5B As further shown, the sacrificial layer 210 may be recessed, and the inner spacer 502 may be formed on the recessed sidewalls of the sacrificial layer 210. For example, the sidewalls of the sacrificial layer 210 may be recessed to form cavities in the nanosheet stack 206. In some embodiments of the invention, the inner spacer 502 is formed on the recessed sidewalls of the sacrificial layer 210 by filling these cavities with a dielectric material. In some embodiments of the invention, a portion of the inner spacer 502 extending beyond the sidewalls of the nanosheet stack 206 is removed using, for example, reactive ion etching (RIE). In this way, the sidewalls of the inner spacer 502 are coplanar with the sidewalls of the semiconductor layer 208.

[0060] In some embodiments of the invention, the inner spacer 502 is formed using CVD, PECVD, ALD, PVD, chemical solution deposition, or other similar processes combined with wet or dry etching processes. The inner spacer 502 can be made of any suitable material, such as, for example, low-k dielectrics, nitrides, silicon nitride, silicon dioxide, SiON, SiC, SiOCN, or SiBCN.

[0061] Figure 6A and Figure 6B Describing the process following one or more embodiments of the present invention. Figure 1 The cross-sectional view of the semiconductor structure 100 obtained by lines X and Y is shown. In some embodiments of the invention, source and drain regions 602 are formed on the bottom isolation structure 202 between opposite sidewalls of the dielectric pillar 402. In some embodiments of the invention, the source and drain regions 602 are formed to a thickness (height) of 10 nm or greater, for example, 40 nm to 70 nm, although other thicknesses are also within the scope of the invention.

[0062] The source and drain regions 602 can be epitaxially grown using, for example, vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. The source and drain regions 602 can be semiconductor materials epitaxially grown from a gaseous or liquid precursor.

[0063] In some embodiments of the invention, the gas source for epitaxial deposition of semiconductor materials includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, a Si layer can be epitaxially deposited (or grown) from a silicon gas source selected from silane, dichlorosilane, propane, tetrasilane, hexachlorodichlorosilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldichlorosilane, hexamethyldichlorosilane, and combinations thereof. A germanium layer can be epitaxially deposited from a germanium gas source selected from germanane, dichlorogerane, halogerane, dichlorogerane, trichlorogerane, tetrachlorogerane, and combinations thereof. A silicon-germanium alloy layer can be epitaxially formed using combinations of these gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used. In some embodiments of the invention, the epitaxial semiconductor material includes silicon-doped carbon (Si:C). The Si:C layer can be grown in the same chamber used for other epitaxial steps, or in a dedicated Si:C epitaxial chamber. Si:C may include carbon in the range of about 0.2% to about 3.0%.

[0064] Epitaxially grown silicon and germanium can be doped by adding n-type dopant (e.g., P or As) or p-type dopant (e.g., Ga, B, BF2, or Al). In some embodiments of the invention, the source and drain regions 602 can be epitaxially formed and doped by various methods, such as, for example, in-situ doped epitaxy (doping during deposition), post-epitaxy, or by implantation and plasma doping. The dopant concentration in the doped regions can be 1 × 10⁻⁶. 19 cm -3 Up to 2×10 21 cm -3 Within the range, or within 1×10 20 cm -3 With 1×10 21 cm -3 between.

[0065] In some embodiments of the invention, the source and drain regions 602 are made of silicon or silicon-germanium. In some embodiments of the invention, the source and drain regions 602 are made of silicon-germanium with a germanium concentration of about 10% to about 65% (e.g., 50%), but other germanium concentrations are also within the scope of the invention.

[0066] Figure 7A and Figure 7B Describing one or more embodiments of the present invention after the processing operation along Figure 1The cross-sectional view of the semiconductor structure 100 obtained by lines X and Y. In some embodiments of the invention, a liner 702 is formed over the source and drain regions 602 and the dielectric pillars 402.

[0067] In some embodiments of the invention, liner 702 is deposited using, for example, ALD conformal deposition, although other conformal deposition processes are within the scope of the invention. Liner 702 can be made of any suitable material, such as, for example, low-k dielectrics, nitrides, silicon nitride, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the invention, liner 702 comprises silicon nitride (e.g., SiN). Liner 702 can be formed to a nominal (conformal) thickness of about 5 nm or less, or 3 nm or less, although other thicknesses are within the scope of the invention.

[0068] In some embodiments of the invention, an interlayer dielectric 704 is formed on the liner 702. The interlayer dielectric 704 serves as an isolation structure for the semiconductor device 100. The interlayer dielectric 704 can be made of any suitable dielectric material, such as, for example, porous silicates, carbon-doped oxides, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide (SiC), or other dielectric materials. In some embodiments of the invention, the interlayer dielectric 704 comprises SiO2. Any known method for forming the interlayer dielectric 704 can be used, such as, for example, CVD, PECVD, ALD, flowable CVD, spin-coated dielectric, or PVD. In some embodiments of the invention, the interlayer dielectric 704 and the shallow trench isolation region 212 are made of the same dielectric material.

[0069] like Figure 7B As shown, the sacrificial layer 210, sacrificial gate 214 and hard mask 216 can be removed and replaced with gate 706 (sometimes called active or conductive gate).

[0070] Gate 706 may be a high-k metal gate (HKMG) formed over the channel region of the nanosheet stack 206 using, for example, a known replacement metal gate (RMG) process or a so-called gate-first process. As used herein, a “channel region” refers to a portion of the semiconductor layer 208 on which gate 706 is formed and through which current flows from the source to the drain in the final device (not shown). In some embodiments of the invention, gate 706 is formed by removing sacrificial gate 214, selectively removing sacrificial layer 210 to release the nanosheet channel (semiconductor layer 208 in the channel region), and depositing high-k / metal gate material into the cavity left after the removal of sacrificial gate 214 and sacrificial layer 210.

[0071] In some embodiments of the present invention, gate 706 may include one or more gate dielectrics (not shown) and a work function metal stack (not shown). In some embodiments, gate 706 includes a body formed of one or more bulk conductive gate materials.

[0072] In some embodiments of the present invention, the gate dielectric is a high-k dielectric film formed on the surface (sidewall) of the semiconductor layer 208. The high-k dielectric film may be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, high-k materials, or any combination thereof. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k material may further include dopants such as lanthanum and aluminum. In some embodiments of the present invention, the high-k dielectric film may have a thickness of about 0.5 nm to about 4 nm. In some embodiments of the present invention, the high-k dielectric film includes hafnium oxide and has a thickness of about 1 nm, although other thicknesses are also within the scope of the present invention.

[0073] In some embodiments of the present invention, gate 706 includes one or more work function layers (sometimes referred to as work function metal stacks) formed between a high-k dielectric film and a body gate material. In some embodiments of the present invention, gate 706 includes one or more work function layers, but does not include a body gate material.

[0074] If present, the work function layer can be made of, for example, aluminum, lanthanum oxide, magnesium oxide, strontium titanate, strontium oxide, titanium nitride, tantalum nitride, hafnium nitride, tungsten nitride, molybdenum nitride, niobium nitride, hafnium silicon nitride, titanium aluminum nitride, tantalum silicon nitride, titanium aluminum carbide, tantalum carbide, and combinations thereof. The work function layer can be used to modify the work function of the gate 706 and enable adjustment of the device threshold voltage. The work function layer can be formed to a thickness of about 0.5 to 6 nm, although other thicknesses are also within the scope of this invention. In some embodiments of the invention, each work function layer can be formed to a different thickness. In some embodiments of the invention, the work function layer comprises a TiN / TiC / TiCAl stack.

[0075] In some embodiments, gate 706 comprises a body formed of one or more bulk conductive gate materials deposited on the work function layer and / or gate dielectric. The bulk gate material may include any suitable conductive material, such as, for example, metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metal compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), conductive carbon, graphene, or any suitable combination of these materials. The conductive gate material may also include dopants incorporated during or after deposition.

[0076] like Figure 7B As further described herein, gate 706 may include gate hard mask 708. Gate hard mask 708 may be made of any suitable material, such as, for example, silicon nitride. Since gate hard mask 708 is aligned with gate 706 in the spacing between spacers 218, gate hard mask 1002 may be considered a self-aligned hard mask (sometimes referred to as a SAC cap).

[0077] Figure 8A and Figure 8B Describing one or more embodiments of the present invention after the processing operation along Figure 1 The cross-sectional view of the semiconductor structure 100 obtained by lines X and Y. In some embodiments of the invention, a portion of the liner 702 and the interlayer dielectric 704 are removed to form contact trenches 802 that expose the surfaces of the source and drain regions 602.

[0078] In some embodiments of the invention, portions of the liner 702 and the interlayer dielectric 704 are selectively removed from the dielectric pillar 402. In other words, the dielectric pillar 402 can be used as an etch stop for TS trench patterning. Any known method for patterning dielectric materials can be used, such as, for example, wet etching, dry etching, or a combination of sequential wet and / or dry etching. In some embodiments of the invention, a patterning mask (not shown) is formed on the interlayer dielectric 704, and exposed portions of the liner 702 and the interlayer dielectric 704 are removed using, for example, one or more RIEs.

[0079] Figure 9A and Figure 9B Describing one or more embodiments of the present invention after the processing operation along Figure 1The X and Y axes show cross-sectional views of the semiconductor structure 100. In some embodiments of the invention, the contact trench 802 is filled with a conductive material (e.g., Co) to form a trench silicide 902. In some embodiments of the invention, the trench silicide 902 overfills the contact trench 802, forming an overburden extending from the surface of the interlayer dielectric 704. In some embodiments of the invention, the overburden is removed using, for example, chemical mechanical planarization (CMP).

[0080] like Figure 9A As shown, trench silicide 902 rests on the top surfaces of the source and drain regions 602 and the top surface of the dielectric pillar 402. As previously described, resting trench silicide 902 on the top surfaces of the source and drain regions 602 reduces contact resistance, while resting it on the top surface of the dielectric pillar 402 (instead of on shallow trench isolation as in conventional processes) reduces the TS-to-gate parasitic capacitance by reducing the vertical depth of the trench silicide 902 on the shallow trench isolation 212.

[0081] Figure 10A and Figure 10B It illustrates the process following one or more embodiments of the present invention. Figure 1 The X and Y axes provide a cross-sectional view of the finned semiconductor structure 1000. (Compared to...) Figure 9A and Figure 9B Compared to the nanosheet-type implementation shown, Figure 10A and Figure 10B The semiconductor structure 1000 shown describes a finFET-type implementation of a dielectric pillar for reducing parasitic capacitance.

[0082] In some embodiments of the present invention, the semiconductor structure 1000 may include components that are compatible with... Figure 9A The dielectric pillars 1002 are formed between the semiconductor fins 1004 in a manner similar to the dielectric pillars 402 formed by the adjacent nanosheet stacks 206. In some embodiments of the invention, the semiconductor structure 1000 may include structures that are similar to those in the semiconductor fins 1004. Figure 9A and Figure 9B The source / drain region 1006 is formed on the substrate 1008 in a similar manner as shown. In some embodiments of the invention, the semiconductor structure 1000 can be configured with... Figure 9A and Figure 9B A similar approach is shown, including shallow trench isolation regions 1010 between adjacent fins of semiconductor fin 1004.

[0083] In some embodiments of the present invention, the semiconductor structure 1000 may include components that are compatible with... Figure 9A and Figure 9BA trench silicide 1012 is formed between opposing sidewalls of the interlayer dielectric 1014 in a similar manner as shown. In some embodiments of the invention, the semiconductor structure 1000 can be configured with... Figure 9A and Figure 9B A similar arrangement is shown, including a liner 1016 between the interlayer dielectric 1014 and the dielectric pillar 1002.

[0084] In some embodiments of the present invention, the semiconductor structure 1000 may include a gate (e.g., a high-k metal gate) 1018, which is coupled to... Figure 9A and Figure 9B A similar arrangement is formed over the channel region of the semiconductor fin 1004. In some embodiments of the invention, the gate 1018 is aligned with... Figure 9A and Figure 9B A similar arrangement is shown between the gate spacers 1020. In some embodiments of the invention, the gate 1018 includes a gate cap 1022, in a manner similar to... Figure 9A and Figure 9B The method shown is similar.

[0085] Figure 11 A flowchart 1100 is described, illustrating a method for forming a semiconductor device according to one or more embodiments of the present invention. As shown in block 1102, a stack of nanosheets is formed on a substrate. In block 1104, a dielectric pillar is formed adjacent to the nanosheet stack. The dielectric pillar is located on a shallow trench isolation region of the substrate.

[0086] In box 1106, the nanosheet stack is recessed to expose the surface of the shallow trench isolation region. In some embodiments of the invention, the recessed nanosheet stack includes the removal of sacrificial regions. In box 1108, source or drain (S / D) regions are formed on the exposed surface of the shallow trench isolation region.

[0087] In frame 1110, contact trenches are formed between the surface exposing the S / D region and the surface of the dielectric pillars. In some embodiments of the invention, the dielectric pillars serve as etch stops during the formation of the contact trenches. In some embodiments of the invention, trench silicide is formed in the contact trenches.

[0088] The method may also include forming a bottom isolation structure between the substrate and the nanosheet stack. In some embodiments of the invention, a sacrificial region is formed on the nanosheet stack prior to the formation of the dielectric pillar. As discussed earlier herein, the sacrificial region can be used to widen the source / drain regions.

[0089] In some embodiments of the invention, a conformal liner is formed on the S / D region and the dielectric pillar. In some embodiments of the invention, an interlayer dielectric is formed over the conformal liner. In some embodiments of the invention, forming a contact trench includes removing portions of the interlayer dielectric and the conformal liner.

[0090] Figure 12 A flowchart 1200 describes a method for forming a semiconductor device according to one or more embodiments of the present invention. As shown in block 1202, a bottom isolation structure is formed on a substrate. At block 1204, a nanosheet stack is formed on the bottom isolation structure. The bottom isolation structure is located between the nanosheet stack and the substrate.

[0091] At frame 1206, adjacent nanosheets are stacked to form a dielectric pillar. This dielectric pillar is located on a shallow trench isolation region of the substrate. In some embodiments of the invention, at frame 1212, the dielectric pillar serves as an etch stop during the formation of a contact trench.

[0092] At frame 1208, a conformal liner is formed on the S / D region and the dielectric pillar. At frame 1210, an interlayer dielectric is formed over the conformal liner. At frame 1212, portions of the interlayer dielectric and the conformal liner are removed to form contact trenches exposing the surfaces of the S / D region and the dielectric pillars. At frame 1214, trench silicide is formed in the contact trenches.

[0093] In some embodiments of the invention, a sacrificial region is formed on the nanosheet stack prior to the formation of the dielectric pillar. In some embodiments of the invention, the nanosheet stack is recessed to expose the surface of the shallow trench isolation region. In some embodiments of the invention, recessing the nanosheet stack includes removing the sacrificial region.

[0094] Figure 13 A flowchart 1300 describes a method for forming a semiconductor device according to one or more embodiments of the present invention. As shown in block 1302, semiconductor fins are formed on a substrate. At block 1304, dielectric pillars are formed adjacent to the semiconductor fins. The dielectric pillars are located on a shallow trench isolation region of the substrate.

[0095] At block 1306, a semiconductor fin is recessed to expose the surface of the shallow trench isolation region. In some embodiments of the invention, recessing the semiconductor fin includes removing the sacrificial region. At block 1308, a source or drain (S / D) region is formed on the exposed surface of the shallow trench isolation region.

[0096] At frame 1310, contact trenches are formed between the surface exposing the S / D region and the surface of the dielectric pillars. In some embodiments of the invention, the dielectric pillars serve as etch stops during the formation of the contact trenches. In some embodiments of the invention, trench silicide is formed in the contact trenches.

[0097] In some embodiments of the invention, a sacrificial region is formed on the semiconductor fin prior to the formation of the dielectric pillar. As previously discussed herein, the sacrificial region can be used to widen the source / drain regions.

[0098] In some embodiments of the invention, a conformal liner is formed on the S / D region and the dielectric pillar. In some embodiments of the invention, an interlayer dielectric is formed over the conformal liner. In some embodiments of the invention, forming a contact trench includes removing portions of the interlayer dielectric and the conformal liner.

[0099] The methods and structures described herein can be used to manufacture IC chips. Manufacturers can distribute the resulting IC chips as raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare chips, or in packages. In the latter case, the chips are mounted in a single-chip package (e.g., a plastic carrier with leads that are attached to a motherboard or other more advanced carrier) or a multi-chip package (e.g., a ceramic carrier with one or both surface-mount and buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes the IC chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0100] Various embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments may be devised without departing from the scope of the invention. Although various connections and positional relationships (e.g., above, below, adjacent / proximity, etc.) between elements are illustrated in the following description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent, while maintaining the described functionality even if the orientation is changed. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and the invention is not intended to be limiting in this respect. Similarly, the term "coupling" and its variations describe the presence of a communication path between two elements and do not imply a direct connection between the elements without any intermediate elements / connections between them. All such variations are considered part of the specification. Thus, coupling of entities can refer to direct or indirect coupling, and positional relationships between entities can be direct or indirect positional relationships. As an example of an indirect positional relationship, this specification mentions that forming layer "A" on layer "B" includes cases where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", provided that the relevant characteristics and functions of layer "A" and layer "B" are not substantially altered by the intermediate layers (one or more).

[0101] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms “comprising,” “including,” “having,” “containing,” or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such compositions, mixtures, processes, methods, articles, or apparatus.

[0102] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0103] References to "an embodiment," "embodiment," "example embodiment," etc., in this specification indicate that the described embodiment may include a particular feature, structure, or characteristic; however, each embodiment may or may not include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed that incorporating other embodiments to affect that feature, structure, or characteristic is within the knowledge of those skilled in the art, regardless of whether it is explicitly described.

[0104] For the purposes described below, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall apply to the described structures and methods, as oriented as shown in the accompanying drawings. The terms “cover,” “on top,” “positioned on,” or “positioned on top” indicate that a first element, such as a first structure, is present on a second element, such as a second structure, wherein an intermediate element, such as an interface structure, may be present between the first and second elements. The term “direct contact” refers to the connection of the first element (e.g., the first structure) and the second element (e.g., the second structure) at the interface between the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0105] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “over,” etc., are used herein to describe the relationship between one element or feature and another element(s) or feature(s) as shown in the accompanying drawings. It should be understood that spatial relative terms are intended to include different orientations of the device in use or operation other than those shown in the figures. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features would be oriented as “above” other elements or features. Therefore, the term “below” can include both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0106] The terms “about,” “substantially,” “approximately,” and variations thereof are intended to include the degree of error associated with a measurement based on a specific quantity of the device available at the time of filing this application. For example, “about” may include a range of ±8%, 5%, or 2% of a given value.

[0107] The phrase “selective,” for example, “selective first element to second element,” means that the first element can be etched while the second element can act as an etch stop.

[0108] The term “conformal” (e.g., conformal layer or conformal deposition) means that the thickness of the layer is substantially the same on all surfaces, or the thickness variation is less than 15% of the nominal thickness of the layer.

[0109] The terms "epitaxy growth and / or deposition" and "epitaxy formation and / or growth" refer to the growth of a semiconductor material (crystal material) on a deposition surface of another semiconductor material (crystal material), wherein the grown semiconductor material (crystal capping layer) has substantially the same crystal properties as the semiconductor material (seed material) deposited on the surface. In the epitaxial deposition process, chemical reactants provided by a source gas can be controlled, and system parameters can be set such that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move on the surface, causing the deposited atoms to orient themselves towards the crystal arrangement of atoms on the deposition surface. The epitaxially grown semiconductor material can have substantially the same crystal properties as the deposition surface on which the epitaxial growth material is formed. For example, the semiconductor material deposited on... <100> Semiconductor materials epitaxially grown on oriented crystal surfaces can exhibit <100> Orientation. In some embodiments of the invention, the epitaxial growth and / or deposition process may selectively form on a semiconductor surface and may deposit materials on or not on other exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0110] As previously mentioned, for the sake of brevity, conventional techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. However, as background, a more general description of semiconductor device manufacturing processes that can be used to implement one or more embodiments of the present invention will now be provided. Although specific manufacturing operations used in implementing one or more embodiments of the present invention may be individually known, the combination of described operations and / or the resulting structure of the invention is unique. Thus, the unique combination of operations described in conjunction with the manufacture of semiconductor devices according to the present invention utilizes a variety of individually known physical and chemical processes performed on semiconductor (e.g., silicon) substrates, some of which are described in the following paragraphs.

[0111] Generally, the various processes used to form microchips that will be packaged into ICs are categorized into four general types: film deposition, removal / etching, semiconductor doping, and patterning / photolithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), etc. For example, reactive ion etching (RIE) is a dry etching method that uses chemically reactive plasma to remove material, such as a mask pattern for semiconductor material, by exposing the material to ion bombardment that removes portions of the material from the exposed surface. The plasma is typically generated by an electromagnetic field under low pressure (vacuum). Semiconductor doping alters electrical properties by doping, for example, transistor sources and drains, typically through diffusion and / or ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopants. Films of conductors (e.g., polycrystalline silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of individual regions of a semiconductor substrate allows the substrate's conductivity to change with the application of voltage. By forming structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate so that the pattern can be subsequently transferred onto the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called a photoresist. To build the numerous wirings of the millions of transistors that constitute the complex structure of the transistor and the interconnecting circuits, the photolithography and etching pattern transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped regions are slowly built up to form the final device.

[0112] The flowcharts and block diagrams in the accompanying drawings illustrate possible implementations of manufacturing and / or operating methods according to various embodiments of the invention. Various functions / operations of the method are represented by boxes in the flowcharts. In some alternative implementations, the functions indicated in the boxes may occur in a different order than indicated in the figures. For example, two boxes shown consecutively may actually be executed substantially simultaneously, or these boxes may sometimes be executed in reverse order, depending on the functions involved.

[0113] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the described embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments described herein.

[0114] In a preferred embodiment of the invention described herein, a method for forming a semiconductor device is provided, the method comprising: forming a semiconductor fin on a substrate; forming a dielectric pillar adjacent to the semiconductor fin, the dielectric pillar being located on a shallow trench isolation region of the substrate; recessing the semiconductor fin to expose a surface of the shallow trench isolation region; forming a source or drain (S / D) region on the exposed surface of the shallow trench isolation region; and forming a contact trench between the surface of the exposed S / D region and the surface of the dielectric pillar. The method preferably further comprises forming a sacrificial region on the semiconductor fin prior to forming the dielectric pillar. Recessing the semiconductor fin preferably includes removing the sacrificial region. In another preferred embodiment of the invention described herein, a semiconductor device is provided comprising: a semiconductor fin located on a substrate; a dielectric pillar adjacent to the semiconductor fin, the dielectric pillar being located on a shallow trench isolation region of the substrate; a source or drain (S / D) region on the surface of the shallow trench isolation region; and a trench silicide located on the surface of the S / D region and the surface of the dielectric pillar. The S / D region is preferably confined between opposing sidewalls of the dielectric pillar. The device preferably also includes a conformal liner on the dielectric pillar. The device preferably also includes an interlayer dielectric on a conformal liner, wherein trench silicides are located between opposite sidewalls of the interlayer dielectric.

Claims

1. A method for forming a semiconductor device, the method comprising: A bottom isolation structure is formed on the substrate; A stack of nanosheets is formed on the bottom isolation structure, the bottom isolation structure being between the stack of nanosheets and the substrate; A sacrificial region is formed on the nanosheet stack, and the sacrificial region is in direct contact with the bottom isolation structure; Dielectric pillars are formed adjacent to the nanosheets, and the dielectric pillars are located directly on the shallow trench isolation region of the substrate, and the dielectric pillars are in direct contact with the sidewalls of the sacrificial region; Remove the sacrificial area to expose the surface of the bottom isolation structure and the surface of the shallow trench isolation area; A conformal liner is formed on the source or drain S / D region and the dielectric pillar; An interlayer dielectric is formed on the conformal liner; Remove portions of the interlayer dielectric and the conformal liner to form contact trenches that expose the surface of the S / D region and the surface of the dielectric pillar; as well as Trench silicide is formed in the contact trench.

2. The method of claim 1, wherein the dielectric pillar serves as an etch stop during the formation of the contact trench.

3. A semiconductor device, comprising: Nanosheets stacked on a substrate; Dielectric pillars adjacent to the nanosheet stack are located on the surface of the shallow trench isolation region of the substrate and are in direct contact with it. Source or drain S / D region, the S / D region being on the surface of the shallow trench isolation region and in direct contact with it such that the bottom surface of the S / D region and the bottom surface of the dielectric pillar are coplanar; as well as Trench silicide, the trench silicide being on and in direct contact with the top surface of the S / D region and the trench silicide being on and in direct contact with the top surface of the dielectric pillar.

4. The semiconductor device of claim 3, wherein the S / D region is confined between the opposing sidewalls of the dielectric pillars.

5. The semiconductor device of claim 3, further comprising a bottom isolation structure between the substrate and the nanosheet stack.

6. The semiconductor device of claim 3, further comprising a conformal liner on the dielectric pillar.

7. The semiconductor device of claim 6, further comprising an interlayer dielectric over the conformal liner, wherein the trench silicide is located between opposing sidewalls of the interlayer dielectric.

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