A method of accessing NVM and an NVM controller

Abstract

The application discloses a method for accessing NVM and an NVM controller, comprising: processing a first user command indicating reading NVM by executing a micro instruction sequence, and checking whether block addresses and page addresses corresponding to the first user command are same as block addresses and page addresses corresponding to a second user command according to a block / page reading address checking micro instruction in the micro instruction sequence, wherein the second user command indicates reading NVM, and the second user command appears before the first user command; if the block addresses and the page addresses corresponding to the first user command are same as the block addresses and the page addresses corresponding to the second user command, reading data from a first cache corresponding to a first parallel unit to be accessed by the first user command to respond to the first user command. Through the technical scheme of the application, a user of a storage device can participate in flexible control of cache utilization without depending on a storage controller to judge whether data is cached.

Description

Technical Field

[0001] This invention relates to solid-state storage devices (SSDs), and more specifically, to the execution of block / page address checking microinstructions in a memory controller. Background Technology

[0002] Similar to hard disk drives (HDDs), solid-state storage devices (SSDs) are also high-capacity, non-volatile storage devices used in computer systems. SSDs typically use non-volatile memory (NVM) such as flash memory as their storage medium. Figure 1 The diagram shown is a block diagram of a prior art storage system. It mainly includes a host system 110 and a solid-state storage device 120. The solid-state storage device 120 includes an interface module 130, a storage controller 140, and a Flash array 160 composed of multiple flash memory chips 150. The interface module 130 is mainly used to implement interface protocols for communication with the host system, such as SATA (Serial Advanced Technology Attachment), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), SCSI (Small Computer System Interface), iSCSI (Internet Small Computer System Interface), and IDE (Integrated Drive Electronics). Through the interface module 130, the solid-state storage device presents a standard storage device with a certain logical or physical address space to the host system. The storage controller 140 is the control core of the entire storage device, mainly responsible for the transmission of control signals and data between the interface module 130 and the flash array 160, flash memory management, conversion or mapping of host logical addresses to flash physical addresses, wear leveling, and / or bad block management. The storage controller 140 can be implemented by software, hardware, firmware, or a combination thereof.

[0003] The storage controller 140 accesses the flash memory chips 150 in the flash memory array 160 by sending commands to them. Commands for accessing the flash memory chips 150 include, for example, reading, programming, and / or erasing. Data is written to or read from the flash memory chips 150 on a page-by-page basis. The flash memory chips 150 provide predetermined page sizes, with each page being, for example, 2KB, 4KB, 8KB, or 16KB.

[0004] The host 110's file system or device driver also accesses the storage device in data blocks of a predetermined size. These predetermined-size data blocks can be referred to as blocks, pages, or sectors. The size of these data blocks may be the same as or different from the page size of the flash memory chip 150.

[0005] Chinese patent application CN1414468A discloses a scheme for processing CPU (Central Processing Unit) instructions by executing microinstruction sequences. When the CPU needs to process a specific instruction, a conversion logic circuit converts the specific instruction into a corresponding microinstruction sequence, and the function of the specific instruction is implemented by executing the microinstruction sequence. The microinstruction sequence or a template of the microinstruction sequence is stored in ROM (Read Only Memory). During the process of converting a specific instruction into a microinstruction sequence, the microinstruction sequence template can be filled to correspond to the specific instruction.

[0006] A memory target is one or more logic units within a NAND flash memory chip's 150 package that share a chip enable (CE) signal. Each logic unit has a logic unit number (LUN). A NAND flash memory package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, while multiple logic units within a NAND flash memory chip can execute commands and report status independently of each other. The meanings of target, logic unit, LUN, and plane are provided in the "Open NAND Flash Interface Specification (Revision 3.0)" available at http: / / www.micron.com / ~ / media / Documents / Products / Other%20Documents / ONF I3_0Gold.ashx.

[0007] Chinese patent application CN102177556A discloses a flash memory translation layer (FTL) and illustrates an example of a lookup table for parallel cells in the FTL. Since logic units in a flash memory chip can be accessed in parallel, parallel cells can also be logic units. A logic unit can include multiple planes, and parallel cells can also be planes. Summary of the Invention

[0008] In some application scenarios, the page size of the NVM differs from the page size requested by the application. For example, the data unit size for an operating system's I / O access request might be 512 bytes, while the NVM page size might be 4KB, 8KB, or 16KB. After data is read from the NVM in response to an I / O access request, a significant amount of the read data may not be used by the current I / O request. However, due to data locality or other reasons, the data read from the NVM might be used in subsequent I / O access requests. Therefore, when data needs to be read from flash memory, a flexible way to determine whether the data already exists in the storage controller's cache is desirable. There are various reasons why data might be cached, and the method for determining whether data already exists in the storage controller's cache should be adaptable to different reasons. Furthermore, it is expected that users of the storage device can participate in the flexible control of cache utilization, rather than relying on the storage controller to determine whether data is cached.

[0009] To achieve the above objectives, this invention responds to commands from a host or user by executing a sequence of microinstructions. The microinstruction execution unit executes the microinstruction sequence to issue operation commands to the flash memory chips and / or receive data or other information read from the flash memory chips. Users of the storage device can participate in the flexible control of the cache utilization of the storage controller by programming, updating, and / or modifying the microinstruction sequence.

[0010] According to a first aspect of the present invention, a method for accessing an NVM is provided, comprising: processing a first user command instructing the reading of an NVM; checking whether the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to a second user command, wherein the second user command instructs the reading of an NVM, the second user command occurs before the first user command, and the second command and the first user command access the same first parallel unit; if the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, reading data from a first cache corresponding to the first parallel unit to respond to the first user command.

[0011] According to one embodiment of the first aspect of the present invention, the method further includes: if the block address and page address corresponding to the first user command are different from the block address and page address corresponding to the second user command, issuing an NVM read command to the NVM.

[0012] According to one embodiment of the first aspect of the invention, a first cache is provided for a first user command to access a first parallel unit, and a second cache is provided for a first user command to access a second parallel unit.

[0013] According to one embodiment of the first aspect of the present invention, in response to the second user command, data corresponding to the block address and page address corresponding to the second user command is read from the NVM and written to the first cache.

[0014] According to one embodiment of the first aspect of the present invention, if the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, a flag register is set; and if the block address and page address corresponding to the first user command are different from the block address and page address corresponding to the second user command, the flag register is cleared.

[0015] According to one embodiment of the first aspect of the present invention, if the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, the execution jumps to the first microinstruction sequence to read data from the first cache corresponding to the first parallel unit; and if the block address and page address corresponding to the first user command are different from the block address and page address corresponding to the second user command, the execution jumps to the second microinstruction sequence to issue an NVM read command to the NVM.

[0016] According to one embodiment of the first aspect of the present invention, in response to the first user command, if the block address and page address corresponding to the first user command are different from the block address and page address corresponding to the second user command, data corresponding to the block address and page address corresponding to the first user command is further read from the NVM and written to the first cache.

[0017] According to one embodiment of the first aspect of the present invention, the first user command corresponds to a first segment address, and the second user command corresponds to a second segment address.

[0018] According to one embodiment of the first aspect of the present invention, the first user command instructs the acquisition of data in a first address range, and the second user command instructs the acquisition of data in a second address range.

[0019] According to one embodiment of the first aspect of the present invention, in response to the second user command, page data corresponding to the block address and page address corresponding to the second user command is read from the NVM and written to the first cache, wherein the page data includes first segment data and second segment data.

[0020] According to one embodiment of the first aspect of the present invention, the method further includes: processing a third user command instructing the reading of the NVM, accessing a second parallel unit according to the third user command, and reading data from the NVM corresponding to the block address and page address corresponding to the third user command and writing it into a second cache.

[0021] According to one embodiment of the first aspect of the present invention, if the flag register is set, execution jumps to a first microinstruction sequence to read data from a first cache corresponding to the first parallel unit; and if the flag register is cleared, execution jumps to a second microinstruction sequence to issue an NVM read command to the NVM.

[0022] According to a second aspect of the present invention, a method for accessing an NVM is also provided, comprising: processing a first user command instructing the reading of the NVM; checking whether the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to a second user command, wherein the second user command instructs the writing of the NVM, the second user command occurs before the first user command, and the second command and the first user command access the same parallel unit; if the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, reading data from a cache corresponding to the parallel unit to respond to the first user command.

[0023] According to an embodiment of the second aspect of the present invention, it further includes: if the block address and page address corresponding to the user command are different from the block address and page address corresponding to the second user command, issuing an NVM read command to the NVM.

[0024] According to a third aspect of the present invention, an NVM controller is also provided, comprising: a microinstruction memory for storing a sequence of microinstructions; a microinstruction execution unit for decoding the microinstructions and executing the operations corresponding to the microinstructions; a program counter for indicating the storage location of the microinstructions in the microinstruction memory; a general-purpose register set, wherein registers in the general-purpose register set can be accessed through the microinstructions in the sequence of microinstructions; a user command memory for storing user commands; and a context memory for storing context information corresponding to the sequence of microinstructions.

[0025] According to an embodiment of a third aspect of the present invention, the microinstruction execution unit retrieves a first microinstruction from the microinstruction memory based on a program counter; the microinstruction execution unit decodes the first microinstruction, and when the first microinstruction is a read address check microinstruction, the microinstruction execution unit accesses the user command memory based on the offset value of the read address check microinstruction to obtain a first block address and a first page address; the microinstruction execution unit accesses the context memory to obtain a second block address and a second page address stored in the context information of the current microinstruction sequence; the microinstruction execution unit compares the first block address with the second address, and the first page address with the second page address; if the first block address and the second address are the same, and the first page address and the second page address are the same, the microinstruction execution unit sets the general-purpose register indicated by the register index in the general-purpose register group based on the register index of the read address check microinstruction.

[0026] According to an embodiment of a third aspect of the present invention, if the first block address is different from the second block address, or the first page address is different from the second page address, the microinstruction execution unit checks the register index of the microinstruction based on the read address and clears the general-purpose registers in the general-purpose register set indicated by the register index; and the microinstruction execution unit increments the program counter.

[0027] According to an embodiment of a third aspect of the present invention, the microinstruction execution unit accesses the user command memory to further obtain the address of the first parallel unit; the microinstruction execution unit accesses the user command memory to obtain the address of the second block and the address of the second page stored in the context information of the current microinstruction sequence based on the address of the first parallel unit.

[0028] According to one embodiment of a third aspect of the present invention, execution of a microinstruction sequence is initiated in response to a user command in a user command memory, and a first context memory is executed for the microinstruction sequence according to a parallel unit accessed by the user command. The microinstruction execution unit accesses the first context memory to obtain a second block address and a second page address stored in the context information of the current microinstruction sequence.

[0029] According to a fourth aspect of the present invention, an NVM controller is also provided, comprising: a microinstruction memory for storing microinstruction sequences; a microinstruction execution unit for decoding microinstructions and executing operations corresponding to the microinstructions; a program counter for indicating the storage location of microinstructions in the microinstruction memory; a user command memory for storing user commands; and a context memory for storing context information corresponding to the microinstruction sequences.

[0030] According to a fourth aspect of the present invention, the microinstruction execution unit retrieves a first microinstruction from a microinstruction memory based on a program counter. The microinstruction execution unit decodes the first microinstruction. When the first microinstruction is a read address check microinstruction, the microinstruction execution unit accesses a user command memory based on the offset value of the read address check microinstruction to obtain a first block address and a first page address. The microinstruction execution unit accesses a context memory to obtain a second block address and a second page address stored in the context information of the current microinstruction sequence. The microinstruction execution unit compares the first block address with the second address, and the first page address with the second page address. If the first block address and the second address are the same, and the first page address and the second page address are the same, the microinstruction execution unit sets the program counter based on the first address of the read address check microinstruction. If the first block address and the second address are different, or the first page address and the second page address are different, the microinstruction execution unit increments the program counter to the second address.

[0031] According to a fourth aspect of the present invention, the microinstruction execution unit retrieves a first microinstruction from a microinstruction memory based on a program counter. The microinstruction execution unit decodes the first microinstruction. When the first microinstruction is a read address check microinstruction, the microinstruction execution unit accesses a user command memory based on the offset value of the read address check microinstruction to obtain a first block address and a first page address. The microinstruction execution unit accesses a context memory to obtain a second block address and a second page address stored in the context information of the current microinstruction sequence. The microinstruction execution unit compares the first block address with the second address, and the first page address with the second page address. If the first block address and the second address are different, or the first page address and the second page address are different, the microinstruction execution unit sets the program counter based on the first address of the read address check microinstruction. If the first block address and the second address are the same, and the first page address and the second page address are the same, the microinstruction execution unit increments the program counter to the second address.

[0032] According to one embodiment of the fourth aspect of the invention, the context memory further stores data read from a second block address and a second page address in the NVM prior to processing the user command.

[0033] According to one embodiment of the fourth aspect of the invention, the context memory further stores data written to a second block address and a second page address of the NVM before processing the user command.

[0034] According to one embodiment of a fourth aspect of the present invention, the microinstruction memory stores a sequence of microinstructions for retrieving data from a cache, starting from the first address.

[0035] According to one embodiment of the fourth aspect of the present invention, the microinstruction memory stores a sequence of microinstructions for issuing an NVM read command to the NVM, starting from the second address.

[0036] According to one embodiment of a fourth aspect of the present invention, the microinstruction memory stores a sequence of microinstructions for issuing an NVM read command to the NVM, starting from the first address.

[0037] According to one embodiment of a fourth aspect of the invention, the microinstruction memory stores a sequence of microinstructions for retrieving data from a cache, starting from the second address.

[0038] According to a fifth aspect of the present invention, a method for executing a read address check microinstruction in an NVM interface controller is also provided, comprising: retrieving a first microinstruction; decoding the first microinstruction to determine that the first microinstruction is a read address check microinstruction, wherein the read address check microinstruction includes a register index and an offset value, the register index being used to indicate a flag register storing the execution result of the read address check instruction, and the offset value being used to indicate the storage location of a user command; obtaining a first block address and a first page address corresponding to the user command based on the offset value; obtaining a second block address and a second page address based on the context information of the read address check microinstruction; if the first block address and the second address are the same, and the first page address and the second page address are the same, then setting the flag register according to the register index; if the first block address and the second address are different, or the first page address and the second page address are different, then clearing the flag register according to the register index.

[0039] According to a sixth aspect of the present invention, a method for executing a read address check microinstruction in an NVM interface controller is also provided, comprising: retrieving the read address check microinstruction, wherein the read address check microinstruction includes a register index and an offset value, the register index being used to indicate a flag register storing the execution result of the read address check instruction, and the offset value being used to indicate the storage location of a user command; decoding the read address check microinstruction; obtaining a first block address and a first page address corresponding to the user command based on the offset value; obtaining a second block address and a second page address based on the context information of the read address check microinstruction; if the first block address and the second address are the same, and the first page address and the second page address are the same, then setting the flag register based on the register index; if the first block address and the second address are different, or the first page address and the second page address are different, then clearing the flag register based on the register index.

[0040] According to a sixth aspect of the present invention, the second block address and the second page address are the block address and page address of the NVM corresponding to a user command that occurred prior to the user command.

[0041] According to a sixth aspect of the present invention, the user command instructs the reading of data from the storage locations corresponding to the first block address and the first page address of the NVM.

[0042] According to one embodiment of the sixth aspect of the invention, the remaining user commands are commands instructing the reading of data from the NVM or the writing of data to the NVM.

[0043] According to a seventh aspect of the present invention, a method for executing a read address check microinstruction in an NVM interface controller is also provided, comprising: retrieving the read address check microinstruction, wherein the read address check microinstruction includes a register index and an offset value, the register index being used to indicate a flag register storing the execution result of the read address check instruction, and the offset value being used to indicate the storage location of a user command; decoding the read address check microinstruction; obtaining a first parallel unit address, a first block address, and a first page address corresponding to the user command based on the offset value; obtaining a second block address and a second page address based on the first parallel unit address, wherein if the first block address and the second address are the same, and the first page address and the second page address are the same, then the flag register is set according to the register index; if the first block address and the second address are different, or the first page address and the second page address are different, then the flag register is cleared according to the register index.

[0044] According to a seventh aspect of the present invention, the second block address and the second page address are the block address and page address of the NVM corresponding to other user commands that occurred before the user command.

[0045] According to a seventh aspect of the present invention, the user command instructs the reading of data from the storage location corresponding to the first block address and the first page address of the NVM.

[0046] According to one embodiment of the seventh aspect of the invention, the remaining user commands are commands instructing the reading of data from the NVM or the writing of data to the NVM.

[0047] According to an eighth aspect of the present invention, a method for executing a read address check microinstruction in an NVM interface controller is also provided, comprising: retrieving the read address check microinstruction, wherein the read address check microinstruction includes a register index and an offset value, the register index being used to indicate a flag register storing the execution result of the read address check instruction, the offset value being used to indicate the storage location of a user command, the read address check instruction further including a first address; decoding the read address check microinstruction; obtaining a first block address and a first page address corresponding to the user command based on the offset value; obtaining a second block address and a second page address based on the context information of the read address check microinstruction, wherein if the first block address and the second address are the same, and the first page address and the second page address are the same, then setting the program counter of the NVM interface controller to the first address; wherein a sequence of microinstructions for retrieving data from a cache is stored starting from the first address.

[0048] According to an embodiment of the eighth aspect of the present invention, if the first block address is different from the second block address, or the first page address is different from the second page address, the program counter of the NVM interface controller is set to the second address; wherein the second address begins to store the microinstruction sequence for issuing an NVM read command to the NVM.

[0049] According to an eighth aspect of the present invention, if the first block address is the same as the second block address and the first page address is the same as the second page address, the method further includes: setting a flag register according to a register index.

[0050] According to an eighth aspect of the present invention, if the first block address is different from the second block address, or the first page address is different from the second page address, the method further includes: clearing the flag register based on the register index.

[0051] According to a ninth aspect of the present invention, a method for executing a read address check microinstruction in an NVM interface controller is also provided, comprising: retrieving the read address check microinstruction, wherein the read address check microinstruction includes a register index and an offset value, the register index being used to indicate a flag register storing the execution result of the read address check instruction, the offset value being used to indicate the storage location of a user command, the read address check instruction further including a first address; decoding the read address check microinstruction; obtaining a first block address and a first page address corresponding to the user command based on the offset value; obtaining a second block address and a second page address based on the context information of the read address check microinstruction, wherein if the first block address and the second address are the same, and the first page address and the second page address are different, then setting the program counter of the NVM interface controller to the first address; wherein a sequence of microinstructions for issuing an NVM read command to the NVM is stored starting from the first address.

[0052] According to one embodiment of the ninth aspect of the present invention, if the first block address is different from the second block address, or the first page address is different from the second page address, the program counter of the NVM interface controller is set to the second address; wherein the second address begins to store the microinstruction sequence for retrieving data from the cache.

[0053] According to a ninth aspect of the present invention, if the first block address is the same as the second block address and the first page address is the same as the second page address, the method further includes: setting a flag register according to a register index.

[0054] According to a ninth aspect of the present invention, if the first block address is different from the second block address, or the first page address is different from the second page address, the method further includes: clearing the flag register based on the register index.

[0055] According to a tenth aspect of the present invention, a computer program comprising computer program code is provided, which, when loaded into and executed on a computer system, causes the computer system to perform the method described above.

[0056] According to an eleventh aspect of the present invention, a program including program code is provided, which, when loaded into a storage device and executed on the storage device, causes the storage device to perform the method described above.

[0057] The technical solution of this invention enables flexible determination of whether data already exists in the cache of the storage controller, allowing users of the storage device to participate in flexible control of cache utilization without relying on the storage controller to determine whether data is cached. Attached Figure Description

[0058] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings, letter designations following reference numerals indicate multiple identical parts, and when referring to these parts generically, their final letter designations are omitted. In the drawings:

[0059] Figure 1 A block diagram of a prior art storage system is shown;

[0060] Figure 2 A structural block diagram of the components of a memory controller for processing microinstructions according to an embodiment of the present invention is shown;

[0061] Figure 3 A schematic diagram illustrating the format of a block / page read address checking microinstruction according to an embodiment of the present invention is shown;

[0062] Figure 4-1 A flowchart illustrating a method for accessing the NVM according to an embodiment of the present invention is shown;

[0063] Figure 4-2 A flowchart illustrating a method for accessing the NVM according to an embodiment of the present invention is shown;

[0064] Figure 4-3 A flowchart illustrating a method for accessing the NVM according to an embodiment of the present invention is shown;

[0065] Figure 5 A flowchart of a method for accessing the NVM according to another embodiment of the present invention is shown;

[0066] Figure 6A A flowchart is shown illustrating a method for executing read address check microinstructions in an NVM interface controller according to another embodiment of the present invention;

[0067] Figure 6B A flowchart illustrating a method for executing read address check microinstructions in an NVM interface controller and subsequent operations according to another embodiment of the present invention is shown.

[0068] Figure 7A A flowchart illustrating a method for executing read address check microinstructions in an NVM interface controller according to another embodiment of the present invention is shown; and

[0069] Figure 7BA flowchart illustrating a method for executing read address check microinstructions in an NVM interface controller and subsequent operations according to another embodiment of the present invention is shown.

[0070] In the accompanying drawings, the same or similar labels are used to refer to the same or similar elements. Detailed Implementation

[0071] The present invention will now be further described with reference to the accompanying drawings and specific embodiments.

[0072] Figure 2 A structural block diagram of components of a memory controller for processing microinstructions according to an embodiment of the present invention is shown. To implement the processing of microinstructions, the memory controller of the storage device may include a microinstruction execution unit 210, a command queue 220, an interface controller 230, a microinstruction memory 240, a context memory 260, and / or general-purpose registers 250.

[0073] Microinstruction memory 240 is used to store microinstructions. Microinstruction execution unit 210 reads and executes microinstructions from microinstruction memory 240. Microinstructions cause microinstruction execution unit 210 to issue commands to the flash memory chip via interface controller 230 to access the flash memory chip, including, for example, commands such as read, program, erase, pause, read flash memory chip characteristics, and / or read set flash memory chip characteristics. Microinstructions also cause microinstruction execution unit 210 to obtain data read from the flash memory chip via interface controller 230. One or more microinstructions may correspond to one of the commands to access the flash memory chip, such as read, program, erase, and / or pause. Microinstructions also include branch and jump microinstructions, which cause microinstruction execution unit to change the order in which microinstructions are executed. Microinstructions also include block / page read address check microinstructions. These will be discussed in conjunction with... Figure 3 A detailed explanation of the block / page read address checking microinstructions.

[0074] The microinstruction memory 240 can store one or more microinstruction sequences. For example, in... Figure 2 The microinstruction memory 240 stores n microinstruction sequences, including microinstruction sequence 1, microinstruction sequence 2, ..., and microinstruction sequence n. Each of microinstruction sequence 1, microinstruction sequence 2, ..., and microinstruction sequence n contains multiple microinstructions.

[0075] Multiple microinstructions in a microinstruction sequence can be executed by the microinstruction execution unit 210. Each microinstruction sequence has its own execution state, allowing the execution of each microinstruction to be paused and resumed. The microinstruction execution unit 210 can pause the currently executing microinstruction sequence and select to execute other microinstruction sequences. Concession microinstructions can also be provided in the microinstruction sequence; when a concession microinstruction is executed, the microinstruction execution unit 210 can schedule and execute other microinstruction sequences. When the microinstruction execution unit 210 pauses the currently executing microinstruction sequence or executes a concession microinstruction, the execution state of the currently executing microinstruction sequence is saved; when the microinstruction execution unit resumes the execution of the microinstruction sequence, it reads the saved execution state and continues the execution of the resumed microinstruction sequence.

[0076] The interface controller 230 is coupled to the flash memory chip and is used to issue commands to the flash memory chip to access the flash memory chip, including, for example, read, program, erase, pause and / or resume; it is also used to obtain data read from the flash memory chip.

[0077] Command queue 220 is used to cache commands from the user or upper-level system. Commands from the user or upper-level system may include read, write, delete, and mark as invalid commands, as well as commands to read storage device status, read / set flash memory chip characteristics, and user-defined commands. Command queue 220 may be implemented using memory, a first-in-first-out memory register file, etc. Microinstruction execution unit 210 can access command queue 220. For example, when executing a microinstruction, microinstruction execution unit 210 accesses command queue 220 according to the microinstruction.

[0078] When processing commands in command queue 220, a microinstruction sequence corresponding to the command is obtained, and the microinstruction execution unit 210 executes the microinstruction sequence to complete the processing of commands in command queue 220. The conversion from processing commands in command queue 220 to microinstruction sequences can be implemented by a conversion circuit (not shown). Alternatively, the microinstruction execution unit 210 can also implement the conversion. During the process of obtaining the microinstruction sequence, it can be padded or adapted based on the commands in command queue 220 to make the microinstruction sequence compatible with the commands in command queue 220. The microinstruction sequence also controls the microinstruction execution unit 210 to access and process commands in command queue 220, and selects the corresponding microinstruction sequence to execute based on the commands in command queue 220.

[0079] General-purpose register 250 is coupled to microinstruction execution unit 210 and is used to store and provide the execution state of the microinstruction sequence. The execution state of the microinstruction sequence includes the program counter (PC), general-purpose registers (GR), physical address registers, and / or timers, etc. The program counter indicates the address of the currently executing microinstruction in the microinstruction sequence. The physical address register indicates the address of the flash memory chip accessed by the microinstruction sequence.

[0080] Context memory 260 is used to store the execution state of microinstruction sequences. The execution state of the microinstruction sequences stored in context memory 260 may include the contents of general-purpose register 250. Context memory 260 can store the execution state of one or more microinstruction sequences. Microinstruction sequences with their state information stored in context memory 260 can be scheduled to resume execution. By restoring the state information corresponding to a microinstruction sequence stored in context memory 260 to general-purpose register 250, microinstruction execution unit 210 can resume the execution of that microinstruction sequence. The executed microinstruction sequence is called a thread. The same microinstruction sequence has its own execution state each time it is executed, thus multiple threads can be created based on the same microinstruction sequence. Context memory 260 stores the execution state for each thread.

[0081] In embodiments of the invention, threads are created or used based on the parallel units to be accessed. For example, a first thread is used to access a first parallel unit, and / or a second thread is used to access a second parallel unit. In one example, the number of threads that the context memory 260 can accommodate is the same as... Figure 2 The number of parallel cells of the flash memory chips coupled to the microinstruction processing unit is the same; a thread is allocated or reserved for each parallel cell; when a request for a parallel cell is processed, the thread corresponding to that parallel cell is scheduled. In one example, the number of threads that the context memory 260 can accommodate is less than the number of parallel cells coupled to the microinstruction processing unit. Figure 2 The number of parallel units coupled to the component that processes microinstructions. When processing a request for a parallel unit, either use the thread already allocated to process that parallel unit or allocate a new thread to process the request.

[0082] A parallel cell cache is provided to store data read from or written to the parallel cell. A parallel cell cache is provided for each thread. The size of the parallel cell cache corresponds to 150 flash memory chips (see [link]). Figure 1 The page size. Providing a larger parallel cell cache is beneficial for improving performance. In one example, the parallel cell cache is provided in context memory 260. In another example, it is provided by DRAM or other external... Figure 2 The memory of the microinstruction processing unit is used to provide parallel unit cache.

[0083] Figure 3 The format of a block / page read address check microinstruction according to an embodiment of the present invention is shown. The block / page read address check microinstruction includes an opcode field, a register field, and an offset field. The opcode field indicates that the microinstruction is a block / page read address check microinstruction through a specific identifier or value. The register field indicates the general-purpose register modified by the block / page read address check microinstruction (see [link to documentation]). Figure 2 The name or number of the general-purpose register 250. The offset value field indicates the command corresponding to the microinstruction checked for the block / page read address in command queue 220 (see...). Figure 2 The position within the command queue 220. In one example, the offset value field indicates the storage location of the command to be inspected within the command queue 220. For instance, the command to be inspected is a read command or a programming command that was processed before the currently being processed command.

[0084] In one example, the value indicated by the offset field is incremented at the base address to obtain the storage location of the command in command queue 220. Note that the base address field is not included in this block / page read address check microinstruction; instead, a global base address register or base address index is provided for the thread or individual microinstructions, allowing the base address to be obtained when executing the block / page read address check microinstruction. In another example, the offset field is used alone to obtain the storage location of the command in command queue 220. In yet another example, the offset field indicates the offset between the command being checked and the currently processed command. In yet another example, the offset field is a register address or number, allowing the offset information to be modified at runtime by modifying the contents of the registers through the execution of a microinstruction sequence.

[0085] The commands within command queue 220 provide the parallel cell address, block address, and page address accessed by the command, thereby allowing the determination of a specific flash memory chip 150 (see [link to command queue]). Figure 1 ) Specific blocks and pages. For example, user_cmd[base+offset].block_page_address represents the block and page in command queue 220 (see reference). Figure 2 The combination of block address and page address provided by the command indexed by the offset value field in the command.

[0086] In embodiments of the present invention, each thread is provided with a block address register and a page address register that can serve as thread context, for storing block addresses and page addresses respectively. The block address and page address can be stored in various ways; for example, the block address and page address can be combined and stored in the same register. For example, `block_page_address` can represent the combination of block address and page address serving as a thread context. Microinstructions belonging to the same thread can access the block address and page address serving as thread context.

[0087] When executing the block / page read address check microinstruction according to the present invention, the microinstruction execution unit 210 (see...) Figure 2 The block / page read address check microinstruction compares the block and page addresses of the thread context with those of the commands in the command queue 220 processed by the thread. If they are the same, the general-purpose register indicated by the register (Reg) field of the block / page read address check microinstruction is set. If they are different, the general-purpose register indicated by the register (Reg) field of the block / page read address check microinstruction is cleared. A register set operation corresponds to writing a logical "1" or a logical "0" to a specific location in the register, while a register clear operation writes the opposite value to the register set operation to the same location. For example, the semantic representation of the block / page read address check microinstruction is as follows: GR[Reg] = (block_page_address == user_cmd[base+offset].block_page_address) ? 1 : 0. When block_page_address is the same as user_cmd[base+offset].block_page_address, the general-purpose register GR[Reg] is set to 1; otherwise, it is set to 0.

[0088] In an embodiment of the invention, a conditional branch microinstruction is also provided. Upon execution, the conditional branch microinstruction checks a specified general-purpose register. Depending on whether the specified general-purpose register is set or cleared, the conditional branch microinstruction sets the program counter (PC) to one of two different values ​​to instruct the microinstruction execution unit 210 to fetch the next microinstruction to be executed from a different location in the microinstruction memory 240.

[0089] In another embodiment of the invention, the operation of a block / page read address check microinstruction is combined with that of a conditional branch microinstruction to provide a fused microinstruction. The fused microinstruction includes a branch target field in addition to the opcode field, register field, and offset field.

[0090] When executing fused microinstructions, the microinstruction execution unit 210 (see...) Figure 2The block address and page address of the thread context are compared with the block address and page address of the commands in the command queue 220 processed by the thread. Based on the comparison result, the program counter (PC) is set to different values ​​to instruct the microinstruction execution unit 210 to fetch the next microinstruction to be executed from different locations in the microinstruction memory. For example, when the comparison result is true, the microinstruction execution unit 210 is instructed to fetch the microinstruction to be executed from the address of the next microinstruction after the current microinstruction; while when the comparison result is false, the microinstruction execution unit 210 is instructed to fetch the microinstruction to be executed from the address indicated by the branch target field. In this way, it is no longer necessary to use separate block / page read address checking microinstructions and conditional branch microinstructions; instead, the conditional branch semantics are integrated into the execution of the block / page read address checking microinstruction, thereby reducing the length of the microinstruction sequence and the storage space occupied by the microinstruction sequence in the microinstruction memory 240.

[0091] In another embodiment of the invention, when executing yet another fused microinstruction, the microinstruction execution unit 210 (see [reference]) Figure 2 The block address and page address used as the thread context are compared with the block address and page address of the commands in the command queue 220 processed by the thread. Based on the comparison result, the program counter (PC) is set to a different value to instruct the microinstruction execution unit 210 to fetch the next microinstruction to be executed from a different location in the microinstruction memory; and the general-purpose register indicated by the register (Reg) field of the block / page read address check microinstruction is set or cleared.

[0092] Figure 4-1 A flowchart illustrating a method for accessing the NVM according to an embodiment of the present invention is shown.

[0093] like Figure 4-1 As shown, the method for accessing NVM includes: Step 410: Processing a first user command; Step 420: Checking whether the block address and page address of the first user command are the same as the block address and page address corresponding to the second user command; Step 430: If the block address and page address of the first user command are the same as the block address and page address corresponding to the second user command, retrieving data from the first cache.

[0094] In step 410, for example, the first user command is the first read command, and processing of the first read command begins. (See previous section) Figure 2 The next command to be processed is retrieved from the command queue 220 and identified as the first read command. The microinstruction execution unit 210 executes the corresponding microinstruction sequence to process the first read command. In step 420, the microinstruction execution unit 210 executes the block / page read address check microinstruction provided according to the present invention (see also...). Figure 3The system uses a multi-step process to determine whether the block address and / or page address of the first read command are the same as the block address and / or page address of the second user command. The second user command is a command that the microinstruction execution unit 210 obtains from the command queue 210 and processes before processing the first read command. If they are the same, the process proceeds to step 430, where the data required by the first read command is retrieved from the cache. In an embodiment of the present invention, the second user command can be a read command or a write command. When processing the second user command, the data corresponding to the block address and / or page address of the second user command is moved to the cache. Therefore, when the first read command and the second user command have the same block address and / or page address, the data required by the first read command already exists in the cache. The data to be read by the first read command can be obtained from the cache, and there is no need to issue an NVM read command again, thereby speeding up the processing speed of the first read command.

[0095] Figure 4-2 A flowchart illustrating a method for accessing the NVM according to an embodiment of the present invention is shown.

[0096] like Figure 4-2 As shown, the method for accessing NVM includes: Step 410: Processing a first user command; Step 420: Checking whether the block address and page address of the first user command are the same as the block address and page address corresponding to the second user command; Step 430: If the block address and page address of the first user command are the same as the block address and page address corresponding to the second user command, retrieving data from the first cache. Figure 4-2 The method for accessing the NVM shown in the figure further includes step 440: if the block address and page address of the first user command are not the same as the block address and page address corresponding to the second user command, issue an NVM read command to the NVM.

[0097] Figure 4-3 A flowchart illustrating a method for accessing the NVM according to an embodiment of the present invention is shown.

[0098] like Figure 4-3 As shown, the method for accessing NVM includes: Step 410: Processing a first user command; Step 420: Checking whether the block address and page address of the first user command are the same as the block address and page address corresponding to the second user command; Step 430: If the block address and page address of the first user command are the same as the block address and page address corresponding to the second user command, retrieving data from the first cache; Step 440: If the block address and page address of the first user command are not the same as the block address and page address corresponding to the second user command, issuing an NVM read command to NVM. Figure 4-3 The method for accessing the NVM shown in the figure further includes step 450 after issuing an NVM read command to the NVM in step 440: reading data from the NVM and writing the data into the first cache.

[0099] In step 450, in response to the second user command, data corresponding to the block address and page address corresponding to the second user command is read from the NVM and written to the first cache.

[0100] In a further embodiment, a dedicated cache is allocated to each parallel unit (LUN) of the NVM, thereby making it easy to obtain the cache address when accessing the cache (e.g., moving data to or from the cache) and reducing the overhead of cache management.

[0101] Example 1

[0102] In Embodiment 1 of the present invention, a page in the NVM includes multiple sectors. A first read command and a second user command access the same parallel unit and carry the same block address and page address, but access different sectors. The first command accesses the first sector, while the second user command accesses the second sector. The second user command is a read command and is placed in the command queue before the first read command (see...). Figure 2 (Command queue 220). Although the second user command reads data from the second sector, the NVM interface is capable of transferring data page by page. When accessing the NVM according to the second user command, the entire page, including the second sector, is transferred to the buffer. The first read command is then placed in command queue 220. The first read command is processed by executing microinstructions (see...). Figure 4-1 (Step 410). Execute the block / page read address check microinstruction, comparing the block address and page address of the first read command with those of the second user command (see...). Figure 4-1 (Step 420) It is found that the block address of the first read command is the same as the block address of the second user command, and the page address of the first read command is the same as the page address of the second user command. This means that due to the execution of the second user command, the data required by the first read command has been moved to the cache. As an example, the block / page read address check microinstruction is executed, and based on the comparison result, the data is moved to the general-purpose register (see...) Figure 2 A flag is set in general-purpose register 250. The next microinstruction, based on the set flag, determines the microinstruction to execute corresponding to step 430. Therefore, execution continues with the microinstruction to retrieve data from the cache (see [link to microinstruction]). Figure 4-1 (Step 430). In this way, the data to be accessed can be obtained without issuing a data read command to the NVM, saving the execution time of the first read command and improving efficiency.

[0103] Example 2

[0104] In Embodiment 2 of the present invention, a page is the basic unit for reading the NVM. The first read command and the second user command access the same parallel unit and carry the same block address and page address. The second user command is a read command and is placed in the command queue before the first read command (see...). Figure 2 Command queue 220). Therefore, the first read command and the second user command are consecutive read commands to the same address. When accessing the NVM according to the preceding second user command, the entire page data is transferred to the cache. The first read command is then placed in command queue 220. The first read command is processed by executing microinstructions (see command queue 220). Figure 4-1 (Step 410). Execute the block / page read address check microinstruction to compare the block address and page address of the first read command with those of the second user command (step 420). It is found that the block address of the first read command is the same as that of the second user command, and the page address of the first read command is also the same as that of the second user command. This means that due to the execution of the second user command, the data required by the first read command has been moved to the cache. Therefore, continue executing the microinstruction to retrieve the data from the cache (step 430). In this way, the data to be accessed can be obtained without issuing a data read command to the NVM, saving the execution time of the first read command and improving efficiency.

[0105] Example 3

[0106] In embodiment 3 of the present invention, a page is the basic unit for reading the NVM, and the first read command and the second user command access the same parallel unit. However, the block address and / or page address carried by the first read command and the second user command are different. The second user command is a read command and is placed in the command queue before the first read command (see...). Figure 2 Command queue 220). When accessing the NVM according to the preceding second user command, the entire page data is transferred to the cache. Subsequently, the first read command is placed in command queue 220. The first read command is processed by executing microinstructions (see command queue 220). Figure 4-3 (Step 410). Execute the block / page read address check microinstruction, comparing the block address and page address of the first read command with the second user command (step 420). It is found that the block address of the first read command differs from the block address of the second user command, or the page address of the first read command differs from the page address of the second user command. Therefore, the data required by the first read command is very likely not in the cache. For example, executing the block / page read address check microinstruction, based on the comparison result, in the general-purpose register (see...) Figure 2 A flag is set in the general-purpose register 250. The next microinstruction, based on the set flag, determines the microinstruction to execute corresponding to step 440. Therefore, the microinstruction continues execution to issue an NVM read command to the NVM (step 440). The microinstruction operates through the interface controller (see...). Figure 2 The interface controller 230 issues an NVM read command. It also receives data read from the NVM and writes the data to a buffer by executing microinstructions (step 450). This data appears in the command queue after the first read command (see...). Figure 2When the block address and page address of the third user command in command queue 220 are the same as those of the first read command, it means that the data to be accessed by the third user command already exists in the buffer. The data required by the third user command can be retrieved from the buffer without issuing a data read command to the NVM again.

[0107] Figure 5 A flowchart illustrating a method for accessing the NVM according to another embodiment of the present invention is shown. By executing a sequence of microinstructions, the microinstruction execution unit 210 (see...) Figure 2 ) Execution in Figure 5 The method for accessing NVM is shown in the image.

[0108] like Figure 5 As shown, the method for accessing the NVM includes: Step 510: Processing a first read command; Step 520: Reading first data from the NVM and writing the first data into a first cache; Step 530: Processing a second read command; Step 540: Checking whether the block address and page address of the first read command are the same as those of the second read command; Step 550: If the block address and page address of the first read command are the same as those of the second read command, retrieving the first data from the first cache; Step 560: If the block address and page address of the first read command are different from those of the second read command, issuing an NVM read command; Step 570: Retrieving the second data read from the NVM and writing the second data into the cache.

[0109] In step 510, in command queue 220 (e.g.) Figure 2 When an unprocessed first read command appears in (as shown), the first read command is processed by executing a microinstruction sequence. In step 520, data is read from the NVM according to the first read command by executing the microinstruction sequence, and the read data is written to the cache. In one example, when reading data from the NVM according to the first read command, the block / page read address check microinstruction according to the present invention is also executed, and it is determined that the block address and page address of the first read command are different from the block address and page address of the previous read / write command, thereby sending an NVM read command to the NVM according to the first read command. In another example, the first read command is command queue 220 (see...). Figure 2 The system detects only the read or write command in the cache, thus determining that the data required by the first read command is not present in the cache. In step 530, in response to the appearance of a second read command in the command queue, the second read command is processed by executing a sequence of microinstructions. In step 540, the block / page read address check microinstruction according to the invention is executed, and it is determined whether the block address and page address of the second read command are the same as the block address and page address of the preceding read / write command (in this example, the first read command).

[0110] If the block address and page address of the second read command are the same as those of the first read command, it means that the data required by the second read command has been moved to the cache by the execution of the first read command. In step 550, the data required by the second read command is retrieved from the cache by executing the corresponding microinstruction. In a further example, the processing of the first read command has not yet been completed, so the processing of the second read command is temporarily suspended, and it is set that the processing of the second read command will resume after the data is retrieved by the first read command, and the data required by the second read command will be retrieved from the cache.

[0111] If the block address and page address of the second read command are different from those of the first read command, it means that the data required by the second read command is very unlikely to be in the cache. In step 560, an NVM read command is issued to the NVM by executing microinstructions. In step 570, the data read from the NVM is obtained by executing microinstructions and written to the cache.

[0112] The following specific embodiments are described in detail:

[0113] Example 4

[0114] In embodiment 4 of the present invention, command queue 220 (see Figure 2 In the command queue 220, the first user command is a write command, and the second user command is a read command. Both the first and second user commands access the same parallel unit and carry the same block and page addresses. In response to an unprocessed first user command appearing in the command queue 220, the data to be written by the first user command is moved to the buffer by executing a microinstruction sequence, and then transmitted via the interface controller 230 (see...). Figure 2 The NVM programming command is issued to the NVM. In response to an unprocessed second user command appearing in the command queue 220, the microinstruction execution unit 210 (see...) issues an NVM programming command. Figure 2 The block / page read address check microinstruction according to the present invention is executed to determine that the block address and page address accessed by the first user command and the second user command are the same, respectively. Based on this, it is determined that the data required by the second user command exists in the cache, and the data is retrieved from the cache by executing the microinstruction.

[0115] Example 5

[0116] In embodiment 5 of the present invention, command queue 220 (see Figure 2In the command queue 220, the first user command is a write command, and the second user command is a read command. Both commands access the same parallel unit and carry the same block and page addresses. The first user command writes an entire page of data, while the second user command reads a portion of that page. The address range carried in the second user command indicates the portion of the page data to be read. In response to an unprocessed first user command in the command queue 220, the entire page of data to be written by the first user command is moved to the buffer by executing a microinstruction sequence, and then transmitted via the interface controller 230 (see...). Figure 2 The NVM programming command is issued to the NVM. In response to an unprocessed second user command appearing in the command queue 220, the microinstruction execution unit 210 (see...) issues an NVM programming command. Figure 2 The block / page read address check microinstruction according to the present invention is executed to determine that the block address and page address accessed by the first user command and the second user command are the same, respectively. Based on this, it is determined that the data required by the second user command exists in the cache, and the required partial page data is retrieved from the cache by executing the microinstruction.

[0117] Example 6

[0118] In embodiment 6 of the present invention, command queue 220 (see Figure 2 The first user command in the sequence is a read command, the second user command following the first is a read ID command, and the third user command following the second is a read command. The first and third user commands access the same parallel unit and carry the same block and page addresses. In response to an unprocessed first user command appearing in command queue 220, the data to be written by the first user command is moved to the cache by executing a microinstruction sequence, and then transmitted via interface controller 230 (see...). Figure 2 The system issues NVM programming commands to the NVM. In response to an unprocessed second user command appearing in command queue 220, an NVM read ID command is issued to the NVM by executing a microinstruction sequence. In response to an unprocessed third user command appearing in command queue 220, the microinstruction execution unit 210 (see...) Figure 2 The block / page read address check microinstruction according to the present invention is executed to determine that the block address and page address accessed by the first user command and the second user command are different, and the block / page read address check microinstruction according to the present invention is executed again to determine that the block address and page address accessed by the first user command and the third user command are the same. Based on this, it is determined that the data required by the third user command exists in the cache, and the data is retrieved from the cache by executing microinstructions.

[0119] Example 7

[0120] In embodiment 7 according to the present invention, command queue 220 (see Figure 2The first user command in the sequence is a read command, the second user command following the first is a Set Feature command, and the third user command following the second is a read command. The first and third user commands access the same parallel unit and carry the same block and page addresses. In response to an unprocessed first user command appearing in command queue 220, the data to be written by the first user command is moved to the buffer by executing a microinstruction sequence, and then transmitted via interface controller 230 (see...). Figure 2 The system issues an NVM programming command to the NVM. In response to an unprocessed second user command appearing in command queue 220, an NVM Set Feature command is issued to the NVM by executing a microinstruction sequence. In response to an unprocessed third user command appearing in command queue 220, the system executes microinstructions to determine that the second user command in the command queue will cause the data expected by the third user command to be different from the data read by the first user command. Therefore, the block / page read address check microinstruction according to the invention is not executed, or the check result of the block / page read address check microinstruction is ignored, and an NVM read command is issued to the NVM according to the third user command.

[0121] Figure 6A A flowchart is shown illustrating a method for executing read address check microinstructions in an NVM interface controller according to another embodiment of the present invention.

[0122] like Figure 6A As shown, the method for executing a read address check microinstruction in the NVM interface controller includes: Step 610: Obtain the first microinstruction; Step 620: Decode the first microinstruction to determine that the first microinstruction is a read address check microinstruction; Step 630: Obtain the first block address and the first page address corresponding to the user command; Step 640: Check whether the first block address and the first page address are the same as the already stored block address and page address. If they are the same, proceed to Step 650: Set the flag register; if they are not the same, proceed to Step 660: Clear the flag register.

[0123] In step 610, the microinstruction execution unit 210 retrieves the microinstruction from the microinstruction memory 240 (see [link to microinstruction memory]) based on the program counter (PC) in the general-purpose register 250. Figure 2 The microinstruction is retrieved from the specified location of the block / page read address check microinstruction. For example, the block / page read address check microinstruction is one of the microinstructions in a sequence of microinstructions used to process read commands. In step 620, the microinstruction execution unit 210 decodes the microinstruction read from the microinstruction memory 240 and determines that the microinstruction is a block / page read address check microinstruction. In step 630, the microinstruction execution unit 210 retrieves the microinstruction based on the offset value field of the block / page read address check microinstruction (see...). Figure 3The microinstruction execution unit 210 accesses the command queue 220 and retrieves the block address and page address of the first command preceding the current read command. The microinstruction execution unit 210 also retrieves the block address and page address of the current read command from the context memory 260. In step 640, the microinstruction execution unit 210 compares the block address and page address of the first command with those of the current read command. If they are the same, in step 650, the microinstruction execution unit 210 checks the Reg field of the microinstruction based on the block / page read address (see...). Figure 3 The general-purpose register index provided sets the flag register in general-purpose register 250; if they are different, in step 660, microinstruction execution unit 210 checks the Reg field of the microinstruction based on the block / page read address (see...). Figure 3 The provided general-purpose register index clears the flag register in general-purpose register 250.

[0124] In the example above, the microinstruction execution unit 210 obtains the block address and page address of the current read command from the context memory 260.

[0125] Optionally, in another embodiment of the invention, a second offset value field is provided in the block / page read address check microinstruction to indicate the current read command in command queue 220 (see...). Figure 2 The microinstruction execution unit 210 retrieves the block address and page address of the current read command from the command queue 220 based on the second offset value field, and compares them with the block address and page address of the first command indicated by the first offset value field.

[0126] Alternatively, in yet another embodiment of the invention, the microinstruction execution unit 210 (see also...) Figure 2 Maintain context identifiers to identify the context of a microinstruction sequence, specifically the context of the microinstruction sequence in context memory 260 (see context memory 260). Figure 2 The microinstruction execution unit 210 retrieves the block address and page address of the current read instruction from the context memory 260 based on the context identifier. This eliminates the need to indicate the context identifier in each microinstruction.

[0127] Alternatively, in yet another embodiment of the invention, command queue 220 (see also...) Figure 2 Unprocessed commands in ) cause microinstruction execution unit 210 (see Figure 2 ) Executes a sequence of microinstructions, providing a context identifier in the command to identify the context of the microinstruction sequence, specifically the context of the microinstruction sequence in context memory 260 (see... Figure 2The block address and page address carried in the command are stored in the context storage 260. When executing the block / page address check microinstruction, the microinstruction execution unit 210 (see...) Figure 2 Based on the context identifier, the block address and page address of the current read instruction are obtained from the context memory 260.

[0128] Alternatively, in yet another embodiment of the invention, command queue 220 (see also...) Figure 2 Unprocessed commands in ) cause microinstruction execution unit 210 (see Figure 2 ) Executes a sequence of microinstructions, providing a parallel unit identifier in the command, and using the parallel unit identifier to identify the context of the microinstruction sequence, specifically the context of the microinstruction sequence in context memory 260 (see... Figure 2 The block address and page address carried in the command are stored in the context memory 260. This allows commands accessing the same parallel unit to be assigned the same context. The block address and page address are also stored in the context memory 260. When executing the block / page address check microinstruction, the microinstruction execution unit 210 retrieves the block address and page address of the current read instruction from the context memory 260 based on the parallel unit identifier.

[0129] Alternatively, in yet another embodiment of the invention, the microinstruction execution unit 210 (see also...) Figure 2 Maintain thread identifiers to identify the thread to which a microinstruction sequence belongs. And in context memory 260 (see...) Figure 2 The microinstruction execution unit 210 stores the thread's context information in the context memory 260. It also determines the storage location of the thread context in the context memory 260 based on the thread identifier. The microinstruction execution unit 210 retrieves the block address and page address of the current read instruction from the context memory 260 based on the thread identifier.

[0130] Figure 6B A flowchart illustrating a method for executing read address check microinstructions in an NVM interface controller and subsequent operations according to another embodiment of the present invention is shown.

[0131] like Figure 6B As shown, after executing the read address check microinstruction in the NVM interface controller, the system further executes step 680 to read data from the first cache based on the execution result of the read address check microinstruction; or executes step 670 to read the second data from the NVM and write the second data into the first cache.

[0132] In step 680, the subsequent microinstruction (e.g., branch microinstruction) of the block / page read address check microinstruction checks the flag register. If the flag register is set, the program counter (PC) value is modified accordingly, causing the microinstruction execution unit to retrieve the next microinstruction based on the updated PC value. By executing this next microinstruction and the subsequent microinstruction sequence, the unit reads the data required for the current read command from the cache. In step 670, the subsequent microinstruction (e.g., branch microinstruction) of the block / page read address check microinstruction checks the flag register. If the flag register is cleared, the program counter (PC) value is modified accordingly, causing the microinstruction execution unit to retrieve the next microinstruction based on the updated PC value. By executing this next microinstruction and the subsequent microinstruction sequence, the unit issues an NVM read command to the NVM, retrieves the data read from the NVM, and writes it to the cache.

[0133] Figure 7A A flowchart is shown illustrating a method for executing read address check microinstructions in an NVM interface controller according to another embodiment of the present invention.

[0134] like Figure 7A As shown, the method for executing a read address check microinstruction in the NVM interface controller includes: Step 710: Obtaining a first microinstruction; Step 720: Decoding the first microinstruction to determine that it is a read address check microinstruction; Step 730: Obtaining the first block address and the first page address corresponding to the user command; Step 740: Checking whether the first block address and the first page address are the same as the stored second block address and the second page address. If they are the same, proceed to Step 750: Setting the program counter to the first address; if they are not the same, proceed to Step 760: Setting the program counter to the second address.

[0135] In step 710, the microinstruction execution unit 210 retrieves the microinstruction from the microinstruction memory 240 (see [link to microinstruction memory]) based on the program counter (PC) in the general-purpose register 250. Figure 2 The microinstruction is retrieved from the designated location of the microinstruction memory 240. In step 720, the microinstruction execution unit 210 decodes the first microinstruction read from the microinstruction memory 240 and determines that the first microinstruction is a block / page read address check microinstruction. In step 730, the microinstruction execution unit 210 checks the offset value field of the microinstruction according to the block / page read address (see...). Figure 3The microinstruction execution unit 210 accesses command queue 220 and retrieves the block address and page address of the first command preceding the current read command. The microinstruction execution unit 210 also retrieves the block address and page address of the current read command from context memory 260. In step 740, the microinstruction execution unit 210 compares the block address and page address of the first command with those of the current read command. If they are the same, in step 750, the microinstruction execution unit 210 sets the program counter (PC) in general-purpose register 250 to a first value; if they are different, in step 760, the microinstruction execution unit 210 sets the program counter (PC) in general-purpose register 250 to a second value. At this point, the block / page read address check microinstruction execution is complete.

[0136] Figure 7B A flowchart illustrating a method for executing read address check microinstructions in an NVM interface controller and subsequent operations according to another embodiment of the present invention is shown.

[0137] like Figure 7B As shown, after executing the read address check microinstruction in the NVM interface controller, step 770 is executed based on the execution result of the read address check microinstruction: obtain the second microinstruction from the address indicated by the program counter.

[0138] In step 770, the microinstruction execution unit 210 (see...) Figure 2 The microinstruction unit obtains the next microinstruction based on the updated program counter (PC) value, and executes the next microinstruction and subsequent microinstruction sequences. When the program counter (PC) value is set to the first value in step 750, the microinstruction execution unit reads the data required for the current read command from the cache by executing the next microinstruction and subsequent microinstruction sequences. When the program counter (PC) value is set to the second value in step 760, the microinstruction execution unit issues an NVM read command to the NVM by executing the next microinstruction and subsequent microinstruction sequences, obtains the data read from the NVM, and writes it to the cache.

[0139] In an optional embodiment, the block / page read address check microinstruction is executed in the microinstruction execution unit 210 (see [link to microinstruction execution unit 210]). Figure 2 When setting the program counter (PC) to its first value, the microinstruction's Reg field is also checked based on the block / page read address (see [link]). Figure 3 The general-purpose register index provided by the microinstruction unit 210 sets the flag register in general-purpose register 250; when the microinstruction execution unit 210 sets the program counter (PC) to the second value, it also checks the Reg field of the microinstruction based on the block / page read address (see...). Figure 3 The provided general-purpose register index clears the flag register in general-purpose register 250.

[0140] In this invention, an example of NVM is flash memory. Those skilled in the art will recognize that embodiments of this invention can also be applied to other types of storage media, such as phase-change memory, resistive memory, ferroelectric memory, etc.

[0141] According to one aspect of the present invention, the present invention also provides a computer program comprising computer program code, which, when loaded into and executed on a computer system, causes the computer system to perform the methods described above.

[0142] According to another aspect of the invention, a program including program code is also provided, which, when loaded into a storage device and executed on the storage device, causes the storage device to perform the methods described above.

[0143] The technical solution of this invention enables flexible determination of whether data already exists in the cache of the storage controller, allowing users of the storage device to participate in flexible control of cache utilization without relying on the storage controller to determine whether data is cached.

[0144] It should be understood that each box in a block diagram and flowchart, as well as combinations of boxes in block diagrams and flowcharts, can be implemented by various means including computer program instructions. These computer program instructions can be loaded onto a general-purpose computer, a special-purpose computer, or other programmable data control equipment to produce a machine, such that the instructions, which execute on the computer or other programmable data control equipment, create means for implementing the functions specified in one or more flowchart boxes.

[0145] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data control device to function in a particular manner, thereby enabling the manufacture of an article of art comprising computer-readable instructions for implementing the functions specified in one or more flowchart blocks using the instructions stored in the computer-readable storage medium. The computer program instructions may also be loaded onto a computer or other programmable data control device to cause a series of operational steps to be performed on the computer or other programmable data control device, thereby producing a computer-implemented process, wherein the instructions, which execute on the computer or other programmable data control device, provide steps for implementing the functions specified in one or more flowchart blocks.

[0146] Therefore, the blocks in block diagrams and flowcharts support combinations of means for performing a specified function, combinations of steps for performing a specified function, and combinations of program instruction means for performing a specified function. It should also be understood that each block in a block diagram and flowchart, as well as combinations of blocks in block diagrams and flowcharts, can be implemented by a hardware-based dedicated computer system that performs the specified function or steps, or by a combination of dedicated hardware and computer instructions.

[0147] At least some of the aforementioned blocks, operations, and techniques can be executed by using hardware to execute firmware instructions, software instructions, or any combination thereof. When executed by a control device that executes firmware and software instructions, the software or firmware instructions can be stored in any computer-readable storage medium, such as a disk, optical disk, or other storage medium, in RAM or ROM or flash memory, control device, hard disk, optical disk, etc. Similarly, the software and firmware instructions can be transmitted to the user or system via any known or desired transmission method, including, for example, on a computer-readable disk or other portable computer storage mechanism or via a communication medium. Communication media typically embody computer-readable instructions, data structures, sequence modules, or other data in modulated data signals, such as carrier waves or other transmission mechanisms. By way of example, and not limitation, communication media include wired media such as wired networks or single-wire connections, and wireless media such as sound, radio frequencies, infrared, and other wireless media. Thus, software and firmware instructions can be transmitted to the user or system via communication channels such as telephone lines, DSL lines, cable television lines, fiber optic cables, wireless channels, the Internet, etc. (such software provided via portable storage media is considered identical or interchangeable). The software or firmware instructions may include machine-readable instructions that, when executed by a control device, cause the control device to perform different actions. When executed in hardware, the hardware may include one or more discrete components, integrated circuits, application-specific integrated circuits (ASICs), etc.

[0148] It should be understood that this invention can be implemented in pure software, pure hardware, firmware, and various combinations thereof. Hardware can be, for example, a control device, an application-specific integrated circuit (ASIC), a large-scale integrated circuit, etc.

[0149] While examples of the present invention have been described, they are for illustrative purposes only and not as limitations on the invention. Changes, additions and / or deletions to the embodiments may be made without departing from the scope of the invention.

[0150] Those skilled in the art who benefit from the teachings presented in the above description and associated drawings will recognize many modifications and other embodiments of the invention described herein. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terminology is used herein, it is used only in its general and descriptive sense and not for limiting purposes.

Claims

1. A method for accessing NVM, characterized in that, include: The first user command to read the NVM is executed by processing the microinstruction sequence, and the block address and page address corresponding to the first user command are checked against the block / page read address check microinstruction in the microinstruction sequence to see if they are the same as the block address and page address corresponding to the second user command, wherein the second user command indicates reading the NVM and the second user command appears before the first user command; If the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, data is read from the first cache that caches the data corresponding to the block address and page address corresponding to the second user command, and used to respond to the first user command.

2. The method according to claim 1, characterized in that, The microinstruction sequence checks whether the block and page addresses corresponding to the first user command and the second user command are the same, including: Based on the block / page read address, check the offset value of the microinstruction to access the user command memory and obtain the block address and page address corresponding to the first user command; and access the context memory to obtain the block address and page address corresponding to the second user command; check whether the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command.

3. The method according to claim 1 or 2, characterized in that, If the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, set the flag register; as well as If the block address and page address corresponding to the first user command are different from those corresponding to the second user command, clear the flag register.

4. The method according to claim 3, characterized in that, The microinstruction sequence also includes conditional branch microinstructions. By executing the conditional branch microinstruction, the flag register is checked to see if it is set or cleared, and the value of the program counter is set. The position of the next conditional microinstruction to be executed is obtained based on the value of the program counter.

5. The method according to claim 4, characterized in that, If the flag register is set, the execution jumps to the first microinstruction sequence to read data from the first cache; and if the flag register is cleared, the execution jumps to the second microinstruction sequence to issue an NVM read command to the NVM.

6. An NVM controller, characterized in that, include: Microinstruction memory, used to store multiple microinstruction sequences; The microinstruction execution unit is used to decode microinstructions and execute the operations corresponding to the microinstructions; The program counter is used to indicate the storage location of microinstructions in the microinstruction memory; A general-purpose register set, wherein registers in the general-purpose register set are accessible via microinstructions in the microinstruction sequence; User command storage, used to store user commands; as well as A context memory is used to store context information corresponding to a microinstruction sequence; wherein, the microinstruction execution unit accesses the user command memory, initiates the execution of a microinstruction sequence in response to a user command in the user command memory, and obtains the context information corresponding to the microinstruction sequence by using the parallel unit to be accessed by the user command as the microinstruction sequence execution context memory. When the first microinstruction obtained is a block / page read address check microinstruction, the microinstruction execution unit accesses the user command memory based on the offset value of the block / page read address check microinstruction to obtain the first block address and the first page address; the microinstruction execution unit accesses the context memory to obtain the second block address and the second page address stored in the context information of the current microinstruction sequence; the microinstruction execution unit compares the first block address with the second address, and the first page address with the second page address; if the first block address and the second address are the same, and the first page address and the second page address are the same, the microinstruction execution unit sets the general-purpose register indicated by the register index in the general-purpose register group based on the register index of the block / page read address check microinstruction.

7. The NVM controller according to claim 6, characterized in that, in, Based on the program counter, the microinstruction execution unit retrieves the first microinstruction from the microinstruction memory. The microinstruction execution unit decodes the first microinstruction. When the first microinstruction is a block / page read address check microinstruction, the microinstruction execution unit accesses the user command memory based on the offset value of the block / page read address check microinstruction to obtain the first block address and the first page address. The microinstruction execution unit accesses the context memory to obtain the second block address and the second page address stored in the context information of the current microinstruction sequence. The microinstruction execution unit compares the first block address with the second block address, and the first page address with the second page address. If the first block address and the second block address are the same, and the first page address and the second page address are the same, the microinstruction execution unit checks the register index of the microinstruction based on the block / page read address and sets the general-purpose register indicated by the register index in the general-purpose register group. If the first block address and the second address are different, or the first page address and the second page address are different, the microinstruction execution unit checks the register index of the microinstruction based on the read address and clears the general-purpose register indicated by the register index in the general-purpose register group.

8. The NVM controller according to claim 7, characterized in that, The microinstruction execution unit retrieves a first microinstruction; decodes the first microinstruction to determine that it is a read address check microinstruction, wherein the read address check microinstruction includes a register index and an offset value, the register index being used to indicate the flag register storing the execution result of the read address check instruction, and the offset value being used to indicate the storage location of the user command; obtains the first block address and the first page address corresponding to the user command based on the offset value; obtains the second block address and the second page address based on the context information of the read address check microinstruction; if the first block address and the second address are the same, and the first page address and the second page address are the same, then the flag register is set according to the register index; if the first block address and the second address are different, or the first page address and the second page address are different, then the flag register is cleared according to the register index.

9. The NVM controller according to claim 8, characterized in that, The microinstruction execution unit compares the first block address with the second block address, and the first page address with the second page address. If the first block address and the second block address are the same, and the first page address and the second page address are the same, the microinstruction execution unit sets the program counter based on the first address of the microinstruction checked by the read address. If the first block address and the second address are different, or the first page address and the second page address are different, the microinstruction execution unit increments the program counter to the second address.

10. The NVM controller according to any one of claims 6-9, characterized in that, The microinstruction execution unit initiates the execution of a microinstruction sequence in response to a user command in the user command memory. Based on the parallel unit accessed by the user command, the microinstruction execution unit executes the first context memory for the microinstruction sequence. The microinstruction execution unit accesses the first context memory to obtain the second block address and the second page address stored in the context information of the current microinstruction sequence.

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