FPGA online upgrading method based on serial communication

Abstract

This invention relates to an FPGA upgrade method, specifically an online FPGA upgrade method based on serial communication. It overcomes the technical problem of high upgrade and maintenance costs caused by traditional upgrade methods that require product disassembly after delivery of inertial combination products. This invention uses only common solutions for inertial combination products, without requiring additional equipment or components. After the inertial combination product is delivered to the user, the FPGA program is upgraded online via a serial communication interface. This allows for FPGA program upgrades in the field without disassembly; simultaneously, it does not affect the use of a dedicated USB downloader or programmer for FPGA debugging and upgrades during the design and debugging phases of the inertial combination product.

Description

Technical Field

[0001] This invention relates to an FPGA upgrade method, specifically an online FPGA upgrade method based on serial communication. Background Technology

[0002] FPGA (Field-Programmable Gate Array) evolved from logic devices such as PAL and GAL. It belongs to the category of semi-custom circuits within application-specific integrated circuits (ASICs) and is a programmable logic array. Its basic structure generally includes programmable input / output modules (IOBs), configurable logic modules (CLBs), and routing resources. By loading different programming data onto these internal hardware resources of the FPGA and organizing them into a specific structure, the required FPGA logic function can be realized. Furthermore, FPGAs allow for an unlimited number of programming iterations.

[0003] FPGAs are generally based on SRAM lookup table technology, where programming data is stored in SRAM. Since this programming data is immediately lost when SRAM is powered off, external non-volatile memory is required to store the programming data. After power-on, the FPGA automatically retrieves the programming data from the non-volatile memory and loads it into the internal SRAM; this process is called FPGA configuration. FPGAs support multiple configuration modes, including active configuration, passive configuration, and JTAG configuration.

[0004] Inertial navigation systems (INS) are widely used in navigation, guidance, and control systems of various weapon platforms across the sea, land, air, and space, and are core components of modern weapon systems. FPGAs, with their superior expansion interfaces, logic control, and digital signal processing capabilities, are widely used in INS products; therefore, the programming and upgrade methods for FPGAs have become a focus of attention for INS products.

[0005] When the FPGA program of an inertial combination product needs to be upgraded, the traditional method is to establish a connection between the FPGA configuration non-volatile memory and the PC through a dedicated USB downloader or programmer. The new FPGA programming data is then stored in the FPGA configuration non-volatile memory through a dedicated downloader on the PC, thus completing the FPGA upgrade.

[0006] Using this method, when the inertial navigation system (INS) is in the design and debugging phase, the FPGA program can be upgraded via a dedicated USB downloader or programmer. However, once the INS has been delivered to the user, upgrading the FPGA program requires opening the product cover. For some products, the FPGA's mounting location is unique, making it difficult to connect a USB downloader or programmer, necessitating product disassembly. Furthermore, if the product is already integrated into the system, disassembly becomes even more difficult, significantly increasing the maintenance cost of FPGA program upgrades. Summary of the Invention

[0007] The purpose of this invention is to provide an online FPGA upgrade method based on serial communication, overcoming the technical problem that traditional upgrade methods for inertial combination products require product disassembly, resulting in high upgrade and maintenance costs. This invention uses only common solutions for inertial combination products, requiring no additional equipment or components. After the inertial combination product is delivered to the user, the FPGA program can be upgraded without disassembly; simultaneously, it does not affect the use of a dedicated USB downloader or programmer for FPGA debugging and upgrades during the design and debugging phases of the inertial combination product.

[0008] The technical solution of this invention is to provide an FPGA online upgrade method based on serial communication, applicable to the online upgrade of FPGAs in inertial combination products. Its unique feature is that it includes the following steps:

[0009] Step 1: The FPGA programming data file is transferred to the DSP via the ground testing equipment. The DSP temporarily stores the programming data file in the memory chip and verifies the correctness of the programming data file. If the verification is correct, the DSP notifies the FPGA to start the upgrade and proceeds to Step 2. If the verification fails, the ground testing equipment is notified to retransmit the FPGA programming data file.

[0010] Step 2: The FPGA enters the upgrade state. The FPGA takes over the communication interface of the configuration chip and erases the configuration chip. After this, until the inertial combination product is powered off, the configuration chip cannot be accessed through a dedicated USB downloader or programmer.

[0011] Step 3: The DSP transmits the FPGA's programming data file to the FPGA in blocks. The FPGA verifies the data after receiving each block. If the verification is correct, the data is written to the configuration chip through the configuration chip communication interface. If the verification fails, the process returns to Step 2 until the DSP has transmitted all the programming data files and notifies the FPGA to start the upgrade verification.

[0012] Step 4: The FPGA enters the upgrade verification state. The FPGA reads the programming data file from the configuration chip in blocks and sends it back to the DSP. This continues until all programming data files are sent back, at which point the DSP is notified that the transmission is complete.

[0013] Step 5: The DSP compares and verifies the programming data file in the memory chip with the programming data file returned by the FPGA. If the verification is correct, the FPGA upgrade is successful, and the FPGA is configured with the upgraded programming data file. If the verification fails, proceed to Step 2 until the FPGA upgrade is successful.

[0014] Furthermore, step three specifically includes the following steps:

[0015] Step 3.1: The DSP sends the first programming data file. After the FPGA receives the first programming data file, if the verification is correct, it replies with a correct response. The DSP then proceeds to the next step. If the verification fails, it replies with an incorrect response. The DSP then returns to step two.

[0016] Step 3.2: The DSP sends a start programming command frame. After receiving the command frame, the FPGA writes the first programming data file to the configuration chip and sends an upload data request frame to the DSP to proceed to the next step.

[0017] Step 3.3: Upon receiving the request, the DSP sends the next block of programming data file;

[0018] Step 3.4: After the FPGA receives the programming data file, if the verification is correct, it writes it to the configuration chip and sends an upload data request to the DSP, then returns to step 3.3. If the verification fails, it replies with an error response, which the DSP receives and returns to step two. This process continues until the DSP has transmitted all the programming data files, at which point it notifies the FPGA to start the upgrade verification.

[0019] Furthermore, in step one, the ground test equipment transmits the FPGA programming data file to the DSP frame by frame.

[0020] Furthermore, step one specifically includes the following steps:

[0021] Step 1.1: The ground surveying equipment sends an FPGA upgrade command to the DSP. After the DSP responds, it proceeds to the next step.

[0022] Step 1.2: The ground surveying equipment sends a frame of programming data to the DSP. If the DSP verifies the data correctly, it stores the programming data in the memory chip and sends a correct response before starting to transmit the next frame. If the verification fails, it sends an error response and returns to step 1.1.

[0023] Furthermore, the inertial combination product also includes an FPGA configuration control circuit;

[0024] In step five, after the FPGA upgrade is successful, the DSP uses GPIO to control the state of the FPGA configuration control circuit, and directly controls the upgraded FPGA programming data file.

[0025] Furthermore, the FPGA configuration control circuit includes pull-up resistors, capacitors, and a microprocessor monitoring chip;

[0026] The GPIO pins of the DSP are connected to the MR pins of the microprocessor monitoring chip, and the RESET pins of the microprocessor monitoring chip are connected to the PROG_B pins of the FPGA.

[0027] The DSP's GPIO pins are in a high-impedance state by default. Pull-up resistors ensure that the MR pin is at a high level when the FPGA configuration control circuit is working properly. After the FPGA upgrade is successful, the DSP controls the GPIO signal to go low. The low level is maintained for more than 500ns before going high. After that, the microprocessor monitors the chip's RESET signal and outputs a low level for 200ms. Then the FPGA configures the upgraded programming data file.

[0028] The present invention also provides an FPGA upgrade method for inertial combination products, which is characterized by including upgrade methods for inertial combination products during the design and debugging stages as well as upgrade methods after delivery of inertial combination products;

[0029] The upgrade of inertial combination products during the design and debugging phase is as follows:

[0030] A connection is established between the FPGA configuration non-volatile memory and the PC via a dedicated USB downloader or programmer. The new FPGA programming data is then stored in the FPGA configuration non-volatile memory via a dedicated download program on the PC, thus completing the FPGA upgrade. Alternatively, any of the above-mentioned online FPGA upgrade methods based on serial communication can be used to upgrade the FPGA.

[0031] The upgrade method after delivery of the inertial combination product is as follows: upgrade the FPGA using any of the above-mentioned online FPGA upgrade methods based on serial communication.

[0032] The beneficial effects of this invention are:

[0033] 1. This method utilizes common solutions for inertial navigation array (INS) products, requiring no additional equipment or components. It enables online upgrades of the FPGA program via the INS's external serial communication interface. When the INS has already been delivered to the user, this method replaces the method of upgrading the FPGA program using a dedicated USB downloader or programmer. It eliminates the need for opening, disassembling, or removing the INS from the entire system, saving time and maintenance costs, reducing operational risks associated with opening and disassembly, and improving the reliability and maintainability of the INS.

[0034] 2. When the inertial combination product is in the design and debugging stage, a connection can be established between the FPGA configuration non-volatile memory and the PC through a dedicated USB downloader or programmer. The new FPGA programming data can be stored in the FPGA configuration non-volatile memory through the dedicated download program on the PC, thus completing the FPGA upgrade. Attached Figure Description

[0035] Figure 1 This is a block diagram illustrating the principle of the inertial combination product of the present invention;

[0036] Figure 2 This is a flowchart of the FPGA online upgrade process based on serial communication according to the present invention;

[0037] Figure 3 This is a block diagram of the FPGA configuration control circuit of the present invention; Detailed Implementation

[0038] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0039] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0040] This invention uses only common solutions for inertial combination products, without requiring additional equipment and components. See the schematic diagram below. Figure 1 As shown. This method does not affect the debugging and upgrading of FPGAs using a dedicated USB programmer. After the inertial combination product is delivered to the user, the FPGA program can be upgraded without disassembly. From Figure 1 As can be seen, inertial navigation system (INS) products generally have a serial communication interface for connecting to external ground measurement equipment. INS products use a DSP as the main control chip, which communicates with the ground measurement equipment and connects to a storage chip to store INS data. The FPGA in the INS product generally acts as a coprocessor, communicating with the DSP to provide operating data. The FPGA connects to the configuration chip via a communication interface to write programming data to the configuration chip; alternatively, a dedicated USB programmer can be used to write programming data to the configuration chip. After the INS is powered on, the FPGA obtains the programming data from the configuration chip through the configuration interface and enters the working state.

[0041] like Figure 2 As shown, the process of online upgrade of the FPGA program in this invention is as follows:

[0042] Step 1: The FPGA programming data file is transferred from the ground testing equipment to the DSP. The DSP temporarily stores the programming data file in the memory chip. The DSP verifies the correctness of the programming data file. If the verification is correct, it notifies the FPGA to start the upgrade. If the verification fails, it notifies the ground testing equipment to retransmit the programming data file.

[0043] Step 2: The FPGA enters the upgrade state. The FPGA takes over the communication interface of the configuration chip and erases the configuration chip. After this, until the inertial combination product is powered off, the configuration chip cannot be accessed through the dedicated USB downloader.

[0044] Step 3: The DSP transmits the programming data file to the FPGA in blocks. The FPGA verifies the data of each block it receives. If the verification is correct, it writes the data to the configuration chip through the configuration chip communication interface. If the verification fails, the transmission of this block of programming data file is restarted until the DSP has transmitted all the programming data files and then notifies the FPGA to start the upgrade verification.

[0045] Step 4: The FPGA enters the upgrade verification state. The FPGA reads the programming data file from the configuration chip in blocks and sends it back to the DSP. This continues until all programming data files are sent back, at which point the DSP is notified that the transmission is complete.

[0046] Step 5: The DSP compares and verifies the programming data file in the memory chip with the programming data file returned by the FPGA. If the verification is correct, the FPGA upgrade is successful. If the verification fails, it re-enters Step 2.

[0047] Step Six: Configure the upgraded programming data file for the FPGA.

[0048] The following is a specific example illustrating a method for online upgrade of an inertial navigation system product's FPGA program via 1553B communication.

[0049] The ground test equipment communicates with the inertial navigation system's (INS) DSP via a 1553B interface. The FPGA's programming data file is 512KB in size. The ground test equipment performs a CRC-32 checksum on the programming data file, generating 4 bytes of CRC checksum data. The ground test equipment sends the programming data file to be upgraded to the INS DSP frame by frame, transmitting 58 bytes of data per frame, with frame verification using a cumulative checksum. The DSP communicates with the FPGA via an RS422 interface, also sending the programming data file to be upgraded to the FPGA frame by frame, transmitting 512 bytes of data per frame, with frame verification using a cumulative checksum. The FPGA communicates with the configuration chip via a JTAG interface.

[0050] The online upgrade process is as follows:

[0051] 1. The ground test equipment sends an FPGA upgrade command to the DSP, and the DSP responds and proceeds to the next step.

[0052] 2. The ground test equipment sends a frame of data to the DSP. If the DSP verifies the data correctly, it stores the data in the SDRAM and sends a correct response before starting to transmit the next frame. If the verification fails, it sends an error response and returns to step 1.

[0053] 3. After transmitting all programming data files and CRC check data, the DSP uses the data in SDRAM to perform CRC-32 check. The check result is compared with the received CRC check data. If the comparison is correct, a correct response is sent and the process proceeds to the next step. If the comparison is incorrect, the process returns to step 1.

[0054] 4. The DSP sends a start erase command frame. After receiving the frame, the FPGA takes over the JTAG interface, starts the PROM erase operation, and sends an erase response frame after the erase is complete. Upon receiving the response, the DSP proceeds to the next step.

[0055] 5. The DSP sends the first program upload data frame. After the FPGA receives the program upload data frame, if the verification is correct, it replies with a correct response. The DSP then proceeds to the next step. If the verification fails, it replies with an incorrect response. The DSP then returns to step 4.

[0056] 6. The DSP sends a start programming command frame. After receiving the command frame, the FPGA writes the first frame of data into the configuration chip and sends an upload data request frame to the DSP to proceed to the next step.

[0057] 7. The DSP receives the request frame and sends a new program upload data frame.

[0058] 8. After the FPGA receives a new program upload data frame, if the verification is correct, it writes the data to the configuration chip and simultaneously sends an upload data frame to the DSP, returning to step 7. If the verification fails, it sends an error response, which the DSP receives and returns to step 4. After the FPGA receives and writes 1000 frames of data, it sends a write completion response and proceeds to the next step.

[0059] 9. Upon receiving the write completion acknowledgment, the DSP sends a start verification command to the FPGA;

[0060] 10. After receiving the command frame, the FPGA starts downloading program data from the PROM. Every time the FPGA completes the reading of 1024 bytes of data, it forms a program verification data frame and sends it to the DSP. The DSP receives the data and stores it in the SDRAM. After transmitting all 512 frames of data, it proceeds to the next step.

[0061] 11. After the FPGA has sent 512 frames of data, the verification readback is complete, and the process proceeds to the next step.

[0062] 12. Once the DSP receives the verification readback completion, it begins to compare the programming data read back from the FPGA with the programming data uploaded by the ground testing equipment. If they match, it sends an upgrade success response to the ground testing equipment and proceeds to step 14. If they do not match, it sends an upgrade failure response to the ground testing equipment and proceeds to the next step.

[0063] 13. The geodetic equipment received an upgrade failure response and returned to step 1.

[0064] 14. Once the ground survey equipment receives a successful upgrade response, the inertial navigation system can be powered on again, and the FPGA can be configured with new programming data to begin operation.

[0065] If an FPGA configuration control circuit is added to an inertial navigation system (INS), and the DSP uses GPIO to control the state of the FPGA configuration control circuit, the DSP can control the FPGA to reconfigure after the FPGA upgrade is completed. The INS will then be able to operate according to the new programming data without the need to power on the INS again.

[0066] The specific FPGA configuration and control circuit structure is as follows: Figure 3 As shown, the system includes pull-up resistors, capacitors, and a microprocessor monitoring and control chip. In the diagram, the MAX708S is the microprocessor monitoring chip, providing reset control functionality. MR is the manual reset signal, and RESET is the reset output signal. When MR is low, RESET is low. When MR returns to high, the internal counter counts for 200ms, after which the RESET signal goes high.

[0067] As shown in the diagram, the DSP's GPIO pins are connected to the MR pins of the MAX708S for reset control. The FPGA's PROG_B signal is the FPGA's asynchronous reset logic configuration pin, active low, which can initiate FPGA reconfiguration and is driven by the MAX708S's reset output signal.

[0068] The DSP's GPIO pins are in a high-impedance state by default. Pull-up resistors ensure that MR is high when the circuit is working properly. After the FPGA upgrade is successful, the DSP controls the GPIO signal to go low, maintains the low level for more than 500ns, and then goes high. After that, the microprocessor monitors the chip's reset signal output to go low for about 200ms. Then the FPGA is reconfigured, loads the new programming data, and starts working again according to the new program.

Claims

1. A method for online FPGA upgrade based on serial communication, applicable to online FPGA upgrades of inertial combination products, characterized in that, Includes the following steps: Step 1: The FPGA programming data file is transferred to the DSP through ground testing equipment. The DSP temporarily stores the programming data file in the memory chip and verifies the correctness of the programming data file. If the verification is successful, notify the FPGA to start the upgrade and proceed to step two; if the verification fails, notify the ground testing equipment to retransmit the FPGA's programming data file. Step 2: The FPGA enters upgrade mode, and the FPGA begins to take over the communication interface of the configuration chip and erases the configuration chip; Step 3: The DSP transmits the FPGA's programming data file to the FPGA in blocks. The FPGA verifies the data after receiving each block of the programming data file. If the verification is successful, the configuration chip is written via the configuration chip communication interface; if the verification fails, return to step two until the DSP has transferred all programming data files and notifies the FPGA to start the upgrade verification; specifically, the following steps are included: Step 3.1: The DSP sends the first programming data file. After the FPGA receives the first programming data file, if the verification is correct, it replies with a correct response. The DSP then proceeds to the next step. If the verification fails, it replies with an incorrect response. The DSP then returns to step two. Step 3.2: The DSP sends a start programming command frame. After receiving the command frame, the FPGA writes the first programming data file to the configuration chip and sends an upload data request to the DSP to proceed to the next step. Step 3.3: Upon receiving the request, the DSP sends the next block of programming data file; Step 3.4: After receiving the programming data file, if the verification is correct, the FPGA writes it to the configuration chip and sends an upload data request to the DSP, then returns to step 3.

3. If the verification fails, it replies with an error response. After receiving the error response, the DSP returns to step two. This process continues until the DSP has transmitted all programming data files, at which point it notifies the FPGA to start the upgrade verification. Step 4: The FPGA enters the upgrade verification state. The FPGA reads the programming data file from the configuration chip in blocks and sends it back to the DSP. This continues until all programming data files are sent back, at which point the DSP is notified that the transmission is complete. Step 5: The DSP compares and verifies the programming data file in the memory chip with the programming data file returned by the FPGA. If the verification is correct, the FPGA upgrade is successful, and the FPGA configures the upgraded programming data file. If the verification fails, proceed to Step 2 until the FPGA upgrade is successful. The inertial combination product also includes an FPGA configuration control circuit. After the FPGA upgrade is successful, the DSP uses GPIO to control the state of the FPGA configuration control circuit, and directly controls the FPGA to configure the upgraded programming data file. The FPGA configuration control circuit includes pull-up resistors, capacitors, and a microprocessor monitoring chip. The GPIO pins of the DSP are connected to the MR pins of the microprocessor monitoring chip, and the RESET pins of the microprocessor monitoring chip are connected to the PROG_B pins of the FPGA.

2. The FPGA online upgrade method based on serial communication according to claim 1, characterized in that: In step one, the ground surveying equipment transmits the FPGA programming data file to the DSP frame by frame.

3. The FPGA online upgrade method based on serial communication according to claim 2, characterized in that, Step one specifically includes the following steps: Step 1.1: The ground surveying equipment sends an FPGA upgrade command to the DSP. After the DSP responds, it proceeds to the next step. Step 1.2: The ground surveying equipment sends a frame of programming data to the DSP. If the DSP verifies the data correctly, it stores the programming data in the memory chip and sends a correct response before starting to transmit the next frame. If the verification fails, it sends an error response and returns to step 1.

1.

4. The FPGA online upgrade method based on serial communication according to claim 3, characterized in that: The DSP's GPIO pins are in a high-impedance state by default. Pull-up resistors ensure that the MR pin is at a high level when the FPGA configuration control circuit is working properly. After the FPGA upgrade is successful, the DSP controls the GPIO signal to go low. The low level is maintained for more than 500ns before going high. After that, the microprocessor monitors the chip's RESET signal and outputs a low level for 200ms. Then the FPGA configures the upgraded programming data file.

5. A method for upgrading an inertial combination product using an FPGA, characterized in that: This includes upgrade methods for inertial combination products during the design and commissioning phases, as well as upgrade methods after delivery of inertial combination products; The upgrade of inertial combination products during the design and debugging phase is as follows: A connection is established between the FPGA configuration non-volatile memory and the PC via a dedicated USB downloader or programmer. The new FPGA programming data is then stored in the FPGA configuration non-volatile memory via a dedicated download program on the PC, thus completing the FPGA upgrade; or the FPGA upgrade is achieved using the FPGA online upgrade method based on serial communication as described in any of claims 1-4. The upgrade method after delivery of the inertial combination product is as follows: the FPGA is upgraded using the FPGA online upgrade method based on serial communication as described in any one of claims 1-4.

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