A method and system for implementing sine and cosine functions based on transcendental function acceleration instructions

Abstract

The present invention discloses a method and system for implementing sine and cosine functions based on transcendental function acceleration instructions. The method of the present invention includes reducing each element of the incoming vector operand vd to the interval [-π / 4, π / 4] to obtain the corresponding integer vector vql and the floating-point vector vdr within the interval [-π / 4, π / 4]; taking the remainder of the integer vector vql to obtain the integer vector vqln; according to the Taylor series expansion method, using transcendental function acceleration instructions to perform polynomial approximation calculations on the floating-point vector vdr and the integer vector vqln to obtain the calculation result vr of the vector sine function or the vector cosine function. For an instruction set architecture encoded with fixed-length instructions, the present invention does not require additional address calculation instructions and vector load instructions to obtain the coefficient constants of polynomial approximation from the constant pool, thereby greatly improving the performance of the vector sine function and the vector cosine function.

Description

Technical Field

[0001] The present invention belongs to the technical field of processor data parallelism and vector trigonometric function calculation, and particularly relates to a method and system for implementing sine and cosine functions based on transcendental function acceleration instructions, which are used to implement vector sine functions and vector cosine functions without memory access instructions in an instruction set architecture with fixed-length instruction encoding. Background Art

[0002] An instruction set architecture is all the instructions, registers, data types, and byte-level encoding methods of instructions defined by a processor. Different processor families have different instruction set architectures. For example, the IA32 and x86_64 instruction sets of Intel processors, the ARMv8 and ARMv9 instruction sets of ARM processors, the MIPS instruction set architecture, and the SPARC64 V instruction set developed by Fujitsu based on the open-source SPARC V9 instruction set. In terms of instruction encoding, some of these instruction set architectures use fixed-length instruction encoding, that is, all instructions in the instruction set architecture are encoded using bytecodes of the same length (32 bits or 64 bits). For example, ARMv8, ARMv9, MIPS, SPARC V9, and SPARC64 all use 32-bit fixed-length instruction encoding. Complex instruction sets such as IA32 and x86_64 use variable-length instruction encoding, and the encoding length of instructions ranges from 8 bits to 120 bits. Instruction sets using fixed-length instruction encoding simplify the instruction decoding process of the microarchitecture and reduce the complexity of the microarchitecture. However, they cannot encode immediate numbers and memory addresses of 64 bits or even 32 bits into instructions, and have to solve the problem that the instruction set cannot use immediate numbers (constants) or constant memory addresses in the form of a constant pool. These instruction set architectures store immediate numbers or memory addresses in a memory address space (constant pool) close to the instruction. When the instruction is executed, it will first calculate the memory address of the immediate number or constant memory address in the constant pool, then use a load instruction to load the immediate number or memory address at this memory address into a register, and finally the instruction uses this register for subsequent operations. For instruction sets using variable-length instruction encoding, immediate numbers and memory addresses are encoded into specific instructions for the instruction to directly use the immediate number for operations without using a constant pool and other additional instructions for address calculation and loading operations.

[0003] Modern processors contain vector processing units that can perform data-level parallelism and are important components of the processors. The instruction set architecture will include a part of instructions to operate the vector processor unit, and this part of the instruction set is called the SIMD instruction set (also known as the floating-point instruction set, vector instruction set). Vector registers, also known as floating-point registers, can store multiple elements compared to ordinary general-purpose registers and are the core storage components for running the SIMD instruction set. One SIMD instruction in the SIMD instruction set can operate on multiple elements stored in the vector register simultaneously. For an instruction set encoded with 32-bit fixed-length instructions, immediate constants cannot be encoded into SIMD instructions either. Instead, a constant pool is needed to store the immediate constants, and the memory address needs to be calculated before calling the corresponding SIMD instruction, and multiple immediate constants in the constant pool are loaded into each element of the vector register using the vector load instruction. Common SIMD instruction sets include the SSE2, AVX, AVX2, AVX512 instruction sets of Intel processors, the ADVSIMD and SVE instruction sets of ARM processors, and there are also corresponding SIMD extensions for the SPARC64 V instruction set. The industry also refers to various SIMD instructions as vector operations. The essence of vector operations is to apply ordinary scalar operations to each element in the vector register (or vector) and store the results in the corresponding elements of the vector register.

[0004] SIMD instruction set intrinsics are a set of C language interfaces provided by the SIMD instruction set. SIMD instruction set intrinsics enable programmers to directly use vector registers through the vector variable types provided by them in C / C++ languages, and directly use the corresponding vector instructions through the vector intrinsics functions provided by them. Since the vector registers and the intrinsics vector types correspond one by one, and the SIMD instructions and the SIMD intrinsics functions correspond one by one, in the implementation of this article, the intrinsics vector types are synonymous with the vector registers. In the implementation of this article, vectors refer to both vector registers and the intrinsics vector types, and vector operations and vector operations refer to both SIMD instructions and vector intrinsics functions.

[0005] The computer implementation process of sine and cosine functions generally consists of three steps: reduction, approximation, and reconstruction. Reduction is to use the symmetry and periodicity of trigonometric functions to map any interval into a specified interval (such as [-π / 4, π / 4]). Approximation is to calculate the approximate values of trigonometric functions in the interval [-π / 4, π / 4] through Taylor series expansion. For example, sin(x) can be approximated as:

[0006]

[0007] Reconstruction is to represent the trigonometric function values in any interval by the trigonometric function values in the interval [-π / 4, π / 4]. The vector sine function and the vector cosine function are vectorized using SIMD instructions internally. According to the vector width of the SIMD instruction set used, a single vector trigonometric function call will calculate multiple floating-point operands simultaneously, thus achieving several times of performance improvement. The vector sine and vector cosine functions will also follow these three steps and use SIMD instructions for vectorization.

[0008] The reduction of the sine function and the cosine function means reducing the function input x to the interval [0, C] or [-C / 2, C / 2]. The reduced result y can be obtained by the formula y = x - k×C (k is an integer and satisfies:

[0009]

[0010] In the above formula, represents the floor function.

[0011] For the IEEE 754 standard floating-point system widely used in today's computers, rounding errors may occur due to the loss of low-order digits in the calculation result of k multiplied by the floating-point constant C when the floating-point number x is large. The industry uses the Cody-Waite reduction algorithm to solve this problem. The Cody-Waite reduction algorithm splits the constant C into two double-precision floating-point numbers C1 and C2 to save the high-order and low-order bits of the constant C respectively (C = 1 + 2), thus avoiding errors in the reduction. The reduced result y is y = x - C1×k - C2×k. The industry also uses variants of the Cody-Waite algorithm (splitting C into 3 or 4 double-precision floating-point numbers or splitting k into two double-precision floating-point numbers) to improve the accuracy when the input x is very large. The vector function uses the vectorized Cody-Waite algorithm for reduction, adjusting each element of the input vector to the specified interval. The vector Cody-Waite algorithm is obtained by vectorizing each step of the ordinary Cody-Waite algorithm using the corresponding SIMD instructions.

[0012] The polynomial approximation of the sine function and the cosine function calculates the approximate value of the trigonometric function in the specified interval through Taylor series expansion. After the function input is reduced to [-π / 4, π / 4], it is obtained through Taylor series expansion (usually expanded 8 times):

[0013]

[0014] Due to the precision problem of the floating-point system, the computer implementation will use the formula that extracts x 2 :

[0015]

[0016] where x2 If it is calculated only once and reused repeatedly later, then the entire sine function implementation can be approximated as 8 consecutive floating-point multiply-add operations (multiply-add operation, also known as multiply-accumulate operation, which means adding the product of A and B to another number C as A×B + C) and 1 floating-point multiplication operation, and their addition operands are all constant coefficients. Similarly, the polynomial approximation of the cosine function is as follows:

[0017]

[0018] The cosine function implementation can also be approximated as 8 consecutive floating-point multiply-add operations and 1 floating-point multiplication operation. The difference is that the constant coefficients used in the 8 floating-point multiply-add operations and the constant 1 is used as the multiplication operand in the final multiplication operation. Vectorization of the polynomial approximation means replacing the 8 floating-point multiply-add operations and 1 floating-point multiplication element it uses with the corresponding vector floating-point multiply-add operation and vector multiplication operation.

[0019] The polynomial approximation process of the vector sine function and the vector cosine function will use 8 consecutive floating-point multiply-add operations, and their addition operands are all constant immediate numbers. For instruction sets with fixed-length instruction encoding, these 8 constants will be stored in the constant pool. Before each use of the vector floating-point multiply-add instruction, two steps will be experienced: calculating the address of the constant immediate number in the constant pool and using the vector load instruction to load the constant into the vector register. This means that in addition to using 8 consecutive vector floating-point multiply-add instructions in the entire polynomial approximation process, 8 additional address calculation instructions and 8 time-consuming vector load instructions will be introduced, which undoubtedly greatly reduces the performance of the vector sine function and the vector cosine function on these instruction set architectures.

[0020] Regarding this problem, some instruction set architectures have proposed solutions. They provide three transcendental function acceleration instructions to avoid obtaining the constants required in the polynomial approximation from the constant pool. Specifically: 1) The transcendental function multiply-add instruction trimad. This instruction uses two vector register operands vreg1 and vreg2 and an integer type immediate number as inputs. The immediate number input is used by the instruction to look up the constant coefficients required for the polynomial approximation from the hardware structure. This constant coefficient will be used as the addition operand to perform a vector floating-point multiply-add operation with the two vector registers. The numerical range of the immediate number is [0, 7], corresponding to the 8 constant coefficients used in the polynomial approximation of the sine function or the cosine function. The initial value of vreg1 is 0, corresponding to one of the multiplication operands in each vector floating-point multiply-add operation, and at the same time saving the result of this calculation as the input for the next time. vreg2 corresponds to x in the polynomial approximation 2 , since x 2 is a non-negative number and its sign bit (the 63rd bit) is always 0, so the sign bit of each element of this register is designed to save the positive or negative x 2, so that the trimad instruction can select, based on the sign bit, the constant coefficient using the polynomial approximation of the sine function or cosine function as the addition operand. 2) The transcendental function square instruction trimul is used to calculate the ±x required by the trimad instruction 2 , which uses two vector register operands vreg1 and vreg2 as inputs. vreg1 corresponds to the input x in the polynomial approximation. This instruction calculates the square value of x, and uses the 0th bit of the vreg2 element as the sign bit of the corresponding element of the calculation result, so as to determine whether the trimad instruction uses the constant coefficient of the sine function or cosine function. 3) The transcendental function selection instruction trisel is used to select whether the coefficient used in the last vector floating-point multiplication operation in the polynomial approximation calculation is x required by the sine function or the constant 1 required by the cosine function. This instruction uses two vector register operands vreg1 and vreg2 as inputs. vreg1 corresponds to the input x in the polynomial approximation. The 0th bit of the vreg2 element is used by this instruction to select whether to use the x or the constant 1 saved in the corresponding element of vreg1 as the output of the instruction. The 1st bit of the vreg2 element is used by this instruction to set the sign bit of the corresponding element of the output result, so as to determine whether it is necessary to take the opposite of the entire polynomial approximation result of the corresponding element. These three transcendental function acceleration instructions are implemented on the ARM processor, and the instruction names are the transcendental function square instruction ftsmul, the transcendental function selection instruction ftssel, and the transcendental function multiply-add instruction ftmad respectively. They are also implemented on the SPARC64 V instruction set developed by Fujitsu, and the instruction names are ftrismuld, ftrisseld, and ftrimaddd respectively.

[0021] Although these three transcendental function acceleration instructions are implemented on the ARM and SPARC64 V instruction sets, there has not yet been a mature implementation of vector sine function and vector cosine function based on transcendental function acceleration instructions in the industry. The commonly used vector math libraries SLEEF, FDLIBM, and Vector-libm in the industry also do not use transcendental function acceleration instructions to improve the performance of their vector sine function and vector cosine function. Summary of the Invention

[0022] The technical problem to be solved by the present invention: Aiming at the above problems of the prior art, the present invention provides a method and system for implementing sine and cosine functions based on transcendental function acceleration instructions. The present invention provides a method for implementing vector sine function and vector cosine function. For an instruction set architecture using fixed-length instruction encoding, there is no need to use additional address calculation instructions and vector load instructions to obtain the constant coefficients of the polynomial approximation from the constant pool, thereby greatly improving the performance of the vector sine function and vector cosine function.

[0023] To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0024] A method for implementing sine and cosine functions based on transcendental function acceleration instructions, comprising:

[0025] 1) Reducing each element of the incoming vector operand vd to the interval [-π / 4, π / 4], obtaining the corresponding integer vector vql and the floating-point vector vdr within the interval [-π / 4, π / 4];

[0026] 2) Obtaining the integer vector vqln by taking the modulus of the integer vector vql according to vqln = vql mod 4;

[0027] 3) According to the Taylor series expansion method, using transcendental function acceleration instructions to perform polynomial approximation calculations on the floating-point vector vdr and the integer vector vqln, obtaining the calculation result vr of the vector sine function or vector cosine function corresponding to the vector operand vd.

[0028] Optionally, step 1) includes:

[0029] 1.1) Judging whether all element values of the vector operand vd are within the preset interval [-CD, CD], where the value of the constant CD is 15. If all element values of the vector operand vd are within the preset interval [-CD, CD], then execute step 1.2); if any element value of the vector operand vd is not within the preset interval [-CD, CD], then execute step 1.3);

[0030] 1.2) Using the preset reduction algorithm 1 to reduce each element of the vector operand vd whose all element values are within the preset interval [-CD, CD] to the interval [-π / 4, π / 4], obtaining the corresponding integer vector vql and the floating-point vector vdr within the interval [-π / 4, π / 4], and each element in the integer vector vql satisfies vd - vql × SR × 2 = vdr, where the value of the constant SR is π / 4; execute step 2);

[0031] 1.3) Using the preset reduction algorithm 2 to reduce each element of the vector operand vd whose any element is not within the interval [-CD, CD] to the interval [-π / 4, π / 4], obtaining the corresponding integer vector vql and the floating-point vector vdr within the interval [-π / 4, π / 4], and each element in the integer vector vql satisfies vd - vql × SR × 2 = vdr, where the value of the constant SR is π / 4; execute step 2).

[0032] Optionally, determining whether all element values of the vector operand vd in step 1.1) are within a preset interval [-CD, CD] includes: first, broadcasting the constant CD into a floating-point vector vcond, then performing a vector floating-point absolute value operation on the vector operand vd and determining whether each element value in the operation result of the vector floating-point absolute value operation is less than the corresponding element value of the floating-point vector vcond, obtaining a comparison result of logical yes or logical no, and placing the comparison result in the floating-point vector vtmp. Finally, determining whether all values of the floating-point vector vtmp are logical yes. If all are logical yes, it is determined that all element values of the vector operand vd are within the preset interval [-CD, CD]; otherwise, it is determined that not all element values of the vector operand vd are within the preset interval [-CD, CD].

[0033] Optionally, step 1.2) includes: first, broadcasting the constants CM_2_PI, CNPID2_A2, and CNPID2_B2 required for reduction into floating-point vectors v_m_2_pi, vnppid2_a2, and vnpid2_b2, then obtaining the result of performing a vector floating-point multiplication operation on the vector operand vd and the floating-point vector v_m_2_pi, and performing integer rounding on each element of the result in a round-to-nearest mode to obtain a floating-point vector vdql. Then, using a vector type conversion function to perform integer type conversion on each element of the floating-point vector vdql to obtain an integer vector vql. At the same time, using the vector operand vd as an addition operand to perform a vector floating-point multiply-add operation with the floating-point vectors vdql and vnppid2_a2 to obtain a floating-point vector vdr as the result. Then, using the vector floating-point vector vdr as an addition operand to perform another vector floating-point multiply-add operation with the floating-point vectors vdql and vnpid2_b2, and saving the operation result in the floating-point vector vdr, so that the result in the floating-point vector vdr is the result of reducing the input vector operand vd to the interval [-SR, SR]. vql is an integer vector that satisfies vd - vql × SR × 2 = vdr, where the value of the constant SR is π / 4.

[0034] Optionally, step 1.3) includes: First, broadcast the constants M_2_PI_1_2_24, CM_2_PI, NPID2_A, NPID2_B, NPID2_C, NPID2_D, and C16 required for the reduction into floating-point vectors vm_2_pi_1_2_24, vm_2_pi, vnpid2_a, vnpid2_b, vnpid2_c, vnpid2_d, and vc16 respectively. Then perform a vector floating-point multiplication operation on the vector operand vd and the floating-point vector vm_2_pi_1_2_24, and round each element of the result of the vector floating-point multiplication operation in the round-towards-zero mode to obtain a vector integer rounding result. Then perform a vector floating-point multiplication operation on the rounded result and the floating-point vector vc16 to obtain a floating-point vector vdqh; then obtain the result of the vector floating-point multiply-add operation with the floating-point vector vdqh as the addition operand, the vector operand vd, and the floating-point vector vm_2_pi, and round the result in the round-to-nearest mode to obtain a floating-point vector vdql; then perform six vector floating-point multiply-add operations on the floating-point vector vdql and the floating-point vector vdqh in sequence. The first multiplication operand of these six vector floating-point multiplication operations is vnpid2_a, vnpid2_a, vnpid2_b, vnpid2_b, vnpid2_c, and vnpid2_c in sequence, and the second multiplication operand is the floating-point vector vdqh, vdql, vdqh, vdql, vdqh, and vdql in sequence. The addition operand of these vector floating-point multiply-add operations is the vector operand vd, and the result of each multiply-add operation is also placed in the vector operand vd for a vector floating-point multiply-add operation with continuous 6-time result accumulation; finally, obtain the result of the vector floating-point addition operation of the floating-point vector vdqh and the floating-point vector vdql, and perform another vector floating-point multiply-add operation on the result, the vector operand vd, and the floating-point vector vnpid2_d as the multiplication operand to obtain a floating-point vector vdr; meanwhile, after calculating the floating-point vector vdql, perform an integer type coercion on each element of the floating-point vector vdql to obtain an integer vector vql, so that the result of the floating-point vector vdr is the result of the input vector operand vd reduced to [-SR, SR], and the integer vector vql is the integer vector that satisfies vd - vql × SR × 2 = vdr, where the value of the constant SR is π / 4.

[0035] Optionally, step 2) includes: first broadcasting the integer constants 0x3 and 0x1 as integer vectors vci3 and vci1 respectively; then determining the type of the sine and cosine function implementation method. For example, if the type is to calculate the sine function of the vector operand vd, the integer vector vqln is obtained by getting the result of the vector bitwise logical AND operation between the integer vector vql and the integer vector vci3 (equivalent to taking the modulus of vql to get vqln); if the type is to calculate the cosine function of the vector operand vd, first perform a vector integer addition operation on the integer vector vql and the integer vector vci1, and then perform a vector bitwise logical AND operation on the operation result and the integer vector vci3 to obtain the integer vector vqln.

[0036] Optionally, the transcendental function acceleration instructions used in step 3) include the transcendental function square instruction trimul, the transcendental function select instruction trisel, and the transcendental function multiply-add instruction trimad.

[0037] Optionally, step 3) includes: first generating a floating-point vector vt with all elements being 0, then using the transcendental function square instruction trimul to perform a vector floating-point square operation on the floating-point vector vdr to obtain the square operation result vd2, setting the sign bit of the square operation result vd2 according to the integer vector vqln, and at the same time using the transcendental function select instruction trisel to perform a vector conditional selection according to the floating-point vector vdr and the integer vector vqln to obtain the last coefficient vls and its sign for the subsequent polynomial approximation calculation; then continuously using the transcendental function multiply-add instruction trimad eight times to perform a vector floating-point multiply-add operation with hardware table lookup support on the floating-point vector vt and the square operation result vd2. The immediate operand of these eight trimad instructions is 7, 6, 5, 4, 3, 2, 1, 0 in sequence. The transcendental function multiply-add instruction trimad performs hardware table lookup according to the used immediate operand to obtain the addition operand required in the vector floating-point multiply-add operation, and the calculation result of each transcendental function multiply-add instruction trimad also needs to be put into the floating-point vector vt for continuous accumulation. Finally, obtain the vector floating-point multiplication operation result of the floating-point vector vt and the coefficient vls as the calculation result vr of the vector sine function or vector cosine function corresponding to the vector operand vd.

[0038] In addition, the present invention also provides a sine and cosine function implementation system based on transcendental function acceleration instructions, including a microprocessor and a memory connected to each other. The microprocessor is programmed or configured to execute the steps of the sine and cosine function implementation method based on transcendental function acceleration instructions.

[0039] In addition, the present invention also provides a computer-readable storage medium, in which a computer program is stored, and this computer program is used to be executed by a microprocessor to implement the steps of the method for implementing sine and cosine functions based on transcendental function acceleration instructions.

[0040] Compared with the prior art, the present invention mainly has the following advantages:

[0041] 1. The method of the present invention is the first in the industry to provide a complete implementation of vector sine function and vector cosine function based on transcendental function acceleration instructions. For an instruction set architecture using fixed-length instruction encoding, the implementation of the method of the present invention can avoid using additional address calculation instructions and vector load instructions to load the constant coefficients required for polynomial approximation from the constant pool, thus greatly improving the performance of the vector sine function and vector cosine function implemented by this method.

[0042] 2. The present invention is not limited to a hardware platform, and the method of the present invention can be implemented on any instruction set architecture that provides transcendental function acceleration instructions. Therefore, the method of the present invention has good applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic diagram of the basic process of the method of the embodiment of the present invention.

[0044] Figure 2 It is a schematic diagram of the judgment branch process for the vector operand vd in the method of the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] As Figure 1 shown, the method for implementing sine and cosine functions based on transcendental function acceleration instructions in this embodiment includes:

[0046] 1) Reducing each element of the incoming vector operand vd to the interval [-π / 4, π / 4] to obtain the corresponding integer vector vql and the floating-point vector vdr within the interval [-π / 4, π / 4];

[0047] 2) Obtaining the integer vector vqln by taking the modulus of the integer vector vql according to vqln = vql mod 4;

[0048] 3) According to the Taylor series expansion method, using transcendental function acceleration instructions to perform polynomial approximation calculations on the floating-point vector vdr and the integer vector vqln to obtain the calculation result vr of the vector sine function or vector cosine function corresponding to the vector operand vd.

[0049] Referring to Figure 2 , step 1) of this embodiment includes:

[0050] 1.1) Determine whether all the element values of the vector operand vd are within the preset interval [-CD, CD], where the value of the constant CD is 15. If all the element values of the vector operand vd are within the preset interval [-CD, CD], then execute step 1.2); if any element value of the vector operand vd is not within the preset interval [-CD, CD], then execute step 1.3).

[0051] 1.2) Reduce each element of the incoming vector operand vd to the interval [-π / 4, π / 4] to obtain the corresponding integer vector vql and the floating-point vector vdr within the interval [-π / 4, π / 4], and each element in the integer vector vql satisfies vd - vql × SR × 2 = vdr, where the value of the constant SR is π / 4; execute step 2).

[0052] 1.3) Reduce each element of the incoming vector operand vd to the interval [-π / 4, π / 4] to obtain the corresponding integer vector vql and the floating-point vector vdr within the interval [-π / 4, π / 4], and each element in the integer vector vql satisfies vd - vql × SR × 2 = vdr, where the value of the constant SR is π / 4; execute step 2).

[0053] In this embodiment, determining whether all the element values of the vector operand vd are within the preset interval [-CD, CD] in step 1.1) includes: First, broadcast the constant CD as the floating-point vector vcond, then perform a vector floating-point absolute value operation on the vector operand vd and determine whether each element value in the operation result of the vector floating-point absolute value operation is less than the corresponding element value of the floating-point vector vcond to obtain a comparison result of logical yes or logical no, and place the comparison result in the floating-point vector vtmp. Finally, determine whether all the values of the floating-point vector vtmp are logical yes. If all are logical yes, then it is determined that all the element values of the vector operand vd are within the preset interval [-CD, CD]; otherwise, it is determined that not all the element values of the vector operand vd are within the preset interval [-CD, CD].

[0054] The method for implementing the vector sine and cosine functions based on the transcendental function acceleration instruction in this embodiment uses the periodicity and symmetry of the trigonometric functions to implement the vector sine function. The calculation result of the sine function for any input vd is represented by the calculation result of the sine function or cosine function in the interval [-π / 4, π / 4]. Any input vd in the real number domain can be expressed as vd = vdr + vql × π / 2, where vdr is a real number with a value range of [-π / 4, π / 4], and vql is a positive integer. vql can be expressed as:

[0055] vql = 4 × N + vqln,

[0056] In the above formula, N is a positive integer, and vqln = {0, 1, 2, 3}.

[0057] Then, sin(vd) will have four different calculation implementations due to the four values of vqln:

[0058] sin(vd) = sin(vdr + N×2π) = sin(vdr); vql = 4×N + vqln; vqln = 0,

[0059]

[0060] sin(vd) = sin(vdr + N×2π + π) = -sin(vdr); vql = 4×N + vqln; vqln = 2,

[0061]

[0062] This means that by first using the reduction algorithm to obtain the representation vdr (vdr = vd - vql×π / 2) in which vd is reduced to [-π / 4, π / 4], and vqln (vqln = vql mod 4), the sine function calculation result of vd can be calculated by the above four formulas for vdr, and vqln is used to select whether to use sin(vdr), cos(vdr), -sin(vdr), or -cos(vdr) for calculation.

[0063] Similarly, in this embodiment, the periodicity and symmetry of trigonometric functions are also used to implement the vector cosine function. The cosine function calculation result of the input vd is represented by the sine function or cosine function calculation result in the interval [-π / 4, π / 4]. cos(vd) will have four different calculation implementations due to the four values of vqln:

[0064] cos(vd) = cos(vdr + N×2π) = cos(vdr); vql = 4×N + vqln; vqln = 0,

[0065]

[0066] cos(vd) = cos(vdr + N×2π + π) = -cos(vdr); vql = 4×N + vqln; vqln = 2,

[0067]

[0068] By utilizing the periodicity and symmetry of the sine and cosine functions for reconstruction, the implementation of the vector sine function or the vector cosine function ultimately evolves into the actual calculation of the reduced vdr using sin(vdr), cos(vdr), -sin(vdr), or -cos(vdr). The difference between the sine function and the cosine function lies only in the different correspondence relationships between each vqln value and the calculation of sin(vdr), cos(vdr), -sin(vdr), or -cos(vdr). Therefore, in the method of this embodiment, the vector sine function and the vector cosine function share the same polynomial approximation calculation kernel, and the vqln generated by the reduction of the cosine function is adjusted to make it correspond to the correct calculation. Thus, this embodiment will first use the reduction algorithm to process the input vd, obtain the vdr adjusted to [-π / 4, π / 4] and the integer multiple vql of vd relative to vdr, then take the modulo of vql by 4 to obtain vqln, and specify the use of sin(vdr), cos(vdr), -sin(vdr), or -cos(vdr) for subsequent polynomial approximation calculation according to the value of vqln (specifying whether to calculate sin(vdr) or cos(vdr), and whether the calculation result needs to be negated). Since the vector sine function and the vector cosine function of this example share the same polynomial approximation calculation kernel using transcendental function acceleration instructions, this kernel accepts vdr and vqln as inputs, and vqln indicates that the kernel actually calculates sin(vdr), cos(vdr), -sin(vdr), or -cos(vdr). When calculating the sine function, when vqln is 0, the kernel uses sin(vdr) for calculation, when vqln is 1, it uses cos(vdr) for calculation, when vqln is 2, it uses -sin(vdr) for calculation, and when vqln is 3, it uses -cos(vdr) for calculation. When calculating the cosine function, the implementation of the vector cosine function in this example will add 1 to each element of the vql obtained by vector reduction and then take the modulo by 4 to obtain vqln. In fact, it adjusts the calculation corresponding to the vqln of the cosine function through coordinate rotation to make it correspond to the correct calculation of cos(vdr), -sin(vdr), -cos(vdr), or sin(vdr).

[0069] Based on the above principle description, the pseudocode of the vector sine function vsin in this embodiment can be expressed as:

[0070]

[0071] In the above pseudocode, vfloat_t and vint_t are used to represent the floating-point vector type and the integer vector type respectively. First, the vbcast_f() function is used to broadcast the constant CD (CD = 15) to each element of the vector vcond. Then, the vabs_f() function is used to calculate the absolute value of each element of the input vector vd, and the vcmplt_f() function is used to determine whether each element of the resulting vector is less than the corresponding element value of vcond. The comparison results are placed in the vector vtmp. Then, the testallones() function is used to determine whether each element value of vtmp is logically true, so as to achieve the purpose of determining whether each element of the input vector vd is within the interval [-CD, CD]. Then, according to the judgment results, reduction code 1 or reduction code 2 is used to perform reduction calculations, and the reduced results are placed in the vectors vdr and vql (vql is an integer multiple of vd compared to vdr). Reduction code 1 is directly implemented using the Cody-Waite algorithm and can only accurately reduce vd whose numerical range of each element is within the interval [-CD, CD]. When any element value of vd is outside the interval [-CD, CD], reduction code 2 needs to be used for reduction calculations. Reduction code 2 uses a variant of the Cody-Waite algorithm, and this variant algorithm can reduce vd whose numerical range is outside the interval [-CD, CD], but has higher complexity and worse performance. Therefore, in this example, two different reduction codes are used to handle the two cases where all elements of the input vector vd are within the interval [-CD, CD] and where any element is not within the interval [-CD, CD], so as to balance the performance and accuracy of the reduction algorithm in this embodiment. After obtaining vdr and vql through the reduction calculation in this example, the vand_i() function is used to calculate the bitwise logical AND operation result vqln of the vectors vql and 0x3 (0x3 is broadcast into the vector vci3 by the vbcast_i() function) to quickly calculate the remainder of vql divided by 4. Finally, the polynomial approximation calculation kernel code calculates the reduced vdr according to the indication of vqln, so as to obtain the calculation result vr of the entire vector sine function.

[0072] The pseudocode for implementing the vector cosine function vcos in this embodiment can be expressed as:

[0073]

[0074]

[0075] The pseudocode for implementing the vector cosine function vcos is similar to the vector sine function vsin in the previous text of this embodiment, and the only difference is that the vadd_i() function is first used to add 1 to each element of the reduced vector vql and then calculate the remainder of vql divided by 4 to achieve the purpose of adjusting vql.

[0076] In this embodiment, the pseudo-code of step 1.2) can be expressed as:

[0077]

[0078] vdr ← vd - vdql × PID2_A2;

[0079] vdr ← vdr - vdql × PID2_B2;

[0080] vql ← (int)vdql;

[0081] The above pseudo-code uses the Cody-Waite reduction algorithm to calculate vdr = vd - vql × π / 2 (vql is an integer multiple of vd by π / 2 In this embodiment, π / 2 is split into two double-precision floating-point constants PID2_A2 and PID2_B2 for storage (PID2_A2 stores an approximation of π / 2 using the upper 49 bits of the mantissa, and PID2_B2 stores the remaining significant digits of π / 2), and in the reduction code, vdr is calculated through vdr = vd - vql × PID2_A2 - vql × PID2_B2 (lines 2 and 3 of the above pseudo-code), and vql is obtained by multiplying vd by the reciprocal of π / 2 and then performing integer rounding (line 1), so as to avoid time-consuming division operations. vql ← (int)vdql means that the floating-point vector vdql is rounded to an integer vector vql.

[0082] The pseudo-code corresponding to step 1.2) implemented using C / C++ intrinsics can be expressed as:

[0083]

[0084]

[0085] The above pseudocode uses vfloat_t and vint_t to represent the floating-point vector type and the integer vector type respectively. Its implementation includes: using the vbcast_f function to broadcast the constants CM_2_PI, CNPID2_A2, and CNPID2_B2 required for reduction (CM_2_PI is the double-precision floating-point constant representation of 2 / π, and CNPID2_A2 and CNPID2_B2 are the opposites of the constants PID2_A2 and PID2_B2 respectively) to generate the vectors v_m_2_pi, vnpid2_a2, and vnpid2_b2. Then use the vmul_f() function to obtain the result of the vector floating-point multiplication operation of vd and v_m_2_pi, and use the vroundtozero_f() function to round each element of the result to an integer in the mode of rounding towards 0 to obtain the floating-point vector vdql. Then use the vcast_ftoi() function to cast each element of vdql to obtain the integer vector vql. At the same time, use the vmadd_f() function to perform a vector floating-point multiply-add operation on the vector vd as the addition operand, the vector vdql, and vnppid2_a2 to obtain the result vector vdr. Then use the vector vdr as the addition operand and perform a vector floating-point multiply-add operation with the vectors vdql and vnpid2_b2, and save the operation result to the floating-point vector vdr. The result in the vector vdr is the result after the input operand vd is reduced to the interval [-SR, SR] (SR = π / 4), and vql is the integer vector that satisfies vd - vql × SR × 2 = vdr. It should be noted that the constants CNPID2_A2 and CNPID2_B2 can be the same as the constants PID2_A2 and PID2_B2, so that the subsequent multiply-subtract function vmsub_f() can be used to replace the two multiply-add functions vmadd_f().

[0086] In this embodiment, the pseudocode for vector reduction of the input vector vd with any element not in the interval [-CD, CD] in step 1.3) can be expressed as:

[0087]

[0088] vdql ← [vd × CM_2_PI - vdqh];

[0089] vql ← (int)vdql;

[0090] vqh ← (int)vdqh;

[0091] vd ← vd - vdqh × PID2_A;

[0092] vd ← vd - vdql × PID2_A;

[0093] vd ← vd - vdqh × PID2_B;

[0094] vd ← vd - vdql × PID2_B;

[0095] vd ← vd - vdqh × PID2_C;

[0096] vd ← vd - vdql × PID2_C;

[0097] vd ← vd - (vdql + vdqh) × PID2_D;

[0098] This protocol code uses a variant of the Cody - Waite protocol algorithm to calculate vdr = vd - vq × π / 2 to improve the protocol accuracy. In this embodiment, the constant is split into 4 double - precision floating - point constants (π / 2 = PID2_A + PID2_B + PID2_C + PID2_D), and the variable vq is also split into 2 double - precision floating - point variables (vq = vqh + vql) to participate in the calculation of vdr. Thus, vdr is calculated by the following formula:

[0099] vdr = vd - (vqh × vql) × (PID2_A + PID2_B + PID2_C + PID2_D) = vd - vqh × PID2_A - vql × PID2_A - vqh × PID2_B - vql × PID2_B - vqh × PID2_C - vql × PID2_C - (vql + vqh) × PID2_D;

[0100] The calculation of vdr corresponds to 7 lines of multiply - accumulate code in lines 5 to 11 of the aforementioned pseudocode. vqh and vql are calculated by the code in lines 1 and 2. vdqh and vdql are obtained by separately calculating the multiple and remainder of vq with respect to C16. In this embodiment, C16 is set to C16 = 1 << 24, so that the lower 24 bits of the mantissa of vdqh and vdql are zero. Then, in lines 3 and 4, the floating - point numbers vdqh and vdql are respectively cast to integer variables vql and vqh using (int).

[0101] The pseudocode implemented using C / C++ intrinsics corresponding to step 1.3) can be expressed as:

[0102]

[0103]

[0104] The above pseudocode uses vfloat_t and vint_t to represent the floating-point vector type and integer vector type respectively. Its implementation includes: first, use the vbcast_f() function to broadcast the constants M_2_PI_1_2_24, CM_2_PI, NPID2_A, NPID2_B, NPID2_C, NPID2_D and C16 (M_2_PI_1_2_24 and CM_2_PI are the double-precision floating-point constant representations of (2 / ) / (16) and 2 / respectively, and NPID2_A, NPID2_B, NPID2_C and NPID2_D are the opposites of the constants PID2_A, PID2_B, PID2_C and PID2_D respectively) into the floating-point vectors vm_2_pi_1_2_24, vm_2_pi, vnpid2_a, vnpid2_b, vnpid2_c, vnpid2_d and vc16. Then use the vmul_f() function to perform a vector floating-point multiplication operation on vd and vm_2_pi_1_2_24, and use the vroundtozero_f() function to perform integer rounding on each element of the operation result in the round-towards-zero mode. Then perform a vector floating-point multiplication operation on the rounded result and vc16 to obtain the floating-point vector vdqh. Then use the vmadd_f() function to obtain the result of performing a vector floating-point multiply-add operation with the vector vdqh as the addition operand and the vectors vd and vm_2_pi, and use the vroundtoneast_f() function to perform vector integer rounding on the result in the round-to-nearest mode to obtain the floating-point vector vdql. Then perform six vector floating-point multiply-add operations on vdql and vdqh in sequence. The first multiplication operand of these six vector floating-point multiply-add operations is vnpid2_a, vnpid2_a, vnpid2_b, vnpid2_b, vnpid2_c and vnpid2_c in sequence, and the second multiplication operand is vdqh, vdql, vdqh, vdql, vdqh and vdql in sequence. The addition operand of these vector floating-point multiply-add operations is the vector vd, and the result of each multiply-add operation is also placed in the vector vd for accumulation. Finally, use the vadd_f() function to obtain the vector floating-point addition operation result of the vectors vdqh and vdql, and use vnpid2_d as the multiplication operand to perform another vector floating-point multiply-add operation on the result and the vector vd to obtain the floating-point vector vdr. At the same time, after calculating vdql, perform integer coercion on each element of vdql to obtain the integer vector vql. The result of the vector vdr is the result after the input operand vd is normalized to [-SR, SR], and vql is the integer vector that satisfies vd - vql × SR × 2 = vdr.It should be noted that the constants NPID2_A, NPID2_B, NPID2_C, and NPID2_D can be the same as the constants PID2_A, PID2_B, PID2_C, and PID2_D, so that the subsequent multiplication-subtraction function vmsub_f() can be used to replace the seven multiplication-addition functions vmadd_f().

[0105] In this embodiment, the transcendental function acceleration instructions used in step 3) include the transcendental function square instruction trimul, the transcendental function selection instruction trisel, and the transcendental function multiply-add instruction trimad. Specifically, step 3) includes: first generating a floating-point vector vt with all elements being 0, then performing a vector floating-point square operation on the floating-point vector vdr using the transcendental function square instruction trimul to obtain a square operation result vd2, setting the sign bit of the square operation result vd2 according to the integer vector vqln, and at the same time using the transcendental function selection instruction trisel to perform a vector conditional selection according to the floating-point vector vdr and the integer vector vqln to obtain the last coefficient vls and its sign for the subsequent polynomial approximation calculation; then continuously using the transcendental function multiply-add instruction trimad eight times to perform a vector floating-point multiply-add operation with hardware table lookup support on the floating-point vector vt and the square operation result vd2. The immediate operand of these eight trimad instructions is 7, 6, 5, 4, 3, 2, 1, 0 in sequence. The transcendental function multiply-add instruction trimad performs a hardware table lookup according to the used immediate operand to obtain the addition operand required in the vector floating-point multiply-add operation, and the calculation result of each transcendental function multiply-add instruction trimad also needs to be placed in the floating-point vector vt for continuous accumulation. Finally, the vector floating-point multiplication operation result of the floating-point vector vt and the coefficient vls is obtained as the calculation result vr of the vector sine function or vector cosine function corresponding to the vector operand vd. The pseudo-code implemented using C / C++ intrinsics for the above step 3) can be expressed as:

[0106]

[0107]

[0108] Among them, vt = vbcast_f(0.0) means generating a floating-point vector vt with all elements being 0; vd2 = vtrimul_f(vdr, vqln) means performing a vector floating-point square operation on the floating-point vector vdr using the trimul instruction to obtain the square operation result vd2; vls = vtrisel_f(vdr, vqln) means performing a vector conditional selection on the floating-point vector vdr and the integer vector vqln using the transcendental function selection instruction trisel to obtain the last coefficient vls for subsequent polynomial approximation calculations; subsequent vtrimad_f(vt, vd2, 7) to vtrimad_f(vt, vd2, 0) respectively mean continuously performing vector floating-point multiply-add operations for hardware table lookup support on the floating-point vector vt and the square operation result vd2 using the transcendental function multiply-add instruction trimad eight times; vr = vmul_f(vt, vls) means obtaining the vector floating-point multiplication operation result of the floating-point vector vt and the coefficient vls. In this embodiment, the pseudo-code implemented using assembly in step 3) can be expressed as:

[0109]

[0110] In the above pseudo-code implemented using assembly, the built-in functions used correspond one-to-one with the instructions in the pseudo-code implemented by C / C++ intrinsics mentioned above, and will not be elaborated here one by one.

[0111] In step 3) of this embodiment, vdr is used as the input for polynomial approximation calculation, vqln is used to control the constant coefficient of the sine function or cosine function in the polynomial approximation calculation, and to control whether the final calculation result needs to take the opposite number, so as to control whether the actual calculation content of the polynomial approximation calculation is sin(vdr), cos(vdr), -sin(vdr), or -cos(vdr). The value of vqln is {0, 1, 2, 3}. When vqln is 0 (the lower 2 bits of vqln are both 0), the trimul instruction sets the sign bit of vdr to 0. Setting the sign bit of vdr to 0 will cause the subsequent 8 polynomial approximation multiply-accumulate instructions trimad to use the constant coefficient of the sine function. vqln being 0 will also cause trisel to select the multiplication operand of the polynomial approximation calculation to be vdr required by the sine function, so that in step 6), sin(vdr) is finally calculated. When vqln is 1 (the lower 2 bits of vqln are 01), the trimul instruction sets the sign bit of vdr to 1. Setting the sign bit of vdr to 1 will cause the 8 trimad instructions to use the constant coefficient of the cosine function. vqln being 1 will also cause the trisel instruction to use the constant 1 required by the cosine function as the final multiplication operand, so that cos(vdr) is finally calculated. When vqln is 2 (the lower 2 bits of vql are 10), the trimul instruction sets the sign bit of vdr to 0, causing the trimad instruction to use the constant coefficient of the sine function. vqln being 2 will also cause trisel to use -vdr required by the sine function as the final multiplication operand, so that -sin(vdr) is finally calculated. Similarly, when vqln is 3, -cos(vdr) is finally calculated.

[0112] It should be noted that the immediate numbers used in the 8 trimad instructions in step 3) can be any 8 different constant immediate numbers, as long as these 8 immediate numbers correspond to the 8 constant coefficients required for polynomial approximation calculation in sequence. The immediate numbers used in the 8 trimad instructions in step 3) of this embodiment are 7, 6, 5, 4, 3, 2, 1, 0, that is, the immediate number 7 corresponds to the constant -1 / (15!) or -1 / (14!), the immediate number 6 corresponds to the constant 1 / (13!) or 1 / (12!), etc. If the trimad instruction implemented by the instruction set uses a different mapping relationship, the 8 immediate numbers used in step 3) also need to be modified accordingly to satisfy that the first trimad instruction of the polynomial approximation calculation uses -1 / (15!) or -1 / (14!) as the constant coefficient, the second trimad instruction uses 1 / (13!) or 1 / (12!) as the constant coefficient, etc.

[0113] It should also be noted that the vectors used in the process from step 1) to step 3) in this embodiment refer to both the vector registers in the SIMD instruction set and various vector types in the SIMD instruction set vector intrinsics. The vector operations implemented in the process from step 1) to step 3) can be either the vector instructions in the SIMD instruction set or the corresponding vector intrinsic functions in the SIMD instruction set vector intrinsics.

[0114] It should also be noted that the built-in functions, variable types, variable names, instruction names, and register names used in the process from step 1) to step 3) in this embodiment are only for illustrative purposes. In actual use, there is no need to be limited to the same names. Any built-in functions and assembly instructions that can perform the operations required in step 1) to step 3) of this embodiment can be used in the implementation of this method.

[0115] In summary, the method for implementing sine and cosine functions based on transcendental function acceleration instructions in this embodiment includes passing in the vector operand vd, and selecting two different vector reduction methods according to the numerical range of the vector operand to reduce each element of vd, so as to adjust the values of the elements of vd to the interval [-SR, SR] (SR = π / 4). Then, according to the Taylor series expansion method, the transcendental function acceleration instruction is used to perform polynomial approximation calculation on the reduced result vector vdr, so as to obtain the calculation results of the vector sine function or vector cosine function for the input vector vd. For the instruction set architecture with fixed-length instruction encoding, the method for implementing sine and cosine functions based on transcendental function acceleration instructions in this embodiment provides a method for implementing vector sine and cosine functions that avoids using memory access instructions in polynomial approximation calculation. For the instruction set architecture using fixed-length instruction encoding, this method does not need to use additional address calculation instructions and vector load instructions to obtain the constant coefficients of polynomial approximation from the constant pool, thereby greatly improving the performance of vector sine and cosine functions. Moreover, the method of this embodiment is not limited to the hardware platform and can be implemented on any instruction set architecture that provides transcendental function acceleration instructions, with good applicability.

[0116] In addition, this embodiment also provides a system for implementing sine and cosine functions based on transcendental function acceleration instructions, including a microprocessor and a memory connected to each other. The microprocessor is programmed or configured to execute the steps of the method for implementing sine and cosine functions based on transcendental function acceleration instructions described above.

[0117] In addition, this embodiment also provides a computer-readable storage medium, in which a computer program is stored. The computer program is used to be executed by the microprocessor to implement the steps of the method for implementing sine and cosine functions based on transcendental function acceleration instructions described above.

[0118] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in the flow Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks

[0119] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A method for implementing sine and cosine functions based on transcendental function acceleration instructions, belonging to the technical field of processor data parallelism and vector trigonometric function calculation, characterized in that The method for implementing the sine and cosine functions includes: 1) Reducing each element of the incoming vector operand vd to the interval [-π / 4, π / 4] to obtain the corresponding integer vector vql and the floating-point vector vdr within the interval [-π / 4, π / 4]; 2) Obtaining the integer vector vqln by taking the modulus of the integer vector vql according to vqln = vql mod 4; 3) According to the Taylor series expansion method, using transcendental function acceleration instructions to perform polynomial approximation calculations on the floating-point vector vdr and the integer vector vqln to obtain the calculation result vr of the vector sine function or vector cosine function corresponding to the vector operand vd; The transcendental function acceleration instructions used in step 3) include the transcendental function square instruction trimul, the transcendental function selection instruction trisel, and the transcendental function multiply-add instruction trimad; step 3) includes: first generating a floating-point vector vt with all elements being 0, then using the transcendental function square instruction trimul to perform vector floating-point square operation on the floating-point vector vdr to obtain the square operation result vd2, and setting the sign bit of the square operation result vd2 according to the integer vector vqln. At the same time, using the transcendental function selection instruction trisel to perform vector conditional selection according to the floating-point vector vdr and the integer vector vqln to obtain the last coefficient vls and its sign for the subsequent polynomial approximation calculation; then continuously using the transcendental function multiply-add instruction trimad eight times to perform vector floating-point multiply-add operations with hardware table lookup support on the floating-point vector vt and the square operation result vd2. The immediate operand of these eight trimad instructions is 7, 6, 5, 4, 3, 2, 1, 0 in sequence. The transcendental function multiply-add instruction trimad performs hardware table lookup according to the immediate operand used to obtain the addition operand required in the vector floating-point multiply-add operation, and the calculation result of each transcendental function multiply-add instruction trimad also needs to be placed in the floating-point vector vt for continuous accumulation. Finally, the vector floating-point multiplication operation result of the floating-point vector vt and the coefficient vls is obtained as the calculation result vr of the vector sine function or vector cosine function corresponding to the vector operand vd.

2. The method for implementing sine and cosine functions based on transcendental function acceleration instructions according to claim 1, wherein Step 1) includes: 1.1) Determine whether all element values of the vector operand vd are within a preset interval where the value of the constant CD is 15. If all element values of the vector operand vd are within the preset interval then perform step 1.2); if any element value of the vector operand vd is not within the preset interval then perform step 1.3); 1.2) For each element of the vector operand vd whose all element values are within a preset interval reduce it to the interval [-π / 4, π / 4] using a preset reduction algorithm 1, obtain the corresponding integer vector vql and the floating-point vector vdr within the interval [-π / 4, π / 4], and each element in the integer vector vql satisfies , where the constant has a value of π / 4; execute step 2); 1.3) For each element of the vector operand vd whose any element is not located in the interval use the preset reduction algorithm 2 to reduce it to the interval [-π / 4, π / 4], obtain the corresponding integer vector vql and the floating-point vector vdr located in the interval [-π / 4, π / 4], and each element in the integer vector vql satisfies , where the constant has a value of π / 4; execute step 2).

3. The method for implementing sine and cosine functions based on transcendental function acceleration instructions according to claim 2, characterized in that, In step 1.1), it is determined whether all element values of the vector operand vd are within a preset interval This includes: First, broadcast the constant CD as a floating-point vector vcond, then perform a vector floating-point absolute value operation on the vector operand vd and determine whether each element value in the operation result of this vector floating-point absolute value operation is less than the corresponding element value of the floating-point vector vcond, obtaining a comparison result of logical yes or logical no, and placing the comparison result in the floating-point vector vtmp. Finally, determine whether all values of the floating-point vector vtmp are logical yes. If they are all logical yes, it is determined that all element values of the vector operand vd are within the preset interval Otherwise, it is determined that not all element values of the vector operand vd are within the preset interval inside.

4. The method for implementing sine and cosine functions based on transcendental function acceleration instructions according to claim 2, wherein Step 1.2) includes: First, broadcast the constants CM_2_PI, CNPID2_A2, and CNPID2_B2 required for the reduction into floating-point vectors v_m_2_pi, vnppid2_a2, and vnpid2_b2. Then, obtain the result of the vector floating-point multiplication operation between the vector operand vd and the floating-point vector v_m_2_pi, and perform integer rounding on each element of the result in the round-to-nearest mode to obtain the floating-point vector vdql. Next, use the vector type conversion function to perform integer type conversion on each element of the floating-point vector vdql to obtain the integer vector vql. At the same time, use the vector operand vd as the addition operand to perform a vector floating-point multiply-add operation with the floating-point vectors vdql and vnppid2_a2 to obtain the floating-point vector vdr as the result. Then, use the vector floating-point vector vdr as the addition operand to perform another vector floating-point multiply-add operation with the floating-point vectors vdql and vnpid2_b2, and save the operation result to the floating-point vector vdr, so that the result in the floating-point vector vdr is the result of reducing the input vector operand vd to the interval, and vql is an integer vector that satisfies , where the constant has a value of π / 4.

5. The method for implementing sine and cosine functions based on transcendental function acceleration instructions according to claim 2, wherein Step 1.3) includes: First, broadcast the constants M_2_PI_1_2_24, CM_2_PI, NPID2_A, NPID2_B, NPID2_C, NPID2_D, and C16 required for the reduction into floating-point vectors vm_2_pi_1_2_24, vm_2_pi, vnpid2_a, vnpid2_b, vnpid2_c, vnpid2_d, and vc16 respectively. Then, perform a vector floating-point multiplication operation on the vector operand vd and the floating-point vector vm_2_pi_1_2_24, and round each element of the result of the vector floating-point multiplication operation in the round-towards-zero mode to obtain a vector integer rounding result. Then, perform a vector floating-point multiplication operation on the rounded result and the floating-point vector vc16 to obtain the floating-point vector vdqh. Then, obtain the result of the vector floating-point multiply-add operation with the floating-point vector vdqh as the addition operand, the vector operand vd, and the floating-point vector vm_2_pi, and round the result in the round-to-nearest mode to obtain the floating-point vector vdql. Then, perform six vector floating-point multiply-add operations on the floating-point vector vdql and the floating-point vector vdqh in sequence. The first multiplication operand of these six vector floating-point multiplication operations is vnpid2_a, vnpid2_a, vnpid2_b, vnpid2_b, vnpid2_c, and vnpid2_c in sequence, and the second multiplication operand is the floating-point vector vdqh, vdql, vdqh, vdql, vdqh, and vdql in sequence. The addition operand of these vector floating-point multiply-add operations is the vector operand vd, and the result of each multiply-add operation is also placed in the vector operand vd for a continuous 6-time result accumulation vector floating-point multiply-add operation. Finally, obtain the result of the vector floating-point addition operation of the floating-point vector vdqh and the floating-point vector vdql, and perform another vector floating-point multiply-add operation on the result, the vector operand vd, and the floating-point vector vnpid2_d as the multiplication operand to obtain the floating-point vector vdr. At the same time, after calculating the floating-point vector vdql, perform an integer type coercion on each element of the floating-point vector vdql to obtain the integer vector vql, so that the floating-point vector vdr is the result of reducing the input vector operand vd to and the integer vector vql is the integer vector that satisfies , where the constant has a value of π / 4.

6. The method for implementing sine and cosine functions based on transcendental function acceleration instructions according to claim 1, wherein Step 2) includes: first broadcasting the integer constants 0x3 and 0x1 as the integer vectors vci3 and vci1 respectively; then judging the type of the method for implementing the sine and cosine functions. If the type is to calculate the sine function of the vector operand vd, then obtaining the integer vector vqln by getting the vector bitwise logical AND operation result of the integer vector vql and the integer vector vci3; if the type is to calculate the cosine function of the vector operand vd, then first performing vector integer addition operation on the integer vector vql and the integer vector vci1, and then performing vector bitwise logical AND operation on the operation result and the integer vector vci3 to obtain the integer vector vqln.

7. A sine and cosine function implementation system based on transcendental function acceleration instructions, comprising a microprocessor and a memory connected to each other, characterized in that The microprocessor is programmed or configured to execute the steps of the method for implementing the sine and cosine functions based on transcendental function acceleration instructions described in any one of claims 1 to 6.

8. A computer-readable storage medium storing a computer program therein, characterized in that, The computer program is used to be executed by a microprocessor to implement the steps of the method for implementing sine and cosine functions based on transcendental function acceleration instructions according to any one of claims 1 to 6.

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