Paper Count Measurement System and Method Based on Capacitive Sensor

Abstract

This invention relates to a paper count measurement system based on a capacitive sensor, comprising a paper sampling calibration or measurement device, a data processing device for processing the sampling calibration or measurement data, and a power supply device for powering the paper sampling calibration or measurement device and the data processing device. This invention also provides a paper count measurement method, including a paper count calibration step, a paper count detection step, and a paper count query step. This invention achieves high-speed, high-precision paper count measurement, and has advantages such as good stability, high reliability, good compatibility, good scalability, and abundant and flexible resources, overcoming the disadvantages of large errors and low efficiency associated with manual or mechanical counting methods.

Description

Technical Field

[0001] This invention belongs to the field of paper detection and counting technology, and particularly relates to a paper count measurement system and method using a capacitive sensor. Background Technology

[0002] With the rapid development of information technology and the widespread application of modern electronic technology, the repeated counting of batches of paper has become particularly important in the actual industrial production activities of the printing and papermaking industries. Currently, the core issue in paper counting is converting the non-electrical quantity of paper into electrical parameters (such as voltage, current, and frequency). One of the key factors in paper counting is the breakthrough and integrated application of sensor detection principles and data acquisition technologies. The field of data acquisition is becoming increasingly complex, placing higher demands on the speed and accuracy of data acquisition. Traditional sampling methods, due to their low clock frequency and slow peripheral speeds, greatly limit the performance of sensor data acquisition.

[0003] Currently, the main methods for counting paper quantities include manual or mechanical counting, thickness or weight measurement, and machine vision recognition. However, traditional methods have large errors and low efficiency, while machine vision recognition requires high paper edge quality. The main problems with existing paper counting systems are: first, the lack of a time-efficient, high-accuracy, and highly reliable system; second, the method of using dedicated sensors to convert changes in paper count into changes in capacitance, and further into changes in voltage or frequency, and then counting paper by measuring voltage or frequency, cannot meet the requirements of paper counting in environments with complex factors; and third, the measurement systems have poor versatility, high maintenance costs, and poor portability.

[0004] Therefore, there is a need to develop a paper counting system that is time-efficient, highly accurate, reliable, low-cost, stable, has rich interfaces, and is highly versatile, providing rich interfaces for the business expansion of user applications and effectively solving the core technical problem of paper counting. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a paper counting system and method based on capacitive sensors that can overcome the problems of manual or mechanical counting of paper counts, effectively improve the stability, reliability and efficiency of paper count measurement, reduce measurement time and hardware cost of paper count measurement devices, and provide rich resource interfaces for easy expansion.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a paper number measurement system based on a capacitive sensor, comprising a paper sampling calibration or measurement device, a data processing device for processing the sampling calibration or measurement data, and a power supply device for supplying power to the paper sampling calibration or measurement device and the data processing device;

[0007] The paper sampling calibration or measurement device includes a capacitive plate probe for sampling, calibrating, or measuring the number of sheets of paper. The capacitive plate probe is the integrating capacitor of the integrating circuit. A DDS signal generator is electrically connected to the integrating circuit and the signal conditioning circuit in sequence via a power amplifier circuit. The DDS signal generator is used to amplify the sinusoidal excitation signal through the power amplifier circuit and output it to the integrating circuit and the signal conditioning circuit. The integrating circuit and the signal conditioning circuit are used to output the input sinusoidal excitation signal as a voltage amplitude signal. The device also includes a reference voltage source circuit electrically connected to the power amplifier circuit and the signal conditioning circuit, respectively. The reference voltage source circuit is used to provide a reference voltage for the power amplifier circuit and the signal conditioning circuit.

[0008] The data processing device includes a processor chip. The integration circuit is connected to the analog-to-digital converter (ADC) of the processor chip through a signal conditioning circuit. The voltage amplitude signal output by the signal conditioning circuit is within the sampling voltage range of the ADC. The ADC is used to quantize the voltage amplitude signal output by the signal conditioning circuit to obtain the sampling calibration or measurement amplitude value.

[0009] The data processing device further includes a cache SDRAM, an E2PROM memory, and an SD-Card for storing data, and is electrically connected to the processor chip. In data storage, the processor chip stores multiple sets of instantaneous voltage values ​​obtained by sampling, calibration, or measurement in the cache SDRAM of the processor chip, and calculates the calibration amplitude value from the multiple sets of instantaneous voltage values. At the same time, the calibration data corresponding to the number of sampled sheets and the multiple sets of calibration amplitude values ​​obtained by the processor chip through cyclic sampling, calibration, or measurement are stored sequentially in the E2PROM memory of the processor chip according to the calibration or measurement order, and the result of the number of sheets to be measured by sampling and measurement is stored in the SD-Card.

[0010] It also includes a TFT-LCD touch screen electrically connected to the processor chip, which is used to provide users with an interactive interface to query historical measurement records.

[0011] Furthermore, the reference voltage source circuit includes a 12V DC power supply, which is connected to the second pin of the Zener diode U1 via a current-limiting resistor R1. The third pin of the Zener diode U1 is grounded, and the first pin of the Zener diode U1 is left floating. The reference voltage 5V output from the second pin of the Zener diode U1 is filtered by a capacitor C1 and then connected in series with voltage divider resistors R2 and R6 and a precision adjustable potentiometer R4 to ground. The precision adjustable potentiometer R4 outputs a first reference voltage Vref1 from its center tap, which is used to provide a reference voltage for the power amplifier circuit.

[0012] The center tap of the first adjustable potentiometer R4 is connected to the filter capacitor C2. The second pin of the Zener diode U1 outputs a reference voltage of 5V, which is connected in series with the voltage divider resistors R3 and R7 and the adjustable potentiometer R5 to ground. Adjusting the knob of the adjustable potentiometer R5 connects to the filter capacitor C3 from the center tap and outputs a second reference voltage Vref2, which is used to provide a reference voltage for the signal conditioning circuit 16.

[0013] The 12V DC power supply has the following characteristics: the resistance of the current-limiting resistor R1 is 2-10kΩ; the capacitance of the filter capacitor C1 is 50-220uF; the resistance of the voltage divider resistor R2 is 5-20kΩ; the resistance of the precision adjustable potentiometer R4 is 50-200kΩ; the resistance of the voltage divider resistor R6 is 5-20kΩ; the capacitance of the filter capacitor C2 is 1-22uF; the resistance of the third voltage divider resistor R3 is 5-20kΩ; the resistance of the adjustable potentiometer R5 is 50-200kΩ; and the resistance of the seventh voltage divider resistor R7 is 5-20kΩ.

[0014] Furthermore, the DDS signal generating device includes a DDS signal generator U2 and a non-inverting operational amplifier U3. The operating voltage terminal of the DDS signal generator U2 is connected to a DC power supply of 5V. The frame synchronization signal terminal FSY, serial clock input terminal SCK, serial data input terminal SDA, reset terminal RST, frequency selection terminal FS, and phase selection terminal PA of the DDS signal generator U2 are connected to the GPIO interface of the processor chip. The output terminal VOUT of the DDS signal generator U2 is filtered by an electrolytic filter capacitor C6 and a ceramic filter capacitor C5, and then passed through a bias current. A balancing resistor R10 is connected to the non-inverting input terminal IN+ of the non-inverting operational amplifier U3. The output terminal OUT of the non-inverting operational amplifier U3 is connected to ground via an adjustable dividing resistor VR2, a voltage dividing resistor R16, and a voltage dividing resistor R18. The common terminal of the voltage dividing resistors R16 and R18 is connected to the inverting input terminal IN- of U3. The output terminal OUT of the non-inverting operational amplifier U3 is also connected to the inverting input terminal IN- of the differential amplifier U4 via a feedback resistor R11. The VS+ terminal of the non-inverting operational amplifier U3 is connected to a positive 12V DC power supply, and the VS- terminal is connected to a negative 12V DC power supply.

[0015] The reference voltage provided by the reference voltage source circuit is grounded through voltage divider resistors R12 and R14 in series. The common terminal of voltage divider resistors R12 and R14 is connected to the non-inverting input terminal IN+ of the differential amplifier U4. The VS+ terminal of the differential amplifier U4 is connected to a positive 12V DC power supply, and the VS- terminal is connected to a negative 12V DC power supply. The output terminal OUT of the differential amplifier U4 is connected to the filter resistor R13 and filter capacitor C7 of the RC passive filter in series and grounded. The common connection point of the filter resistor R13 and filter capacitor C7 is connected to the PNP transistor Q2 of the Class B push-pull power amplifier. At the same time, the output terminal OUT of the differential amplifier U4 is connected to the inverting input terminal IN- of the differential amplifier U4 after being connected in series with the adjustable feedback resistor VR1 and the feedback resistor R9.

[0016] The PNP transistor Q2 and NPN transistor Q1 are connected in series between a DC power supply of +12V and a DC power supply of -12V. The system also includes a first resistor R8, a diode D1, a diode D2, and a resistor R17 connected in parallel with the PNP transistor Q2 and NPN transistor Q1, and connected in series sequentially. These components provide a static operating point bias current for the NPN transistor Q1 and the PNP transistor Q2. The common terminal of the resistor R8 and the diode D1 is connected to the NPN transistor. The base input terminal of Q1, the common terminal of diode D2 and resistor R17 are connected to the base input terminal of transistor Q2. The collector terminal of transistor Q1 is connected to a DC power supply of positive 12V, and the collector terminal of transistor Q2 is connected to a DC power supply of negative 12V. After the emitter terminals of NPN transistors Q1 and Q2 are connected, a series coupling capacitor C4 is connected to output a sinusoidal excitation signal Vsine with adjustable voltage amplitude and DC component. The sinusoidal excitation signal Vsine is connected to ground by a load resistor R15.

[0017] Furthermore, the electrolytic filter capacitor C6 has a capacitance of 1–22 μF; the ceramic filter capacitor C5 has a capacitance of 0.01–0.47 μF; the bias current balancing resistor R10 has a resistance of 5–20 kΩ; the voltage divider resistor R16 has a resistance of 5–20 kΩ; the voltage divider resistor R18 has a resistance of 5–20 kΩ; the adjustable voltage divider resistor VR2 has a resistance of 50–200 kΩ; the feedback resistor R11 has a resistance of 5–20 kΩ; and the voltage divider resistor R12 has a resistance of 5–20 kΩ. Ω; the resistance of voltage divider resistor R14 is 10~50kΩ; the resistance of feedback resistor R9 is 5~20kΩ; the resistance of feedback resistor VR1 is 5~20kΩ; the resistance of filter resistor R13 is 50~200kΩ; the capacitance of filter capacitor C7 is 0.01~0.47uF; the resistance of resistor R8 is 5~20kΩ; the resistance of resistor R17 is 5~20kΩ; the capacitance of series coupling capacitor C4 is 50~220uF; the resistance of resistor R15 is 1~5kΩ.

[0018] Furthermore, the integrating circuit includes an integrating resistor R21. The sinusoidal excitation signal Vsine output by the DDS signal generator is connected in series with the integrating resistor R21 and then connected to the inverting input terminal IN- of the integrating operational amplifier U5. A feedback resistor R19 and a capacitive plate probe 14 are connected in parallel between the output terminal OUT and the inverting input terminal IN- of the integrating operational amplifier U5. The non-inverting input terminal IN+ of the integrating operational amplifier U5 is connected in series with a resistor R25 and then grounded. The VS+ terminal of U5 is connected to a positive 12V DC power supply, and the VS- terminal of the integrating operational amplifier U5 is connected to a negative 12V DC power supply.

[0019] The output terminal OUT of the integrating operational amplifier U5 is connected to the non-inverting input terminal IN+ of the voltage follower U6. The output terminal OUT of the voltage follower U6 is directly connected to the inverting input terminal IN-. The VS+ terminal of the voltage follower U6 is connected to a positive 12V DC power supply, and the VS- terminal of U6 is connected to a negative 12V DC power supply.

[0020] The signal conditioning circuit includes a differential amplifier U7. The output terminal OUT of the voltage follower U6 is connected to the inverting input terminal IN- of the differential amplifier U7 after being connected in series with the input resistor R22. The output terminal OUT of the differential amplifier U7 is connected to the inverting input terminal IN- of the differential amplifier U7 after being connected in series with the adjustable feedback resistor VR3 and the feedback resistor R20. The reference voltage output by the reference voltage source circuit is grounded through voltage divider resistors R23 and R26 in series. The common terminal of voltage divider resistors R23 and R26 is connected to the non-inverting input terminal IN+ of the differential amplifier U7. The VS+ terminal of the differential amplifier U7 is connected to a positive 12V DC power supply, and the VS- terminal of the differential amplifier U7 is connected to a negative 12V DC power supply. The output terminal OUT of the differential amplifier U7 is connected to the filter resistor R24 ​​and the filter capacitor C8 of the RC passive filter in series and grounded. The common connection point of the filter resistor R24 ​​and the filter capacitor C8 is the output voltage amplitude signal Vadc of the signal conditioning circuit.

[0021] Furthermore, the resistance value of the integrating resistor R21 is 5-20kΩ; the resistance value of the resistor R25 is 5-20kΩ; the resistance value of the feedback resistor R19 is 50-200kΩ; the resistance value of the input resistor R22 is 5-20kΩ; the resistance value of the voltage divider resistor R23 is 5-20kΩ; the resistance value of the voltage divider resistor R26 is 5-20kΩ; the resistance value of the feedback resistor R20 is 5-20kΩ; the resistance value of the adjustable feedback resistor VR3 is 50-200kΩ; the resistance value of the filter resistor R24 ​​is 50-200kΩ; and the capacitance value of the filter capacitor C8 is 0.01-0.47uF.

[0022] Furthermore, the processor chip is also electrically connected to a buzzer, mechanical buttons, a UART interface, and a JTAG interface; the buzzer is used to indicate the end or start of sampling calibration or measurement, the mechanical buttons are used to control the start of sampling calibration or measurement, the UART interface is used to output running process information for debugging programs, and the JTAG interface is used to download and trace debugging programs.

[0023] The UART interface uses the integrated chip MAX3232CSE; the SD-Card uses the FAT32 format and the FatFs R0.14 file system.

[0024] Furthermore, the integration circuit and signal conditioning circuit use the integrated chip OP37GP; the processor chip uses the integrated chip MIMXRT1052DVL6B based on the ARM embedded system; the E2PROM memory uses the integrated chip AT24C16N; the SDRAM cache uses the integrated chip W9825G6KH-6; the TFT-LCD touch screen is a 5-inch LCD screen based on MS90C385; and there are two capacitive electrode probes, with coaxial shielded cables used for the probe leads.

[0025] The present invention also includes a paper count measurement method for the paper count measurement system based on the capacitive sensor, comprising the following steps:

[0026] 1) Paper calibration steps: Place the calibration paper in the sensing area of ​​the capacitive electrode probe, and use the mechanical button to start the paper calibration. The DDS signal generator sends a sinusoidal excitation signal Vsine with an amplitude of 1-230mV and a frequency of 1-100000Hz to the integrating circuit. The integrating circuit outputs the sinusoidal excitation signal Vsine as a cosine signal with a constant frequency and a decrease in amplitude of 1-100mV. The cosine signal then outputs a voltage signal through the signal conditioning circuit and is processed by the processor chip. The chip quantizes the voltage signal into at least (10-20) × 1024 sets of instantaneous voltage values ​​and stores the instantaneous voltage values ​​in the cache SDRAM. The processor chip calculates a set of calibration amplitude values ​​and the corresponding number of sheets for the at least (10-20) × 1024 sets of instantaneous voltage values. The instantaneous voltage values ​​are collected cyclically to obtain multiple sets of calibration amplitude values ​​and corresponding number of sheets. The calibration amplitude values ​​and the calibration data corresponding to the number of sampled sheets are stored in the E2PROM memory to complete the calibration of the number of sheets.

[0027] 2) Paper Count Measurement Steps: Place the paper to be measured within the sensing area of ​​the capacitive electrode probe. Use the mechanical button to start the paper measurement. The DDS signal generator sends a sinusoidal excitation signal Vsine with an amplitude of 1-230mV and a frequency of 1-100000Hz to the integrating circuit. The integrating circuit outputs a cosine signal with a constant frequency and a decrease in amplitude of 1-100mV from the sinusoidal excitation signal Vsine. The cosine signal then outputs a voltage signal through the signal conditioning circuit. The processor chip quantizes the voltage signal into an instantaneous voltage value. The measured instantaneous voltage value is compared with the multiple sets of amplitude values ​​to obtain the corresponding paper count, which is the final actual paper count. Simultaneously, the processor chip stores the actual measured paper count in the SD-Card, completing the paper count measurement.

[0028] Furthermore, the processor chip displays the query information on the TFT-LCD touch screen using the data stored in the SD-Card and E2PROM memory. The TFT-LCD touch screen is used to enable users to query historical measurement records through an interactive interface.

[0029] The beneficial effects of this invention are: the technical solution of this invention adopts a system architecture that combines two capacitive parallel plate probe sensors and signal conditioning circuits with an embedded processor measurement system, realizing high-speed and high-precision measurement of the number of papers. It has the advantages of good stability, high reliability, good compatibility, good scalability, and abundant and flexible resources, and overcomes the disadvantages of large errors and low efficiency of manual or mechanical counting. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the paper count measurement system in this invention;

[0031] Figure 2 This is the circuit diagram of the reference voltage in this invention;

[0032] Figure 3 This is a power amplifier circuit diagram of the DDS module in this invention;

[0033] Figure 4 This is the capacitive sensor signal conditioning circuit in this invention;

[0034] Figure 5 This is a flowchart of the main control program of the paper number measurement system in this invention.

[0035] In the diagram: 1. Paper sampling calibration or measuring device; 11. DDS signal generator; 12. Power amplifier circuit; 13. Reference voltage source circuit; 14. Capacitive electrode probe; 15. Integrating circuit; 16. Signal conditioning circuit; 2. Data processing device; 21. Processor chip; 22. UART interface; 23. SD-Card card; 24. JTAG interface; 25. TFT-LCD touch screen; 26. E2PROM memory; 27. Buffer SDRAM; 28. Mechanical buttons; 29. ​​Buzzer; 3. Power supply device. Detailed Implementation

[0036] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0037] To achieve the above objectives, the present invention provides the following specific embodiments:

[0038] Example 1: As Figures 1 to 5 As shown, a paper counting system based on a capacitive sensor includes a paper sampling calibration or measuring device 1, a data processing device 2 for processing sampling calibration or measuring data, and a power supply device 3 for supplying power to the paper sampling calibration or measuring device 1 and the data processing device 2.

[0039] like Figure 1 As shown, the paper sampling calibration or measurement device 1 includes a capacitive electrode probe 14 for sampling, calibrating, or measuring the number of sheets of paper. The capacitive electrode probe 14 is the integrating capacitor of the integrating circuit 15. The DDS signal generator 11 is electrically connected to the integrating circuit 15 and the signal conditioning circuit 16 in sequence through the power amplifier circuit 12. The DDS signal generator 11 is used to amplify the sinusoidal excitation signal through the power amplifier circuit 12 and output it to the integrating circuit 15 and the signal conditioning circuit 16. The integrating circuit 15 and the signal conditioning circuit 16 are used to output the input sinusoidal excitation signal as a voltage amplitude signal. The device also includes a reference voltage source circuit 13 that is electrically connected to the power amplifier circuit 12 and the signal conditioning circuit 16 respectively. The reference voltage source circuit 13 is used to provide a reference voltage for the power amplifier circuit 12 and the signal conditioning circuit 16.

[0040] like Figure 2As shown, the reference voltage source circuit 13 includes a 12V DC power supply. The 12V DC power supply is connected to the second pin of the Zener diode U1 via a current-limiting resistor R1. The third pin of the Zener diode U1 is grounded, and the first pin of the Zener diode U1 is left floating. The reference voltage 5V output from the second pin of the Zener diode U1 is filtered by a filter capacitor C1 and then connected in series with the voltage divider resistors R2 and R6 and the precision adjustable potentiometer R4 to ground. The precision adjustable potentiometer R4 outputs a first reference voltage Vref1 from the center tap, which is used to provide a reference voltage for the power amplifier circuit 12.

[0041] The center tap of the first adjustable potentiometer R4 is connected to the filter capacitor C2. The second pin of the Zener diode U1 outputs a reference voltage of 5V, which is connected in series with the voltage divider resistors R3 and R7 and the adjustable potentiometer R5 to ground. Adjusting the knob of the adjustable potentiometer R5 connects to the filter capacitor C3 from the center tap and outputs a second reference voltage Vref2, which is used to provide a reference voltage for the signal conditioning circuit 16.

[0042] The 12V DC power supply is supplied through a current-limiting resistor R1 with a resistance of 2–10kΩ; a filter capacitor C1 with a capacitance of 50–220uF; a voltage divider resistor R2 with a resistance of 5–20kΩ; a precision adjustable potentiometer R4 with a resistance of 50–200kΩ; a voltage divider resistor R6 with a resistance of 5–20kΩ; a filter capacitor C2 with a capacitance of 1–22uF; a third voltage divider resistor R3 with a resistance of 5–20kΩ; an adjustable potentiometer R5 with a resistance of 50–200kΩ; and a seventh voltage divider resistor R7 with a resistance of 5–20kΩ.

[0043] like Figure 3 As shown, the DDS signal generator 11 includes a DDS signal generator U2 and a non-inverting operational amplifier U3. The operating voltage terminal of the DDS signal generator U2 is connected to a DC power supply of 5V. The frame synchronization signal terminal FSY, serial clock input terminal SCK, serial data input terminal SDA, reset terminal RST, frequency selection terminal FS, and phase selection terminal PA of the DDS signal generator U2 are connected to the GPIO interface of the processor chip 21. The output terminal VOUT of the DDS signal generator U2 is filtered by an electrolytic filter capacitor C6 and a ceramic filter capacitor C5, and then passed through a bias current leveling device. The balancing resistor R10 is connected to the non-inverting input terminal IN+ of the non-inverting operational amplifier U3. The output terminal OUT of the non-inverting operational amplifier U3 is connected to ground via an adjustable dividing resistor VR2, voltage dividing resistors R16 and R18 in series. The common terminal of voltage dividing resistors R16 and R18 is connected to the inverting input terminal IN- of U3. The output terminal OUT of the non-inverting operational amplifier U3 is also connected to the inverting input terminal IN- of the differential amplifier U4 via a feedback resistor R11 in series. The VS+ terminal of the non-inverting operational amplifier U3 is connected to a positive 12V DC power supply, and the VS- terminal is connected to a negative 12V DC power supply.

[0044] The reference voltage provided by the reference voltage source circuit 13 is grounded through voltage divider resistors R12 and R14 in series. The common terminal of voltage divider resistors R12 and R14 is connected to the non-inverting input terminal IN+ of differential amplifier U4. The VS+ terminal of differential amplifier U4 is connected to a positive 12V DC power supply, and the VS- terminal is connected to a negative 12V DC power supply. The output terminal OUT of differential amplifier U4 is connected to the filter resistor R13 and filter capacitor C7 of the RC passive filter in series and grounded. The common connection point of filter resistor R13 and filter capacitor C7 is connected to the PNP transistor Q2 of the Class B push-pull power amplifier. At the same time, the output terminal OUT of differential amplifier U4 is connected to the inverting input terminal IN- of differential amplifier U4 after being connected in series with adjustable feedback resistor VR1 and feedback resistor R9.

[0045] PNP transistor Q2 and NPN transistor Q1 are connected in series between a DC power supply of +12V and -12V. The system also includes a first resistor R8, diode D1, diode D2, and resistor R17 connected in parallel with PNP transistor Q2 and NPN transistor Q1, and connected in series sequentially. These components provide the static operating point bias current for NPN transistor Q1 and PNP transistor Q2. The common terminal of resistor R8 and diode D1 is connected to the base of NPN transistor Q1. At the input, the common terminal of diode D2 and resistor R17 is connected to the base input terminal of transistor Q2. The collector terminal of transistor Q1 is connected to a DC power supply of positive 12V, and the collector terminal of transistor Q2 is connected to a DC power supply of negative 12V. After the emitter terminals of NPN transistor Q1 and NPN transistor Q2 are connected, a coupling capacitor C4 is connected in series to output a sinusoidal excitation signal Vsine with adjustable voltage amplitude and DC component. The sinusoidal excitation signal Vsine is connected to ground by a load resistor R15.

[0046] Among them, the electrolytic filter capacitor C6 has a capacitance of 1–22 uF; the ceramic filter capacitor C5 has a capacitance of 0.01–0.47 uF; the bias current balancing resistor R10 has a resistance of 5–20 kΩ; the voltage divider resistor R16 has a resistance of 5–20 kΩ; the voltage divider resistor R18 has a resistance of 5–20 kΩ; the adjustable voltage divider resistor VR2 has a resistance of 50–200 kΩ; the feedback resistor R11 has a resistance of 5–20 kΩ; and the voltage divider resistor R12 has a resistance of 5–20 kΩ. The resistance of the voltage regulator R14 is 10–50 kΩ; the resistance of the feedback resistor R9 is 5–20 kΩ; the resistance of the feedback resistor VR1 is 5–20 kΩ; the resistance of the filter resistor R13 is 50–200 kΩ; the capacitance of the filter capacitor C7 is 0.01–0.47 uF; the resistance of the resistor R8 is 5–20 kΩ; the resistance of the resistor R17 is 5–20 kΩ; the capacitance of the series coupling capacitor C4 is 50–220 uF; and the resistance of the resistor R15 is 1–5 kΩ.

[0047] like Figure 4 As shown, the integrating circuit 15 includes an integrating resistor R21. The sinusoidal excitation signal Vsine output by the DDS signal generator 11 is connected in series with the integrating resistor R21 and then connected to the inverting input terminal IN- of the integrating operational amplifier U5. A feedback resistor R19 and a capacitive plate probe 14 are connected in parallel between the output terminal OUT and the inverting input terminal IN- of the integrating operational amplifier U5. The non-inverting input terminal IN+ of the integrating operational amplifier U5 is connected in series with the resistor R25 and then grounded. The VS+ terminal of U5 is connected to a positive 12V DC power supply, and the VS- terminal of the integrating operational amplifier U5 is connected to a negative 12V DC power supply.

[0048] The output terminal OUT of the integrating operational amplifier U5 is connected to the non-inverting input terminal IN+ of the voltage follower U6. The output terminal OUT of the voltage follower U6 is directly connected to the inverting input terminal IN-. The VS+ terminal of the voltage follower U6 is connected to a positive 12V DC power supply, and the VS- terminal of U6 is connected to a negative 12V DC power supply.

[0049] The signal conditioning circuit 16 includes a differential amplifier U7. The output terminal OUT of the voltage follower U6 is connected in series with the input resistor R22 and then connected to the inverting input terminal IN- of the differential amplifier U7. The output terminal OUT of the differential amplifier U7 is connected in series with the adjustable feedback resistor VR3 and the feedback resistor R20 and then connected to the inverting input terminal IN- of the differential amplifier U7. The reference voltage output by the reference voltage source circuit 13 is grounded through voltage divider resistors R23 and R26 in series. The common terminal of voltage divider resistors R23 and R26 is connected to the non-inverting input terminal IN+ of the differential amplifier U7. The VS+ terminal of the differential amplifier U7 is connected to a positive 12V DC power supply, and the VS- terminal of the differential amplifier U7 is connected to a negative 12V DC power supply. The output terminal OUT of the differential amplifier U7 is connected in series with the filter resistor R24 ​​and the filter capacitor C8 of the RC passive filter and grounded. The common connection point of the filter resistor R24 ​​and the filter capacitor C8 is the output voltage amplitude signal Vadc of the signal conditioning circuit 16.

[0050] The values ​​of the integrating resistor R21, R25, R19, and input resistors are as follows: 5-20kΩ; 5-20kΩ; 50-200kΩ; 5-20kΩ; 5-20kΩ; 5-20kΩ; 5-20kΩ; 5-20kΩ; 5-20kΩ; 5-20kΩ; 50-200kΩ; 50-200kΩ; 50-200kΩ; 50-200kΩ; 50-200kΩ; 50-200kΩ; and 0.01-0.47uF.

[0051] The power supply device 3 includes a power management and voltage regulation circuit 33 and a 24V adapter and a 24V battery that are electrically connected to the power management and voltage regulation circuit 33, both of which are existing equipment.

[0052] The data processing device 2 includes a processor chip 21. The integration circuit 15 is connected to the analog-to-digital converter (ADC) of the processor chip 21 through a signal conditioning circuit 16. The voltage amplitude signal output by the signal conditioning circuit 16 is within the sampling voltage range of the analog-to-digital converter (ADC). The analog-to-digital converter (ADC) is used to quantize the voltage amplitude signal output by the signal conditioning circuit 16 to obtain the sampling calibration or measurement amplitude value.

[0053] The data processing device 2 also includes a cache SDRAM 27, an E2PROM memory 26, and an SD-Card 23 for storing data, and is electrically connected to the processor chip 21. In data storage, the processor chip 21 stores multiple sets of instantaneous voltage values ​​for sampling calibration or measurement in the cache SDRAM 27 of the processor chip 21, and calculates the calibration amplitude value from the multiple sets of instantaneous voltage values. At the same time, the calibration data corresponding to the number of sampled papers and the multiple sets of calibration amplitude values ​​obtained by the processor chip 21 through cyclic sampling calibration or measurement are stored sequentially in the E2PROM memory 26 of the processor chip 21 according to the calibration or measurement order, and the result of the number of papers to be measured by sampling measurement is stored in the SD-Card 23.

[0054] It also includes a TFT-LCD touch screen 25 electrically connected to the processor chip 21, which is used to provide users with an interactive interface to query historical measurement records.

[0055] like Figure 1 As shown, the processor chip 21 is also electrically connected to a buzzer 29, a mechanical button 28, a UART interface 22, and a JTAG interface 24; the buzzer 29 is used to indicate the end or start of sampling calibration or measurement, the mechanical button 28 is used to control the start of sampling calibration or measurement, the UART interface 22 is used to output running process information for debugging programs, and the JTAG interface 24 is used to download and trace debugging programs.

[0056] The UART interface 22 uses the integrated chip MAX3232CSE; the SD-Card 23 uses the FAT32 format and the FatFs R0.14 file system.

[0057] The integrating circuit 15 and the signal conditioning circuit 16 use the integrated chip OP37GP; the processor chip 21 uses the integrated chip MIMXRT1052DVL6B based on the ARM embedded system; the E2PROM memory 26 uses the integrated chip AT24C16N; the SDRAM cache 27 uses the integrated chip W9825G6KH-6; the TFT-LCD touch screen 25 is a 5-inch LCD screen based on MS90C385; there are two capacitive electrode probes 14, and the wires of the capacitive electrode probes 14 use coaxial shielded cables.

[0058] Example 2, as Figure 5 As shown, the present invention also includes a paper count measurement method based on a capacitive sensor paper count measurement system, comprising the following steps:

[0059] 1. Paper Calibration Steps: Place the calibration paper within the sensing area of ​​the capacitive electrode probe 14. Use the mechanical button to start the paper calibration. The DDS signal generator 11 sends a sinusoidal excitation signal Vsine with an amplitude of 1–230 mV and a frequency of 1–100,000 Hz to the integrating circuit 15. The integrating circuit 15 outputs a cosine signal with a constant frequency and a decreased amplitude of 1–100 mV from the sinusoidal excitation signal Vsine. The cosine signal then passes through the signal conditioning circuit 16 to output a voltage signal, which is then processed. The processor chip 21 quantizes the voltage signal into at least (10~20)×1024 sets of instantaneous voltage values ​​and stores the instantaneous voltage values ​​in the cache SDRAM 27. The processor chip 21 calculates a set of calibration amplitude values ​​and the corresponding number of sheets of paper for the at least (10~20)×1024 sets of instantaneous voltage values. The instantaneous voltage values ​​are collected in a loop to obtain multiple sets of calibration amplitude values ​​and the corresponding number of sheets of paper. The calibration data corresponding to the calibration amplitude values ​​and the number of sampled sheets of paper is stored in the E2PROM memory 26 to complete the calibration of the number of sheets of paper.

[0060] 2. Paper Count Measurement Steps: Place the paper to be measured within the sensing area of ​​the capacitive electrode probe 14. Use the mechanical button to start the paper measurement. The DDS signal generator 11 sends a sinusoidal excitation signal Vsine with an amplitude of 1-230mV and a frequency of 1-100000Hz to the integrating circuit 15. The integrating circuit 15 outputs a cosine signal with a constant frequency and a decrease in amplitude of 1-100mV from the sinusoidal excitation signal Vsine. The cosine signal then outputs a voltage signal through the signal conditioning circuit 16. The processor chip 21 quantizes the voltage signal into an instantaneous voltage value. The measured instantaneous voltage value is compared with multiple sets of amplitude values ​​to obtain the corresponding paper count, which is the final actual paper count. At the same time, the processor chip 21 stores the actual measured paper count in the SD-Card 23, completing the paper count measurement.

[0061] 3. The processor chip 21 displays the query information on the TFT-LCD touch screen 25 through the data stored in the SD-Card card 23 and E2PROM memory 26. The TFT-LCD touch screen 25 is used to enable users to query historical measurement records through the interactive interface.

[0062] In application, the present invention first performs calibration sampling of the number of sheets. The sample sheet is placed in the sensing area of ​​the capacitive electrode probe 14, and the instantaneous voltage value of the sheet is collected repeatedly to obtain the calibration amplitude value of the sample sheet. The number of sheets corresponding to the calibration amplitude value Vpp is then calculated, as shown in the table below:

[0063] Number of sheets Vpp(V) Number of sheets Vpp(V) Number of sheets Vpp(V) 1 3.1515 18 2.6392 35 2.2276 2 3.1405 19 2.6021 36 2.2158 3 3.1271 20 2.5618 37 2.2034 4 3.1114 21 2.5254 38 2.1914 5 3.0913 22 2.4914 39 2.1802 6 3.0682 23 2.4612 40 2.1678 7 3.0415 24 2.4331 41 2.1609 8 3.0123 25 2.3944 42 2.1505 9 2.9848 26 2.3762 43 2.1449 10 2.9525 27 2.3550 44 2.1389 11 2.9224 28 2.3399 45 2.1315 12 2.8893 29 2.3192 46 2.1273 13 2.8426 30 2.3004 47 2.1204 14 2.8034 31 2.2846 48 2.1152 15 2.7567 32 2.2679 49 2.1101 16 2.7155 33 2.2515 50 2.1048 17 2.6756 34 2.2393 51 2.1005

[0064] Then, the actual number of papers is measured. During the measurement, the paper to be tested is placed in the sensing area of ​​the capacitive electrode probe 14. The instantaneous voltage value of the paper is collected and the amplitude value is calculated. Then, according to the table above, the accurate number of papers can be obtained.

[0065] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A paper sheet number measuring system based on a capacitive sensor, characterized by, The paper sampling calibration or measurement device (1), the data processing device (2) for processing the sampling calibration or measurement data, and the power supply device (3) for supplying power to the paper sampling calibration or measurement device (1) and the data processing device (2); The paper sampling calibration or measurement device (1) includes a capacitive plate probe (14) for sampling calibration or measurement of the number of paper, and the capacitive plate probe (14) is an integral capacitor of an integral circuit (15); a DDS signal generating device (11) is electrically connected with the integral circuit (15) and a signal conditioning circuit (16) in sequence through a power amplification circuit (12), and the DDS signal generating device (11) is used for outputting a sine wave excitation signal to the integral circuit (15) and the signal conditioning circuit (16) after signal power amplification through the power amplification circuit (12); the integral circuit (15) and the signal conditioning circuit (16) are used for outputting the input sine wave excitation signal as a voltage amplitude signal; and a reference voltage source circuit (13) is electrically connected with the power amplification circuit (12) and the signal conditioning circuit (16), and the reference voltage source circuit (13) is used for providing a reference voltage for the power amplification circuit (12) and the signal conditioning circuit (16); The data processing device (2) includes a processor chip (21), the integral circuit (15) is connected with an analog-to-digital converter ADC of the processor chip (21) through the signal conditioning circuit (16), the voltage amplitude signal output by the signal conditioning circuit (16) is within the sampling voltage range of the analog-to-digital converter ADC, and the analog-to-digital converter ADC is used for quantifying the voltage amplitude signal output by the signal conditioning circuit (16) to obtain the amplitude value of the sampling calibration or measurement; The data processing device (2) further includes a cache SDRAM (27) for storing data, an E2PROM memory (26), and an SD-Card card (23), which are electrically connected with the processor chip (21), respectively; in data storage, the processor chip (21) is used for storing a plurality of voltage instantaneous values of the sampling calibration or measurement in the cache SDRAM (27) of the processor chip (21), and calculating the plurality of voltage instantaneous values to obtain calibration amplitude values; meanwhile, the calibration data corresponding to the plurality of calibration amplitude values and the sampling paper number obtained by the cyclic sampling calibration or measurement processing are stored in the E2PROM memory (26) of the processor chip (21) according to the calibration or measurement order, and the sampling measurement result of the paper number to be measured is stored in the SD-Card card (23); Further, a TFT-LCD touch display screen (25) is electrically connected with the processor chip (21), and the TFT-LCD touch display screen (25) is used for providing an interactive interface for the user to query the historical measurement record; The paper number measurement method of the paper number measurement system based on the capacitive sensor includes the following steps: 1) paper number calibration step: the calibration paper is placed in the sensing area of the capacitive plate probe (14), and the mechanical button is used to control the start of paper calibration. The DDS signal generating device (11) sends a sine wave excitation signal Vsine with an amplitude of 1-230 mV and a frequency of 1-100000 Hz to the integration circuit (15). The integration circuit (15) outputs the sine wave excitation signal Vsine as a cosine wave signal with a frequency unchanged and an amplitude decreased by 1-100 mV. The cosine wave signal is further output as a voltage signal through the signal conditioning circuit (16), and the voltage signal is quantized into at least (10-20)╳1024 groups of voltage instantaneous values by the processor chip (21), and the voltage instantaneous values are stored in the cache SDRAM (27). A group of calibration amplitude values and the paper number corresponding to the calibration amplitude values are calculated in the processor chip (21). The voltage instantaneous values are collected in a loop to obtain multiple groups of calibration amplitude values and corresponding paper numbers. The calibration amplitude values and the calibration data corresponding to the sampled paper numbers are stored in the E2PROM memory (26), and the calibration of the paper number is completed. 2) paper number measurement step: the paper to be measured is placed in the sensing area of the capacitive plate probe (14), and the mechanical button is used to control the start of paper measurement. The DDS signal generating device (11) sends a sine wave excitation signal Vsine with an amplitude of 1-230 mV and a frequency of 1-100000 Hz to the integration circuit (15). The integration circuit (15) outputs the sine wave excitation signal Vsine as a cosine wave signal with a frequency unchanged and an amplitude decreased by 1-100 mV. The cosine wave signal is further output as a voltage signal through the signal conditioning circuit (16), and the voltage signal is quantized into voltage instantaneous values by the processor chip (21), and the measured voltage instantaneous values are compared with the multiple amplitude values to obtain the corresponding paper number, which is the final actual measured paper number. At the same time, the processor chip (21) stores the actual measured paper number in the SD-Card card (23), and the measurement of the paper number is completed.

2. The paper sheet number measurement system based on a capacitive sensor according to claim 1, wherein The reference voltage source circuit (13) includes a 12V DC power supply, which is connected to the 2nd pin of the voltage stabilizing diode U1 through a current limiting resistor R1, the 3rd pin of the voltage stabilizing diode U1 is grounded, the 1st pin of the voltage stabilizing diode U1 is suspended, and the 2nd pin of the voltage stabilizing diode U1 outputs a reference voltage of 5V after filtering through a capacitor C1, and is connected to a voltage dividing resistor R2, a voltage dividing resistor R6 and a precision adjustable potentiometer R4 in series and grounded. The precision adjustable potentiometer R4 knob outputs a first reference voltage Vref1 from the middle tap, which is used to provide a reference voltage for the power amplification circuit (12). The precision adjustable potentiometer R4 middle tap connects filter capacitor C2, the second pin of voltage stabilizing diode U1 outputs reference voltage 5V, and is connected with voltage dividing resistor R3, voltage dividing resistor R7 and adjustable potentiometer R5 in series to ground; the knob of adjustable potentiometer R5 is connected with filter capacitor C3 from the middle tap, and outputs second reference voltage Vref2, which is used for providing reference voltage for the signal conditioning circuit (16); The 12V DC power supply is connected with current limiting resistor R1 with a resistance of 2-10kΩ; filter capacitor C1 has a capacitance of 50-220uF; voltage dividing resistor R2 has a resistance of 5-20kΩ; precision adjustable potentiometer R4 has a resistance of 50-200kΩ; voltage dividing resistor R6 has a resistance of 5-20kΩ; filter capacitor C2 has a capacitance of 1-22uF; third voltage dividing resistor R3 has a resistance of 5-20kΩ; adjustable potentiometer R5 has a resistance of 50-200kΩ; and seventh voltage dividing resistor R7 has a resistance of 5-20kΩ.

3. The paper sheet number measurement system based on a capacitive sensor according to claim 1, wherein The DDS signal generating device (11) comprises DDS signal generator U2 and non-inverting proportional operational amplifier U3; the working voltage end of the DDS signal generator U2 is connected to 5V DC power supply; the frame synchronization signal end FSY, serial clock input end SCK, serial data input end SDA, reset end RST, frequency selection end FS and phase selection end PA of the DDS signal generator U2 for inputting data are connected to the GPIO interface of the processor chip (21); the output end VOUT of the DDS signal generator U2 is connected to the non-inverting input end IN+ of the non-inverting proportional operational amplifier U3 after being filtered by electrolytic filter capacitor C6 and porcelain chip filter capacitor C5; the output end OUT of the non-inverting proportional operational amplifier U3 is connected to ground in series with adjustable voltage dividing resistor VR2, voltage dividing resistor R16 and voltage dividing resistor R18; the common end of the voltage dividing resistor R16 and the voltage dividing resistor R18 is connected to the inverting input end IN- of U3; the output end OUT of the non-inverting proportional operational amplifier U3 is also connected to the inverting input end IN- of the differential amplifier U4 in series with feedback resistor R11; the VS+ end of the non-inverting proportional operational amplifier U3 is connected to 12V DC power supply positive, and the VS- end is connected to 12V DC power supply negative; The reference voltage provided by the reference voltage source circuit (13) is connected to ground in series with voltage dividing resistor R12 and voltage dividing resistor R14; the common end of the voltage dividing resistor R12 and the voltage dividing resistor R14 is connected to the non-inverting input end IN+ of the differential amplifier U4; the VS+ end of the differential amplifier U4 is connected to 12V DC power supply positive, and the VS- end is connected to 12V DC power supply negative; the output end OUT of the differential amplifier U4 is connected to ground in series with filter resistor R13 and filter capacitor C7 of the RC passive filter; the common connection point of the filter resistor R13 and the filter capacitor C7 is connected to PNP type transistor Q2 of the class B push-pull power amplifier; meanwhile, the output end OUT of the differential amplifier U4 is connected to the inverting input end IN- of the differential amplifier U4 in series with adjustable feedback resistor VR1 and feedback resistor R9. The PNP type transistor Q2 and the NPN type transistor Q1 are connected in series between the positive 12V DC power supply and the negative 12V DC power supply, and further comprising the first resistor R8, the diode D1, the diode D2 and the resistor R17 connected in series and in parallel with the PNP type transistor Q2 and the NPN type transistor Q1, for providing the static working point bias current for the NPN type transistor Q1 and the PNP type transistor Q2; the common end of the resistor R8 and the diode D1 is connected to the base input end of the NPN transistor Q1, the common end of the diode D2 and the resistor R17 is connected to the base input end of the transistor Q2, the collector end of the transistor Q1 is connected to the positive 12V DC power supply, the collector end of the transistor Q2 is connected to the negative 12V DC power supply, the emitter end of the NPN transistor Q1 is connected to the emitter end of the NPN transistor Q2, and then the series coupling capacitor C4 outputs the voltage amplitude and DC component adjustable sine wave excitation signal Vsine, and the sine wave excitation signal Vsine is connected with the load resistor R15.

4. The paper sheet number measurement system based on a capacitive sensor according to claim 3, wherein The capacitor value of the electrolytic filter capacitor C6 is 1-22uF; the capacitor value of the porcelain chip filter capacitor C5 is 0.01-0.47uF; the resistance value of the bias current balance resistor R10 is 5-20kΩ; the resistance value of the voltage dividing resistor R16 is 5-20kΩ; the resistance value of the voltage dividing resistor R18 is 5-20kΩ; the resistance value of the adjustable voltage dividing resistor VR2 is 50-200kΩ; the resistance value of the feedback resistor R11 is 5-20kΩ; the resistance value of the voltage dividing resistor R12 is 5-20kΩ; the resistance value of the voltage dividing resistor R14 is 10-50kΩ; the resistance value of the feedback resistor R9 is 5-20kΩ; the resistance value of the feedback resistor VR1 is 5-20kΩ; the resistance value of the filter resistor R13 is 50-200kΩ; the capacitor value of the filter capacitor C7 is 0.01-0.47uF; the resistance value of the resistor R8 is 5-20kΩ; the resistance value of the resistor R17 is 5-20kΩ; the capacitor value of the series coupling capacitor C4 is 50-220uF; and the resistance value of the resistor R15 is 1-5kΩ.

5. The capacitance sensor-based paper sheet number measurement system according to claim 1, wherein the capacitance sensor is a mutual capacitance sensor. The integral circuit (15) comprises an integral resistor R21, and the sine wave excitation signal Vsine output by the DDS signal generating device (11) is connected to the inverting input end IN- of the integral operational amplifier U5 after being connected to the integral resistor R21, and the output end OUT and the inverting input end IN- of the integral operational amplifier U5 are provided with the feedback resistor R19 and the capacitive electrode plate probe (14) connected in parallel with each other, the non-inverting input end IN+ of the integral operational amplifier U5 is connected to the ground after being connected to the resistor R25, the VS+ end of U5 is connected to the positive 12V DC power supply, and the VS- end of the integral operational amplifier U5 is connected to the negative 12V DC power supply; The output end OUT of the integral operational amplifier U5 is connected to the non-inverting input end IN+ of the voltage follower U6, the output end OUT and the inverting input end IN- of the voltage follower U6 are directly connected, the VS+ end of the voltage follower U6 is connected to the positive 12V DC power supply, and the VS- end of U6 is connected to the negative 12V DC power supply; The signal conditioning circuit (16) includes a differential amplifier U7, the output end OUT of the voltage follower U6 is connected to the inverting input end IN- of the differential amplifier U7 through an input resistor R22, the output end OUT of the differential amplifier U7 is connected to the inverting input end IN- of the differential amplifier U7 through an adjustable feedback resistor VR3 and a feedback resistor R20, the reference voltage output by the reference voltage source circuit (13) is connected to the ground through a voltage dividing resistor R23 and a voltage dividing resistor R26 in series, the common end of the voltage dividing resistor R23 and the voltage dividing resistor R26 is connected to the non-inverting input end IN+ of the differential amplifier U7, the VS+ end of the differential amplifier U7 is connected to a positive 12V DC power supply, the VS- end of the differential amplifier U7 is connected to a negative 12V DC power supply, the output end OUT of the differential amplifier U7 is connected to the ground through a filter resistor R24 and a filter capacitor C8 in series, and the common connection point of the filter resistor R24 and the filter capacitor C8 is the output voltage amplitude signal Vadc of the signal conditioning circuit (16).

6. The paper sheet number measurement system based on a capacitive sensor according to Claim 5, wherein The resistance value of the integration resistor R21 is 5-20kΩ, the resistance value of the resistor R25 is 5-20kΩ, the resistance value of the feedback resistor R19 is 50-200kΩ, the resistance value of the input resistor R22 is 5-20kΩ, the resistance value of the voltage dividing resistor R23 is 5-20kΩ, the resistance value of the voltage dividing resistor R26 is 5-20kΩ, the resistance value of the feedback resistor R20 is 5-20kΩ, the resistance value of the adjustable feedback resistor VR3 is 50-200kΩ, the resistance value of the filter resistor R24 is 50-200kΩ, and the capacitance value of the filter capacitor C8 is 0.01-0.47uF.

7. The capacitance sensor-based paper sheet number measuring system according to claim 1, wherein The processor chip (21) is further electrically connected with a buzzer (29), a mechanical key (28), a UART interface (22) and a JTAG interface (24); the buzzer (29) is used for prompting the end or the start of sampling calibration or measurement, the mechanical key (28) is used for controlling the start of sampling calibration or measurement, the UART interface (22) is used for debugging program output running process information, and the JTAG interface (24) is used for downloading and tracking a debugging program; The UART interface (22) adopts an integrated chip MAX3232CSE; the SD-Card card (23) adopts a FAT32 format and a FatFs R0.14 file system.

8. The paper sheet number measurement system based on a capacitive sensor according to any one of claims 1 to 7, characterized by, The integration circuit (15) and the signal conditioning circuit (16) adopt an integrated chip OP37GP; the processor chip (21) adopts an integrated chip MIMXRT1052DVL6B based on an ARM embedded system; the E2PROM memory (26) adopts an integrated chip AT24C16N; the cache SDRAM (27) adopts an integrated chip W9825G6KH-6; the TFT-LCD touch display screen (25) is a 5-inch liquid crystal screen based on an MS90C385; and the capacitive plate probe (14) is two pieces, and the lead wire of the capacitive plate probe (14) adopts a coaxial shield cable.

9. The paper sheet number measurement system based on a capacitive sensor according to any one of claims 1 to 7, characterized by, Also included is a paper query step, the processor chip (21) through the SD-Card card (23) and E2PROM memory (26) in the storage data will query information displayed on the TFT-LCD touch display screen (25), TFT-LCD touch display screen (25) for realizing user interface query history measurement record.

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