A read calibration circuit for MRAM sense amplifier based on 1T1R array

Abstract

This invention relates to the field of magnetic tunnel junction technology, specifically to a read calibration circuit for an MRAM sensitive amplifier based on a 1T1R array. It includes: a cross-coupling circuit for sensing and amplifying the input voltage; a logic control circuit for generating various control signals; a Vclamp voltage generation circuit for generating Vclamp_R and Vclamp_L voltages; a 1T1R array for storing data; a reference array for generating the reference level required for reading; row and column decoding to ensure selection of the information bit to be read; a pre-amplification circuit for pre-amplifying small read voltages; and voltage calibration modules: the left voltage calibration module consists of transistors MN2, MN4, and MN7, with switches S0_0 and S0_1 controlling the conduction of transistor MN7, and switch S2_0 controlling the conduction of transistor MN4; the right voltage calibration module consists of MN3, MN5, and MN8, with switches S1_0 and S1_1 controlling the conduction of transistor MN8, and switch S2_1 controlling the conduction of transistor MN8, ensuring the correctness of the read results and further accelerating the readout speed.

Description

Technical Field

[0001] This invention relates to the field of magnetic tunnel junction technology, and more specifically to an MRAM sensitive amplifier read calibration circuit based on a 1T1R array. Background Technology

[0002] Magnetic tunnel junctions (MTJs) have advantages such as power-off retention, long lifespan, and natural radiation resistance, making them promising candidates for use in novel memory technologies.

[0003] A prior art sensitive amplifier comprises a cross-coupled circuit 200, a pre-amplification circuit 204, a logic control circuit, a row and column decoder, a reference array 202, and a 1T1R array 203. Its working principle is as follows: the row and column decoder selects one cell in the 1T1R array and a group of reference cells in the reference array; the logic control circuit generates L0 and R0 signals, selecting one of BL and REF to be turned on; initially, the SAE control signal is low, transistor MP2 is turned on, and transistor MN6 is turned off, pre-charging the sensitive amplifier; after pre-charging, the SAE signal becomes high, transistor MP2 is turned off, transistor MN6 is turned on, the cross-coupled circuit starts working, and the BL and REF branches simultaneously begin discharging, forming a voltage difference. The voltage signal is amplified through the cross-coupled structure to output the OUT voltage.

[0004] Figure 1 While the traditional sensitive amplifier can read out unit information, it has the following drawbacks: 1) During the reading process, due to manufacturing limitations, the reference voltage generated by the REF branch may deviate from the originally designed value, resulting in a smaller voltage difference amplified by the pre-amplifier circuit, ultimately leading to reading errors. 2) The voltage-type sensitive amplifier discharges slowly to form a voltage difference. Due to the instability of the REF and BL voltages, the discharge is slow or the voltages of BL and REF reverse during discharge, ultimately resulting in slow or incorrect readings. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a read calibration circuit for an MRAM sensitive amplifier based on a 1T1R array. This circuit calibrates the voltage of the read branch according to the voltage of the reference circuit, enabling the sensitive amplifier to correctly read the data of the cell, thereby reducing read errors, ensuring the accuracy of the read results, and further accelerating the read speed.

[0006] This invention is achieved through the following technical solution:

[0007] A read calibration circuit for an MRAM sensitive amplifier based on a 1T1R array, comprising:

[0008] Cross-coupled circuit: used to sense the magnitude of the input voltage and amplify it;

[0009] Logic control circuit: generates various control signals;

[0010] Vclamp voltage generation circuit: used to generate Vclamp_R and Vclamp_L voltages;

[0011] 1T1R array: Stores data information;

[0012] Reference array: generates the reference level required for reading;

[0013] Row and column decoding: to ensure that the information bits that need to be read are selected;

[0014] Pre-amplifier circuit: pre-amplifies small read voltages;

[0015] Voltage calibration module: The voltage calibration module on the left consists of transistors MN2, MN4 and MN7. Switches S0_0 and S0_1 control the conduction of transistor MN7, and switch S2_0 controls the conduction of transistor MN4. The voltage calibration module on the right consists of transistors MN3, MN5 and MN8. Switches S1_0 and S1_1 control the conduction of transistor MN8, and switch S2_1 controls the conduction of transistor MN8.

[0016] Preferably, when the 1T1R array is used for data reading, one of the switches is turned on, and the information state of the magnetic tunnel junction in the information bit connected to the selected bit line BL is known.

[0017] Preferably, when the reference array is used for data reading, one of the switches is turned on to select a reference array composed of cells.

[0018] Preferably, the logic control circuit generates S0_0, S0_1, S1_0, S1_1, S2_0, and S2_1, controlling the combination of switches to enable the voltage calibration module to generate different read modes, generating EN, SAE, L0, and R0 signals, controlling the pre-charge and operation of the sensitive amplifier, and selecting the read branch.

[0019] Preferably, the pre-amplifier circuit pre-amplifies small voltage differences and inputs them into transistors MN4 and MN5 or MN7 and MN8.

[0020] Preferably, the Vclamp voltage generating circuit generates Vclamp_R and Vclamp_L voltages, which will produce different voltages, causing the current flowing through MN2 and MN3 to be inconsistent.

[0021] Preferably, it also includes the following working state a:

[0022] The logic control circuit generates control signals such as S0_0, S0_1, S1_0, S1_1, S2_0, and S2_1, causing switches S0_0 and S0_1 to be in the open state, S1_0 and S1_1 to be in the open state, and S2_0 and S2_1 to be in the closed state, and transistors MN4 and MN5 to be in the working state; the Vclamp voltage generation circuit generates two voltages suitable for working state a, Vclamp_R and Vclamp_L; the row and column decoder selects a cell and a reference column in the 1T1R array and the reference array, and the L0 and R0 signals select the switch, choosing one of BL and REF; EN turns on the pre-amplification module, making... Its operation involves pre-amplifying the minute voltage difference between BL and REF, with the pre-amplification result input into IN- and IN+. When the SAE signal is low, transistor MP2 is turned on, transistor MN6 is turned off, and the VDD power supply pre-charges the two branches of the sensitive amplifier. When SAE is high, MP2 is turned off, MN6 is turned on, and the IN+ and IN- branches discharge. At this time, the working branches are MN2-MN4-MN6 on the left and MN3-MN5-MN6 on the right, generating a voltage difference that allows the cross-coupled structure to correctly amplify the minute voltage difference, outputting the correct value at OUT. The adaptive Vclamp voltage increases the current in the branches, improving the readout speed.

[0023] Preferably, the following working state b is also included:

[0024] When the REF and BL voltages are low, the voltage difference preamplified by the first-stage preamplifier circuit is relatively small. The logic control circuit generates control signals such as S0_0, S0_1, S1_0, S1_1, S2_0, and S2_1, causing switches S0_0 and S0_1 to be closed, S1_0 and S1_1 to be closed, and S2_0 and S2_1 to be open, and the input pairs of MN7 and MN8 to be in working state. The Vclamp voltage generation circuit generates two voltages, Vclamp_R and Vclamp_L, suitable for working state b. The generated two voltages are used by the row and column decoder to select a certain cell and a certain element in the 1T1R array and the reference array. In the reference column, the L0 and R0 signals select the switch, choosing one of BL and REF. When the SAE signal is low, transistor MP2 is turned on and transistor MN6 is turned off. The VDD power supply pre-charges the two branches of the sensitive amplifier. When SAE is high, MP2 is turned off and MN6 is turned on, and the IN- and IN+ branches discharge. At this time, the working branches are MN2-MN7-MN6 on the left and MN3-MN8-MN6 on the right, so that the cross-coupling structure can correctly amplify small voltage differences and output the correct value at OUT. When the pre-amplified voltage difference is small, the voltage calibration module correctly amplifies the voltage difference between the two sides, improving the readout accuracy of the sensitive amplifier.

[0025] Compared with existing technologies, the technical solution of the present invention has the following beneficial effects:

[0026] 1. When the pre-amplified voltage is too low, the voltage on IN+ and IN- can be calibrated through the voltage calibration module to reduce readout errors of the sensitive amplifier.

[0027] 2. Due to the symmetrical design on both sides, the impedance matching of BL and REF is further guaranteed, ensuring that the sensitive amplifier can correctly read the results.

[0028] 3. The readout of the sensitive amplifier can be accelerated by adjusting the voltage generated by the Vclamp generator and adjusting the current generated in the IN+ and IN- branches. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a conventional sensitive amplifier reading calibration circuit diagram for this invention.

[0031] Figure 2 This is a circuit diagram of the MRAM sensitive amplifier read calibration circuit based on a 1T1R array according to the present invention.

[0032] Figure 2 In the middle: 100-Cross-coupled circuit, 101-Voltage calibration module, 102-Reference array, 103-1T1R array, 104-Pre-amplifier circuit. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Example 1:

[0035] Please see Figure 2 As shown: This embodiment of the invention specifically discloses a technical solution for an MRAM sensitive amplifier read calibration circuit based on a 1T1R array 103, including:

[0036] Cross-coupled circuit 100: used to sense the magnitude of the input voltage and amplify it;

[0037] Logic control circuit: generates various control signals;

[0038] Vclamp voltage generation circuit: used to generate Vclamp_R and Vclamp_L voltages;

[0039] 1T1R array 103: Stores data information;

[0040] Reference array 102: generates the reference level required for reading;

[0041] Row and column decoding: to ensure that the information bits that need to be read are selected;

[0042] Preamplifier circuit 104: preamplifies small read voltages;

[0043] Voltage calibration module 101: The voltage calibration module 101 on the left is composed of transistors MN2, MN4 and MN7. Switches S0_0 and S0_1 control the conduction of transistor MN7, and switch S2_0 controls the conduction of transistor MN4. The voltage calibration module 101 on the right is composed of MN3, MN5 and MN8. Switches S1_0 and S1_1 control the conduction of transistor MN8, and switch S2_1 controls the conduction of transistor MN8.

[0044] Please continue reading. Figure 2 As shown, in a specific embodiment of the present invention, when the 1T1R array 103 is used for data reading, one of the switches is turned on, and the information state of the magnetic tunnel junction in the information bit connected to the selected bit line BL is known.

[0045] When the reference array 102 is used for data reading, one of the switches is turned on, selecting the reference array 102 composed of cells.

[0046] The logic control circuit generates S0_0, S0_1, S1_0, S1_1, S2_0, and S2_1, which control the combination of switches to enable the voltage calibration module 101 to generate different read modes, generate EN, SAE, L0, and R0 signals, control the pre-charge and operation of the sensitive amplifier, and select the read branch.

[0047] The pre-amplifier circuit 104 pre-amplifies small voltage differences and inputs them to transistors MN4 and MN5 or MN7 and MN8.

[0048] The Vclamp voltage generating circuit produces Vclamp_R and Vclamp_L voltages, which will generate different voltages, causing the current flowing through MN2 and MN3 to be inconsistent.

[0049] Please continue reading. Figure 2As shown, in a specific embodiment of the present invention, the following working state a is also included:

[0050] The logic control circuit generates control signals S0_0, S0_1, S1_0, S1_1, S2_0, and S2_1, causing switches S0_0 and S0_1 to be open, S1_0 and S1_1 to be closed, and S2_0 and S2_1 to be closed, thus activating transistors MN4 and MN5. The Vclamp voltage generation circuit generates two voltages, Vclamp_R and Vclamp_L, suitable for operating state a. The row and column decoder selects a cell and a reference column from the 1T1R array 103 and the reference array 102. The L0 and R0 signals select a switch, choosing one of BL and REF. EN activates the preamplifier module. To enable its operation, the small voltage difference between BL and REF is pre-amplified, and the pre-amplified result is input into IN- and IN+. When the SAE signal is low, transistor MP2 is turned on and transistor MN6 is turned off. The VDD power supply pre-charges the two branches of the sensitive amplifier. When SAE is high, MP2 is turned off and MN6 is turned on, and the IN+ and IN- branches discharge. At this time, the working branches are MN2-MN4-MN6 on the left and MN3-MN5-MN6 on the right, generating a voltage difference that allows the cross-coupled structure to correctly amplify the small voltage difference. The OUT output is the correct value, and the adaptive Vclamp voltage increases the current of the branch, improving the readout speed.

[0051] This also includes the following working state b:

[0052] When the REF and BL voltages are low, the voltage difference preamplified by the first-stage preamplifier circuit 104 is relatively small; the logic control circuit generates control signals such as S0_0, S0_1, S1_0, S1_1, S2_0, and S2_1, causing switches S0_0 and S0_1 to be closed, S1_0 and S1_1 to be closed, and S2_0 and S2_1 to be open, and the input pairs of transistors MN7 and MN8 to be in working state; the Vclamp voltage generation circuit generates two voltages suitable for working state b, Vclamp_R and Vclamp_L. The row and column decoder selects a certain cell and a certain reference array from the 1T1R array 103 and the reference array 102. A reference column, L0 and R0 signals select the switch, choosing one of BL and REF; when the SAE signal is low, transistor MP2 is turned on and transistor MN6 is turned off, and the VDD power supply pre-charges the two branches of the sensitive amplifier. When SAE is high, MP2 is turned off and MN6 is turned on, and the IN- and IN+ branches discharge. At this time, the working branches are MN2-MN7-MN6 on the left and MN3-MN8-MN6 on the right, so that the cross-coupling structure can correctly amplify small voltage differences and output the correct value. When the pre-amplified voltage difference is small, the voltage calibration module 101 correctly amplifies the voltage difference on both sides, improving the readout accuracy of the sensitive amplifier.

[0053] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A read calibration circuit for an MRAM sensitive amplifier based on a 1T1R array, characterized in that, include: A cross-coupled circuit, connected to the voltage calibration module, is used to sense the magnitude of the input voltage and amplify it. The logic control circuit is connected to the pre-amplifier circuit, the 1T1R array, and the reference array, respectively, and generates control signals corresponding to switches S0_0, S0_1, S1_0, S1_1, S2_0, and S2_1. These signals control the combination of switches to enable the voltage calibration module to generate different read modes, producing EN, SAE, L0, and R0 signals to control the pre-charge and operation of the sensitive amplifier and the selection of the read branch. The Vclamp voltage generation circuit, connected to the voltage calibration module, is used to generate Vclamp_R and Vclamp_L voltages. The 1T1R array is connected to the pre-amplifier circuit and the row and column decoding circuit respectively, and is used to store data information; The reference array is connected to the pre-amplifier circuit and the row and column decoding circuit, respectively, to generate the reference level required for reading. Row and column decoding circuits are used to ensure that the information bits to be read are selected; The pre-amplification circuit, connected to the voltage calibration module, pre-amplifies small read voltages. The voltage calibration module consists of transistors MN2, MN4, and MN7 on the left. Switches S0_0 and S0_1 control the conduction of transistor MN7, and switch S2_0 controls the conduction of transistor MN4. The voltage calibration module on the right consists of transistors MN3, MN5, and MN8. Switches S1_0 and S1_1 control the conduction of transistor MN8, and switch S2_1 controls the conduction of transistor MN5.

2. The MRAM sensitive amplifier read calibration circuit based on a 1T1R array according to claim 1, characterized in that, When the 1T1R array is used for data reading, one of the switches is turned on, and the information state of the magnetic tunnel junction in the information bit connected to the selected bit line BL is known.

3. The MRAM sensitive amplifier read calibration circuit based on a 1T1R array according to claim 2, characterized in that, When the reference array is used for data reading, one of the switches is turned on, selecting the reference array composed of cells.

4. The MRAM sensitive amplifier read calibration circuit based on a 1T1R array according to claim 1, characterized in that, The pre-amplification circuit pre-amplifies small voltage differences and inputs them into transistors MN4 and MN5 or transistors MN7 and MN8.

5. The MRAM sensitive amplifier read calibration circuit based on a 1T1R array according to claim 4, characterized in that, The Vclamp voltage generating circuit generates Vclamp_R and Vclamp_L voltages, which will produce different voltages, causing the current flowing through transistors MN2 and MN3 to be inconsistent.

6. A read calibration circuit for an MRAM sensitive amplifier based on a 1T1R array according to any one of claims 1-5, characterized in that, It also includes the following working state a: The logic control circuit generates control signals corresponding to switches S0_0, S0_1, S1_0, S1_1, S2_0, and S2_1, causing switches S0_0 and S0_1 to be in the open state, switches S1_0 and S1_1 to be in the open state, switches S2_0 and S2_1 to be in the closed state, and transistors MN4 and MN5 to be in the working state; the Vclamp voltage generation circuit generates two voltages, Vclamp_R and Vclamp_L, suitable for working state a. The row and column decoding circuit selects a cell in the 1T1R array and a reference column in the reference array. The L0 and R0 signals select a switch, choosing one of the bit line BL and the reference voltage REF. The EN signal turns on the pre-amplifier circuit, enabling it to operate and pre-amplify the small voltage difference between the bit line BL and the reference voltage REF. The pre-amplification result is input to the input terminals IN- and IN+ of the voltage calibration module. When the SAE signal is low, transistor MP2 is turned on and transistor MN6 is turned off, and the VDD power supply pre-charges the two branches of the sensitive amplifier. When the SAE signal is high, transistor MP2 is turned off and transistor MN6 is turned on, and the two branches of the voltage calibration module IN+ and IN- discharge. At this time, the working branches are MN2-MN4-MN6 on the left and MN3-MN5-MN6 on the right, generating a voltage difference that allows the cross-coupled circuit to correctly amplify the small voltage difference. The output terminal OUT outputs the correct value, and the adaptive Vclamp voltage increases the current of the branch, improving the readout speed.

7. A read calibration circuit for an MRAM sensitive amplifier based on a 1T1R array according to any one of claims 1-5, characterized in that, This also includes the following working state b: When the reference voltage REF and the bit line BL voltage are low, the voltage difference preamplified by the first-stage preamplifier circuit is relatively small. The logic control circuit generates control signals corresponding to switches S0_0, S0_1, S1_0, S1_1, S2_0, and S2_1, causing switches S0_0 and S0_1 to be closed, switches S1_0 and S1_1 to be closed, and switches S2_0 and S2_1 to be open, and the input pair of transistors MN7 and MN8 to be in the working state. The Vclamp voltage generation circuit generates two voltages suitable for working state b, Vclamp_R and Vclamp_L. The row and column decoding circuit selects a cell in the 1T1R array and the reference array. In the reference column, the L0 and R0 signals select the switch, choosing one of the bit line BL and the reference voltage REF. When the SAE signal is low, transistor MP2 is turned on and transistor MN6 is turned off, and the VDD power supply pre-charges the two branches of the sensitive amplifier. When the SAE signal is high, transistor MP2 is turned off and transistor MN6 is turned on, and the input terminals IN- and IN+ of the voltage calibration module discharge. At this time, the working branches are MN2-MN7-MN6 on the left and MN3-MN8-MN6 on the right, so that the cross-coupled circuit can correctly amplify small voltage differences and output the correct value at the output terminal OUT. When the pre-amplified voltage difference is small, the voltage calibration module correctly amplifies the voltage difference between the two sides, improving the readout accuracy of the sensitive amplifier.

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