Sense amplifier and circuit and method of reading data from a memory cell

Abstract

A sense amplifier and a sense amplifier circuit are provided. A first terminal of a first inverter is connected to a power supply node, and a second terminal of the first inverter is connected to a cell current source. A first terminal of a second inverter is connected to the power supply node, and a second terminal of the second inverter is connected to a reference current source. The first inverter is cross-coupled with the second inverter at a first node and a second node. A precharge circuit is connected to the first node and the second node. A first pull-up transistor and a second pull-up transistor are connected between a supply voltage node and the power supply node. A signal level detector circuit is connected to the second pull-up transistor. When a remaining voltage on one of the first node and the second node is lower than a reference voltage, the signal level detector circuit turns on the second pull-up transistor. Embodiments of the present invention also provide a method for reading data from a memory cell.

Description

Technical Field

[0001] Embodiments of the present invention relate to sense amplifiers and circuits, and methods for reading data from memory cells. Background Art

[0002] Modern electronic devices such as laptop computers include various memories for storing information. Generally, the memory includes a plurality of memory cells arranged in rows and columns. Each memory cell stores a bit of information through a floating gate transistor. A sense amplifier is used to verify the logic state of the memory cell by comparing the memory cell current with a reference current. More specifically, a voltage potential is applied to the control gate of the memory cell, and then in response to the voltage change at the control gate, current flows through the memory cell. The sense amplifier detects the current flowing through the memory cell and compares it with a predetermined reference current. When the memory cell current is greater than the reference current, the sense amplifier reports a logic high, which means the memory cell stores a logic high state. Conversely, when the memory cell current is less than the reference current, the sense amplifier reports a logic low, which reflects the logic low state of the memory cell. Summary of the Invention

[0003] According to one aspect of an embodiment of the present invention, there is provided a sense amplifier, comprising: a first inverter, wherein a first terminal of the first inverter is connected to a power supply node, and a second terminal of the first inverter is connected to a cell current source; a second inverter, wherein a first terminal of the second inverter is connected to the power supply node, wherein a second terminal of the second inverter is connected to a reference current source, and wherein the first inverter is cross-coupled with the second inverter at a first node and a second node; a precharge circuit connected to the first node and the second node; a first pull-up transistor connected between a supply voltage node and the power supply node; a second pull-up transistor connected between the supply voltage node and the power supply node; and a signal level detector circuit connected to the second pull-up transistor, wherein when a remaining voltage at one of the first node and the second node is lower than a reference voltage, the signal level detector circuit turns on the second pull-up transistor.

[0004] In another aspect according to an embodiment of the present invention, a sense amplifier circuit is provided, including: a first transistor, wherein the source of the first transistor is connected to a first node, and wherein the drain of the first transistor is connected to a cell current source; a second transistor, wherein the source of the second transistor is connected to a second node, and wherein the drain of the second transistor is connected to a reference current source; a third transistor, wherein the source of the third transistor is connected to a supply voltage node, and wherein the drain of the third transistor is connected to the first node; a fourth transistor, wherein the source of the fourth transistor is connected to the supply voltage node, and the drain of the fourth transistor is connected to the second node; a comparator, wherein a first input terminal of the comparator is connected to the first node, and wherein a second input terminal of the comparator is connected to the second node; and a signal level detector circuit, wherein an output terminal of the signal level detector circuit is connected to the comparator, and wherein the signal level detector circuit triggers the comparator to compare a remaining voltage of the first node and a remaining voltage of the second node in response to at least one of the following: the remaining voltage of the first node is less than a reference voltage, and the remaining voltage of the second node is less than the reference voltage.

[0005] In yet another aspect according to an embodiment of the present invention, a method for reading data from a memory cell is provided, the method including: receiving a read signal; in response to receiving the read signal, precharging a first node of the sense amplifier and a second node of the sense amplifier to a supply voltage, wherein precharging the first node and the second node includes connecting the first node and the second node to the supply voltage node, wherein the first node is connected to a cell current source, and wherein the second node is connected to a reference current source; after precharging, disconnecting the first node and the second node from the supply voltage node; determining that a remaining voltage on the first node or a remaining voltage on the second node drops below a reference voltage; in response to determining that the remaining voltage on the first node or the remaining voltage on the second node drops below the reference voltage, comparing the remaining voltage on the first node with the remaining voltage on the second node; and providing an output signal based on the comparison, the output signal indicating data stored in the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be emphasized that, according to standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figure 1 is an example diagram of a sense amplifier according to an example embodiment.

[0008] Figure 2 is a diagram showing Figure 1 the voltage levels of the sense amplifier according to some embodiments.

[0009] Figure 3 A block diagram of another sense amplifier in accordance with some embodiments is shown.

[0010] Figure 4 is a diagram showing in accordance with some embodiments Figure 3 of the voltage levels of the sense amplifier.

[0011] Figure 5 is an example diagram of another sense amplifier according to an example embodiment.

[0012] Figure 6 is a diagram showing in accordance with some embodiments Figure 5 of the voltage levels of the sense amplifier.

[0013] Figure 7 A block diagram of another sense amplifier in accordance with some embodiments is shown.

[0014] Figure 8 is a diagram showing in accordance with some embodiments Figure 7 of the voltage levels of the sense amplifier.

[0015] Figure 9 is a flowchart showing an example method of operating a latch in accordance with some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming the first component above or on the second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0018] The sense amplifier includes a voltage-mode sense amplifier and a current-mode sense amplifier. In the voltage-mode sense amplifier, both the memory cell current and the reference current are converted into corresponding voltages, which are then also fed into the input of the voltage-mode sense amplifier. The read operation of the memory cell is performed by comparing the two voltages at the input of the voltage-mode sense amplifier. The voltage-mode sense amplifier reports the logic state of the memory cell based on the comparison result.

[0019] In contrast, the current-mode sense amplifier directly compares the memory cell current with the reference current. In the read operation of the memory cell, an inverter can be used to monitor the difference between the memory cell current and the reference current. More specifically, the input of the inverter is coupled to the reference current and the memory cell current. In addition, the difference between the reference current and the memory cell current is used to charge the input of the inverter. According to the operation of the flash memory circuit, when the memory cell stores a logic low state, the reference current is greater than the memory cell current. As a result, the difference between the reference current and the memory cell current is positive, which means that the charging current will charge the input of the inverter to a level higher than the trigger point of the inverter, so that the current-mode sense amplifier reports a logic low state. In contrast, when the memory cell stores a logic high state, the reference current is less than the memory cell current. As a result, the difference between the reference current and the memory cell current is negative, which means that the discharging current will discharge the input of the inverter to a level lower than the trigger point of the inverter, so that the current-mode sense amplifier reports a logic high state.

[0020] Figure 1 FIG. is an example diagram of a sense amplifier 100 according to an example embodiment. In some embodiments, the sense amplifier reads data stored in memory cells of a cell array. In some examples, the memory cells can be static random access memory (SRAM) cells, resistive random access memory (RRAM) cells, magnetoresistive random access memory (MRAM) cells, flash random access memory (RAM) cells, etc. In some examples, Figure 1 the sense amplifier 100 of is a voltage-mode sense amplifier.

[0021] As Figure 1As shown, the sense amplifier 100 includes a cell current source Icell 102 and a reference current source (Iref) 104. The first terminal of the cell current source Icell 102 is grounded. Additionally, the first terminal of the reference current source Iref 104 is grounded. In an example, the cell current Icell generated by the cell current source Icell 102 has an amplitude corresponding to the programmed state of the memory cell being read. For example, if the data stored in the memory cell is binary "1", the cell current Icell may be a relatively high current. However, if the data stored in the memory cell is binary "0", the cell current Icell may be a relatively low current.

[0022] In some examples, the cell current source Icell 102 and the reference current source Iref 104 are mirrored into the sense amplifier 100. In some embodiments, the reference current source Iref 104 is another memory cell of the memory array, which includes a memory cell serving as the cell current source 102. In some embodiments, the memory cell serving as the reference current source Iref 104 is not used in the memory array to store data (e.g., a dummy memory cell).

[0023] The sense amplifier 100 further includes a first transistor N1 106 and a second transistor N2 108. The drain of the first transistor N1 106 is connected to the second terminal of the cell current source Icell 102, and the source of the first transistor N1 106 is connected to the Q node of the sense amplifier 100. The drain of the second transistor N2 108 is connected to the second terminal of the reference current source Iref 104, and the source of the second transistor N2 108 is connected to the QB node of the sense amplifier 100. The Q node and the QB node are complementary. In some examples, the Q node is also referred to as the first node in the present disclosure. Additionally, the QB node is also referred to as the second node in the present disclosure.

[0024] The gate of the first transistor N1 106 is connected to the gate of the second transistor N2 108. A clamping voltage Vclamp is applied to the respective gates of the first transistor N1 106 and the second transistor N2 108. The Vclamp is applied to set the maximum limit or upper limit of the gate voltages of the bit line (cell side) and the reference bit line (reference side). Thus, in some embodiments, the first transistor N1 106 and the second transistor N2 108 are also referred to as clamping transistors because they prevent high voltages from damaging the cell current source Icell 102 and the reference current source Iref 104.

[0025] In the example, the first transistor N1106 and the second transistor N2108 are n-channel metal-oxide-semiconductor (nMOS) transistors. However, after reading this disclosure, it will be apparent to those of ordinary skill in the art that each of the first transistor N1106 and the second transistor N2108 can use other types of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), p-channel metal-oxide-semiconductor (pMOS) transistors, or complementary metal-oxide-semiconductor (CMOS) transistors. Additionally, each of the first transistor N1106 and the second transistor N2108 is symmetric. That is, the source of each of the first transistor N1106 and the second transistor N2108 can be the drain, and the drain can be the source.

[0026] Continuing to refer to Figure 1 , the sense amplifier 100 further includes a third transistor P1110 and a fourth transistor P2112. The source of the third transistor P1110 is connected to the power supply node 118, and the drain of the third transistor P1110 is connected to the power supply Q node. The gate of the third transistor P1110 is connected to the QB node. The source of the fourth transistor P2112 is connected to the power supply node 118, and the drain of the fourth transistor P2112 is connected to the QB node. The gate of the fourth transistor P2112 is connected to the Q node.

[0027] In the example, each of the third transistor P1110 and the fourth transistor P2112 is a pMOS transistor. However, it will be apparent to those of ordinary skill in the art that after reading this disclosure, each of the third transistors P1 can use other types of transistors, such as MOSFETs, nMOS transistors, or CMOS transistors. Additionally, each of the third transistor P1110 and the fourth transistor P2112 is symmetric. That is, the source of each of the third transistor P1110 and the fourth transistor P2112 can be the drain, and the drain can be the source.

[0028] In some examples, the first transistor N1106 and the third transistor P1110 form a first inverter. Additionally, the second transistor N2108 and the fourth transistor P2112 form a second inverter. The first inverter and the second inverter are cross-coupled at the Q node and the QB node. In some examples, the first inverter and the second inverter can form a latch. Additionally, in some examples, the third transistor P1110 and the fourth transistor P2112 form an amplifier circuit.

[0029] As Figure 1As shown, the sense amplifier 100 further includes a fifth transistor P3114 and a sixth transistor P4116. The source of the fifth transistor P3114 is connected to the supply voltage node, and the drain of the fifth transistor P3114 is connected to the QB node. The source of the sixth transistor P4116 is connected to the supply voltage node, and the drain of the sixth transistor P4116 is connected to the Q node. The gates of the fifth transistor P3114 and the sixth transistor P4116 are both connected to the precharge voltage inverted node. In some embodiments, the supply voltage node provides a voltage VDD, such as 5 volts, 3.3 volts, 2.5 volts, 1.8 volts, 0.9 volts, etc. Additionally, the precharge voltage inverted node provides the inversion of the precharge voltage signal. In some examples, the fifth transistor P3114 and the sixth transistor P4116 are also referred to as a precharge circuit or a set / reset circuit.

[0030] In an example, each of the fifth transistor P3114 and the sixth transistor P4116 is a pMOS transistor. However, it will be apparent to those of ordinary skill in the art that after reading this disclosure, each of the fifth transistor P3114 and the sixth transistor P4116 can use other types of transistors, such as MOSFETs, nMOS transistors, or CMOS transistors. Additionally, each of the fifth transistor P3114 and the sixth transistor P4116 is symmetric. That is, the source of each of the fifth transistor P3114 and the sixth transistor P4116 can be the drain, and the drain can be the source.

[0031] Continuing to refer to Figure 1 the sense amplifier 100 further includes a seventh transistor P5120 and an eighth transistor P6122. The source of the seventh transistor P5120 is connected to the supply voltage node, the drain of the seventh transistor P5120 is connected to the power supply node 118. The gate of the seventh transistor P5120 is connected to the precharge voltage inverted node. The source of the eighth transistor P6122 is connected to the supply voltage node, and the drain of the eighth transistor P6122 is connected to the power supply node 118. The gate of the eighth transistor P6122 is connected to the output terminal of the signal level detector circuit 124. In some examples, the seventh transistor P5120 is also referred to as a first pull-up transistor, and the eighth transistor P6122 is also referred to as a second pull-up transistor.

[0032] The signal level detector circuit 124 determines whether one of the remaining voltage on the Q node and the remaining voltage on the QB node is lower than a reference voltage (e.g., 1 / 2(VDD)). When it is determined that one of the remaining voltage on the Q node and the remaining voltage on the QB node is lower than the reference voltage, the signal level detector circuit 124 provides an output signal at the output terminal, and this output signal is provided to the gate of the eighth transistor P6 and controls the switching of the eighth transistor P6122.

[0033] In some examples, the signal level detector circuit 124 includes an AND logic circuit 128. The AND logic circuit 128 determines the logical AND of the residual voltages on the Q node and the QB node and provides an output signal. For example, when one of the residual voltages on the Q node and the residual voltage on the QB node is lower than a reference voltage, the AND logic circuit 128 provides a logic low output. As Figure 1 shown, a first input terminal of the AND logic circuit 128 is connected to the Q node, and a second input terminal of the AND logic circuit 128 is connected to the QB node. In such an example, the output signal of the AND logic circuit 124 is also referred to as an AND signal. In some examples, the AND logic circuit 128 includes AND logic gates. However, other types of logic gates can be used to form the AND logic circuit 128.

[0034] In an example, each of the seventh transistor P5120 and the eighth transistor P6122 is a pMOS transistor. However, it will be apparent to those of ordinary skill in the art that after reading this disclosure, each of the seventh transistors P5 can use other types of transistors, such as MOSFETs, nMOS transistors, or CMOS transistors. Additionally, each of the seventh transistor P5120 and the eighth transistor P6122 is symmetric. That is, the source of each of the seventh transistor P5120 and the eighth transistor P6122 can be the drain, and the drain can be the source.

[0035] Figure 1 The sense amplifier 100 further includes a first comparator 126. A first input terminal of the first comparator 126 is connected to the Q node, and a second input terminal of the first comparator 126 is connected to the QB node. The first comparator 126 is triggered by a latch signal. When triggered, the first comparator 126 compares the residual voltage on the Q node with the residual voltage on the QB node and provides an output signal (referred to as the DOUT signal) at the output terminal based on the comparison. The DOUT signal indicates the data stored in the memory cell.

[0036] Figure 2FIG. 200 is a graph showing signals of the sense amplifier 100 during a read operation according to some embodiments. For example, the first curve 202 of the graph 200 shows a read signal (i.e., READ signal). The second curve 204 of the graph 200 shows a word line / word line reference signal (i.e., WL / WL_REF signal). The third curve 206 of the graph 200 shows a precharge signal (i.e., PRE signal). The fourth curve 208 of the graph 200 shows an output signal of the signal level detector circuit 124 (i.e., AND signal). The fifth curve 210 of the graph 200 shows a latch signal (i.e., LATCH signal). The sixth curve 212 of the graph 200 shows the remaining voltage signals of the Q node and the QB node (i.e., Q / QB signal). The seventh curve 214 of the graph 200 shows an output signal of the first comparator 126 (i.e., DOUT signal).

[0037] In the example, when the read signal rises from a logic low to a logic high, the read operation is triggered. For example, as shown in the first curve 202 of the graph 200, when the read operation is started, the READ signal changes from a logic low to a logic high. The logic low is also referred to as a first logic value or logic 0, and the logic high is also referred to as a second logic value or logic 1. Moreover, the read signal rising to the logic high starts the precharge phase of the sense amplifier 100.

[0038] After the read signal rises to the logic high, the word line signal or the word line reference signal also rises to the logic high. For example, and as shown in the second curve 204 of the graph 200, after the READ signal becomes logic high, the WL / WL_REF signal also changes from a logic low to a logic high. The first time interval between the READ signal rising to the logic high and the WL / WL_REF signal rising to the logic high is also referred to as the signal input period 216.

[0039] In addition, the precharge signal is logic high and drops to logic low at the end of the precharge phase. For example, as shown in the third curve 206 of the graph 200, after the second time interval from the WL / WL_REF signal rising to the logic high, the PRE signal drops to logic low. The second time interval from the WL / WL_REF signal rising to the logic high and the PRE signal dropping to logic low is also referred to as the precharge period 218. When the precharge signal is at logic high, the precharge inverted signal or the precharge inverted signal node is at logic low. This turns on each of the fifth transistor P3114, the sixth transistor P4116, and the seventh transistor P5120 of the sense amplifier 100.

[0040] The conduction of the seventh transistor P5120 causes the power supply node 118 to be connected to the supply voltage node (i.e., connected to VDD or logic high). Thus, the conduction of the seventh transistor P5120 causes each of the source of the third transistor P1110 and the source of the fourth transistor P2112 to be connected to the supply voltage node (i.e., connected to VDD or logic high). Additionally, the conduction of the fifth transistor P3114 causes the QB node to be connected to the supply voltage node (i.e., connected to VDD or logic high). Further, the conduction of the sixth transistor P4116 causes the Q node to be connected to the supply voltage node (i.e., connected to VDD or logic high). Thus, during the precharge phase, both the Q node and the QB node are at logic high.

[0041] At the end of the precharge phase, the precharge signal drops to logic low. For example, as shown by the third curve 206 of the graph 200, after the precharge cycle 218 in which the WL / WL_REF signal rises to logic high, the PRE signal drops to logic low. When the precharge signal drops to logic low, the precharge inverted signal or the precharge inverted signal node rises to logic high. This causes each of the fifth transistor P3114, the sixth transistor P4116, and the seventh transistor P5120 to turn off. The turn-off of the seventh transistor P5120 causes the power supply node 118 to be disconnected from the supply voltage node, which in turn causes the sources of the third transistor P1110 and the fourth transistor P2112 to be disconnected from the supply voltage node.

[0042] Additionally, the turn-off of the fifth transistor P3114 causes the QB node to be disconnected from the supply voltage node. Further, the turn-off of the sixth transistor P4116 causes the Q node to be disconnected from the supply voltage node. This causes the available voltage on both the Q node and the QB node to discharge. For example, as shown by the sixth curve 212 of the graph 200, since the PRE inverted signal rises to logic high and turns off the fifth transistor P3114, the sixth transistor P4116, and the seventh transistor P5120, the drop of the PRE signal to logic low triggers the gradual drop of the Q / QB signal.

[0043] The signal level detector circuit 124 (i.e., the AND logic circuit 128) determines whether the residual voltage on one of the Q node and the QB node is lower than the reference voltage. For example, the AND logic circuit 128 determines the logical AND of the residual voltages at the Q node and the QB node. When the residual voltage at the Q node or the QB node drops below the reference voltage (i.e., 1 / 2(VDD)), the output signal of the AND logic circuit 128 drops to logic low. For example, as shown by the fourth curve 208 of the graph 200, a drop in one of the Q / QB signals below the reference voltage (i.e., 1 / 2(VDD)) causes the AND signal (i.e., the output signal of the AND logic circuit 128) to drop to logic low. As the AND signal drops to logic low, and as shown by the fifth curve 210 of the graph 200, the LATCH signal rises to logic high. The third period between the PRE signal dropping to logic low and the LATCH signal rising to logic high is also referred to as the develop and latch period 220.

[0044] The LATCH signal rising to logic high triggers the first comparator 126 to compare the residual voltage on the Q node with the residual voltage on the QB node and provide the comparison result at the DOUT signal. The DOUT signal indicates whether the data on the memory cell is binary "1" or "0". For example, as shown by the seventh curve 214 of the graph 200, the LATCH signal rising to logic high causes the first comparator 126 to compare the residual voltage on the Q node with the residual voltage on the QB node and provide the output (i.e., the DOUT) signal. The fourth period between the latch signal rising to logic high and the first comparator 126 providing the DOUT signal is also referred to as the data output period 222.

[0045] Thus, according to the example embodiment, the conduction of one of the third transistor P1110 and the fourth transistor P2112 is delayed until the residual voltage on at least one of the Q node and the QB node drops below the reference voltage. The delay provides a greater difference or a greater gap in the residual voltages at the Q node and the QB node, which increases the accuracy of the first comparator 126. In addition, the greater gap increases the operating range of the sense amplifier 100 to higher temperatures.

[0046] Continue to refer to Figure 2The graph 200, as shown by the sixth curve 212, a drop in one of the Q / QB signals below the reference voltage (e.g., 1 / 2(VDD)) also causes one of the third transistor P1110 and the fourth transistor P2112 to turn on again, and subsequently the other of the third transistor P1110 and the fourth transistor P2112 to turn on. As shown by the sixth curve 212, this causes the remaining voltages on the Q node and the QB node to rise above the reference voltage, and as shown by the fourth curve 208, this in turn causes the AND signal to rise to logic high, and the eighth transistor P6122 to turn off. This brings about the end of the read cycle. Thus, as shown by the first curve 202 and the second curve 204, both the READ signal and the WL / WL_REF signal drop to logic low. Additionally, as shown by the third curve 206, the PRE signal rises to logic high. Also, the Q / QB signal rises to logic high.

[0047] In some examples, the signal level detector circuit 124 can include an implementation different from the AND logic circuit 128. For example, Figure 3 FIG. shows a block diagram of another sense amplifier 300 having another implementation of the signal level detector circuit 124 according to some embodiments. Figure 3 The signal level detector circuit 124 of the sense amplifier 300 includes a second comparator 302. The second comparator 302 compares the remaining voltage on the QB node with the reference voltage of the reference voltage node and provides an output signal (i.e., the DET signal) based on the comparison. After reading this disclosure, it will be apparent to those of ordinary skill in the art that the second comparator 302 can be implemented to compare the remaining voltage on the Q node with the reference voltage and provide the DET signal.

[0048] Figure 3 The sense amplifier 300 also includes a unit current source Icell 102, a reference current source Iref 104, a first transistor N1206, a second transistor N2108, a third transistor P1110, a fourth transistor P2112, a fifth transistor P3114, a sixth transistor P4116, a seventh transistor P5120, an eighth transistor P6122, and a first comparator 126. In the example, each of the first transistor N1106 and the second transistor N2108 is an nMOS transistor, while each of the third transistor P1110, the fourth transistor P2112, the fifth transistor P3114, the sixth transistor P4116, the seventh transistor P5120, and the eighth transistor P6122 is a pMOS transistor. However, other types of transistors are also within the scope of this disclosure.

[0049] As Figure 3As shown, the first terminal of the cell current source Icell 102 is grounded. Additionally, the first terminal of the reference current source Iref 104 is grounded. The drain of the first transistor N1106 is connected to the second terminal of the cell current source Icell 102, and the source of the first transistor N1106 is connected to the Q node of the sense amplifier 300. The drain of the second transistor N2108 is connected to the second terminal of the reference current source Iref 104, and the source of the second transistor N2108 is connected to the QB node of the sense amplifier 300. The gate of the first transistor N1106 is connected to the gate of the second transistor N2108. The clamp voltage Vclamp is applied to the gates of the first transistor N1106 and the second transistor N2108 respectively.

[0050] The source of the third transistor P1110 is connected to the power supply node 118, and the drain of the third transistor P1110 is connected to the Q node. The gate of the third transistor P1110 is connected to the QB node. The source of the fourth transistor P2112 is connected to the power supply node 118, and the drain of the fourth transistor P2112 is connected to the QB node. The gate of the fourth transistor P2112 is connected to the Q node. The source of the fifth transistor P3114 is connected to the supply voltage node, and the drain of the fifth transistor P3114 is connected to the QB node. The source of the sixth transistor P4116 is connected to the supply voltage node, and the drain of the sixth transistor P4116 is connected to the Q node. The gates of the fifth transistor P3114 and the sixth transistor P4116 are both connected to the precharge voltage inverted node.

[0051] The source of the seventh transistor P5120 is connected to the supply voltage node, and the drain of the seventh transistor P5120 is connected to the power supply node 118. The gate of the seventh transistor P5120 is connected to the precharge voltage inverted node. The source of the eighth transistor P6122 is connected to the supply voltage node, the drain of the eighth transistor P6122 is connected to the power supply node 118. The gate of the eighth transistor P6122 is connected to the output terminal of the second comparator 302. The first input terminal of the second comparator 302 is connected to the QB node, and the second input terminal of the second comparator 302 is connected to the reference voltage node.

[0052] The first input terminal of the first comparator 126 is connected to the Q node, and the second input terminal of the first comparator 126 is connected to the QB node. The first comparator 126 is triggered by a latch signal. When triggered, the first comparator 126 compares the remaining voltage on the Q node with the remaining voltage on the QB node and provides a DOUT signal at the output terminal based on the comparison. The DOUT signal indicates the data stored in the memory cell.

[0053] Figure 4is a graph 400 showing signals of the sense amplifier 300 during a read operation according to some embodiments. The first curve 202 of the graph 400 shows the READ signal, the second curve 204 of the graph 400 shows the WL / WL_REF signal, the third curve 206 of the graph 400 shows the PRE signal, the fourth curve 402 of the graph 400 shows the DET signal, the fifth curve 210 of the graph 400 shows the LATCH signal, the sixth curve 212 of the graph 400 shows the Q / QB signal, and the seventh curve 214 of the graph 400 shows the DOUT signal. Figure 3 In the example, when the read signal rises from logic low to logic high, the read operation is triggered. For example, as shown by the first curve 202 of the graph 400, when the read operation is started, the READ signal changes from logic low to logic high. After the read signal rises to logic high, the word line signal or the word line reference signal also rises to logic high. For example, as shown by the second curve 204 of the graph 400, after the READ signal becomes logic high, the WL / WL_REF signal also changes from logic low to logic high. The first time interval between the rise of the READ signal to logic high and the rise of the WL / WL_REF signal to logic high is also referred to as the signal input period 216.

[0054] In addition, the precharge signal is at logic high and drops to logic low at the end of the precharge phase of the read operation. For example, as shown by the third curve 206, after the second time interval in which the WL / WL_REF signal rises to logic high, the PRE signal drops to logic low. The second time interval from the rise of the WL / WL_REF signal to logic high and the drop of the PRE signal to logic low is also referred to as the precharge period 218. When the precharge signal is at logic high, the precharge inverted signal or the precharge inverted signal node is at logic low. This causes each of the fifth transistor P3114, the sixth transistor P4116, and the seventh transistor P5120 of the sense amplifier 300 to conduct.

[0055] The conduction of the seventh transistor P5120 causes the power supply node 118 to be connected to the supply voltage node (i.e., connected to VDD or logic high). Thus, the conduction of the seventh transistor P5120 causes the source of the third transistor P1110 and the source of the fourth transistor P2112 to be each connected to the supply voltage node (i.e., connected to VDD or logic high). In addition, the conduction of the fifth transistor P3114 causes the QB node to be connected to the supply voltage node (i.e., connected to VDD or logic high). Further, the conduction of the sixth transistor P4116 causes the Q node to be connected to the supply voltage node (i.e., connected to VDD or logic high). Thus, during the precharge phase, both the Q node and the QB node are at logic high.

[0056] ​

[0057] In the example embodiment, and as shown by the third curve 206 of graph 400, at the end of the precharge phase, the PRE signal (i.e., the precharge signal) drops to logic low. When the precharge signal drops to logic low, the precharge inverted signal or the precharge inverted signal node rises to logic high. This causes each of the fifth transistor P3114, the sixth transistor P4116, and the seventh transistor P5120 to turn off. The turning off of the seventh transistor P5120 causes the power node 118 to be disconnected from the supply voltage node, which in turn causes the sources of the third transistor P1110 and the fourth transistor P2112 to be disconnected from the supply voltage node. Additionally, the turning off of the fifth transistor P3114 causes the QB node to be disconnected from the supply voltage node. Further, the turning off of the sixth transistor P4116 causes the Q node to be disconnected from the supply voltage node. This causes the available voltages on the Q node and the QB node to discharge. As shown by the sixth curve 212 of graph 400, since the PRE inverted goes high and turns off the fifth transistor P3114, the sixth transistor P4116, and the seventh transistor P5120, the drop of the PRE signal to logic low triggers the gradual drop of the Q / QB signals.

[0058] The signal level detector circuit 124 (i.e., the second comparator 302) determines whether the remaining voltage on the QB node is lower than the reference voltage (i.e., Vref). For example, the second comparator 302 compares the remaining voltage on the QB node with the reference voltage (i.e., Vref). When the remaining voltage of the QB node drops below the reference voltage (i.e., 1 / 2(VDD)), the output signal of the second comparator 302 drops to logic low. For example, as shown by the fourth curve 402 of graph 400, when the QB signal drops below the reference voltage (i.e., 1 / 2(VDD)), the DET signal (i.e., the output signal of the second comparator 302) drops to logic low. Additionally, as shown by the fifth curve 210 of graph 400, after the DET signal drops to logic low, the LATCH signal rises to logic high. The third period between the PRE signal dropping to logic low and the LATCH signal rising to logic high is also referred to as the development and latch period 220.

[0059] Additionally, the output signal of the second comparator 302 falling to logic low causes the latch signal to rise to logic high, which triggers the first comparator 126 to compare the remaining voltage on the Q node with the remaining voltage on the QB node and provide the comparison result at the DOUT signal. The DOUT signal indicates whether the data on the memory cell is binary "1" or "0". For example, as shown by the seventh curve 214 of the graph 400, the LATCH signal rising to logic high causes the first comparator 126 to compare the remaining voltage on the Q node with the remaining voltage on the QB node and provide the output (i.e., DOUT) signal. The fourth period between the LATCH signal rising to logic high and the first comparator 126 providing the DOUT signal is also referred to as the data output period 222.

[0060] Thus, according to the example embodiment, the second comparator 302 delays turning on one of the third transistor P1110 and the fourth transistor P2112 until the remaining voltage on at least one of the Q node and the QB node drops below the reference voltage. The delay provides a greater difference or a greater gap in the remaining voltages at the Q node and the QB node, which increases the accuracy of the first comparator 126. Additionally, the greater gap increases the operating range of the sense amplifier 100 to higher temperatures.

[0061] Continuing to refer to Figure 4 graph 400, as shown by the sixth curve 212, dropping the QB signal below the reference voltage (i.e., 1 / 2(VDD)) also causes one of the third transistor P1110 and the fourth transistor P2112 to turn on, and subsequently causes the other of the third transistor P1110 and the fourth transistor P2112 to turn on. As shown by the sixth curve 212 of graph 400, this causes the remaining voltages on both the Q node and the QB node to rise above the reference voltage, and as shown by the fourth curve 208, this in turn causes the DET signal to rise to logic high and the eighth transistor P6122 to turn off. This brings an end to the read cycle. Thus, as shown by the first curve 202 and the second curve 204, both the READ signal and the WL / WL_REF signal drop to logic low. Additionally, as shown by the third curve 206, the PRE signal rises to logic high. Also, the Q / QB signals rise to logic high level.

[0062] Figure 5 is an example diagram of another sense amplifier 500 according to the example embodiment. In some embodiments, the sense amplifier 500 reads data stored on the memory cells of the cell array. In some examples, the memory cells can be SRAM cells, RRAM cells, MRAM cells, flash RAM cells, etc. In some examples, Figure 5 the sense amplifier 100 of

[0063] AsFigure 5 As shown, the sense amplifier 500 includes a cell current source Icell 502 and a reference current source (Iref) 504. The first terminal of the cell current source Icell 502 is grounded. Similarly, the first terminal of the reference current source Iref 504 is grounded. In an example, the cell current Icell generated by the cell current source Icell 502 has an amplitude corresponding to the programmed state of the memory cell being read. For example, if the data stored in the memory cell is binary "1", the cell current Icell may be a relatively high current. However, if the data stored in the memory cell is binary "0", the cell current Icell may be a relatively low current. In some embodiments, the reference current source Iref 504 is another memory cell of the memory array, which includes a memory cell serving as the cell current source 502. In some embodiments, the memory cell serving as the reference current source Iref 504 is not used in the memory array to store data (e.g., a dummy memory cell).

[0064] Additionally, the sense amplifier 500 includes a first transistor N3506 and a second transistor N4508. The drain of the first transistor N3506 is connected to the second terminal of Icell 502, and the source of the first transistor N3506 is connected to the Q node of the sense amplifier 500. The drain of the second transistor N4508 is connected to the second terminal of Iref 504, and the source of the second transistor N4508 is connected to the QB node of the sense amplifier 500. In an example, the Q node and the QB node are complementary.

[0065] The gate of the first transistor N3506 is connected to the gate of the second transistor N4508. A clamping voltage Vclamp is coupled to the corresponding gates of the first transistor N3506 and the second transistor N4508 to set the ceiling or upper limit of the gate voltages of the bit line (cell side) and the reference bit line (reference side). Thus, in some embodiments, the first transistor N3506 and the second transistor N4508 are also referred to as clamping transistors because they prevent high voltages from damaging the cell current source Icell 502 and the reference current source Iref 504.

[0066] In the example, each of the first transistor N3506 and the second transistor N4508 is an nMOS transistor. However, it will be apparent to those of ordinary skill in the art that after reading this disclosure, each of the first transistor N3506 and the second transistor N4508 can be other types of transistors, such as MOSFETs, pMOS transistors, or CMOS transistors. The first transistor N3506 and the second transistor N4508 are symmetric. That is, the source of each of the first transistor N3506 and the second transistor N4508 can be the drain, and the drain can be the source.

[0067] Continuing to refer to Figure 5 , the sense amplifier 500 further includes a third transistor P1510 and a fourth transistor P2512. The source of the third transistor P1510 is connected to the supply voltage node, and the drain of the third transistor P1510 is connected to the Q node. The source of the fourth transistor P2512 is connected to the supply voltage node, and the drain of the fourth transistor P2512 is connected to the QB node. The gate of the fourth transistor P2512 and the gate of the third transistor 510 are connected to the precharge inverted signal node. The QB node is complementary to the Q node. In some examples, in this disclosure, the Q node is also referred to as the first node. Similarly, in this disclosure, the QB node is also referred to as the second node.

[0068] In the example, each of the third transistor P1510 and the fourth transistor P2512 is a pMOS transistor. However, it will be apparent to those of ordinary skill in the art that after reading this disclosure, each of the third transistor P1510 and the fourth transistor P2512 can use other types of transistors, such as MOSFETs, nMOS transistors, or CMOS transistors. Additionally, each of the third transistor P1510 and the fourth transistor P2512 is symmetric. That is, the source of each of the third transistor P1510 and the fourth transistor P2512 can be the drain, and the drain can be the source. In some examples, the third transistor P1510 and the fourth transistor P2512 form the precharge circuit of the sense amplifier 500. In other examples, the third transistor P1510 and the fourth transistor P2512 form the amplifier circuit of the sense amplifier 500.

[0069] Figure 5The sense amplifier 500 further includes a first comparator 514. A first input terminal of the first comparator 514 is connected to the Q node, and a second input terminal of the first comparator 514 is connected to the QB node. The first comparator 514 is triggered by a latch signal. When triggered, the first comparator 514 compares the residual voltage on the Q node with the residual voltage on the QB node and provides an output (i.e., the DOUT signal) at the output terminal based on the comparison. The DOUT signal indicates whether the data on the memory cell is binary "1" or "0".

[0070] As Figure 5 shown, the latch signal is provided by a signal level detector circuit 516. The signal level detector circuit 516 determines whether one of the residual voltage on the Q node and the residual voltage on the QB node drops below a reference voltage. When it is determined that the residual voltage on the Q node or the residual voltage on the QB node drops below the reference voltage, the signal level detector circuit 516 provides the latch signal. The latch signal triggers the first comparator 514 to compare the residual voltage on the Q node with the residual voltage on the QB node.

[0071] In some examples, the signal level detector circuit 516 includes an AND logic circuit 518. A first input terminal of the AND logic circuit 518 is connected to the Q node, and a second input terminal of the AND logic circuit 518 is connected to the QB node. An output terminal of the AND logic circuit 518 is connected to the first comparator 514. The AND logic circuit 518 determines the logical AND of the residual voltages on the Q node and the QB node, and provides a logic low output when one of the residual voltage on the Q node and the residual voltage on the QB node drops below the reference voltage. The output signal of the AND logic circuit 518 is also referred to as the AND signal. In some examples, the AND logic circuit 518 includes AND logic gates. However, other types of logic gates can be used to form the AND logic circuit 518.

[0072] Figure 6 is a graph 600 showing the signals of the sense amplifier 500 during a read operation according to some embodiments. For example, Figure 6The first curve 602 of the graph 600 shows the read signal (i.e., the READ signal). The second curve 604 of the graph 600 shows the word line / word line reference signal (i.e., the WL / WL_REF signal). The third curve 606 of the graph 600 shows the precharge signal (i.e., the PRE signal). The fourth curve 608 of the graph 600 shows the output signal of the signal level detector circuit 516 (i.e., the AND signal). The fifth curve 610 of the graph 600 shows the remaining voltages on the Q node and the QB node (i.e., the Q / QB signal). The sixth curve 612 of the graph 600 shows the output signal of the comparator 514 (i.e., the DOUT signal).

[0073] In the example, when the read signal rises from logic low to logic high, a read operation is triggered. As Figure 6 shown by the first curve 602 of the graph 600, when the read operation is initiated, the READ signal changes from logic low to logic high. The rising of the read signal to logic high starts the precharge phase of the sense amplifier 500. After the read signal rises to logic high, the word line signal or the word line reference signal also rises to logic high. For example, as shown by the second curve 604 of the graph 600, after the READ signal becomes logic high, the WL / WL_REF signal also changes from logic low to logic high. The first time interval between the rising of the read signal to logic high and the rising of the WL / WL_REF signal to logic high is also referred to as the signal input period 614.

[0074] In addition, and as shown by the fifth curve 610 of the graph 600, during the signal input period, the precharge signal is at logic high. When the precharge signal is at logic high, the precharge inverted signal or the precharge inverted node is at logic low. This causes each of the third transistor P1510 and the fourth transistor P2512 of the sense amplifier 500 to conduct.

[0075] The conduction of the third transistor P1510 causes the Q node to be connected to the supply voltage node (i.e., connected to VDD or logic high). In addition, the conduction of the fourth transistor P2512 causes the QB node to be connected to the supply voltage node (i.e., connected to VDD or logic high). Therefore, during the precharge phase, both the Q node and the QB node are at logic high.

[0076] At the end of the precharge phase, the precharge signal drops to logic low. For example, as shown by the third curve 606 of the graph 600, after the second time interval from the rising of the WL / WL_REF signal to logic high, the PRE signal drops to logic low. The second time interval from the rising of the WL / WL_REF signal to logic high and the dropping of the PRE signal to logic low is also referred to as the precharge period 616.

[0077] When the precharge signal is logic low, the precharge inverted signal or the precharge inverted node rises to logic high. This causes each of the third transistor P1510 and the fourth transistor P2512 to turn off. Additionally, the turn-off of the third transistor P1510 disconnects the Q node from the supply voltage node. Furthermore, the turn-off of the fourth transistor P2512 disconnects the QB node from the supply voltage node. This causes the available voltages on the Q node and the QB node to discharge. For example, as shown by the fifth curve 610 of the graph 600 in Figure 6 when the PRE signal drops to logic low, it triggers the gradual drop of the Q / QB signal.

[0078] The signal level detector circuit 516 (i.e., the AND logic circuit 518) determines whether the remaining voltage on one of the Q node and the QB node is lower than the reference voltage. When the remaining voltage at the Q node or the QB node drops below the reference voltage (e.g., 1 / 2(VDD)), the output signal (i.e., the latch signal) of the AND logic circuit 518 drops to logic low. For example, as shown by the fourth curve 608 of the graph 600, one of the Q / QB signals dropping below the reference voltage (i.e., 1 / 2(VDD)) causes the AND signal to drop to logic low. As shown by the sixth curve 612 of the graph 600, the AND signal dropping to logic low triggers the first comparator 514 to compare the remaining voltage on the Q node with the remaining voltage on the QB node and provide the comparison result at the DOUT signal. For example, as shown by the sixth curve 612 of the graph 600, the DOUT signal indicates whether the data on the memory cell is binary "1" or "0".

[0079] The third period between the PRE signal dropping to logic low and the AND signal rising to logic high is also referred to as the development and latch period 618. The rising of the AND signal to logic high also triggers the read cycle. Thus, as shown by the first curve 602 and the second curve 604 of the graph 600, both the READ signal and the WL / WL_REF signal drop to logic low. Additionally, as shown by the third curve 606, the PRE signal rises to logic high. Furthermore, the Q / QB signal also rises to logic high.

[0080] Therefore, according to the exemplary embodiment, the comparison of the remaining voltages on the Q node and the QB node is delayed until the remaining voltage on the Q node or the QB node drops below the reference voltage (e.g., 1 / 2(VDD)). The delay provides a greater difference or a greater gap in the remaining voltages at the Q node and the QB node, which increases the accuracy of the first comparator 514 and the sense amplifier 500. Additionally, the greater gap increases the operating range of the sense amplifier 500 to higher temperatures.

[0081] Figure 7FIG. 700 shows a block diagram of a sense amplifier 700 according to another embodiment with a signal level detector circuit 516 in accordance with some embodiments. Figure 7 The signal level detector circuit 516 of the sense amplifier 700 includes a second comparator 702. The second comparator 702 compares the residual voltage on the QB node with the reference voltage of the reference voltage node and provides an output signal (i.e., DET signal) based on the comparison. When the residual voltage on the QB node is higher than the reference voltage, the DET signal is logic high, and when the residual voltage on the QB node drops below the reference voltage, the DET signal drops to logic low. It will be apparent to those of ordinary skill in the art that the second comparator 702 may compare the residual voltage on the Q node with the reference voltage and provide the DET signal. In some examples, the second comparator 702 is an amplifier, e.g., an operational amplifier.

[0082] Figure 7 The sense amplifier 700 further includes a cell current source Icell 502, a reference current source Iref 504, a first transistor N3506, a second transistor N4508, a third transistor P1510, a fourth transistor P2512, and a first comparator 514. Each of the first transistor N3506 and the second transistor N4508 is an nMOS transistor, while each of the third transistor P1510 and the fourth transistor P2512 is a pMOS transistor. However, other types of transistors are also within the scope of the present disclosure.

[0083] The first terminal of the cell current source Icell 502 is grounded. Similarly, the first terminal of the reference current source Iref 504 is grounded. The drain of the first transistor N3506 is connected to the second terminal of Icell 502, and the source of the first transistor N3506 is connected to the Q node. The drain of the second transistor N4508 is connected to the second terminal of Iref 504, and the source of the second transistor N4508 is connected to the QB node. The gate of the first transistor N3506 is connected to the gate of the second transistor N4508. The clamp voltage Vclamp is coupled to the corresponding gates of the first transistor N3506 and the second transistor N4508 to set the maximum or upper limit of the gate voltages of the bit line (cell side) and the reference bit line (reference side).

[0084] The source of the third transistor P1510 is connected to the supply voltage node, and the drain of the third transistor P1510 is connected to the Q node. The source of the fourth transistor P2512 is connected to the supply voltage node, and the drain of the fourth transistor P2512 is connected to the QB node. The gate of the fourth transistor P2512 and the gate of the third transistor 510 are connected to the precharge inverted signal node.

[0085] The first input terminal of the first comparator 514 is connected to the Q node, and the second input terminal of the first comparator 514 is connected to the QB node. The first comparator 514 is triggered by a latch signal. When triggered, the first comparator 514 compares the residual voltage on the Q node with the residual voltage on the QB node and provides an output at the output terminal based on the comparison (i.e., the DOUT signal). The DOUT signal indicates whether the data on the memory cell is binary "1" or "0".

[0086] As Figure 7 shown, the latch signal is provided by the second comparator 702. The second comparator 702 determines whether the residual voltage on the QB node drops below a reference voltage (i.e., Vref). When it is determined that the residual voltage on the QB node drops below the reference voltage, the second comparator 702 provides the latch signal. The latch signal triggers the first comparator 514 to compare the residual voltage on the Q node with the residual voltage on the QB node.

[0087] The first input terminal of the second comparator 702 is connected to the reference voltage node, and the second input terminal of the circuit 518 is connected to the QB node. The output terminal of the second comparator 702 is connected to the first comparator 514. The second comparator compares the residual voltage on the QB node with the reference voltage (i.e., Vref), and when one of the residual voltages on the QB node drops below the reference voltage, it provides a logic low output. The output signal of the second comparator 702 is also referred to as the DET signal.

[0088] Figure 8 FIG. 800 is a graph showing the signals of the sense amplifier 700 during a read operation according to some embodiments. For example, Figure 8 the first curve 602 of the graph 800 shows the read signal (i.e., the READ signal). The second curve 604 of the graph 800 shows the word line / word line reference signal (i.e., the WL / WL_REF signal). The third curve 606 of the graph 800 shows the precharge signal (i.e., the PRE signal). The fourth curve 802 of the graph 800 shows the output signal of the second comparator 702 (i.e., the AND signal). The fifth curve 610 of the graph 800 shows the residual voltages on the Q node and the QB node (i.e., the Q / QB signal). The sixth curve 612 of the graph 800 shows the output signal of the comparator 514 (i.e., the DOUT signal).

[0089] In the example, when the read signal rises from logic low to logic high, the read operation is triggered. As Figure 8As shown by the first curve 602 of the graph 800, when a read operation is initiated, the READ signal changes from logic low to logic high. The rising of the read signal to logic high starts the pre-charge phase of the sense amplifier 700. After the read signal rises to logic high, the word line signal or the word line reference signal also rises to logic high. For example, as shown by the second curve 604 of the graph 800, after the READ signal becomes logic high, the WL / WL_REF signal also changes from logic low to logic high. The first time interval between the rising of the READ signal to logic high and the rising of the WL / WL_REF signal to logic high is also referred to as the signal input period 614.

[0090] In addition, and as shown by the fifth curve 610 of the graph 800, during the signal input period, the pre-charge signal is at logic high. When the pre-charge signal is at logic high, the pre-charge inverted signal or the pre-charge inverted node is at logic low. This causes each of the third transistor P1510 and the fourth transistor P2512 of the sense amplifier 700 to conduct.

[0091] The conduction of the third transistor P1510 causes the Q node to be connected to the supply voltage node (i.e., connected to VDD or logic high). In addition, the conduction of the fourth transistor P2512 causes the QB node to be connected to the supply voltage node (i.e., connected to VDD or logic high). Therefore, during the pre-charge phase, both the Q node and the QB node are at logic high.

[0092] At the end of the pre-charge phase, the pre-charge signal drops to logic low. For example, as shown by the third curve 606 of the graph 800, after the second time interval from the rising of the WL / WL_REF signal to logic high, the PRE signal drops to logic low. The second time interval from the rising of the WL / WL_REF signal to logic high to the dropping of the PRE signal to logic low is also referred to as the pre-charge period 616.

[0093] When the pre-charge signal is at logic low, the pre-charge inverted signal or the pre-charge inverted node rises to logic high. This causes each of the third transistor P1510 and the fourth transistor P2512 to cut off. In addition, the cut-off of the third transistor P1510 causes the Q node to be disconnected from the supply voltage node. Moreover, the cut-off of the fourth transistor P2512 causes the QB node to be disconnected from the supply voltage node. This causes the available voltages on the Q node and the QB node to discharge. For example, as Figure 8 shown by the fifth curve 610 of the graph 800, the dropping of the PRE signal to logic low triggers the gradual dropping of the Q / QB signal.

[0094] The second comparator 702 determines whether the remaining voltage on the QB node is lower than a reference voltage (i.e., 1 / 2(VDD)). When the remaining voltage at the QB node drops below the reference voltage (i.e., 1 / 2(VDD)), the output signal of the second comparator 702 (i.e., the DET signal) drops to logic low. For example, as shown by the fourth curve 802 of the graph 800, the QB signal dropping below the reference voltage (i.e., 1 / 2(VDD)) causes the DET signal to drop to logic low. As shown by the sixth curve 612 of the graph 800, the DET signal dropping to logic low triggers the first comparator 514 to compare the remaining voltage on the Q node with the remaining voltage on the QB node and provide the comparison result at the DOUT signal. For example, as shown by the sixth curve 612 of the graph 600, the DOUT signal indicates whether the data on the memory cell is binary "1" or "0".

[0095] The third period between the PRE signal dropping to logic low and the DET signal rising to logic high is also referred to as the development and latch period 618. The DET signal rising to logic high also triggers the end of the read cycle. Thus, as shown by the first curve 602 and the second curve 604 of the graph 800, both the READ signal and the WL / WL_REF signal drop to logic low. Additionally, as shown by the third curve 606, the PRE signal rises to logic high. Furthermore, the Q / QB signals also rise to logic high.

[0096] Thus, according to the example embodiment, the comparison of the remaining voltages on the Q node and the QB node is delayed until the remaining voltage on the Q node or the QB node drops below the reference voltage (e.g., 1 / 2(VDD)). The delay provides a greater difference or gap in the remaining voltages at the Q node and the QB node, which increases the accuracy of the first comparator 514 and the sense amplifier 500. Additionally, the greater gap increases the operating range of the sense amplifier 500 to higher temperatures.

[0097] Figure 9 is a flowchart showing a method 900 for reading data from a memory cell according to some embodiments. For example, the method 900 may be implemented with reference to Figures 1 to 8 the sense amplifiers 100 and 500 described. Additionally, the steps of the method 900 may be stored as instructions in a memory device or a computer-readable medium, which may be executed by a processor to implement the method 900. The computer-readable medium may be a non-transitory computer-readable medium.

[0098] At block 910 of the method 900, a read signal is received. For example, the read signal is received to start reading data stored in a memory cell of a memory device. In some examples, the read signal rises to logic high to initiate the read operation.

[0099] At block 920 of method 900, in response to receiving a read signal, the first node (i.e., the Q node) and the second node (i.e., the QB node) of sense amplifier 100 are precharged to the supply voltage. Precharging the first node (i.e., the Q node) and the second node (i.e., the QB node) includes connecting the first node (i.e., the Q node) and the second node (i.e., the QB node) to the supply voltage node. The first node (i.e., the Q node) is connected to cell current source Icell102. The second node (i.e., the QB node) is connected to reference current source Iref 104.

[0100] In some examples, the Q node is connected to the supply voltage by turning on fifth transistor P3114, and the QB node is connected to the supply voltage by turning on sixth transistor P4116. Additionally, the Q node is connected to cell current source Icell 102 by first transistor N1106. The Q node is connected to reference current source Iref104 by second transistor N2108. In some examples, the Q node and the QB node are precharged in response to the precharge signal rising to a logic high.

[0101] At block 930 of method 900, after precharging, the first node (i.e., the Q node) and the second node (i.e., the QB node) are disconnected from the supply voltage node. For example, the Q node is disconnected from the supply voltage by turning off fifth transistor P3114, and the QB node is disconnected from the supply voltage by turning off sixth transistor P4116. In some examples, the Q node and the QB node are disconnected from the supply voltage node in response to the precharge signal falling to a logic low.

[0102] At block 940 of method 900, it is determined whether the remaining voltage on the first node (i.e., the Q node) or the remaining voltage on the second node (i.e., the QB node) has dropped below a reference voltage. For example, signal level detector circuit 124 determines whether the remaining voltage on the first node (i.e., the Q node) or the remaining voltage on the second node (i.e., the QB node) has dropped below a reference voltage.

[0103] At block 950 of method 900, in response to determining that the remaining voltage on the first node (i.e., the Q node) or the remaining voltage on the second node (i.e., the QB node) has dropped below the reference voltage, the remaining voltage on the first node (i.e., the Q node) is compared with the remaining voltage on the second node (i.e., the Q node). In an example, first comparator 126 compares the remaining voltage on the Q node with the remaining voltage on the QB node.

[0104] At block 960 of method 900, an output signal is provided based on a comparison. The output signal indicates data stored in a memory cell. For example, based on comparing the residual voltage on the Q node with the residual voltage on the QB node, a comparator provides a DOUT signal. The DOUT signal indicates whether the data stored in the memory cell is a bit value 1 or a bit value 0.

[0105] According to an example embodiment, a sense amplifier includes: a first inverter, wherein a first terminal of the first inverter is connected to a power supply node, and a second terminal of the first inverter is connected to a cell current source; a second inverter, wherein a first terminal of the second inverter is connected to the power supply node, wherein a second terminal of the second inverter is connected to a reference current source, and wherein the first inverter is cross-coupled with the second inverter at a first node and a second node; a precharge circuit connected to the first node and the second node; a first pull-up transistor connected between a supply voltage node and the power supply node; a second pull-up transistor connected between the supply voltage node and the power supply node; and a signal level detector circuit connected to the second pull-up transistor, wherein when the residual voltage on one of the first node and the second node is lower than a reference voltage, the signal level detector circuit turns on the second pull-up transistor.

[0106] In the above sense amplifier, a first comparator is further included, wherein a first input terminal of the first comparator is connected to the first node, and a second input terminal of the first comparator is connected to the second node.

[0107] In the above sense amplifier, the first comparator compares the residual voltage of the first node with the residual voltage of the second node, and provides an output signal based on the comparison, and the output signal indicates data stored in the memory cell associated with the cell current source.

[0108] In the above sense amplifier, the comparison between the residual voltage of the first node and the residual voltage of the second node is delayed until the residual potential of the second node drops below the reference voltage.

[0109] In the above sense amplifier, the signal level detector circuit includes an AND logic circuit, wherein a first input terminal of the AND logic circuit is connected to the first node, wherein a second input terminal of the AND logic circuit is connected to the second node, and wherein an output terminal of the AND logic circuit is connected to the gate of the second pull-up transistor.

[0110] In the above sense amplifier, the signal level detector circuit includes a second comparator, wherein a first input terminal of the second comparator is connected to the second node, wherein a second input terminal of the second comparator is connected to a reference voltage node, and wherein an output terminal of the second comparator is connected to the gate of the second pull-up transistor.

[0111] In the above sense amplifier, the second comparator compares the remaining voltage on the second node with the reference voltage of the reference voltage node, and when the remaining voltage on the second node drops below the reference voltage of the reference node, turns on the second pull-up transistor.

[0112] In the above sense amplifier, the first inverter includes a first transistor and a third transistor, wherein the drain of the first transistor is connected to the cell current source, wherein the source of the first transistor is connected to the Q node, wherein the drain of the third transistor is connected to the Q node, and wherein the source of the third transistor is connected to the power supply node.

[0113] In the above sense amplifier, the second inverter includes a second transistor and a fourth transistor, wherein the drain of the second transistor is connected to the reference current source, wherein the source of the second transistor is connected to the QB node, wherein the drain of the fourth transistor is connected to the QB node, and wherein the source of the fourth transistor is connected to the power supply node.

[0114] In the above sense amplifier, the precharge circuit includes a fifth transistor and a sixth transistor, wherein the source of the fifth transistor is connected to the supply voltage node, wherein the drain of the fifth transistor is connected to the first node, wherein the source of the sixth transistor is connected to the supply voltage node, and wherein the drain of the fifth transistor is connected to the second node.

[0115] In the above sense amplifier, when the fifth transistor and the sixth transistor are turned on, the first node and the second node are charged to the supply voltage.

[0116] In the above sense amplifier, the gate of the first pull-up transistor is connected to the precharge inverted signal node, and wherein when the precharge signal is logic high, the first pull-up transistor is turned on to connect the power supply node to the supply voltage node.

[0117] In an exemplary embodiment, a circuit includes: a first transistor, wherein the source of the first transistor is connected to a first node, and wherein the drain of the first transistor is connected to a unit current source; a second transistor, wherein the source of the second transistor is connected to a second node, and wherein the drain of the second transistor is connected to a reference current source; a third transistor, wherein the source of the third transistor is connected to a supply voltage node, and wherein the drain of the third transistor is connected to the first node; a fourth transistor, wherein the source of the fourth transistor is connected to the supply voltage node, and the drain of the fourth transistor is connected to the second node; a comparator, wherein a first input terminal of the comparator is connected to the first node, and wherein a second input terminal of the comparator is connected to the second node; and a signal level detector circuit, wherein an output terminal of the signal level detector circuit is connected to the comparator. Wherein, the signal level detector circuit triggers the comparator to compare the remaining voltage of the first node and the remaining voltage of the second node in response to at least one of the following: the remaining voltage of the first node is less than a reference voltage, and the remaining voltage of the second node is less than a reference voltage.

[0118] In the above circuit, the signal level detector circuit includes an AND logic circuit, wherein a first input terminal of the AND logic circuit is connected to the first node, and wherein a second input terminal of the AND logic circuit is connected to the second node.

[0119] In the above circuit, the signal level detector circuit includes an operational amplifier, wherein a first input terminal of the operational amplifier is connected to a reference voltage node, and a second input terminal of the operational amplifier is connected to the second node.

[0120] In the above circuit, the gates of the first transistor and the second transistor are connected to a clamping voltage node.

[0121] In the above circuit, the gates of the third transistor and the fourth transistor are connected to a precharge voltage inverted node.

[0122] According to an exemplary embodiment, a method for reading data from a memory cell includes: receiving a read signal; in response to receiving the read signal, precharging a first node of a sense amplifier and a second node of the sense amplifier to a supply voltage, wherein precharging the first node and the second node includes connecting the first node and the second node to a supply voltage node, wherein the first node is connected to a cell current source, and wherein the second node is connected to a reference current source; after precharging, disconnecting the first node and the second node from the supply voltage node; determining that a remaining voltage on the first node or a remaining voltage on the second node drops below a reference voltage; in response to determining that the remaining voltage on the first node or the remaining voltage on the second node drops below the reference voltage, comparing the remaining voltage on the first node with the remaining voltage on the second node; and providing an output signal based on the comparison, the output signal indicating data stored in the memory cell.

[0123] In the above method, comparing the remaining voltage on the first node with the remaining voltage on the second node includes: connecting the first node to a first input terminal of an AND logic circuit, and connecting the second node to a second input terminal of the AND logic circuit.

[0124] In the above method, determining that the remaining voltage on the first node or the remaining voltage on the second node drops below the reference voltage includes: comparing the remaining voltage on the first node or the remaining voltage on the second node with the reference voltage using a comparator.

[0125] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and alterations in the present invention without departing from the spirit and scope of the present invention.

Claims

1. A sense amplifier, comprising: A first inverter, wherein a first terminal of the first inverter is connected to a power supply node, and a second terminal of the first inverter is connected to a cell current source; A second inverter, wherein a first terminal of the second inverter is connected to the power supply node, wherein a second terminal of the second inverter is connected to a reference current source, and wherein the first inverter is cross-coupled with the second inverter at a first node and a second node; A precharge circuit, connected to the first node and the second node; A first pull-up transistor, connected between a supply voltage node and the power supply node; A second pull-up transistor, connected between the supply voltage node and the power supply node; and A signal level detector circuit, connected to the second pull-up transistor, wherein when a remaining voltage at one of the first node and the second node is lower than a reference voltage, the signal level detector circuit turns on the second pull-up transistor.

2. The sense amplifier according to claim 1 further includes a first comparator, wherein, A first input terminal of the first comparator is connected to the first node, and a second input terminal of the first comparator is connected to the second node.

3. The sense amplifier according to claim 2, wherein, The first comparator compares the remaining voltage of the first node with the remaining voltage of the second node, and provides an output signal based on the comparison, the output signal indicating data stored in a memory cell associated with the cell current source.

4. The sense amplifier according to claim 3, wherein, The comparison of the remaining voltage of the first node with the remaining voltage of the second node is delayed until the remaining voltage of the second node drops below the reference voltage.

5. The sense amplifier according to claim 1, wherein, The signal level detector circuit includes an AND logic circuit, wherein a first input terminal of the logic circuit is connected to the first node, wherein a second input terminal of the logic circuit is connected to the second node, and wherein an output terminal of the logic circuit is connected to a gate of the second pull-up transistor.

6. The sense amplifier according to claim 1, wherein, The signal level detector circuit includes a second comparator, wherein a first input terminal of the second comparator is connected to the second node, wherein a second input terminal of the second comparator is connected to a reference voltage node, and wherein an output terminal of the second comparator is connected to the gate of the second pull-up transistor.

7. The sense amplifier according to claim 6, wherein, The second comparator compares the remaining voltage on the second node with the reference voltage of the reference voltage node, and turns on the second pull-up transistor when the remaining voltage on the second node drops below the reference voltage of the reference voltage node.

8. The sense amplifier according to claim 1, wherein, The first inverter includes a first transistor and a third transistor, wherein a drain of the first transistor is connected to the cell current source, wherein a source of the first transistor is connected to the first node, wherein a drain of the third transistor is connected to the first node, and wherein a source of the third transistor is connected to the power supply node.

9. The sense amplifier according to claim 1, wherein, The second inverter includes a second transistor and a fourth transistor, wherein the drain of the second transistor is connected to the reference current source, wherein the source of the second transistor is connected to the second node, wherein the drain of the fourth transistor is connected to the second node, and wherein the source of the fourth transistor is connected to the power supply node.

10. The sense amplifier according to claim 1, wherein, The precharge circuit includes a fifth transistor and a sixth transistor, wherein the source of the fifth transistor is connected to the supply voltage node, wherein the drain of the fifth transistor is connected to the second node, wherein the source of the sixth transistor is connected to the supply voltage node, and wherein the drain of the sixth transistor is connected to the first node.

11. The sense amplifier according to claim 10, wherein, When the fifth transistor and the sixth transistor are turned on, the first node and the second node are charged to the supply voltage.

12. The sense amplifier according to claim 1, wherein, The gate of the first pull-up transistor is connected to the precharge inverted signal node, and wherein when the precharge signal is logic high, the first pull-up transistor is turned on to connect the power supply node to the supply voltage node.

13. A sense amplifier circuit, comprising: A first transistor, wherein the source of the first transistor is connected to a first node, and wherein the drain of the first transistor is connected to a cell current source; A second transistor, wherein the source of the second transistor is connected to a second node, and wherein the drain of the second transistor is connected to a reference current source; A third transistor, wherein the source of the third transistor is connected to the supply voltage node, and wherein the drain of the third transistor is connected to the first node; A fourth transistor, wherein the source of the fourth transistor is connected to the supply voltage node, and wherein the drain of the fourth transistor is connected to the second node; A comparator, wherein a first input terminal of the comparator is connected to the first node, and wherein a second input terminal of the comparator is connected to the second node; and A signal level detector circuit, wherein an output terminal of the signal level detector circuit is connected to the comparator, and wherein the signal level detector circuit triggers the comparator to compare a remaining voltage of the first node and a remaining voltage of the second node in response to at least one of the following: The remaining voltage of the first node is less than a reference voltage, and The remaining voltage of the second node is less than the reference voltage.

14. The sense amplifier circuit according to claim 13, wherein, The signal level detector circuit includes an AND logic circuit, wherein a first input terminal of the AND logic circuit is connected to the first node, and wherein a second input terminal of the logic circuit is connected to the second node.

15. The sense amplifier circuit according to claim 13, wherein, The signal level detector circuit includes an operational amplifier, wherein a first input terminal of the operational amplifier is connected to a reference voltage node, and a second input terminal of the operational amplifier is connected to the second node.

16. The sense amplifier circuit according to claim 13, wherein, The gates of the first transistor and the second transistor are connected to a clamped voltage node.

17. The sense amplifier circuit according to claim 13, wherein, The gates of the third transistor and the fourth transistor are connected to a precharge voltage inverted node.

18. A method for reading data from a memory cell, the method comprising: Receiving a read signal; In response to receiving the read signal, precharging a first node of a sense amplifier and a second node of the sense amplifier to a supply voltage, wherein precharging the first node and the second node includes connecting the first node and the second node to a supply voltage node, wherein the first node is connected to a cell current source, and wherein the second node is connected to a reference current source; After precharging, disconnecting the first node and the second node from the supply voltage node; Determining that a remaining voltage on the first node or a remaining voltage on the second node drops below a reference voltage; In response to determining that the remaining voltage on the first node or the remaining voltage on the second node drops below the reference voltage, comparing the remaining voltage on the first node with the remaining voltage on the second node; and Providing an output signal based on the comparison, the output signal indicating data stored in the memory cell.

19. The method according to claim 18, wherein Comparing the remaining voltage on the first node with the remaining voltage on the second node includes: connecting the first node to a first input terminal of a logic circuit and connecting the second node to a second input terminal of the logic circuit.

20. The method according to claim 18, wherein, Determining that the remaining voltage on the first node or the remaining voltage on the second node drops below the reference voltage includes: using a comparator to compare the remaining voltage on the first node or the remaining voltage on the second node with the reference voltage.

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