A WS2-WSe2 lateral heterojunction with different number of layers and its preparation and application

Abstract

The present invention belongs to the field of two-dimensional material preparation, and specifically relates to a method for preparing WS2-WSe2 lateral heterojunctions with different numbers of layers, wherein WSe2 powder is heat-treated at a temperature of 1150-1200°C; using the heat-treated WSe2 as the source material and the WS2 nanosheet as the substrate, a gas-variable deposition method is used to heat the source material to a volatilization temperature under a reverse carrier gas, and then change to a forward carrier gas, and the volatilized source material is laterally deposited on the edge of the WS2 nanosheet, and then the deposited product is quenched from the deposition temperature to room temperature to obtain the WS2-WSe2 lateral heterojunction; the direction of the reverse carrier gas refers to the direction from the substrate to the source material; the volatilization temperature is less than the heat treatment temperature, and the temperature difference is 10-25°C; the temperature of the lateral deposition is 800-950°C. In the present invention, through the combined control of the means and parameters, WSe2 can be synergistically induced to grow laterally at the edge of WS2, successfully preparing the lateral heterojunction, improving the boundary and smoothness, and realizing artificial control of the thickness of the lateral heterojunction nanosheet.

Description

Technical Field

[0001] The invention belongs to the field of nanomaterials and relates to a method for preparing a lateral heterojunction of two-dimensional materials. Technical Background

[0002] The rise of two-dimensional materials can be traced back to 2004, when Science reported that British scientists Geim and Novoselo had obtained a single layer of graphene by tape exfoliation, garnering widespread attention in the academic community. Currently the thinnest material in the world, just one atom thick, graphene has since quickly become a hot topic in physics and materials science. In 2010, they were awarded the Nobel Prize in Physics for this research. However, graphene's unique zero-gap band structure significantly limits its application in electronics and optoelectronics.

[0003] At this time, people gradually paid attention to other two-dimensional materials, such as transition metal dichalcogenides (TMDs). While ensuring the same excellent performance as graphene, they also have a natural band gap and are also called graphene-like materials. As layered materials, TMDs have been prepared by mechanical exfoliation or chemical vapor deposition (CVD), and their properties have also been widely studied. B. Radisavljevic et al. used a single layer of MoS2 to prepare a field effect transistor with an on / off ratio as high as 10 8 , has great application prospects, and new two-dimensional materials represented by single-layer MoS2 have attracted great attention [1] . The atoms within the layers of layered materials such as TMDs are bonded by strong covalent bonds or ionic bonds, and the layers are bonded by weak van der Waals forces, and these 2D-TMDs generally have electronic and optoelectronic properties that depend on the number of material layers. To fully realize the application of these layered semiconductor materials in the fields of electronics and optoelectronics, it is necessary to accurately determine the chemical composition, structure, and spatial distribution of electronic properties of these two-dimensional atomic crystals, which is similar to traditional semiconductor materials represented by silicon in the traditional electronics field. In the traditional electronics industry, heterojunctions define the basic structure of modern electronic and optoelectronic devices, such as pn junction diodes, photovoltaic devices, photodetectors, light-emitting diodes, laser diodes, etc. The preparation of lateral heterojunctions of two-dimensional materials such as 2D-TMDs is crucial for the successful application of related two-dimensional materials in the electronics field and to give full play to their advantages. [2] As atomically thin semiconductor heterojunctions, two-dimensional layered material heterojunctions have many important scientific significances and application values ​​and are extremely promising for research.

[0004] At present, the properties of vertical heterojunctions of two-dimensional materials have been widely studied. However, the research on lateral heterojunctions has been slow due to the harsh process conditions. [2-5]Currently, a variety of two-dimensional lateral heterojunctions have been prepared, including graphene-boron nitride lateral heterojunctions, TMDs series lateral heterojunctions, etc. The preparation methods of two-dimensional lateral heterojunctions include step-by-step synthesis, one-time synthesis, and in-situ change of gas phase reactants. Compared with single-layer crystals and single-layer heterostructures, double-layer structures are more stable under ambient conditions and provide better electrical properties. [6] . In addition, considering the layer number dependence of most 2D materials, heterostructures of two-dimensional materials with different numbers of layers have rich physical properties and potential application prospects. However, the preparation and research of lateral heterojunctions are mostly focused on single-layer materials, while the growth and research of double-layer lateral heterojunctions and asymmetric lateral heterojunctions are still rare. Therefore, there are many challenges in this field that need to be solved. As atomically thin semiconductor heterojunctions, heterojunctions of two-dimensional layered materials with different numbers of layers have many important scientific significances and application values, and are extremely promising for research.

[0005] References

[0006] [1].Geim AK,Grigorieva IV.Van der Waals heterostructures.Nature.499,419-425(2013).

[0007] [2].Yan R,et al.Esaki diodes in Van der Waals heterojunctions withbroken-gap energy band alignment.Nano Lett.15,5791-5798(2015).

[0008] [3].Ross JS,et al.Interlayer exciton optoelectronics in a 2Dheterostructure pn junction.Nano Lett.17,638-643(2017).

[0009] [4].Li MY,et al.Epitaxial growth of a monolayer WSe2-MoS2 lateral p-njunction with an atomically sharp interface.Science.349,524-528(2015).

[0010] [5].Huang C, et al. Lateral heterojunctions within monolayer MoSe2–WSe2semiconductors. NatMater.13,1096-1101(2014).

[0011] [6]. Sahoo PK, et al. Bilayer lateral heterostructures of transition-metal dichalcogenides and their optoelectronic response. ACS Nano. 13, 12372-12384 (2019). Summary of the Invention

[0012] In order to solve the problems of current lateral heterojunctions such as a single number of layers, difficulty in control, unclear boundaries, and uneven surfaces, the purpose of the present invention is to provide a method for preparing WS2-WSe2 lateral heterojunctions with different numbers of layers, aiming to prepare a WS2-WSe2 lateral heterojunction with clear boundaries, smooth surface, and controllable number of layers.

[0013] The second object of the present invention is to provide a WS2-WSe2 lateral heterojunction obtained by the preparation method.

[0014] The third object of the present invention is to provide the application of the WS2-WSe2 lateral heterojunction in the preparation of optoelectronic devices and the prepared optoelectronic devices.

[0015] A method for preparing WS2-WSe2 lateral heterojunctions with different numbers of layers comprises the following steps:

[0016] Step (a): heat treating WSe2 powder at a temperature of 1150-1200°C;

[0017] Step (b): Using heat-treated WSe2 as the source material and WS2 nanosheets as the substrate, a gas-shift deposition method is used to heat the source material to the volatilization temperature (also known as the evaporation temperature) under a reverse carrier gas, and then switch to a forward carrier gas to laterally deposit the volatilized source material on the edge of the WS2 nanosheet. The deposited product is then quenched from the deposition temperature to room temperature to obtain the WS2-WSe2 lateral heterojunction.

[0018] The direction of the reverse carrier gas is from the substrate to the source material; the volatilization temperature is lower than the heat treatment temperature, and the temperature difference is 10 to 25°C;

[0019] The temperature of lateral deposition is 800-950°C.

[0020] The preparation of WS2-WSe2 lateral heterojunctions requires addressing numerous difficulties, including the difficulty in controlling lateral deposition, as well as interference between the lateral deposition processes, resulting in unclear boundaries, uneven surfaces, and uncontrollable number of layers. To address these difficulties, the present invention, through in-depth research, has discovered that pre-heat treatment of WSe2, followed by variable temperature deposition and quenching at the required temperature difference, can synergistically induce the lateral growth of WSe2 at the edge of WS2, successfully preparing the lateral heterojunction. Furthermore, this can improve the boundaries and smoothness, and enable artificial control of the thickness of the lateral heterojunction nanosheets.

[0021] The WS2 nanosheets are nanosheets with 1 to 4 layers, preferably single-layer or double-layer nanosheets.

[0022] In the present invention, the WS2 nanosheets can be prepared based on existing means.

[0023] For example, it can be prepared by PVD or CVD methods;

[0024] Preferably, the growth temperature of the PVD process for preparing WS2 nanosheets is 1150℃-1200℃, preferably 1150℃-1180℃; the growth time is preferably 1-5min, preferably 3-5min; the carrier gas in the growth process is protective gas; and the flow rate of the carrier gas is preferably 50-150sccm.

[0025] It is further preferred to prepare WS2 nanosheets using gas change technology; for example, WS2 is heated to a volatilization temperature under a reverse carrier gas, and then switched to a forward carrier gas, so that the volatilized material is deposited on the substrate at the required growth temperature to obtain the WS2 nanosheets; the reverse direction refers to the direction from the substrate to the WS2.

[0026] The present invention has found that the combination of the WSe2 heat treatment, the gradient gas deposition and the quenching process is the key to collaboratively solving the mutual interference, unclear boundaries and uneven surface in the heterojunction growth process.

[0027] In the present invention, the heat treatment is performed in a protective gas atmosphere. The protective gas is at least one of nitrogen and an inert gas. The inert gas is, for example, Ar. The direction of the protective gas flow is not critical.

[0028] Preferably, the heat treatment temperature is 1150-1170°C.

[0029] In the present invention, the heat-treated raw material is cooled (e.g., in a furnace) to obtain the heat-treated raw material. Research has found that controlling the temperature and duration of the heat treatment can improve its physical phase, which facilitates coordination with subsequent deposition processes and allows for artificial control of the number of layers of laterally grown selenide nanosheets.

[0030] Preferably, the heat treatment time is 10 to 30 minutes, more preferably 20 to 25 minutes; the number of laterally deposited WSe2 layers is two.

[0031] Preferably, the heat treatment time is 40 to 90 min, preferably 45 to 85 min; the number of layers of laterally deposited WSe2 is a single layer.

[0032] In the present invention, the control of the heat treatment temperature, subsequent gas volatilization, deposition and temperature difference, and further combined with the quenching process, can unexpectedly solve the preparation problems of unclear boundaries and uneven surfaces of lateral heterojunctions.

[0033] Preferably, in step (b), the carrier gas is a protective gas, preferably at least one of nitrogen and an inert gas.

[0034] Preferably, in step (b), the flow rates of the reverse carrier gas and the forward carrier gas are 50-150 sccm respectively.

[0035] In the present invention, in step (b), the WSe2 evaporation temperature is 1130-1140° C. That is, after being heated to this temperature under reverse carrier gas, it is changed to forward carrier gas.

[0036] In the present invention, the combined control of the heat treatment temperature, the temperature difference between the evaporation temperature, and the lateral deposition temperature helps to improve the boundary and surface smoothness of the lateral heterojunction in combination with the quenching process.

[0037] Preferably, the temperature difference between the evaporation temperature in step (b) and the heat treatment temperature is 15-20°C;

[0038] Preferably, during the lateral deposition process, the distance between the source material and the substrate is 12-15 cm;

[0039] Preferably, the temperature of the lateral deposition is 800-950°C, more preferably 850-900°C;

[0040] Preferably, the lateral deposition time is 1-5 minutes.

[0041] After the lateral deposition is completed, the reacted substrate is pulled out of the deposition temperature zone and placed in a room temperature environment for a quenching treatment.

[0042] In the present invention, the room temperature is 10 to 50°C;

[0043] Preferably, the atmosphere during the quenching process is a protective atmosphere;

[0044] Preferably, the quenching process is carried out under a countercurrent flow, which also refers to the direction from the substrate to the source material.

[0045] The present invention provides a preferred method for preparing a WS2-WSe2 lateral heterojunction with different numbers of layers, comprising the following steps:

[0046] Step (1): Using WS2 powder as a raw material, heating it to the growth temperature under a reverse carrier gas flow, and then vapor-depositing it on the substrate surface under a forward carrier gas flow to form WS2 nanosheets of varying numbers; the WS2 growth temperature is 1150°C-1200°C, preferably 1150°C-1180°C; the growth time is 1-5 minutes, preferably 3-5 minutes; and the carrier gas flow rate is 50-150 sccm. The substrate is a Si / SiO2 substrate, a sapphire substrate, or a mica substrate; more preferably, a Si / 285nm SiO2 substrate.

[0047] Step (2): heat-treating the WSe2 powder; the heat-treating temperature is 1150°C-1200°C, preferably 1150°C-1170°C; the heat-treating time is 10-90 min;

[0048] Step (3): Using the WS2 nanosheets of different numbers obtained in step (1) as a substrate, the WSe2 powder that has been heat-treated in step (3) is again heated to the volatilization temperature under a reverse carrier gas flow, and then switched to a forward gas flow to deposit it laterally on the edge of the WS2 nanosheet. Subsequently, under a reverse carrier gas flow, the laterally deposited product is placed from the deposition temperature zone to room temperature and quenched to obtain the WS2-WSe2 lateral heterojunction. Two-dimensional WS2-WSe2 lateral heterojunctions with different numbers of WSe2 epitaxy are obtained (including double-layer-double-layer and single-layer-double-layer WS2-WSe2 lateral heterojunctions of double-layer WSe2 epitaxy and double-layer-single-layer and single-layer-single-layer WS2-WSe2 lateral heterojunctions of single-layer WSe2 epitaxy). The temperature difference between the evaporation temperature and the heat treatment temperature is 10-25°C, the distance between the source material and the substrate is 12-15 cm (the temperature of lateral deposition is 800-950°C); the time of lateral deposition is 1-5 min, preferably 1 to 2 min, and the carrier gas flow rate is 50-150 sccm, preferably 60-120 sccm.

[0049] In the present invention, through the joint control of growth process and parameter conditions, the problem of difficult-to-control nucleation at the boundary during the lateral epitaxial growth of two-dimensional materials can be solved, and the atomic-level flatness at the boundary can be further improved; it can also solve the material damage caused by deposition, the appearance of three-dimensional islands at the boundary, the weakening of growth controllability, the occurrence of unstable growth, the growth of three-dimensional structures and other unfavorable results.

[0050] The present invention also provides a vapor deposition device for implementing the preparation method, comprising a quartz tube, wherein the central chamber of the quartz tube is a high-temperature constant temperature zone, in which the raw material powder of the two-dimensional material is placed, and the device is further provided with a heating device for heating the high-temperature constant temperature zone; the chamber at one end of the quartz tube is a variable temperature deposition zone, in which the substrate and / or the substrate deposited with WS2 is placed;

[0051] Both ends of the quartz tube are provided with air holes.

[0052] The variable temperature deposition zone is arranged on one side of the high temperature constant temperature zone and is either not equipped with a heating device or is equipped with a heating device.

[0053] In the vapor deposition apparatus of the present invention, during the heterojunction preparation process, the raw material powder of the two-dimensional material is heated to the growth temperature. The green arrow represents the reverse airflow (the substrate points in the direction of the source material), and the red arrow represents the forward airflow.

[0054] In the present invention, when preparing WS2 nanosheets, a reverse airflow (green arrow) is first introduced to clean the pipeline for ten minutes. Under the continuous purge of the reverse carrier gas, the WS2 powder is continuously heated in the high-temperature constant temperature area. After heating to the growth temperature, the airflow direction of the carrier gas is changed to the forward direction (red arrow) to obtain WS2 nanosheets.

[0055] In step (2), WSe2 powder is loaded into an alumina boat and placed in a high-temperature constant temperature area; first, a reverse airflow is introduced (green arrow, the base points in the direction of WSe2), the pipeline is cleaned, and the temperature is increased under continuous purge of the reverse carrier gas. When the temperature of WSe2 is heated to the heat treatment temperature, the reverse airflow is maintained, the heat treatment is carried out, and then the heat treatment is carried out with the furnace to obtain the heat-treated WSe2 powder;

[0056] In step (3), after cleaning the pipeline, the silicon wafer with WS2 deposited is placed downstream of the tube furnace and heated under continuous purge of reverse carrier gas. When the temperature of WSe2 after heat treatment rises to the evaporation temperature, the airflow direction is switched, and WSe2 grows laterally along the edge of the WS2 nanosheet (forward airflow). After the growth is completed, it is switched to reverse airflow and the sample is pulled to room temperature for quenching to obtain lateral heterojunction WS2-WSe2 with different numbers of layers; the temperature difference between the evaporation temperature and the heat treatment temperature is 10-25°C.

[0057] A preferred method for preparing a two-dimensional material heterojunction of the present invention comprises the following steps:

[0058] Step (1): Load the WS2 powder source into an alumina boat and place it in the middle high-temperature constant temperature area of ​​a quartz tube (2-10 cm diameter) in a tube furnace; place a silicon oxide wafer (Si / 285 nm SiO2) as a substrate for material deposition in the variable temperature deposition area of ​​the tube furnace;

[0059] Argon gas is first passed through the pipeline for cleaning (e.g., 400-800 sccm of argon gas flow rate for 5-30 minutes). Argon gas is used as a carrier gas during the heating process. The growth temperature of WS2 is 1150°C-1200°C, the growth time is 1-5 minutes, and the carrier gas flow rate is 50-150 sccm.

[0060] After the deposition is completed, double-layer or single-layer single-crystal WS2 nanosheets will be deposited on the substrate surface;

[0061] Step (2): heat treating the WSe2 powder source;

[0062] Loaded in an alumina boat, placed in the middle high-temperature constant temperature area of ​​a tubular furnace quartz tube (2-10 cm diameter);

[0063] Argon is first passed through the pipeline for cleaning (the flow rate of argon is, for example, 400-800 sccm, and the passage time is, for example, 10-30 minutes), and argon is used as the carrier gas during the heating process; WSe2 is heated to 1150℃-1200℃ for heat treatment. During this period, the carrier gas is forward or reverse, and there is no requirement for the carrier gas flow rate, for example, 50-150 sccm.

[0064] Step (3): Preparation of lateral WS2-WSe2 heterojunction of two-dimensional materials, including the following steps

[0065] The substrate prepared in step (1) and deposited with a double-layer or single-layer two-dimensional WS2 is placed in the downstream variable temperature deposition area of ​​the tube furnace;

[0066] First, argon gas is passed through the pipeline (the flow rate of argon gas is, for example, 400-800 sccm, and the introduction time is, for example, 20-40 minutes), and a reverse airflow is introduced during the reaction temperature rising stage. When the evaporation temperature is reached, a forward airflow is introduced. WSe2 volatilizes at 1130℃-1140℃ and is laterally deposited on the substrate. The lateral deposition time (deposition temperature is 800-950℃) is 1-2 minutes, and the carrier gas flow rate is 60-120 sccm. After the growth is completed, the reverse carrier gas is switched, and the sample is pulled out of the furnace and placed at room temperature for quenching to obtain the WS2-WSe2 lateral heterojunctions with different numbers of epitaxial layers, including double-layer-double-layer, single-layer-double-layer, double-layer-single-layer and single-layer-single-layer WS2-WSe2 lateral heterojunctions.

[0067] The present invention also provides a WS2-WSe2 lateral heterojunction with different numbers of layers prepared by the preparation method; comprising a WS2 nanosheet, and WSe2 nanosheets sequentially grown laterally on the edge of the WS2 nanosheet;

[0068] Preferably, the WS2 nanosheet is a single-layer to four-layer nanosheet; the WSe2 nanosheet is a single-layer or double-layer nanosheet;

[0069] Preferably, the WS2-WSe2 lateral heterojunction with different numbers of layers is at least one of a single-layer WS2-single-layer WSe2 lateral heterojunction, a single-layer WS2-double-layer WSe2 lateral heterojunction, a double-layer WS2-single-layer WSe2 lateral heterojunction, and a double-layer WS2-double-layer WSe2 lateral heterojunction.

[0070] The present invention also provides an application of WS2-WSe2 lateral heterojunctions with different numbers of layers prepared by the preparation method, which is used to prepare optoelectronic devices;

[0071] Preferably, the optoelectronic device is at least one of a pn junction diode, a photovoltaic device, a photodetector, a light emitting diode, and a laser diode.

[0072] The present invention can be based on existing equipment and means to make optoelectronic devices from the WS2-WSe2 lateral heterojunctions with different numbers of layers described in the present invention.

[0073] The present invention also provides a photoelectric device comprising a WS2-WSe2 lateral heterojunction with different numbers of layers prepared by the preparation method.

[0074] Beneficial effects

[0075] In the present invention, WSe2 is heat-treated in advance and then deposited and quenched under a gas-changing method and the required temperature difference, which can synergistically induce WSe2 to grow laterally at the edge of WS2 and successfully prepare the lateral heterojunction. Not only that, it can also improve the boundary and smoothness, and realize the artificial control of the thickness of the lateral heterojunction nanosheet. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 Schematic diagram of the device for preparing lateral heterojunctions of two-dimensional materials with different numbers of layers;

[0077] Figure 2 The WS2 test images prepared in Example 1, where (a) is an optical microscope photo of a double-layer WS2 and (b) is an optical microscope photo of a single-layer WS2;

[0078] Figure 3Test images of the double-layer-double-layer lateral heterojunction WS2-WSe2 prepared in Example 1, where (a) is an optical microscope image, (b) is an atomic force microscope image, and (c) is a height change diagram at the point indicated by the arrow in (b);

[0079] Figure 4 The single-layer-double-layer lateral heterojunction WS2-WSe2 test diagram prepared in Example 2, wherein (a) is an optical microscope image, (b) is an atomic force microscope image, and (c) is a height change diagram at the point indicated by the arrow in (b);

[0080] Figure 5 The test image of the double-layer-single-layer lateral heterojunction WS2-WSe2 prepared in Example 3, wherein (a) is an optical microscope image, (b) is an atomic force microscope image, and (c) is a height change diagram at the point indicated by the arrow in (b);

[0081] Figure 6 The test diagram of the single-layer-single-layer lateral heterojunction WS2-WSe2 prepared in Example 4, wherein (a) is an optical microscope photo, (b) is an atomic force microscope photo, and (c) is a height change diagram at the point indicated by the arrow in (b);

[0082] Figure 7 Test images of the double-layer-double-layer and single-layer-single-layer WS2-WSe2 FET devices prepared in Example 5, where (a) is an optical microscope photo of the double-layer-double-layer WS2-WSe2 FET device, (b) is its output characteristic curve, (c) is an optical microscope photo of the single-layer-single-layer WS2-WSe2 FET device, and (d) is its output characteristic curve;

[0083] Figure 8 This is an optical microscope photograph of the double-layer-double-layer WS2-WSe2 lateral heterojunction prepared in Comparative Example 1;

[0084] Figure 9 This is an optical microscope photograph of the double-layer-double-layer WS2-WSe2 lateral heterojunction prepared in Comparative Example 2;

[0085] Figure 10 This is an optical microscope photograph of the lateral heterojunction of WS2-WSe2 prepared in Comparative Example 3;

[0086] Figure 11 This is an optical microscope photograph of the lateral heterojunction of WS2-WSe2 prepared in Comparative Example 4;

[0087] Figure 12 This is an optical microscope photograph of the lateral heterojunction of WS2-WSe2 prepared in Comparative Example 4; DETAILED DESCRIPTION

[0088] The present invention is further described below through examples of implementation, but the content of the present invention is not limited to the following content.

[0089] Example 1

[0090] Step (1): Preparation of WS2 nanosheets:

[0091] 1 g of WS2 powder source was weighed and loaded into an alumina boat, which was then placed in the middle high-temperature area of ​​a quartz tube (2 cm diameter) in a tubular furnace.

[0092] The pipeline was first purged by passing 600 sccm of argon gas for 5 minutes. During the heating process, argon was used as a carrier gas at a flow rate of 60 sccm. WS2 was heated to 1150°C under countercurrent flow. The flow was then switched to forward carrier gas flow and allowed to grow at this temperature for 4 minutes before cooling to room temperature. Double-layer WS2 nanosheets were obtained. Single-layer WS2 nanosheets were obtained at 1180°C.

[0093] Figure 2 To prepare the optical images of double-layer and single-layer WS2, the edges are regular and smooth without etching. In Figure 2, the scale bar in (a) and (b) is 50μm.

[0094] Step (2): Heat treatment of WSe2 powder

[0095] Weigh 1 g of WSe2 powder source and load it into an alumina boat, which is then placed in the middle high-temperature area of ​​a quartz tube (2 cm diameter) in a tubular furnace.

[0096] The pipeline was first cleaned by passing 600 sccm argon for 10 minutes. Argon was used as the carrier gas during the heating process with a gas flow rate of 60 sccm. WSe2 was heated to 1150°C under reverse airflow, maintained at this temperature for 20 minutes, and cooled to room temperature.

[0097] Step (3): Preparation of double-layer-double-layer WS2-WSe2 lateral heterojunction:

[0098] A WSe2 powder source was placed in a high-temperature zone, and a silicon oxide wafer (Si / 285nm SiO2) on which a large-area double-layer WS2 was grown was placed in the variable temperature deposition zone of a tube furnace as a deposition substrate for the material (prepared in step (1)). Within the reaction furnace, the distance between the substrate and the WSe2 powder source was 12 cm. The pipeline was cleaned by passing 600 sccm of argon gas for 20 minutes. Argon was used as a carrier gas at a gas flow rate of 60 sccm. The WSe2 powder source was heated to 1130°C under a countercurrent flow. The flow was then reversed, and the volatilized raw material grew laterally along the edge of the double-layer WS2 (growth zone temperature was 895-900°C) for 1-2 minutes, resulting in a large-area double-layer-double-layer WS2-WSe2 lateral heterojunction deposited on the silicon oxide. The reverse carrier gas flow was then switched, and the sample was pulled out of the high-temperature furnace using a magnet and a quartz hook to room temperature (25-30°C) for quenching.

[0099] Figure 3 Optical images and atomic force microscopy maps of the samples were prepared to confirm that the obtained samples were a double-layer-double-layer structure with a clear interface and no etching. Figure 2 The scale bars in (a) and (b) are 10 μm.

[0100] Example 2

[0101] Preparation of single-layer-double-layer WS2-WSe2 lateral heterojunction:

[0102] Compared with Example 1, the only difference is that in step (3), the prepared single-layer WS2 silicon oxide wafer is used as the lateral deposition substrate. Figure 4 Optical images and atomic force microscopy maps of the prepared samples were obtained to confirm that the obtained samples were a single-layer-double-layer structure. Figure 4 The scale bars in (a) and (b) are 10 μm.

[0103] Example 3

[0104] The preparation of a double-layer-single-layer WS2-WSe2 lateral heterojunction includes the following steps:

[0105] Compared with Example 1, the only difference is that in step (2), the heat treatment time is extended to 50 minutes. Figure 5 Optical images and atomic force microscopy maps of the prepared samples were obtained to confirm that the obtained samples were a double-layer-single-layer structure. Figure 5 The scale bars in (a) and (b) are 5 μm.

[0106] Example 4

[0107] The preparation of a single-layer-single-layer WS2-WSe2 lateral heterojunction includes the following steps:

[0108] Compared with Example 3, the only difference is that in step (3), the single layer WS2 obtained in step (1) is used as the substrate for lateral growth. Figure 6 Optical images and atomic force microscopy maps of the samples were prepared to confirm that the obtained samples were a single-layer-single-layer structure. Figure 6 The scale bars in (a) and (b) are 10 μm.

[0109] Example 5

[0110] The preparation of WS2-WSe2 lateral heterojunction FET device includes the following steps:

[0111] Step (a): Spin-coat PMMA glue on the silicon wafer with the sample, expose the mark using EBL, and develop and fix until the glue on the mark is completely removed; then use software to draw the electrode shape to be exposed, expose the electrode again, and develop and fix the electrode shape;

[0112] Step (b): Use an evaporator to deposit 10nm / 30nm Cr / Au on the silicon wafer, soak the silicon wafer in acetone for 20-40 minutes to remove the PMMA glue and the gold on it;

[0113] Step (c): Use a probe station to perform testing.

[0114] Figure 7 Figures 1 and 2 show the test results of the double-layer-double-layer WS2-WSe2 FET device prepared in Example 1 and the single-layer-single-layer WS2-WSe2 FET device prepared in Example 4. (a) shows an optical microscope photograph of the double-layer-double-layer WS2-WSe2 FET device, and (b) shows its output characteristic curve. (c) shows an optical microscope photograph of the single-layer-single-layer WS2-WSe2 FET device, and (b) shows its output characteristic curve. It can be seen that the current and on / off ratio of the double-layer-double-layer heterojunction are significantly higher than those of the single-layer-single-layer sample.

[0115] Comparative Example 1

[0116] Compared with Example 1, the only difference is that no quenching treatment is performed, that is, the product is not pulled from the deposition temperature zone to room temperature after the deposition is completed.

[0117] Figure 8 To prepare an optical image of the sample. Figure 6 The scale bar in the figure is 20 μm. WS2 undergoes significant thermal etching, resulting in an uneven interface.

[0118] Comparative Example 2

[0119] Compared with Example 1, the difference is that there is no temperature difference between the heat treatment temperature and the growth temperature of step (3), that is, the growth temperature of the heterojunction is 1150°C. Figure 9The optical image of the prepared sample is shown in Figure 9. The scale bar in Figure 9 is 20 μm. WS2 is etched, resulting in increased defects and an uneven interface.

[0120] Comparative Example 3

[0121] Compared with Example 1, the difference is that there is no temperature difference between the heat treatment temperature and the growth temperature of step (3), that is, the growth temperature of the heterojunction is 1130°C. Figure 10 To prepare an optical image of the sample. Figure 10 The scale bar in the figure is 40 μm. The WSe2 epitaxial thickness is uneven, with multiple nuclei present.

[0122] Comparative Example 4

[0123] Compared with Example 1, the difference is that the heat treatment in step (2) is not performed. Figure 11 To prepare an optical image of the sample. Figure 11 The scale bar in the figure is 40 μm. The WSe2 epitaxial thickness is uneven, with multiple nuclei present.

[0124] Comparative Example 5

[0125] The source material is directly placed in the high temperature zone, the substrate in step (1) is placed in the deposition temperature zone, and the forward deposition is directly performed after the reverse heat treatment (without step-by-step treatment). Figure 11 To prepare an optical image of the sample. Figure 11 The scale bar in the figure is 100μm. Due to being at high temperature for too long, WS2 is almost completely etched away.

Claims

1. A method for preparing WS2-WSe2 lateral heterojunctions with different numbers of layers, characterized in that: The following steps are involved: Step (a): heat treating WSe2 powder at a temperature of 1150-1200°C; Step (b): Using heat-treated WSe2 as the source material and WS2 nanosheets as the substrate, a gas-shift deposition method is used to heat the source material to a volatilization temperature under a reverse carrier gas, and then switch to a forward carrier gas to laterally deposit the volatilized source material on the edge of the WS2 nanosheet. The deposited product is then quenched from the deposition temperature to room temperature to obtain the WS2-WSe2 lateral heterojunction. The direction of the reverse carrier gas is from the substrate to the source material; the volatilization temperature is lower than the heat treatment temperature, and the temperature difference is 10-25°C; The temperature of lateral deposition is 800~950℃; Heat treatment is carried out in a protective gas atmosphere: The heat treatment time is 10-30 min; the number of WSe2 layers deposited laterally is two; The heat treatment time is 40~90min; the number of layers of WSe2 deposited laterally is a single layer; The room temperature is 10-50°C; the atmosphere during the quenching process is a protective atmosphere; and the quenching process is carried out under reverse airflow.

2. The method for preparing a lateral heterojunction of WS2-WSe2 with different numbers of layers according to claim 1, characterized in that: The heat treatment temperature is 1150~1170℃.

3. The method for preparing a lateral heterojunction of WS2-WSe2 with different numbers of layers according to claim 1, characterized in that: The WS2 nanosheets are nanosheets with 1 to 4 layers.

4. The method for preparing a lateral heterojunction of WS2-WSe2 with different numbers of layers according to claim 1, characterized in that: Prepared by PVD or CVD method.

5. The method for preparing a WS2-WSe2 lateral heterojunction with different numbers of layers according to claim 4, characterized in that: The growth temperature of the PVD process for preparing WS2 nanosheets is 1150℃~1200℃; the growth time is 1~5min; the carrier gas in the growth process is protective gas; and the flow rate of the carrier gas is 50~150sccm.

6. The method for preparing a lateral heterojunction of WS2-WSe2 with different numbers of layers according to claim 1, characterized in that: In step (b), the carrier gas is a protective gas, which is at least one of nitrogen and an inert gas.

7. The method for preparing a WS2-WSe2 lateral heterojunction with different numbers of layers according to claim 1, characterized in that: The volatilization temperature of WSe2 is 1130~1140℃.

8. The method for preparing a WS2-WSe2 lateral heterojunction with different numbers of layers according to claim 1, characterized in that: In step (b), the flow rates of the reverse carrier gas and the forward carrier gas are 50-150 sccm, respectively.

9. The method for preparing a lateral heterojunction of WS2-WSe2 with different numbers of layers according to claim 1, characterized in that: The temperature difference between the evaporation temperature in step (b) and the heat treatment temperature is 15-20°C.

10. The method for preparing a lateral heterojunction of WS2-WSe2 with different numbers of layers according to claim 1, characterized in that: During the lateral deposition process, the distance between the source material and the substrate was 12–15 cm.

11. The method for preparing a lateral heterojunction of WS2-WSe2 with different numbers of layers according to claim 1, characterized in that: The temperature of lateral deposition is 800~950℃.

12. The method for preparing a lateral heterojunction of WS2-WSe2 with different numbers of layers according to claim 1, characterized in that: The lateral deposition time is 1~5min.

13. A WS2-WSe2 lateral heterojunction with different numbers of layers prepared by the preparation method according to any one of claims 1 to 12; characterized in that: It includes WS2 nanosheets and WSe2 nanosheets grown laterally on its edges.

14. A lateral heterojunction of WS2-WSe2 with different numbers of layers prepared by the preparation method according to claim 13; characterized in that: The WS2 nanosheets are single-layer to four-layer nanosheets; the WSe2 nanosheets are single-layer or double-layer nanosheets.

15. A WS2-WSe2 lateral heterojunction with different numbers of layers prepared by the preparation method according to claim 14; characterized in that, The WS2-WSe2 lateral heterojunction with different numbers of layers is at least one of a single-layer WS2-single-layer WSe2 lateral heterojunction, a single-layer WS2-double-layer WSe2 lateral heterojunction, a double-layer WS2-single-layer WSe2 lateral heterojunction, and a double-layer WS2-double-layer WSe2 lateral heterojunction.

16. An application of a WS2-WSe2 lateral heterojunction with different numbers of layers prepared by the preparation method according to any one of claims 1 to 12, characterized in that: It is used to prepare optoelectronic devices.

17. The use according to claim 16, characterized in that The photoelectric device is at least one of a pn junction diode, a photovoltaic device, a photodetector, a light emitting diode, and a laser diode.

18. A photoelectric device, characterized in that: A WS2-WSe2 lateral heterojunction having different numbers of layers prepared by the preparation method according to any one of claims 1 to 12.

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