A method of forming a semiconductor device

Abstract

The application provides a semiconductor device forming method, which comprises the following steps: providing a semiconductor substrate, depositing a silicon dioxide layer, a polysilicon layer and a hard mask layer on the semiconductor substrate in sequence, and etching the hard mask layer, the polysilicon layer and the silicon dioxide layer in sequence to form a pseudo polysilicon gate; forming a side wall one and a side wall two on both sides of the laminated silicon dioxide layer, the pseudo polysilicon gate and the hard mask layer in sequence; forming a photoresist, opening the photoresist on the pseudo polysilicon gate and the side wall one and the side wall two through a photoetching process; removing the side wall two exposed by the photoresist through a wet removal process, so that the side wall one is exposed; removing the hard mask layer, and simultaneously removing the horn of the pseudo polysilicon gate where the side wall one is higher than the pseudo polysilicon gate. The wet removal process is added to remove the side wall two, so that the side wall one is exposed, and the side wall one is directly etched in the process of back-etching, thereby solving the problem that the horn is difficult to remove.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronic semiconductor manufacturing technology, in particular to a forming method of a semiconductor device. BACKGROUND

[0002] In a high-k / metal gate (HKMG) process such as 28nm HKMG, a high-k gate dielectric layer and a metal gate (MG) are simultaneously formed. In a post-metal gate process, a dummy poly gate (i.e. a polysilicon gate of a dummy gate structure) technology is usually used to form a dummy poly gate, a spacer on the sidewall of the dummy poly gate, a gate dielectric layer at the bottom of the dummy poly gate and the spacer, and source / drain regions on both sides of the dummy poly gate (a channel region is between the source / drain regions), as shown in FIG. 1. Then, the dummy poly gate is removed (DPR), and the removed area of the dummy poly gate is filled with a metal to form a metal gate. A hard mask layer (not shown) is usually formed on the polysilicon layer to perform corresponding photolithography and etching to form the dummy poly gate. Therefore, the spacer formed on the dummy poly gate covers the sidewall of the hard mask layer, which causes the top of the spacer to be higher than the dummy poly gate and forms a horn 401, as shown in FIG. 2. Figure 1 Figure 1 .

[0003] Ideally, the horn 401 can be completely removed in the process of removing the hard mask layer when the metal gate is replaced. However, due to the size and pattern density of the polysilicon, the photoresist (PR) loading on the polysilicon (poly) in different device regions is different. The horn in some large polysilicon regions or pattern density regions cannot be completely removed, which causes residue in the subsequent process, affects wafer acceptance test and chip probing. SUMMARY

[0004] The present application provides a forming method of a semiconductor device to solve the problem of difficult removal of the horn.

[0005] To solve the above technical problems, the present application provides a forming method of a semiconductor device, comprising:

[0006] ​A semiconductor substrate is provided, on which a silicon dioxide layer, a polysilicon layer and a hard mask layer are sequentially deposited, and the hard mask layer, the polysilicon layer and the silicon dioxide layer are sequentially etched to form a pseudo polysilicon gate;

[0007] A first side wall and a second side wall are sequentially formed on both sides of the laminated silicon dioxide layer, the pseudo polysilicon gate and the hard mask layer.

[0008] A photoresist is formed, and the photoresist on the pseudo polysilicon gate and the first and second side walls is opened by a photolithography process.

[0009] The second side wall exposed by the photoresist is removed by wet etching, and the first side wall is exposed.

[0010] The hard mask layer is removed, and the horn of the first side wall protruding from the pseudo polysilicon gate is also removed, so that the height of the pseudo polysilicon gate is flush with the top of the first side wall.

[0011] Preferably, the semiconductor substrate has a first device region and a second device region, the size of the pseudo polysilicon gate in the first device region is larger than that in the second device region; after the photoresist is formed, the photoresist on the pseudo polysilicon gate and the first and second side walls in the first device region is opened by the photolithography process, and the remaining photoresist masks the second device region; before the hard mask layer is removed, the photoresist is etched back to open the photoresist on the pseudo polysilicon gate and the first and second side walls in the second device region; and the hard mask layer is removed, and the horn of the first side wall in the first device region and the horn of the first side wall and the second side wall in the second device region are simultaneously removed.

[0012] Preferably, the semiconductor substrate in the first device region and the second device region is provided with a well region.

[0013] Preferably, the semiconductor substrate at the bottom of the well region is further provided with a deep well region, and the conduction type of the deep well region is opposite to that of the well region.

[0014] Preferably, the material of the first side wall includes carbon silicon nitride, and the second side wall includes silicon nitride.

[0015] Preferably, the cleaning agent used for wet etching the second side wall exposed by the photoresist includes phosphoric acid.

[0016] Preferably, the cleaning time of the wet etching is at least 200s.

[0017] Preferably, the hard mask layer includes a hard mask oxide layer and a hard mask nitride layer which are sequentially laminated on the top of the pseudo polysilicon gate, and the process of removing the hard mask layer includes:

[0018] Firstly, a first etching process is used to remove the hard mask oxide layer, and the hard mask oxide layer is removed at the same time, and the corresponding horn of the side wall one and the remaining side wall two are removed;

[0019] Then, a second etching process is used to remove the hard mask nitride layer.

[0020] Preferably, the material of the hard mask nitride layer comprises silicon nitride, and the hard mask oxide layer comprises silicon dioxide.

[0021] Preferably, after the hard mask layer is removed and the horn of the side wall one protruding from the pseudo polysilicon gate is removed, the method further comprises: removing the pseudo polysilicon gate and the silicon dioxide layer at the bottom of the pseudo polysilicon gate to form a gate trench; and depositing a high dielectric layer in the gate trench and filling a metal material to form a metal gate.

[0022] In the method for forming the semiconductor device, the side wall two is removed by adding a wet removal process, so that the side wall one is exposed, and then in the process of photoresist back etching, the side wall one can be directly etched, so that the height of the side wall one is flush with the pseudo polysilicon gate, thereby the problem that the horn is difficult to remove and causes residue in subsequent processes and reduces product yield can be solved.

[0023] Compared with the existing process for solving the horn problem, the thickness of the nickel silicide on the surface of the source and drain region is sacrificed, the method is simple, the risk is small, and the process has no other adverse effects, effectively reduces the difficulty of reducing the height of the horn in the PREB (Photo Resistance Etchback) process, improves the in-plane uniformity, reduces the difficulty of subsequent processes, expands the PREB process window, and is conducive to product mass production. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a structure schematic diagram after the hard mask layer is removed in the prior art;

[0025] Figure 2 is a flow chart in the method for forming the semiconductor device according to an embodiment of the present application;

[0026] Figure 3 is a device cross-sectional structure schematic diagram when the pseudo polysilicon gate is formed in the method for forming the semiconductor device according to an embodiment of the present application;

[0027] Figure 4 is a device cross-sectional structure schematic diagram when the side wall one and the side wall two are formed in the method for forming the semiconductor device according to an embodiment of the present application;

[0028] Figure 5This is a schematic diagram of a device cross-sectional structure in which the photoresist on the polysilicon gate, the first sidewall and the second sidewall is opened in a method for forming a semiconductor device according to an embodiment of the present invention;

[0029] Figure 6 1 is a schematic diagram of a cross-sectional structure of a semiconductor device after removing the second sidewall spacer in a method for forming the semiconductor device according to an embodiment of the present invention;

[0030] Figure 7 1 is a schematic diagram of a cross-sectional structure of a semiconductor device after removing a hard mask oxide layer in a method for forming the semiconductor device according to an embodiment of the present invention;

[0031] Figure 8 1 is a schematic diagram of a cross-sectional structure of a semiconductor device after the hard mask nitride layer is removed in a method for forming the semiconductor device according to an embodiment of the present invention;

[0032] Figure 9a It is the wafer defect map obtained under the current technology;

[0033] Figure 9b This is a wafer defect map obtained using the method provided by the present invention.

[0034] The structures corresponding to the numbers in the figure are as follows:

[0035] 1. Pseudo polysilicon gate; 2. Hard mask nitride layer; 3. Hard mask oxide layer; 4. Spacer 1; 401, horn; 5. Spacer 2; 6. Well region; 7. Deep well region; 8. Source region; 9. Drain region. DETAILED DESCRIPTION

[0036] The following is a further detailed description of the semiconductor device formation method proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0037] In the current gate-last process, after forming the pseudo-polysilicon gate, sidewalls, and source / drain regions and before replacing the metal gate, a metal silicide (e.g., nickel silicide, NiSi) is typically formed on the source / drain regions. Furthermore, when the metal gate needs to be replaced, the entire device surface is first covered with photoresist (PR) and photolithography is performed to expose the hard mask layer on top of the large-sized pseudo-polysilicon gate. The PR is then etched back (PREB) to expose the hard mask layer on top of the small-sized pseudo-polysilicon gate. The hard mask layer and the pseudo-polysilicon gate are then removed sequentially under the masking effect of the remaining photoresist to form a gate trench. The gate trench is then covered with a high-K dielectric layer and filled with a metal gate to complete the metal gate replacement.

[0038] If the horn problem needs to be solved, the thickness of the photoresist in the PREB is reduced to expose the horn to be removed, and the horn is removed when the hard mask layer is removed. Obviously, the thickness of the photoresist after the PREB is required to be high. If the thickness of the photoresist after the PREB is too low, the source and drain regions on the surface of the active area (AA) on both sides of the pseudo polysilicon gate (for example, embedded source and drain regions, the material is, for example, silicon germanium SiGe, etc.) are not protected by the PR, and even the entire AA is not protected by the PR, which finally causes damage to the metal silicide (for example, nickel silicide NiSi) on the surface of the source and drain regions for reducing the contact resistance or the source and drain regions themselves, affecting the performance of the device; if the thickness of the photoresist after the PREB is too large, the process window of the pattern sparse (ISO) region is insufficient, and the dry etching process for removing the hard mask layer produces residues (hard mask residues or pseudo polysilicon gate residues), which is not conducive to mass production. Therefore, in the current process, the lower limit of the PREB process window needs to ensure that the metal silicide on the surface of the source and drain regions is good, and the upper limit needs to ensure that the Horn of each device region (especially the pattern dense region) is small and there is no residue left.

[0039] Based on this, the core idea of the present application is to form at least two layers of side walls on the sidewall of the pseudo polysilicon gate 1, and before the current PREB process is performed, the outer side wall 5 is removed, so that the inner side wall is exposed, and the top of the exposed side wall is etched by wet etching, so that the height of the horn 401 can be reduced, the height of the pseudo polysilicon gate 1 is flush with the side wall 4, the process window of the PREB is expanded, and the horn 401 is avoided to leave residues in the subsequent process, affecting the yield.

[0040] Specifically, please refer to Figures 2-8 , which is a schematic diagram of an embodiment of the present application. A method for forming a semiconductor device includes the following steps:

[0041] First, a semiconductor substrate is provided, and a silicon dioxide layer (not labeled), a polysilicon layer for making a pseudo polysilicon gate 1, a hard mask nitride layer 2 and a hard mask oxide layer 3 are sequentially deposited on the semiconductor substrate, wherein the hard mask oxide layer 3 and the hard mask nitride layer 2 are stacked to form a hard mask layer;

[0042] Then, through photoresist coating, exposure and development processes, a patterned photoresist layer (not shown) capable of defining a pseudo polysilicon gate 1 pattern is formed, and the hard mask oxide layer 3 and the hard mask nitride layer 2 are etched with the patterned photoresist layer as a mask to form a patterned hard mask layer. After removing the patterned photoresist layer, the polysilicon layer and the silicon dioxide layer are etched in sequence with the patterned hard mask layer as a mask to form a pseudo polysilicon gate 1, as shown in Figure 3 ;

[0043] Afterwards, side wall one 4 and side wall two 5 are formed on both sides of the stacked silicon dioxide layer, the pseudo-polysilicon gate 1 and the hard mask layer, see Figure 4 wherein, as an example, the material of the side wall one 4 includes carbon-nitride-silicon, and the material of the side wall two 5 includes silicon-nitride;

[0044] Then, photoresist is formed, and the photoresist on the pseudo-polysilicon gate 1 and the side wall one 4 and the side wall two 5 is opened by a photolithography process, see Figure 5

[0045] Next, the side wall two 5 exposed by the photoresist is removed by wet method (which can also be referred to as wet cleaning), so that the side wall one 4 is exposed, see Figure 6 wherein, as an example, the cleaning agent used for removing the side wall two 5 exposed by the photoresist by wet method includes phosphoric acid, and the cleaning time of the wet method is at least 200s;

[0046] Afterwards, the hard mask layer is removed, and at the same time, the horn 401 of the side wall one 4 protruding from the pseudo-polysilicon gate 1 is removed, so that the height of the pseudo-polysilicon gate 1 is flush with the top of the side wall one 4, see Figure 8

[0047] It should be noted that, after the wet method is performed and before the hard mask layer is removed, the side wall two 5 is removed by cleaning with phosphoric acid, and the side wall one 4 is exposed, so that the side wall one 4 is directly contacted by the etching agent during the process of removing the hard mask layer by using the corresponding etching agent (such as etching gas or plasma, etc.), and is etched at the same time, and finally, the height of the horn 401 of the side wall one 4 is improved by at least 30% relative to the existing step of removing the hard mask layer, the in-plane uniformity is improved, and the process difficulty of PREB, Slim Spacer Wet RM (thinned spacer wet removal) and ILD0-CMP (interlayer dielectric polishing) on the subsequent metal gate is effectively reduced.

[0048] The technical solution of the present application, compared with the prior art, after opening the photoresist and before removing the hard mask layer, a step of removing the side wall two 5 by wet method (which can also be referred to as wet cleaning) to expose the horn 401 of the side wall one 4 is added. As an example, under the same conditions (wherein the present application and the prior art both have the side wall one 4 and the side wall two 5), as shown in Table 1 below, the technical solution of the present application only adds a wet cleaning step after opening the photoresist and before removing the hard mask layer relative to the prior art, and the final Horn Height (horn height) obtained is significantly lower than the Horn Height (horn height) obtained under the existing BSL (Back-side-illumination backside illumination process) ​​​

[0049]

[0050] Table 1 Horn Height before and after WET

[0051] Therefore, the technical scheme of the present application can effectively improve the defect condition due to the reduced height of the horn 401, and further realize defect free on the basis of PREB other conditions, thereby effectively expanding the PREB window, and being conducive to mass production.

[0052] In one embodiment, Figure 9a is a wafer defect map of the prior art (under the current BSL condition), Figure 9b is a wafer defect map after the process of adding wet removal of the side wall two 5 of the present application relative to the prior art, and the comparison Figure 9a and Figure 9b It can be clearly seen that under the condition of adding the wet removal process of the present application, the number of defects is reduced, and after Figure 9b It can also be seen that the wet removal process has no other adverse effects on the manufacturing process.

[0053] In one embodiment, the semiconductor substrate has a first device region and a second device region (not shown), and the size of the dummy poly-silicon gate 1 on the first device region is greater than the size of the dummy poly-silicon gate 1 on the second device region. The method of the present embodiment can open the photoresist on the dummy poly-silicon gate 1 and the side wall one 4 and the side wall two 5 of the first device region by a photoetch process after forming the photoresist, and the remaining photoresist masks the second device region; further, before removing the hard mask layer, the photoresist is etched back to open the photoresist on the dummy poly-silicon gate 1 and the side wall one 4 and the side wall two 5 of the second device region. Thus, the horn 401 of the side wall one 4 of the first device region and the horn 401 of the side wall one 4 and the side wall two 5 of the second device region are removed at the same time as the hard mask layer is removed.

[0054] In the above embodiment, a photolithography process is first performed to open the photoresist on the pseudo-polysilicon gate 1 and the sidewall 1 4 and the sidewall 2 5 in the first device region (not shown), that is, to open the photoresist on the large-sized pseudo-polysilicon gate 1, and a wet removal process is performed to remove the sidewall 2 5 on the sidewall of the large-sized pseudo-polysilicon gate 1. The large-sized pseudo-polysilicon gate 1 is usually the pseudo-polysilicon gate 1 located on the P-well (PW), and the pseudo-polysilicon gate 1 on the P-well has the same structure as the pseudo-polysilicon gate 1 located on the N-well. Then, a photoresist (PR) is etched back (etched back) to remove the pseudo-polysilicon gate 1. Back, EB) is the first etch back process EB1, which opens the photoresist on the pseudo polysilicon gate 1 and the sidewall 1 4 and the sidewall 2 5 in the second device area (not shown), that is, the photoresist on the small-sized pseudo polysilicon gate 1 is opened, thereby overcoming the photoresist loading on the large-sized polysilicon gate. At this time, all the pseudo polysilicon gates 1 have been opened; after that, the second etch back process EB2 is performed to remove the hard mask layer, the sidewall 1 and the remaining sidewall 2 5. Since the sidewall 2 5 of the large-sized pseudo polysilicon gate 1 is removed in the wet removal process, the height of the bull horn 401 structure on the outer periphery of the top of the large-sized pseudo polysilicon gate 1 is gradually reduced in the etch back process and finally removed.

[0055] Since the hard mask oxide layer 3 and the hard mask nitride layer 2 are stacked to form a hard mask layer, the process of removing the hard mask layer may optionally include:

[0056] First, the hard mask oxide layer 3 is removed by a first etching process, and while removing the hard mask oxide layer 3, the corresponding horns 401 of the sidewall 1 4 and the remaining sidewall 2 5 are removed. Figure 7 ;

[0057] Then, the hard mask nitride layer 2 is removed by a second etching process. Figure 8 .

[0058] Specifically, the material of the hard mask nitride layer 2 includes silicon nitride, and the material of the hard mask oxide layer 3 includes silicon dioxide.

[0059] After removing the hard mask layer and removing the corner 401 of the sidewall 4 that is higher than the pseudo polysilicon gate 1, the process also includes: removing the pseudo polysilicon gate 1 and the silicon dioxide layer at its bottom to form a gate groove; depositing a high dielectric layer in the gate groove and filling it with metal material to form a metal gate.

[0060] As one of the structures of the embodiment, the semiconductor substrate is a silicon substrate, the semiconductor substrate of the first device region and the second device region is provided with a well region 6, the semiconductor substrate at the bottom of the well region 6 is also optionally provided with a deep well region 8 to isolate noise, the conductive type of the deep well region 8 is opposite to that of the well region 6 of the first device region, for example, the well region 6 is a P well region, the deep well region 8 is a deep N well, further, the gate structure adjacent to the P well region can be set as an N well region, and the noise is isolated through the deep N well.

[0061] As can be seen from the above, in the forming method of the semiconductor device provided by the embodiment of the present application, the wet removal process is added before the photoresist re-etching process, the side wall two 5 is removed, the side wall one 4 is exposed, and then the side wall one 4 is directly etched in the photoresist re-etching process, the height of the horn 401 is reduced, the height of the side wall one 4 is flush with the pseudo polysilicon gate 1, and thus the problem that the horn 401 is difficult to remove, the subsequent process is left with residues, and the product yield is reduced can be solved.

[0062] The above description is only a description of the preferred embodiment of the present application, and does not limit the scope of the present application in any way, and any modification or modification of the present application by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: Providing a semiconductor substrate, depositing a silicon dioxide layer, a polysilicon layer and a hard mask layer in sequence on the semiconductor substrate, and etching the hard mask layer, the polysilicon layer and the silicon dioxide layer in sequence to form a pseudo polysilicon gate (1); Forming a side wall 1 (4) and a side wall 2 (5) in sequence on both sides of the stacked silicon dioxide layer, the pseudo polysilicon gate (1), and the hard mask layer; forming a photoresist, and opening the photoresist on the pseudo polysilicon gate (1) and the first sidewall (4) and the second sidewall (5) through a photolithography process; Wet-processing to remove the second sidewall (5) exposed by the photoresist, so that the first sidewall (4) is exposed; The hard mask layer is removed, and at the same time, the corners (401) of the sidewall (4) that are higher than the pseudo polysilicon gate (1) are removed, so that the height of the pseudo polysilicon gate (1) is flush with the top of the sidewall (4); wherein the semiconductor substrate has a first device region and a second device region, and the size of the pseudo polysilicon gate (1) on the first device region is larger than the size of the pseudo polysilicon gate (1) in the second device region; after forming the photoresist, the pseudo polysilicon gate (1) in the first device region is firstly formed by a photolithography process. and the photoresist on the sidewall 1 (4) and the sidewall 2 (5), and the remaining photoresist masks the second device region; before removing the hard mask layer, the photoresist is first etched back to open the pseudo polysilicon gate (1) and the photoresist on the sidewall 1 (4) and the sidewall 2 (5) in the second device region; while removing the hard mask layer, the horns (401) of the sidewall 1 (4) in the first device region and the horns (401) and the sidewall 2 (5) of the sidewall 1 (4) in the second device region are removed simultaneously; The hard mask layer comprises a hard mask oxide layer (3) and a hard mask nitride layer (2) sequentially stacked on top of the pseudo polysilicon gate (1), and the process of removing the hard mask layer comprises: First, the hard mask oxide layer (3) is removed by a first etching process, and while removing the hard mask oxide layer (3), the corresponding horns (401) of the first sidewall (4) and the remaining second sidewall (5) are removed; Then, a second etching process is used to remove the hard mask nitride layer (2).

2. The method for forming a semiconductor device according to claim 1, wherein: Well regions (6) are provided on the semiconductor substrates of the first device region and the second device region.

3. The method for forming a semiconductor device according to claim 2, wherein: A deep well region (8) is also provided in the semiconductor substrate at the bottom of the well region (6), and the conductivity type of the deep well region (8) is opposite to that of the well region (6).

4. The method for forming a semiconductor device according to claim 1, wherein: The material of the side wall 1 (4) includes silicon carbon nitride, and the material of the side wall 2 (5) includes silicon nitride.

5. The method for forming a semiconductor device according to claim 1, wherein: The cleaning agent used for wet removal of the sidewall 2 (5) exposed by the photoresist includes phosphoric acid.

6. The method for forming a semiconductor device according to claim 1, wherein: The cleaning time of the wet removal is at least 200 seconds.

7. The method for forming a semiconductor device according to claim 1, wherein: The material of the hard mask nitride layer (2) includes silicon nitride, and the material of the hard mask oxide layer (3) includes silicon dioxide.

8. The method for forming a semiconductor device according to claim 1, wherein: After removing the hard mask layer and removing the corner (401) of the sidewall (4) that is higher than the pseudo polysilicon gate (1), the method further includes: removing the pseudo polysilicon gate (1) and the silicon dioxide layer at its bottom to form a gate groove; depositing a high dielectric layer in the gate groove and filling it with metal material to form a metal gate.

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