Trench MOS structure and manufacturing method thereof

Abstract

The present application provides a Trench MOS structure and a method for manufacturing the same. First, the epitaxial layer is implanted with body to form an implantation region and annealed. Then, source ion implantation and annealing are performed in the implantation region to form a source. Then, the epitaxial layer is etched to form a groove, a gate oxide layer is grown in the groove, and polysilicon is filled in the groove. In this solution, body implantation and source ion implantation and annealing are performed first in the manufacturing process, and then trench manufacturing and polysilicon filling are performed. In this way, the high temperature of annealing after body implantation and source ion implantation can be effectively avoided to affect the polysilicon, thereby affecting the device performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a Trench MOS structure and a manufacturing method thereof. Background Art

[0002] Trench MOS is already a mature process in semiconductor technology. Trench MOS is a trench metal oxide field effect transistor with lower on-resistance Rdson and gate-drain charge density, which can achieve lower conduction and switching losses and faster switching speed. Trench MOS adopts the most advanced trench technology and chip layout, has the characteristics of strong impact resistance, high output efficiency and low cost, and can be used in various application fields with operating frequency less than 100kHz.

[0003] In the traditional Trench MOS process flow, Body implantation and source ion implantation and annealing are placed after trench fabrication and Poly filling. Since the annealing temperature of Poly is lower than that of Boby implantation and source ion implantation, in the traditional process flow, when annealing Boby and source ion implantation, Poly is exposed to the environment, and Poly is doped with heavy boron or phosphorus atoms, which can easily diffuse to the surface of the wafer and accumulate on the surface at a high temperature above 1000°C, and even diffuse to the surface of other wafers through the high temperature environment. The diffusion and accumulation of these impurities will affect the electrical properties of the final test of the wafer, such as leakage, on-resistance, etc. In addition, after Poly annealing, it undergoes two anneals after Body and source ion implantation, and the temperature gradient is too large, which will lead to increased thermal stress and serious wafer bending and deformation, thus affecting subsequent processes such as photolithography. Summary of the invention

[0004] The purpose of the present application includes, for example, providing a Trench MOS structure and a method for manufacturing the same, which can prevent the influence of high annealing temperature on device performance.

[0005] The embodiments of the present application can be implemented as follows:

[0006] In a first aspect, the present application provides a method for manufacturing a Trench MOS structure, the method comprising:

[0007] forming an epitaxial layer on one side of a provided substrate;

[0008] Performing body implantation on the epitaxial layer to form an implantation region, and performing annealing treatment;

[0009] Performing source ion implantation and annealing treatment in the implantation region of the epitaxial layer to form a source;

[0010] Etching the epitaxial layer to form a groove, wherein the groove is located between the source electrodes;

[0011] A gate oxide layer is grown in the trench and polysilicon is filled in the trench.

[0012] In an optional embodiment, the step of performing source ion implantation and annealing treatment in the implantation region in the epitaxial layer to form a source comprises:

[0013] forming a photoresist layer on a side of the epitaxial layer away from the substrate;

[0014] Performing photolithography on the photoresist layer to expose a portion of the epitaxial layer;

[0015] Performing source ion implantation based on the exposed epitaxial layer, and performing annealing at a temperature of 1000° C. to 1200° C. to form a source;

[0016] Remove the remaining photoresist layer.

[0017] In an optional embodiment, the step of etching the epitaxial layer and the substrate to form a groove includes:

[0018] forming a hard mask layer on a side of the epitaxial layer away from the substrate;

[0019] Performing photolithography on the hard mask layer to define an etching area on the epitaxial layer where a groove needs to be formed;

[0020] The epitaxial layer is etched based on the etched area to form a trench.

[0021] In an optional embodiment, the method further comprises:

[0022] BPSG is deposited over the hard mask layer and the polysilicon.

[0023] In an optional embodiment, the method further comprises:

[0024] After the polysilicon is filled in the trench, an annealing treatment is performed at a temperature of 800° C. to 1000° C.;

[0025] Etch back or chemical mechanical polishing is used to make the filled polysilicon layer flush with the hard mask layer.

[0026] In an optional embodiment, the depth of the groove is 0.3um to 8um.

[0027] In an optional embodiment, the hard mask layer has a thickness of 2000 Å to 5000 Å.

[0028] In a second aspect, the present application provides a Trench MOS structure, which is obtained by using the manufacturing method described in any one of the aforementioned embodiments, and the Trench MOS structure includes:

[0029] substrate;

[0030] An epitaxial layer formed on one side of the substrate, wherein the epitaxial layer has an implantation region formed by body implantation and annealing, and the implantation region has a source formed by source ion implantation and annealing;

[0031] The epitaxial layer has a groove formed by etching, and the groove is located between the source electrodes;

[0032] A gate oxide layer is grown in the trench, and polysilicon is filled in the trench.

[0033] In an optional embodiment, a hard mask layer is formed on a surface of the epitaxial layer except the trench.

[0034] In an optional embodiment, BPSG is deposited on the hard mask layer and the polysilicon.

[0035] The beneficial effects of the embodiments of the present application include, for example:

[0036] The present application provides a Trench MOS structure and a method for manufacturing the same. First, the epitaxial layer is implanted with body to form an implantation region and annealed. Then, source ion implantation and annealing are performed in the implantation region to form a source. Then, the epitaxial layer is etched to form a groove, a gate oxide layer is grown in the groove, and polysilicon is filled in the groove. In this solution, body implantation and source ion implantation and annealing are performed first in the manufacturing process, and then trench manufacturing and polysilicon filling are performed. In this way, the high temperature of annealing after body implantation and source ion implantation can be effectively avoided to affect the polysilicon, thereby affecting the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1(a) to Figure 1(k) The device structure diagram formed by each step in the process flow of traditional Trench MOS;

[0039] Figure 2A flowchart of a method for manufacturing a Trench MOS structure provided in an embodiment of the present application;

[0040] Figures 3 to 12 A diagram of a device structure formed in each step of the method for manufacturing a Trench MOS structure provided in an embodiment of the present application.

[0041] Icon: 10 - substrate; 20 - epitaxial layer; 21 - implantation region; 30 - photoresist layer; 40 - source; 50 - hard mask layer; 60 - trench; 70 - gate oxide layer; 80 - polysilicon; 90 - BPSG. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0044] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0045] In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, or are the orientation or position relationship in which the product of the application is usually placed when used. This is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0046] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0047] In the traditional Trench MOS process, body implantation and source ion implantation and annealing are usually performed after the trench is made and filled with polysilicon. Figure 1(a) to Figure 1(k) As shown, in the conventional process flow of the prior art, the steps are as follows: Figure 1(a) to Figure 1(k) The process is shown in the diagrams. It includes the production of hard mask layer - photolithography of hard mask layer - trench production - removal of hard mask layer - growth of gate oxide layer in trench - filling of polysilicon in trench - body implantation and annealing in epitaxial layer - photolithography based on photoresist layer - source ion implantation and annealing - TEOS deposition in epitaxial layer - BPSG deposition. On this basis, the conventional process flow is carried out in the later stage.

[0048] It can be seen that in the existing process flow, trench production and polysilicon filling are performed before body and source ion implantation and annealing. The high temperature of annealing after body and source ion implantation will cause the boron or phosphorus atoms doped in the polysilicon to diffuse to the wafer surface and accumulate on the surface, thereby affecting the performance of wafer testing. In addition, polysilicon will undergo multiple high-temperature annealings, which can easily cause the wafer to bend and deform.

[0049] Based on the above research findings, the present application provides a method for manufacturing a Trench MOS structure. During the manufacturing process, Body and source ion implantation and annealing are first performed, and then trench fabrication and polysilicon filling are performed, thereby avoiding the impact of high temperature annealing after Body implantation and source ion implantation on polysilicon.

[0050] First embodiment

[0051] See also Figure 2 , is a flow chart of a method for manufacturing a Trench MOS structure provided in an embodiment of the present application. The method for manufacturing a Trench MOS structure in an embodiment of the present application comprises the following steps:

[0052] S101, forming an epitaxial layer 20 on one side of the provided substrate 10, see Figure 3 .

[0053] S102, body implantation is performed on the epitaxial layer 20 to form an implantation region 21, and annealing is performed. Figure 4 .

[0054] S103, performing source ion implantation and annealing treatment on the implantation region 21 in the epitaxial layer 20 to form a source 40, please refer to Figure 5-Figure 6 .

[0055] S104, etching the epitaxial layer 20 to form a groove 60, wherein the groove 60 is located between the source electrodes 40, please refer to Figure 7-Figure 9 .

[0056] S105, growing a gate oxide layer 70 in the trench 60, and filling the trench 60 with polysilicon 80, please refer to Figure 10-11 .

[0057] See also Figure 3 In this embodiment, an epitaxial layer 20 can be grown on the provided substrate 10 using an epitaxial device. The substrate 10 mainly supports and improves the characteristics of the epitaxial layer 20. The epitaxial layer 20 grows on the substrate 10. The material properties of the substrate 10 and the surface shape of the substrate 10 have a great influence on the characteristics of the epitaxial layer 20. In this embodiment, the surface of the substrate 10 needs to have ultra-high flatness, and the epitaxial layer 20 can be an N-type epitaxial layer 20.

[0058] See also Figure 4 Body implantation can be performed in the N-type epitaxial layer 20 to form an implantation region 21. The body implantation can be P-type ion implantation. The implantation can be performed in a single implantation or multiple implantations. The implantation energy can be 50ekV to 100ekV, so that different implantation depths can be achieved.

[0059] After the body is implanted, an annealing process is performed. The annealing temperature after the body implantation can be 1000°C-1200°C. On this basis, the source ion implantation can be performed.

[0060] In this embodiment, the source ion implantation can be performed in the following manner:

[0061] A photoresist layer 30 is formed on the side of the epitaxial layer 20 away from the substrate 10. The photoresist layer 30 is photolithographically processed to expose a portion of the epitaxial layer 20. Figure 5 .

[0062] In this embodiment, a positive photoresist layer 30 or a negative photoresist layer 30 can be formed on the epitaxial layer 20. When a positive photoresist layer 30 is used, after exposure and development, the exposed portion of the photoresist layer 30 is dissolved, and the unexposed portion is retained. When a negative photoresist layer 30 is used, after exposure and development, the exposed portion is retained, and the unexposed portion is dissolved.

[0063] After a portion of the photoresist layer 30 is dissolved, a portion of the epitaxial layer 20 is exposed, and the exposed portion of the epitaxial layer 20 is the region where source ion implantation is required.

[0064] See also Figure 6 , source ion implantation is performed based on the exposed epitaxial layer 20 , and annealing is performed at a temperature of 1000° C. to 1200° C. to form a source 40 , and the residual photoresist layer 30 is removed.

[0065] In this embodiment, the source ion implantation may be an N-type implantation, and the source ions may be As ions, P ions, etc. The implantation energy of the source ion implantation may be 50ekV-100ekV. After the source ion implantation, an annealing treatment is performed, and the annealing treatment temperature is 1000° C.-1200° C. Thereafter, the residual photoresist layer 30 may be removed by wet removal or dry removal.

[0066] For example, the wafer with the photoresist layer 30 can be immersed in an organic solvent to dissolve or decompose the residual photoresist layer 30, thereby removing the photoresist on the surface of the wafer. Alternatively, the residual photoresist layer 30 can be removed by plasma oxidation or decomposition.

[0067] In this embodiment, it can be seen from the above that the annealing temperature after the body implantation and the source ion implantation is between 1000° C. and 1200° C., and the annealing temperatures after the two implantation operations are both relatively high.

[0068] On the basis of the above, the trench 60 is fabricated and the polysilicon 80 is filled. In this embodiment, the trench 60 is fabricated in the following manner:

[0069] See also Figure 7 , a hard mask layer 50 is formed on a side of the epitaxial layer 20 away from the substrate 10 .

[0070] In this embodiment, low pressure chemical vapor deposition can be used to form a hard mask layer 50 on the epitaxial layer 20. The hard mask layer 50 is an inorganic thin film material, and its main components are usually TiN, SiN, SiO2, etc. In this embodiment, the hard mask layer 50 can be made of SiO2. The hard mask layer 50 is mainly used in multiple photolithography processes, by transferring multiple photoresist patterns to the hard mask layer 50, and then transferring the final pattern to the lower layer through the hard mask layer 50.

[0071] In this embodiment, the thickness of the hard mask layer 50 is 2000 Å to 5000 Å.

[0072] See also Figure 8 , the hard mask layer 50 is photolithographically processed to define an etching area on the epitaxial layer 20 where a trench 60 is to be formed.

[0073] In this embodiment, the width of the trench 60 to be etched is defined by photolithography on the hard mask layer 50. The etched region defined on the epitaxial layer 20 may be located between the source electrodes 40 at both ends.

[0074] See also Fig. 9 , the epitaxial layer 20 is etched based on the etched area to form a trench 60 .

[0075] In this embodiment, when the epitaxial layer 20 is etched based on the etching area, the hard mask layer 50 can be used as a protective layer to protect the epitaxial layer 20 except the etching area. When the epitaxial layer 20 at the defined etching area is etched, the hard mask layer 50 will also be affected by the etching, so the thickness of the hard mask layer 50 is also reduced.

[0076] In this embodiment, the depth of the trench 60 formed by etching is 0.3 um to 8 um, and the trench 60 extends from the epitaxial layer 20 toward the substrate 10 .

[0077] In the prior art, body implantation and source 40 ion implantation are performed after the trench 60 is made. The hard mask layer 50 is only used for the trench 60 and needs to be removed later. This increases the process steps and cannot be used as part of the product.

[0078] In this embodiment, after the body implantation and the source ion implantation, the trench 60 is fabricated, and the hard mask layer 50 does not need to be removed after the trench 60 is fabricated, and can be directly used as a barrier layer under the BPSG 90. In this way, two process steps are omitted, the product manufacturing cycle is shortened, and the product manufacturing cost is reduced.

[0079] Based on the above, please refer to Fig.10 In this embodiment, a gate oxide layer 70 is grown on the sidewalls of the trench 60 and the bottom of the trench 60. The thickness of the gate oxide layer 70 may be 500A-5000A, and the growth temperature of the gate oxide layer 70 may be 900°C-1100°C.

[0080] See also Fig.11 After the gate oxide layer 70 is grown in the trench 60, polysilicon 80 may be filled in the trench 60. On this basis, the following steps may also be included:

[0081] After the polysilicon 80 is filled in the trench 60 , an annealing process is performed at a temperature of 800° C. to 1000° C., and etching back or chemical mechanical polishing is performed to make the filled polysilicon 80 flush with the hard mask layer 50 .

[0082] As can be seen from the above, in this embodiment, the annealing temperature after the body implantation and source ion implantation is relatively high, which is higher than the annealing temperature after the filling of the polysilicon 80. The body implantation and source ion implantation and annealing treatment are performed before the trench 60 is made and the polysilicon 80 is filled, which can effectively avoid the influence of the high temperature of the annealing after the body implantation and source ion implantation on the polysilicon 80, thereby avoiding the influence on the device performance.

[0083] In this embodiment, based on the above, the manufacturing method further includes the following steps:

[0084] See also Fig.12 BPSG 90 is deposited on the hard mask layer 50 and the polysilicon 80. BPSG 90 is silicon dioxide containing boron ions. BPSG 90 can be deposited by chemical vapor deposition, and the thickness of BPSG 90 can be 2000A-10000A.

[0085] The pre-grown hard mask layer 50 can serve as a barrier layer for the BPSG 90 to prevent the boron ions in the BPSG 90 from diffusing into the epitaxial layer 20 .

[0086] Based on the above process flow, subsequent conventional process flows may be performed, for example, including the production of contact holes, metal wiring, and passivation layer production.

[0087] The manufacturing method of the Trench MOS structure provided in this embodiment places the Body implantation and source ion implantation and annealing before the manufacturing of the trench 60 and the filling of the polysilicon 80, which can avoid the problem that the polysilicon 80 diffuses to the wafer surface due to the high temperature of the annealing after the Body implantation and source ion implantation, thereby affecting the electrical performance of the wafer. In addition, the manufacturing of the trench 60 is placed after the implantation operation, and the hard mask layer 50 formed in the manufacturing of the trench 60 does not need to be removed and can be directly used as a barrier layer for the subsequent BPSG90, thus shortening the product manufacturing cycle and reducing the product manufacturing cost.

[0088] Second embodiment

[0089] The embodiment of the present application further provides a Trench MOS structure, which can be obtained by a manufacturing method of any one of the implementation modes in the above embodiments.

[0090] Please refer again Fig.12 The Trench MOS structure includes a substrate 10 and an epitaxial layer 20 formed on one side of the substrate 10. The epitaxial layer 20 may be an N-type epitaxial layer 20.

[0091] The epitaxial layer 20 has an implantation region 21 formed by body implantation and annealing. The implantation region 21 may be formed by P-type ion implantation.

[0092] In this embodiment, a source 40 formed by source ion implantation and annealing is provided in the implantation region 21. The source ion implantation may be an N-type implantation, and the source ions may be As ions, P ions, and the like.

[0093] A trench 60 is formed by etching in the epitaxial layer 20 , and the trench 60 is located between the source electrodes 40 . In this embodiment, the depth of the trench 60 is 0.3 um to 8 um, and the trench 60 extends from the epitaxial layer 20 toward the substrate 10 .

[0094] A gate oxide layer 70 is grown in the trench 60, and the trench 60 is filled with polysilicon 80. In this embodiment, the gate oxide layer 70 is formed on the sidewall and bottom of the trench 60, and the thickness of the gate oxide layer 70 may be 500A-5000A.

[0095] In this embodiment, a hard mask layer 50 is formed on the surface of the epitaxial layer 20 except the groove 60. The hard mask layer 50 may be SiO2. The thickness of the hard mask layer 50 may be 2000A to 5000A. BPSG90 is deposited on the hard mask layer 50 and the polysilicon 80. BPSG90 is silicon dioxide containing boron ions. BPSG90 may be deposited by chemical vapor deposition. The thickness of BPSG90 may be 2000A-10000A.

[0096] It should be noted that, in addition to the above parts, the Trench MOS structure may also have other parts. This embodiment only describes the parts that need to be protected. Other levels and structures of the Trench MOS structure can refer to the existing conventional settings, which will not be described in detail in this embodiment.

[0097] For details of the Trench MOS structure not described in this embodiment, please refer to the corresponding description in the above embodiment, and this embodiment will not be described in detail here.

[0098] In summary, the Trench MOS structure and its manufacturing method provided in the embodiment of the present application first perform Body implantation on the epitaxial layer 20 to form the implantation region 21 and perform annealing, and then perform source ion implantation and annealing in the implantation region 21 to form the source 40. Thereafter, the epitaxial layer 20 is etched to form the trench 60, a gate oxide layer 70 is grown in the trench 60, and polysilicon 80 is filled in the trench 60. In this solution, during the manufacturing process, Body implantation and source ion implantation and annealing are performed first, and then the trench 60 is manufactured and filled with polysilicon 80. In this way, the high temperature of annealing after Body implantation and source ion implantation can be effectively avoided to affect the polysilicon 80, thereby affecting the device performance.

[0099] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for manufacturing a Trench MOS structure, characterized in that: The method comprises: forming an epitaxial layer on one side of a provided substrate; Performing body implantation on the epitaxial layer to form an implantation region, and performing annealing treatment; Performing source ion implantation and annealing treatment in the implantation region of the epitaxial layer to form a source; Etching the epitaxial layer to form a groove, wherein the groove is located between the source electrodes; Growing a gate oxide layer in the trench and filling the trench with polysilicon; The step of etching the epitaxial layer to form a groove comprises: Forming a hard mask layer on a side of the epitaxial layer away from the substrate; performing photolithography on the hard mask layer to define an etching area on the epitaxial layer where a groove is to be formed; etching the epitaxial layer based on the etching area to form a groove; The method further comprises: BPSG is deposited above the hard mask layer and the polysilicon, wherein the hard mask layer does not need to be removed after the trench is formed and is directly used as a barrier layer under the BPSG.

2. The method for manufacturing a Trench MOS structure according to claim 1, characterized in that: The step of performing source ion implantation and annealing treatment in the implantation region of the epitaxial layer to form a source comprises: forming a photoresist layer on a side of the epitaxial layer away from the substrate; Performing photolithography on the photoresist layer to expose a portion of the epitaxial layer; Performing source ion implantation based on the exposed epitaxial layer, and performing annealing at a temperature of 1000° C. to 1200° C. to form a source; Remove the remaining photoresist layer.

3. The method for manufacturing a Trench MOS structure according to claim 1, characterized in that: The method further comprises: After the polysilicon is filled in the trench, an annealing treatment is performed at a temperature of 800° C. to 1000° C.; Etch back or chemical mechanical polishing is used to make the filled polysilicon layer flush with the hard mask layer.

4. The method for manufacturing a Trench MOS structure according to claim 1, wherein: The depth of the groove is 0.3um to 8um.

5. The method for manufacturing a Trench MOS structure according to claim 1, characterized in that: The thickness of the hard mask layer is to 6. A Trench MOS structure, characterized in that: The Trench MOS structure is obtained by adopting the manufacturing method according to any one of claims 1 to 5, wherein the Trench MOS structure comprises: substrate; An epitaxial layer formed on one side of the substrate, wherein the epitaxial layer has an implantation region formed by body implantation and annealing, and the implantation region has a source formed by source ion implantation and annealing; The epitaxial layer has a groove formed by etching, and the groove is located between the source electrodes; A gate oxide layer is grown in the trench, and polysilicon is filled in the trench; A hard mask layer is formed on the surface of the epitaxial layer except the trench; BPSG is deposited on the hard mask layer and the polysilicon.

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