Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to semiconductor structures and methods of forming the same. One method includes forming a semiconductor fin that protrudes above a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method also includes forming a gate stack on sidewalls and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. A process gas used to grow the semiconductor region does not have both an n-type dopant-containing gas and a p-type dopant-containing gas. A source / drain region is grown in the upper portion of the trench, where the source / drain region includes p-type or n-type dopants.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures and methods for forming them. Background Technology

[0002] In the fabrication of integrated circuits, forming deep source / drain regions for transistors reduces channel resistance, thereby improving transistor performance. However, the formation of deep source / drain regions can lead to an increase in leakage current. Summary of the Invention

[0003] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a semiconductor fin protruding above a top surface of an isolation region, wherein the semiconductor fin overlaps with a semiconductor strip and the semiconductor strip contacts the isolation region; forming a gate stack on the sidewalls and top surface of a first portion of the semiconductor fin; etching the semiconductor fin and the semiconductor strip to form a trench, wherein the trench includes an upper portion in the semiconductor fin and a lower portion in the semiconductor strip; growing a semiconductor region in the lower portion of the trench, wherein the process gas for growing the semiconductor region does not contain either an n-type dopant gas or a p-type dopant gas; and growing a source / drain region in the upper portion of the trench, wherein the source / drain region includes either a p-type or an n-type dopant.

[0004] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a semiconductor fin protruding above a top surface of an isolation region; forming a gate stack on the semiconductor fin; etching the semiconductor fin to form a trench, wherein the trench further extends into a semiconductor strip below the semiconductor fin and extends into a well region; growing a semiconductor region in the lower portion of the trench, wherein the top surface of the semiconductor region is flush with or below the bottom of the semiconductor fin, and a first dopant concentration of the semiconductor region is lower than a second dopant concentration of the well region, and wherein the first dopant concentration and the second dopant concentration are dopant concentrations of n-type and p-type dopant; and growing a source / drain region above the semiconductor region.

[0005] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a well region in a semiconductor substrate; forming an isolation region extending into the well region; recessing the isolation region, wherein a portion of the well region protrudes above the isolation region to form a semiconductor fin, and a portion of the well region is located between the isolation regions as a semiconductor strip; growing a semiconductor region in the semiconductor strip, wherein a process gas for growing the semiconductor region does not have both p-type and n-type dopants; and forming a source / drain region on the semiconductor region, wherein the semiconductor region has a first doping concentration lower than a second doping concentration of the well region and a third doping concentration of the source / drain region. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figures 1-4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10 , Figure 11A , Figure 11B , Figure 12 , Figure 13A and Figure 13B A cross-sectional view is shown of an intermediate stage in the formation of a fin field-effect transistor (FinFET) according to some embodiments.

[0008] Figure 14 A process flow for forming a FinFET is shown according to some embodiments. Detailed Implementation

[0009] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0010] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0011] A fin field-effect transistor (FinFET) and a method for forming the same are provided. According to some embodiments of this disclosure, a semiconductor fin (on which a gate stack is formed) is etched to form a trench. The trench extends deep into a semiconductor strip beneath the semiconductor fin, such that the trench has more vertical sidewalls in the upper portion of the semiconductor fin and is closer to the channel region of the FinFET. A semiconductor region (undoped or unintentionally doped) is epitaxially grown at the bottom of the trench. The top surface of the semiconductor region may be flush with (within process variations) or slightly below the bottom of the semiconductor fin. Doped source / drain regions are then epitaxially grown on the semiconductor region. By forming semiconductor regions with zero or low doping concentrations, leakage current between adjacent source / drain regions is reduced. The embodiments discussed herein are intended to provide examples enabling the manufacture or use of the subject matter of this disclosure, and modifications that can be made (while remaining within the intended scope of the different embodiments) will be readily understood by those skilled in the art. Similar reference numerals are used to indicate similar elements throughout the various views and illustrative embodiments. While method embodiments may be discussed as being executed in a particular order, other method embodiments may be executed in any logical order.

[0012] Figures 1-4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10 , Figure 11A , Figure 11B , Figure 12 , Figure 13A and Figure 13B A cross-sectional view of an intermediate stage in the formation of a FinFET according to some embodiments of the present disclosure is shown. The corresponding process is also schematically reflected in... Figure 14 The process flow shown in the figure.

[0013] refer to Figure 1 A substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., using p-type or n-type dopants) or undoped. The semiconductor substrate 20 can be part of a wafer 10 (e.g., a silicon wafer). Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; compound semiconductors, including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. According to some embodiments, the substrate 20 is doped with p-type or n-type dopants. The concentration of p-type (or n-type) dopant (which can be intentionally or unintentionally doped) can be around 1E17 / cm³. 3 And about 1E18 / cm 3 Within the range between. According to some embodiments, the top surface of the semiconductor substrate 20 is on the (100) surface plane of the crystalline semiconductor substrate 20.

[0014] Further reference Figure 1 A well region 22 is formed in the substrate 20. The corresponding process is shown as follows. Figure 14Process 202 is shown in the process flow 200. According to some embodiments of this disclosure, the well region 22 is a p-type well region formed by implanting p-type impurities (which may be boron, indium, etc.) into the substrate 20. According to other embodiments of this disclosure, the well region 22 is an n-type well region formed by implanting n-type impurities (which may be phosphorus, arsenic, antimony, etc.) into the substrate 20. The resulting well region 22 can extend to the top surface of the substrate 20. The concentration of n-type or p-type impurities in the well region 22 can be equal to or less than 1E18 / cm³. 3 For example, at approximately 1E18 / cm 3 And approximately 1E19 / cm 3 Within the range between.

[0015] refer to Figure 2 The isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 may optionally be referred to as a shallow trench isolation (STI) region. The corresponding process is shown as follows. Figure 14 Process 204 is shown in the process flow 200. The portion of substrate 20 between adjacent STI regions 24 is referred to as semiconductor strip 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of this disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, wherein the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of this disclosure, the hard mask layer 30 is formed from silicon nitride, for example using atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc. A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. Then, a patterned photoresist is used as an etching mask to pattern the hard mask layer 30 to form a shape such as Figure 2 The hard mask 30 shown.

[0016] Next, the patterned hard mask layer 30 is used as an etching mask to etch the pad oxide layer 28 and the substrate 20, and then the resulting trenches in the substrate 20 are filled with one or more dielectric materials. A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, is performed to remove excess portions of the dielectric material, and the remaining portions of the dielectric material are STI regions 24. STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, etc., formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). STI regions 24 may also include dielectric material located above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, etc. According to some embodiments, the dielectric material located above the liner dielectric may include silicon oxide.

[0017] Semiconductor strip 26 is located between adjacent STI regions 24. According to some embodiments of this disclosure, semiconductor strip 26 is a portion of the original substrate 20 and well region 22, and therefore the material of semiconductor strip 26 is the same as that of substrate 20. According to alternative embodiments of this disclosure, semiconductor strip 26 is a replacement strip formed by etching the portion of substrate 20 located between STI regions 24 to form a groove, and performing epitaxy to regrow another semiconductor material in the groove. Therefore, semiconductor strip 26 is formed of a semiconductor material different from the semiconductor material of substrate 20. According to some embodiments, semiconductor strip 26 is formed of silicon-germanium, silicon-carbon, or group III-V compound semiconductor materials.

[0018] refer to Figure 3 The STI region 24 is recessed, causing the top of the semiconductor strip 26 to protrude above the top surface 24TS of the remaining portion of the STI region 24, forming a protruding fin 36. The corresponding process is shown as follows. Figure 14 Process 206 in process flow 200 shown in the diagram. Etching can be performed using a dry etching process, where, for example, HF and NH3 are used as etching gases. Plasma can be generated during the etching process. Argon gas may also be included. According to an alternative embodiment of this disclosure, a wet etching process is used to perform the recessing of the STI region 24. Etching chemicals may include, for example, diluted HF.

[0019] In the above embodiments, the fins can be patterned using any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fins. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0020] refer to Figure 4 The dummy gate stack 38 is formed to extend on the top surface and sidewalls of the (protruding) fin 36. The corresponding process is shown as follows. Figure 14 Process 208 in process flow 200 shown in the figure. Gate stack 38 may include dummy gate dielectric 40 ( Figure 7A The dummy gate stack 38 comprises a dummy gate electrode 42 located above the dummy gate dielectric 40. The dummy gate electrode 42 may be formed, for example, using polysilicon, and may also use other materials (e.g., amorphous silicon or amorphous carbon). Each dummy gate stack 38 may also include one (or more) hard mask layers 44 located above the dummy gate electrode 42. The hard mask layer 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 38 may intersect with one or more protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a length direction perpendicular to the length direction of the protruding fins 36.

[0021] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. The corresponding process is shown as follows. Figure 14 Process 208 in process flow 200 is shown in the diagram. According to some embodiments of this disclosure, the gate spacer 46 is formed of one or more dielectric materials (e.g., silicon nitride, silicon carbonitride, silicon oxycarbonitride, etc.) and may have a single-layer structure or a multi-layer structure (including multiple dielectric layers). Simultaneously with the formation of the gate spacer 46, fin spacers (not shown) may also be formed on the sidewalls of the protruding fins 36.

[0022] According to some embodiments, an implantation process is performed to form source / drain extension regions 51. Figure 5BThe implantation process may include a tilted implantation process, such that the source / drain extension region 51 extends into the region directly beneath the gate spacer 46 and is located on the opposite side of the channel region 53 of the resulting FinFET. The source / drain extension region 51 has the same conductivity type (p-type or n-type) as the subsequently formed source / drain region 60, and has a lower doping concentration compared to the subsequently formed source / drain region 60. According to some embodiments, the source / drain extension region 51 has a doping concentration below approximately 1E19 / cm². 3 The p-type or n-type doping concentration, for example, at approximately 5E17 / cm². 3 And approximately 1E19 / cm 3 Within the range between. According to an alternative embodiment, the source / drain extension region 51 can be formed in a later process, for example, after the epitaxial process used to form the epitaxial region 60.

[0023] Then an etching process is performed to etch the portion of the protruding fin 36 that is not covered by the dummy gate stack 38 and the gate spacer 46, thereby producing Figure 5A and Figure 5B The structure is shown. The corresponding process is shown as follows. Figure 14 Process 210 in process flow 200 is shown. The levels of the top surface 24TS and the bottom surface 24BS are shown. The recess can be anisotropic, and thus the portion of fin 36 located directly below the dummy gate stack 38 and the gate spacer 46 is protected from etching. According to some embodiments, the top surface of the recessed semiconductor strip 26 can be lower than the top surface 24TS of the STI region 24 and higher than the bottom surface 24BS of the STI region 24. This forms a trench 50. Trench 50 includes portions located on opposite sides of the dummy gate stack 38 and portions located between the remaining portions of the protruding fin 36. Etching can include a dry etching process, which can be performed using process gases (e.g., mixtures of C2F6, CF4, SO2, HF and ozone, mixtures of HBr, Cl2 and O2, mixtures of HBr, Cl2, O2 and CF2, etc.). Etching can be anisotropic.

[0024] refer to Figure 5B (It shows) Figure 5AReferring to the reference cross section 5B-5B, the trench 50 is a deep trench having a bottom 50BOT below the top surface 24TS of the STI region 24. Since the top surface 24TS of the STI region 24 is also at the same level as the bottom of the protruding fin 36, the trench 50 extends to a level below the bottom of the protruding fin 36. According to some embodiments, the depth D1 (which is the depth measured from the bottom of the protruding fin 36 to the bottom of the trench 50) can be greater than about 2 nm, and can be in the range between about 2 nm and about 4 nm. According to some embodiments, the sidewalls 50SW of the trench 50 have a straight and vertical upper portion. Near the bottom of the trench 50, the lower portion of the sidewalls 50SW begins to taper and bend, thus forming a U-shaped or V-shaped bottom (with curved sidewalls and bottom).

[0025] According to some embodiments, the vertical and straight upper portion of the sidewall 50SW extends horizontally to the bottom of the protruding fin 36, and this vertical and straight sidewall is composed of... Figure 5B The dashed line 50SW' indicates this. According to some embodiments, the connection point between the vertical and straight upper sidewall and the curved lower sidewall is located at the top surface level 24TS (which is also the bottom level of the protruding fin 36). According to an alternative embodiment, the curved sidewall portion begins at a level higher than the top surface level 24TS, such as... Figure 5B As shown. Forming a deep trench 50 ensures that the sidewalls 50SW, in significant portions or entirely within the protruding fin 36, are vertical and straight. The bottom proximity S1 (the lateral distance from the channel region 53 of the (derived FinFET) to the nearest source / drain region 60) is small. In contrast, if the trench 50 were formed as a shallow trench (e.g., with the bottom at the same level as the bottom of the protruding fin 36), the bottom proximity would increase to S2 (which is greater than S1). Because proximity S1 or S2 is located in regions with low doping concentrations (source / drain extension regions 51), these regions have higher resistance. Therefore, forming a deep trench 50 reduces the channel resistance and the resistance between the source and drain regions, thereby improving the performance of the resulting FinFET.

[0026] However, extending trench 50 deep into semiconductor strip 26 may cause adjacent source / drain regions 60 ( Figure 13A The leakage current between them is undesirably increased. According to some embodiments, a semiconductor region 56 is formed that is undoped, unintentionally doped, or intentionally doped with a low n-type or p-type doping concentration, such as... Figure 6A , Figure 6B or Figure 6C As shown.

[0027] According to some embodiments, the semiconductor region 56 is formed using a selective epitaxial process. Selective epitaxial processing is also a bottom-up deposition process. The corresponding process is shown as follows: Figure 14Process 212 in process flow 200 is shown in the diagram. Semiconductor region 56 may include silicon (without Ge, C, etc.), SiGe, carbon-doped silicon (SiC), etc. For example, when the resulting FinFET is an n-type FinFET, semiconductor region 56 may include silicon or carbon-doped silicon. When the resulting FinFET is a p-type FinFET, semiconductor region 56 may include silicon, SiGe, or germanium.

[0028] Deposition can be performed using methods such as reduced pressure chemical vapor deposition (RPCVD) and PECVD. The process gas used to deposit the semiconductor region 56 may include silicon-containing gases, such as silane, dichlorosilane (Si₂H₆), and dichlorosilane (DCS). If the resulting semiconductor region 56 is to include germanium, a germanium-containing gas (e.g., germanane (GeH₄), dichlorosilane (Ge₂H₆), etc.) may be used or added to the silicon-containing gas. An etching gas (e.g., HCl) may be added to the process gas to achieve selective deposition on the semiconductor rather than the dielectric. One or more carrier gases (e.g., H₂ and / or N₂) may also be included in the process gas. Bottom-up deposition can be achieved by adjusting process conditions (e.g., the flow rate ratio of the process gases). For example, the ratio of the flow rate of one or more Si / Ge-containing gases to the flow rate of the etching gas can be adjusted. The growth rate of the semiconductor region 56 varies on different surface planes. For example, growth on the (100) surface (which is the surface of the semiconductor strip 26 at the bottom of the trench 50) is faster than growth on the (110) surface (the sidewall surfaces of the substrate 20 and the protruding fins 36). An appropriate flow rate ratio ensures that the semiconductor grown on the (110) surface is etched and completely removed, while the semiconductor grown on the (100) surface is partially etched. The end result is that semiconductor regions are grown on the (100) surface (the top surface of the semiconductor at the bottom of the trench 50), and not on the (110) surface (the sidewall surfaces in the trench 50). Therefore, growth is bottom-up.

[0029] According to some embodiments, the process gas used to form semiconductor region 56 does not contain either an n-type dopant gas or a p-type dopant gas. Therefore, the resulting semiconductor region 56 can be intrinsic. There may or may not be residues in the processing chamber used to grow semiconductor region 56. Depending on the material previously grown in the processing chamber and whether / how the processing chamber is cleaned, residues may include p-type dopant (e.g., boron and / or indium), and / or n-type dopant (e.g., phosphorus, arsenic, antimony, etc.). Other dopants (e.g., oxygen (O)) may also remain in the processing chamber. These residues are doped into semiconductor region 56. In these embodiments, because these dopants are not intended to be doped into semiconductor region 56, these dopants are referred to as unintentionally doped. Unintentionally doped dopants can be p-type or n-type, regardless of the subsequently grown source / drain regions 60 ( Figure 7A Is it p-type or n-type? According to some embodiments, the concentration of unintentionally doped dopant can be below about 1E18 / cm³. 3 Below approximately 1E17 / cm 3 Below approximately 1E16 / cm 3 Below approximately 1E15 / cm 3 Or approximately 1E17 / cm 3 And about 1E18 / cm 3 Any value within the range between. The deposited semiconductor region 56 may also be free of unintentional dopants and therefore intrinsic.

[0030] According to an alternative embodiment, during epitaxy, semiconductor region 56 is intentionally doped in situ to the same conductivity type as the overlying source / drain region 60. In-situ doping is performed by guiding a dopant-containing process gas into the processing chamber. For example, when source / drain region 60 is p-type, boron and / or indium can be doped into semiconductor region 56. When source / drain region 60 is n-type, phosphorus, arsenic, and / or antimony can be doped into semiconductor region 56. For example, semiconductor region 56 can be intentionally doped to a conductivity below about 1E17 / cm. 3 The dopant concentration can also be lower than about 1E16 / cm. 3 1E15 / cm 3 Or approximately 1E14 / cm 3 .

[0031] According to an alternative embodiment, during epitaxy, semiconductor region 56 is intentionally de-doped in situ to have a conductivity type opposite to that of the overlying source / drain region 60. Therefore, the dopant is of the same conductivity type as well region 22. In-situ doping is performed by guiding a dopant-containing process gas. For example, when source / drain region 60 is n-type, boron and / or indium can be de-doped into semiconductor region 56. When source / drain region 60 is p-type, phosphorus, arsenic, and / or antimony can be de-doped into semiconductor region 56. For example, semiconductor region 56 can be intentionally doped to below about 1E17 / cm². 3 The dopant concentration can also be lower than about 1E16 / cm. 3 1E15 / cm 3 Or approximately 1E14 / cm 3 .

[0032] When semiconductor region 56 is intentionally doped, the doping concentration can be controlled (by reducing the flow rate of the dopant-containing process gas) to be lower than that of all well regions 22 (and therefore channel region 53), source / drain extension region 51, and source / drain region 60. Figure 7A The doping concentration in the semiconductor region 56 can be adjusted. For example, the doping concentration in the (deposited) semiconductor region 56 can be in-situ doped to be at least one or two orders of magnitude lower than the doping concentration in the well region 22, the source / drain extension region 51, and the source / drain region 60. The intentionally doped dopant can have a concentration on the same order of magnitude as that of the original semiconductor substrate 20 (before the doped well region 22).

[0033] Figure 6A The outline of a semiconductor region 56 according to some embodiments is shown, wherein the top surface of the semiconductor region 56 is flat or substantially flat, for example, with a height variation of less than about 1 nm or less than about 1 nm. The top surface of semiconductor region 56 can also be at the same level as the bottom of the protruding fin 36 (within process variations), for example, with a height difference of less than about 1 nm or less than about 1 nm. The top surface of semiconductor region 56 may also be slightly lower than the bottom of protruding fin 36 (within process variations), for example, the height difference is in the range of about 1 nm to about 2 nm. Figure 6B The outline of a semiconductor region 56 according to an alternative embodiment is shown, wherein the top surface of the semiconductor region 56 is concave. The apex corner of the semiconductor region 56 may be at the same level as the bottom of the protruding fin 36. Figure 6C The outline of a semiconductor region 56 according to another alternative embodiment is shown, wherein a thin layer of the semiconductor region 56 is grown on the sidewalls of the protruding fin 36, for example, due to incomplete etching of the semiconductor region 56 relative to the sidewalls of the protruding fin 36. The thickness of the sidewall portion can be less than about 1 nm.

[0034] The top surface of semiconductor region 56 can be flush with the bottom of the protruding fin 36 to achieve both increased current and reduced leakage. If the top of semiconductor region 56 is higher than the bottom of the protruding fin 36, then the subsequently formed source / drain region 60 ( Figure 7A The bottom of the fin does not extend to the bottom of the protruding fin, and therefore the bottom portion of the channel region will not be effectively utilized, resulting in a decrease in the saturation current of the FinFET. If the top of the semiconductor region 56 is lower than the bottom of the protruding fin 36, the leakage current will increase.

[0035] Next, refer to Figure 7A and Figure 7B Epitaxial regions (source / drain regions) 60 are formed by selectively growing semiconductor material in trench 50. The corresponding process is shown as follows. Figure 14 Process 214 in the process flow 200 shown in the figure. Figure 7B A perspective view is shown, and Figure 7A It shows Figure 7B Reference cross sections 7A-7A are shown in the figure. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type dopants can be doped in situ as epitaxy progresses. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) or silicon boron (SiB) can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphide (SiP) or silicon carbon phosphide (SiCP) can be grown. According to an alternative embodiment of this disclosure, the epitaxial region 60 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiples thereof. After the trench 50 is filled with the epitaxial region 60, further epitaxial growth of the epitaxial region 60 causes the epitaxial region 60 to extend horizontally and can form a facet. Further growth of the epitaxial region 60 may also cause adjacent epitaxial regions 60 to fuse together. Voids (air gaps) 61 may be generated.

[0036] According to some embodiments, the source / drain region 60 includes multiple sub-layers, which are referred to as 60A, 60B, and 60C. Figure 7ASublayers 60A, 60B, and 60C can have different compositions from each other. For example, the germanium or carbon (if present) in sublayers 60A, 60B, and 60C can be different from each other. The n-type dopant in sublayers 60A, 60B, and 60C (when the corresponding FinFET is an n-type FinFET) can have different concentrations from each other. The p-type dopant in sublayers 60A, 60B, and 60C (when the corresponding FinFET is a p-type FinFET) can have different concentrations from each other. For example, when the source / drain region 60 is an n-type region, sublayer 60A can include SiAs, while sublayers 60B and 60C can include SiP. When the source / drain region 60 is an n-type region, sublayer 60B can also have a higher concentration of n-type dopant than the n-type dopant in sublayers 60A and 60C. Conversely, when the source / drain region 60 is a p-type region, sublayer 60B may also have a higher p-type dopant content than sublayers 60A and 60C. According to some embodiments, the source / drain region 60 has a p-type dopant content of approximately 5E2O / cm². 3 And about 5E21 / cm 3 The n-type or p-type dopant concentration is within the range between [specific values]. According to some embodiments, after epitaxy of the source / drain region 60, no implantation process is performed to implant n-type or p-type dopant, so that the doping concentration in the semiconductor region 56 remains low.

[0037] Figure 8A and Figure 8B A perspective view of the structure after the formation of the contact etch stop layer (CESL) 62 and the interlayer dielectric (ILD) 64 is shown. The corresponding process is illustrated as follows. Figure 14 Process 216 in the process flow 200 shown in the figure. Figure 8B A perspective view is shown, and Figure 8A It shows Figure 8B Reference cross section 8A-8A is shown in the figure. CESL 62 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 64 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition processes. ILD 64 can be formed from an oxygen-containing dielectric material, which can be a silicon oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process (e.g., CMP or mechanical polishing) can be performed to make the top surfaces of ILD 64, dummy gate stack 38, and gate spacer 46 flush with each other.

[0038] Next, the dummy gate stack 38, including the hard mask layer 44, the dummy gate electrode 42, and the dummy gate dielectric 40, is etched to form trenches 66 between the gate spacers 46, such as Figure 9A and Figure 9B As shown. The corresponding process is shown as follows. Figure 14 Process 218 in process flow 200 shown in the diagram. The top surface and sidewalls of the protruding fin 36 are exposed to the groove 66. Figure 9B A perspective view is shown, and Figure 9A It shows Figure 9B Reference cross section 9A-9A in the diagram.

[0039] Next, as Figure 10 As shown, in trench 66 ( Figure 9A and Figure 9B A replacement gate stack 84 is formed in the process. The corresponding process is shown as follows. Figure 14 Process 220 is shown in process flow 200. The replacement gate stack 84 includes a gate dielectric 72 and a corresponding gate electrode 82. According to some embodiments of this disclosure, the gate dielectric 72 includes an interface layer (IL) 68 as its lower portion, such as… Figure 10 As shown. IL 68 is formed on the exposed surface of the protruding fin 36. IL 68 may include an oxide layer (e.g., a silicon oxide layer) formed by a thermal oxidation, chemical oxidation, or deposition process on the protruding fin 36. The gate dielectric 72 may also include a high-k dielectric layer 70 deposited on IL 68. The high-k dielectric layer 70 includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9 and may be greater than about 7.0 or higher. The high-k dielectric layer 70 is formed as a conformal layer and extends on the sidewalls of the protruding fin 36 and the top surface and sidewalls of the gate spacer 46. According to some embodiments of this disclosure, the high-k dielectric layer 70 is formed using ALD, CVD, PECVD, molecular beam deposition (MBD), etc.

[0040] Further reference Figure 10 A gate electrode 82 is formed on a gate dielectric 72. The gate electrode 82 may include a plurality of stacked layers 74, 76, and 78 (which may be formed as conformal layers) and a fill metal region 80 (which fills the remaining portions of the trenches not filled by the plurality of stacked layers 74, 76, and 78). Each of the plurality of stacked layers 74, 76, and 78 may have a basin shape, including a bottom and sidewall portions (the sidewall portions forming a ring and engaging with the bottom). A brief fabrication process for the gate stack 84 is discussed below. It should be understood that the layers discussed are examples, and different layer schemes may be employed.

[0041] According to some embodiments, an adhesion layer (which is also a diffusion barrier layer) 74 is formed on the high-k dielectric layer 70. The adhesion layer 74 may be formed of TiN or titanium silicon nitride (TiSiN), or may include TiN or TiSiN. The TiN layer may be formed using ALD or CVD, and the TiSiN layer may comprise alternating deposited TiN and SiN layers, which may be formed, for example, using ALD. Because the TiN and SiN layers are very thin, these layers may not be distinguishable from each other, and are therefore referred to as TiSiN layers.

[0042] A work function layer 76 is formed on the adhesion layer 74. The work function layer 76 defines the work function of the gate and includes at least one layer, or multiple layers formed of different materials. The material of the work function layer 76 is selected depending on whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer 76 may include TiC, TaC, TiAl, TiAlC, Ti, Al, Sc, Y, Er, La, Hf, their alloys, and / or multiple layers thereof. When the FinFET is a p-type FinFET, the work function layer 76 may include TiN, TaN, TiAlN, TiSiN, WCN, MOCN, Pt, Pd, Ni, Au, their alloys, and / or multiple layers thereof.

[0043] According to some embodiments of this disclosure, a capping layer 78 is formed on the work function layer 76. According to some embodiments, the capping layer 78 may be formed of TiN, and other materials (e.g., TaN) may also be used. According to some embodiments, the capping layer 78 is formed using ALD, CVD, or the like.

[0044] A fill metal region 80 is also formed above the cap layer 78. According to some embodiments, the fill metal region 80 is formed of tungsten, cobalt, aluminum, or alloys thereof, and can be formed using CVD, electroplating, etc. According to some embodiments, WF6, WCl5, WCl6, SiH4, H2, or combinations thereof can be used as process gases for tungsten deposition. After forming the fill metal region 80, a planarization process can be performed to remove excess portions of the deposited layers, including the high-k dielectric layer 70, stacked layers 74, 76, and 78, and the fill metal region 80. The remaining portions of these layers are the gate stack 84, such as... Figure 10 As shown.

[0045] refer to Figure 11A The gate stack 84 is recessed to form a trench (the space occupied by the hard mask 86). The etching process may include a wet etching process, a dry etching process, or a wet etching process and a dry etching process. The hard mask 86 is formed to fill the trench. The corresponding process is shown as follows. Figure 14 Process 222 in the process flow 200 shown in the figure. Figure 11Aand Figure 11B Cross-sectional views and perspective views are shown respectively, in which Figure 11A It shows Figure 11B Reference cross sections 11A-11A are shown in the figure. According to some embodiments of this disclosure, forming the hard mask 86 includes a deposition process for forming a blanket dielectric material and a planarization process for removing excess dielectric material over the gate spacer 46 and ILD 64. The hard mask 86 may be formed from, for example, silicon nitride, silicon oxynitride, silicon carbide nitride, or other similar dielectric materials.

[0046] Figure 12 The formation of the lower source / drain contact plug 88 and the source / drain silicide region 90 is shown. The corresponding process is illustrated as follows. Figure 14 Process 224 in process flow 200 shown in the diagram. According to some embodiments of this disclosure, the formation process includes: etching ILD 64 and CESL 62 to form source / drain contact openings, depositing a metal layer (e.g., a titanium layer, a cobalt layer, etc.) extending into the source / drain contact openings, depositing a barrier layer (e.g., a titanium nitride layer), and performing an annealing process such that the bottom portion of the metal layer reacts with the source / drain region 60 to form a silicide region 90. The barrier layer and the remaining sidewall portions of the metal layer may be removed or not removed. Another barrier layer (e.g., a titanium nitride layer) may be deposited. The remaining source / drain contact openings may be filled with a metallization material, such as cobalt, tungsten, other suitable metals, or alloys thereof. Planarization (e.g., a CMP process or a mechanical polishing process) is then performed to remove excess material and to flush the top surface of the contact plug 88 with the top surface of ILD 64.

[0047] Figure 13A and Figure 13B The formation of an etch stop layer (ESL) 92 and a dielectric layer 94 (which may also be an ILD) above the ESL 92 is shown. The corresponding process is illustrated as follows. Figure 14 Process 226 in process flow 200 shown in the diagram. ESL 92 may be formed from or include the following: silicon nitride, silicon carbonitride, silicon carbide, carbon nitride, aluminum oxide, aluminum nitride, etc., or multiple layers thereof. Dielectric layer 94 may be formed from or include the following: silicon dioxide, low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOC, spin-coated glass, spin-coated polymer, etc. ESL 92 and dielectric layer 94 may be deposited using spin coating, CVD, ALD, LPCVD, PECVD, etc.

[0048] Then, gate contact plug 96 and upper source / drain contact plug 98 are formed. The corresponding process is shown as follows. Figure 14Process 228 in process flow 200 shown in the diagram. The formation process may include: etching dielectric layer 94 and ESL 92 to form an opening until the gate electrode 82 and source / drain contact plug 88 are exposed, filling (one or more) conductive layers to fill the opening, and performing a planarization process to remove excess portions of the conductive layers. Thus, FinFET 102 is formed.

[0049] According to some embodiments, the proximity S1 is reduced at the bottom of the protruding fin 36, for example, the proximity S1 can be in the range of about 6 nm and about 12 nm. As mentioned above, the proximity S1 is reduced by forming a deeper trench. However, a deeper trench may increase the leakage current between adjacent source / drain regions. According to embodiments of this disclosure, the semiconductor region 56 is formed without p / n doping or with low p / n doping to reduce leakage current. A discussion of how the semiconductor region 56 can reduce leakage is provided below. The discussion is provided using an n-type FinFET as an example. It should be understood that this discussion can also be applied to p-type FinFETs.

[0050] The source / drain region 60 of the n-type FinFET is n-type, and the well region 22 of the n-type FinFET is p-type. The semiconductor region 56 can be n-type or p-type due to unintentional doping, intentional doping, or intentional dedoping. The semiconductor region 56 can also be intrinsic, without p-type or n-type doping. The n-type dopant in the source / drain region 60 and the p-type dopant in the well region 22 can diffuse into the semiconductor region 56. Therefore, when the semiconductor region 56 is an intrinsic region or an n-type region during epitaxy, the portion of the semiconductor region 56 near the corresponding overlying source / drain region 60 is n-type, and the portion of the semiconductor region 56 near the well region 22 is p-type. A depletion region is formed at the interface between the n-type and p-type portions. When the semiconductor region 56 is dedoped to p-type, a depletion region is formed at the interface between the n-type source / drain region 60 and the p-type semiconductor region 56.

[0051] Due to the lower dopant concentration in semiconductor region 56, the depletion region is wider than in a conventional FinFET (where semiconductor region 56 is not formed and source / drain regions 60 contact well region 22). Therefore, leakage current is reduced.

[0052] The embodiments of this disclosure have several advantageous features. By forming trenches deeper into the semiconductor strip (which are used to form the source / drain regions), the curved bottom of the opening extends to a lower position, and the proximity (the distance from the source / drain region to the corresponding channel region) is reduced. However, forming deeper trenches can increase leakage current. According to embodiments of this disclosure, the bottom portion of the trench is filled with a semiconductor region (which is undoped or doped (unintentionally and / or intentionally) with a low doping concentration). The resulting depletion region has increased width, and the undesirable increase in leakage current is reduced.

[0053] According to some embodiments of this disclosure, a method includes: forming a semiconductor fin protruding above a top surface of an isolation region, wherein the semiconductor fin overlaps with a semiconductor strip and the semiconductor strip contacts the isolation region; forming a gate stack on the sidewalls and top surface of a first portion of the semiconductor fin; etching the semiconductor fin and the semiconductor strip to form a trench, wherein the trench includes an upper portion in the semiconductor fin and a lower portion in the semiconductor strip; growing a semiconductor region in the lower portion of the trench, wherein the process gas used to grow the semiconductor region does not contain either an n-type dopant gas or a p-type dopant gas; and growing a source / drain region in the upper portion of the trench, wherein the source / drain region includes either a p-type or an n-type dopant. In embodiments, the top surface of the semiconductor region is flush with the bottom surface of the semiconductor fin. In embodiments, the semiconductor region is grown using a bottom-up deposition process. In embodiments, the lower portion of the trench has a depth in the range of about 2 nm to about 4 nm. In embodiments, the semiconductor region is doped to have a first conductivity type opposite to a second conductivity type of the source / drain region. In one embodiment, the semiconductor region is doped to have the same conductivity type as the source / drain regions. In another embodiment, the semiconductor fin has a first sidewall facing the upper part of the trench, and the semiconductor strip has a second sidewall facing the lower part of the trench; the first sidewall is vertical and straight, and the second sidewall is curved. In another embodiment, the first and second sidewalls are joined at a location flush with or below the bottom of the semiconductor fin. In another embodiment, the semiconductor region is grown to have a flat top surface. In another embodiment, the semiconductor region is grown to have a concave top surface. In another embodiment, during the growth of the semiconductor region, the semiconductor region remains exposed above the trench.

[0054] According to some embodiments of this disclosure, a method includes: forming a semiconductor fin protruding above a top surface of an isolation region; forming a gate stack on the semiconductor fin; etching the semiconductor fin to form a trench, wherein the trench further extends into a semiconductor strip below the semiconductor fin and into a well region; growing a semiconductor region in the lower portion of the trench, wherein the top surface of the semiconductor region is flush with or below the bottom of the semiconductor fin, and a first dopant concentration of the semiconductor region is lower than a second dopant concentration of the well region, and wherein the first and second dopant concentrations are dopant concentrations of n-type and p-type dopants; and growing a source / drain region above the semiconductor region. In embodiments, the semiconductor region is an intrinsic region. In embodiments, the growth of the semiconductor region is performed using a process gas that does not contain n-type and p-type dopants. In embodiments, the growth of the semiconductor region is performed using a process gas that includes either n-type or p-type dopants. In embodiments, the semiconductor region and the source / drain region have opposite conductivity types. In one embodiment, the method further includes forming a source / drain extension region in a semiconductor fin, wherein the concentration of the first dopant is also lower than the concentration of the third dopant in the source / drain extension region.

[0055] According to some embodiments of this disclosure, a method includes: forming a well region in a semiconductor substrate; forming an isolation region extending into the well region; recessing the isolation region, wherein a portion of the well region protrudes above the isolation region to form a semiconductor fin, and a portion of the well region lies between the isolation regions as a semiconductor strip; growing a semiconductor region in the semiconductor strip, wherein a process gas for growing the semiconductor region does not contain either p-type or n-type dopants; and forming a source / drain region on top of the semiconductor region, wherein the semiconductor region has a first doping concentration lower than a second doping concentration of the well region and a third doping concentration of the source / drain region. In embodiments, the semiconductor region is doped with a p-type or n-type residue left in the processing chamber for growing the semiconductor region to have a first doping concentration. In embodiments, the interface between the semiconductor region and the source / drain region is at the same level as the top surface of the isolation region.

[0056] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0057] Example 1. A method comprising:

[0058] A semiconductor fin is formed that protrudes above the top surface of the isolation region, wherein the semiconductor fin overlaps with a semiconductor strip and the semiconductor strip contacts the isolation region;

[0059] A gate stack is formed on the sidewall and top surface of the first portion of the semiconductor fin;

[0060] The semiconductor fin and the semiconductor strip are etched to form a trench, wherein the trench includes an upper portion in the semiconductor fin and a lower portion in the semiconductor strip;

[0061] A semiconductor region is grown in the lower part of the trench, wherein the process gas used to grow the semiconductor region does not contain either an n-type dopant gas or a p-type dopant gas; and

[0062] A source / drain region is grown in the upper part of the trench, wherein the source / drain region includes p-type or n-type dopants.

[0063] Example 2. The method according to Example 1, wherein the top surface of the semiconductor region is flush with the bottom surface of the semiconductor fin.

[0064] Example 3. The method according to Example 1, wherein the semiconductor region is grown using a bottom-up deposition process.

[0065] Example 4. The method according to Example 1, wherein the lower portion of the trench has a depth in the range of about 2 nm and about 4 nm.

[0066] Example 5. The method according to Example 1, wherein the semiconductor region is doped to have a first conductivity type opposite to the second conductivity type of the source / drain region.

[0067] Example 6. The method according to Example 1, wherein the semiconductor region is doped to have the same conductivity type as the source / drain region.

[0068] Example 7. The method according to Example 1, wherein the semiconductor fin has a first sidewall facing the upper part of the trench, and the semiconductor strip has a second sidewall facing the lower part of the trench, and the first sidewall is vertical and straight, and the second sidewall is curved.

[0069] Example 8. The method according to Example 7, wherein the first sidewall and the second sidewall are joined at a position flush with or below the bottom of the semiconductor fin.

[0070] Example 9. The method according to Example 1, wherein the semiconductor region is grown to have a flat top surface.

[0071] Example 10. The method according to Example 1, wherein the semiconductor region is grown to have a concave top surface.

[0072] Example 11. The method according to Example 1, wherein, during the growth of the semiconductor region, the semiconductor region remains exposed above the trench.

[0073] Example 12. A method comprising:

[0074] Semiconductor fins are formed that protrude above the top surface of the isolation region;

[0075] A gate stack is formed on the semiconductor fin;

[0076] The semiconductor fin is etched to form a trench, wherein the trench further extends into the semiconductor strip beneath the semiconductor fin and extends into the well region;

[0077] A semiconductor region is grown in the lower part of the trench, wherein the top surface of the semiconductor region is flush with or lower than the bottom of the semiconductor fin, and the first dopant concentration of the semiconductor region is lower than the second dopant concentration of the well region, wherein the first dopant concentration and the second dopant concentration are dopant concentrations of n-type and p-type dopant, respectively; and

[0078] Source / drain regions are grown on the semiconductor region.

[0079] Example 13. The method according to Example 12, wherein the semiconductor region is an intrinsic region.

[0080] Example 14. The method according to Example 12, wherein the growth of the semiconductor region is performed using a process gas that does not contain process gases with n-type and p-type dopants.

[0081] Example 15. The method according to Example 12, wherein the growth of the semiconductor region is performed using a process gas comprising a process gas containing n-type or p-type dopants.

[0082] Example 16. The method according to Example 15, wherein the semiconductor region and the source / drain region have opposite conductivity types.

[0083] Example 17. The method according to Example 16 further includes: forming a source / drain extension region in the semiconductor fin, wherein the first dopant concentration is also lower than the third dopant concentration in the source / drain extension region.

[0084] Example 18. A method comprising:

[0085] A well region is formed in the semiconductor substrate;

[0086] Forming an isolation region that extends into the trap region;

[0087] The isolation region is recessed, wherein a portion of the well region protrudes above the isolation region to form a semiconductor fin, and a portion of the well region is located between the isolation regions as a semiconductor strip;

[0088] A semiconductor region is grown in the semiconductor strip, wherein the process gas used to grow the semiconductor region does not contain either p-type or n-type dopants; and

[0089] A source / drain region is formed on the semiconductor region, wherein the semiconductor region has a first doping concentration that is lower than the second doping concentration of the well region and the third doping concentration of the source / drain region.

[0090] Example 19. The method according to Example 18, wherein the semiconductor region is doped with a p-type residue or an n-type residue remaining in the processing chamber for growing the semiconductor region to have the first doping concentration.

[0091] Example 20. The method according to Example 18, wherein the interface between the semiconductor region and the source / drain region is at the same level as the top surface of the isolation region.

Claims

1. A method for forming a semiconductor structure, comprising: A semiconductor fin is formed that protrudes above the top surface of the isolation region, wherein the semiconductor fin overlaps with a semiconductor strip and the semiconductor strip contacts the isolation region; A gate stack is formed on the sidewall and top surface of the first portion of the semiconductor fin; A source / drain extension region is formed in the semiconductor fin; The semiconductor fin and the semiconductor strip are etched to form a trench, wherein the trench includes an upper portion in the semiconductor fin and a lower portion in the semiconductor strip, and the trench extends into the well region; A semiconductor region is grown in the lower part of the trench, wherein the process gas used to grow the semiconductor region does not contain either an n-type dopant gas or a p-type dopant gas; and A source / drain region is grown in the upper part of the trench, wherein the source / drain region includes p-type or n-type dopant, wherein the semiconductor region is doped to have a conductivity type opposite to or the same as that of the source / drain region, and the doping concentration in the semiconductor region is doped to be at least one order of magnitude lower than that in the well region, the source / drain extension region, and the source / drain region.

2. The method according to claim 1, wherein, The top surface of the semiconductor region is flush with the bottom surface of the semiconductor fin.

3. The method according to claim 1, wherein, The semiconductor region is grown using a bottom-up deposition process.

4. The method according to claim 1, wherein, The lower part of the trench has a depth in the range of about 2 nm to about 4 nm.

5. The method according to claim 1, wherein, The semiconductor fin has a first sidewall facing the upper part of the trench, and the semiconductor strip has a second sidewall facing the lower part of the trench, wherein the first sidewall is vertical and straight, and the second sidewall is curved.

6. The method according to claim 5, wherein, The first sidewall and the second sidewall are joined at a position flush with or below the bottom of the semiconductor fin.

7. The method according to claim 1, wherein, The semiconductor region is grown to have a flat top surface.

8. The method according to claim 1, wherein, The semiconductor region is grown to have a concave top surface.

9. The method according to claim 1, wherein, During the growth of the semiconductor region, the semiconductor region remains exposed above the trench.

10. A method for forming a semiconductor structure, comprising: Semiconductor fins are formed that protrude above the top surface of the isolation region; A gate stack is formed on the semiconductor fin; A source / drain extension region is formed in the semiconductor fin; The semiconductor fin is etched to form a trench, wherein the trench further extends into the semiconductor strip beneath the semiconductor fin and extends into the well region; A semiconductor region is grown in the lower part of the trench, wherein the top surface of the semiconductor region is flush with or lower than the bottom of the semiconductor fin; and A source / drain region is grown on the semiconductor region, wherein the semiconductor region is doped to have a conductivity type that is opposite to or the same as that of the source / drain region, and the doping concentration in the semiconductor region is doped to be at least one order of magnitude lower than that in the well region, the source / drain extension region, and the source / drain region.

11. The method according to claim 10, wherein, The semiconductor region is an intrinsic region.

12. The method according to claim 10, wherein, The growth of the semiconductor region is performed using a process gas that does not contain process gases with n-type and p-type dopants.

13. The method according to claim 10, wherein, The growth of the semiconductor region is performed using a process gas that includes a process gas containing n-type or p-type dopants.

14. A method for forming a semiconductor structure, comprising: A well region is formed in the semiconductor substrate; Forming an isolation region that extends into the trap region; The isolation region is recessed, wherein a portion of the well region protrudes above the isolation region to form a semiconductor fin, and a portion of the well region is located between the isolation regions as a semiconductor strip; A source / drain extension region is formed in the semiconductor fin; A semiconductor region is grown in the semiconductor strip, wherein the process gas used to grow the semiconductor region does not contain either p-type or n-type dopants; and A source / drain region is formed on the semiconductor region, wherein the semiconductor region has a first doping concentration that is lower than the second doping concentration of the well region and the third doping concentration of the source / drain region, the semiconductor region is doped to have a conductivity type that is opposite to or the same as the conductivity type of the source / drain region, and the first doping concentration of the semiconductor region is doped to be at least one order of magnitude lower than the doping concentration of the well region, the source / drain extension region and the source / drain region.

15. The method according to claim 14, wherein, The semiconductor region is doped with a p-type or n-type residue left in the processing chamber for growing the semiconductor region to have the first doping concentration.

16. The method of claim 14, wherein, The interface between the semiconductor region and the source / drain region is at the same level as the top surface of the isolation region.

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