Semiconductor Package

Abstract

A semiconductor package is obtained that can improve heat dissipation and ensure insulation resistance. A plurality of semiconductor chips (1a to 1f, 2a to 2f) are respectively arranged on a plurality of chip pads (3a to 3d). A plurality of lead terminals (6a to 6f) are respectively connected to the plurality of semiconductor chips (1a to 1f, 2a to 2f). The package (7) encapsulates the plurality of chip pads (3a to 3d), the plurality of semiconductor chips (1a to 1f, 2a to 2f) and the plurality of lead terminals (6a to 6f). The plurality of chip pads (3a to 3d) and the plurality of lead terminals (6a to 6f) are exposed from the lower surface of the package (7). On the lower surface of the package (7), grooves (8) are provided between adjacent chip pads (3a to 3d) and between adjacent lead terminals (6a to 6f).

Description

Technical Field

[0001] The present invention relates to semiconductor packages. Background Art

[0002] A non-insulating surface mount module in which a die pad of a semiconductor chip is exposed on the lower surface of a package has been used (for example, refer to Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 11-103003

[0004] In the case of conventional packages, in order to ensure the insulation distance between the lead terminal and the chip pad, the inner end of the lead terminal is not exposed from the lower surface of the package. Therefore, the lead terminal is not in contact with the heat sink, so that the heat generated by the lead terminal when current flows is dissipated into the atmosphere. Therefore, if the current continues to increase, the temperature of the lead terminal exceeds the allowable value, which becomes an obstacle to the increase in the current density of the module. In addition, if multiple adjacent lead terminals are exposed from the lower surface of the package, the insulation distance between the exposed lead terminals cannot be ensured. In addition, in the case of a 6-in-1 package with multiple chip pads, the insulation distance between the exposed chip pads cannot be ensured. Therefore, there is a problem that the required insulation tolerance cannot be ensured. Summary of the invention

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor package capable of improving heat dissipation and ensuring insulation resistance.

[0006] The semiconductor package involved in the present invention is characterized in that it has: a plurality of chip pads; a plurality of semiconductor chips, which are respectively arranged on the plurality of chip pads; a plurality of lead terminals, which are respectively connected to the plurality of semiconductor chips; and a package, which encapsulates the plurality of chip pads, the plurality of semiconductor chips and the plurality of lead terminals, the plurality of chip pads and the plurality of lead terminals are exposed from the lower surface of the package, and grooves are arranged on the lower surface of the package between adjacent chip pads and between adjacent lead terminals.

[0007] Effects of the Invention

[0008] In the present invention, not only a plurality of chip pads but also a plurality of lead terminals are exposed from the lower surface of the package. Therefore, heat dissipation can be improved. In addition, grooves are provided between adjacent chip pads and between adjacent lead terminals on the lower surface of the package. Therefore, the creepage distance between the exposed chip pads and the creepage distance between the exposed lead terminals can be ensured. Thus, the required insulation resistance can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a plan view showing the interior of the semiconductor package according to the first embodiment.

[0010] Figure 2 It is a cross-sectional view showing the semiconductor package according to the first embodiment.

[0011] Figure 3 It is a cross-sectional view showing the semiconductor package according to the first embodiment.

[0012] Figure 4 It is a bottom view showing the semiconductor package according to the first embodiment.

[0013] Figure 5 It is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0014] Figure 6 It is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0015] Figure 7 It is a plan view showing the interior of a semiconductor package according to the third embodiment.

[0016] Figure 8 It is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0017] Fig. 9 It is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0018] Fig.10 It is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0019] Fig.11 It is a cross-sectional view showing a semiconductor package according to the fifth embodiment.

[0020] Fig.12 It is a cross-sectional view showing a semiconductor package according to the fifth embodiment.

[0021] Fig.13 It is a bottom view showing the semiconductor package involved in the fifth embodiment.

[0022] Fig.14 It is a cross-sectional view showing a semiconductor package according to the sixth embodiment.

[0023] Fig.15 It is a bottom view showing the semiconductor package involved in the sixth embodiment. DETAILED DESCRIPTION

[0024] The semiconductor package according to the embodiment will be described with reference to the drawings. The same reference numerals are given to the same or corresponding components, and duplicate descriptions may be omitted.

[0025] Implementation Method 1

[0026] Figure 1 It is a plan view showing the interior of the semiconductor package according to the first embodiment. Figure 2 , 3 It is a cross-sectional view showing the semiconductor package according to the first embodiment. Figure 4 It is a bottom view showing the semiconductor package according to the first embodiment. Figure 2 is along Figure 1 I-II sectional view.

[0027] Figure 3 is along Figure 1 The semiconductor package is a 6-in-1 IPM (Intelligent Power Module).

[0028] The semiconductor chips 1a to 1f are IGBTs (Insulated Gate Bipolar Transistors) that switch the main current on and off. The semiconductor chips 2a to 2f are FWDs (Free Wheeling Diodes) that allow a freewheeling current to flow during shutdown.

[0029] Semiconductor chips 1a and 2a are provided on the die pad 3a. Semiconductor chips 1b and 2b are provided on the die pad 3b. Semiconductor chips 1c and 2c are provided on the die pad 3c. Semiconductor chips 1d to 1f and 2d to 2f are provided on the die pad 3d.

[0030] The upper surface electrodes of semiconductor chips 1a to 1f are connected to the upper surface electrodes of semiconductor chips 2a to 2f respectively through wires. The lower surface electrodes of semiconductor chips 1a and 2a are connected to chip pads 3a. The lower surface electrodes of semiconductor chips 1b and 2b are connected to chip pads 3b. The lower surface electrodes of semiconductor chips 1c and 2c are connected to chip pads 3c. The lower surface electrodes of semiconductor chips 1d to 1f and 2d to 2f are connected to chip pads 3d. The connection between the lower surface electrodes of semiconductor chips 1a to 1f and 2a to 2f and chip pads 3a to 3d uses a bonding material such as solder.

[0031] Control chips 4a and 4b are provided on lead frame 5. Control electrodes of semiconductor chips 1a to 1c are connected to control chip 4a via wires. Control electrodes of semiconductor chips 1d to 1f are connected to control chip 4b via wires. Control chip 4a controls semiconductor chips 1a to 1c. Control chip 4b controls semiconductor chips 1d to 1f.

[0032] The plurality of lead terminals 6a to 6f are connected to the upper surface electrodes of the plurality of semiconductor chips 2a to 2f through wires. The lead terminals 6d to 6f are connected to the die pads 3a to 3c, respectively. The die pads 3a to 3d, the lead frame 5 and the lead terminals 6a to 6f are formed by processing a metal thin plate into a wiring shape.

[0033] The package 7 of epoxy resin or the like packages semiconductor chips 1a to 1f, 2a to 2f, die pads 3a to 3d, lead frame 5, lead terminals 6a to 6f, and wires. The lower surfaces of the die pads 3a to 3d, lead frame 5, and lead terminals 6a to 6f are exposed from the lower surface of the package 7 and function as a heat dissipation surface for dissipating heat. Grooves 8 are provided on the lower surface of the package 7 between adjacent die pads 3a to 3d and between adjacent lead terminals 6a to 6f.

[0034] The semiconductor package having the above structure is mounted on the substrate 9. At this time, the lead frame 5 and the lead terminals 6a to 6f protruding from the side of the package 7 are bent downward and connected to electrodes of the substrate 9, respectively.

[0035] In this embodiment, not only the die pads 3a to 3d are exposed from the lower surface of the package 7, but also the lead terminals 6a to 6f are exposed from the lower surface of the package 7. Therefore, the heat dissipation can be improved. In addition, grooves 8 are provided between adjacent die pads 3a to 3d and between adjacent lead terminals 6a to 6f on the lower surface of the package 7. Therefore, the creepage distance between the exposed die pads 3a to 3d and the creepage distance between the exposed lead terminals 6a to 6f can be ensured. Thus, the required insulation resistance can be ensured.

[0036] Implementation Method 2

[0037] Figure 5 , 6 It is a cross-sectional view showing a semiconductor package according to the second embodiment. Figure 5 The cross sections of 6 correspond to those of the first embodiment. Figure 2 , 3 In the present embodiment, the insulating material 10 is in close contact with the lower surface of the package 7 and enters the groove 8. The insulating material 10 is a polyurethane having a higher thermal conductivity than the material of the package 7, for example, a Young's modulus of 500 [MPa] or less.

[0038] The insulating material 10 enters the groove 8 between the die pads 3a to 3d and between the lead terminals 6a to 6f, thereby ensuring the spatial distance, thereby further improving the insulation resistance. In addition, the heat of the die pads 3a to 3d and the lead terminals 6a to 6f is not only dissipated into the atmosphere, but also dissipated to the substrate 9 via the insulating material 10, thereby improving the heat dissipation. The other structures and effects are the same as those of the first embodiment.

[0039] Implementation 3

[0040] Figure 7 FIG. 8 is a plan view showing the interior of a semiconductor package according to Embodiment 3. FIG. 8 is a cross-sectional view showing a semiconductor package according to Embodiment 3. Figure 8 is along Figure 7 I-II sectional view. In the present embodiment, the shunt resistor 11 is provided on the lead terminals 6a to 6c. One end of the shunt resistor 11 is connected to the lead terminals 6a to 6c, and the other end is grounded via an emitter terminal (not shown). The purpose of the shunt resistor 11 is to detect current for short-circuit protection.

[0041] By embedding the shunt resistor 11 in the package 7, the substrate mounting process and substrate mounting cost of the shunt resistor 11 can be reduced. In addition, the lead terminals 6a to 6c provided with the shunt resistor 11 are exposed from the bottom surface of the package 7 and are in close contact with the insulating material 10, so that the heat dissipation of the shunt resistor 11 is improved.

[0042] Implementation 4

[0043] Fig. 9 , 10 It is a cross-sectional view showing a semiconductor package according to a fourth embodiment. Fig. 9 The cross sections of 10 correspond to those of the first embodiment. Figure 2 , 3 In this embodiment, a metal pattern 12 made of copper or the like is provided on the lower surface of the insulating material 10. Heat dissipation can be achieved from the metal pattern 12 installed on the outside, so the heat dissipation of the chip pads 3a to 3d and the lead terminals 6a to 6f is further improved. Other structures and effects are the same as those of the third embodiment.

[0044] Implementation method 5

[0045] Fig.11 , 12 FIG. 13 is a cross-sectional view showing a semiconductor package according to Embodiment 5. FIG. 13 is a bottom view showing a semiconductor package according to Embodiment 5. Fig.11 , 12 The cross sections correspond to those of Embodiment 1. Figure 2 , 3In this embodiment, the insulating material 10 is encapsulated by a resin 13 such as an epoxy resin. The lower surface of the metal pattern 12 is exposed from the resin 13. The other structures are the same as those of the fourth embodiment.

[0046] The package 7 and the resin 13 form a single package. By embedding the insulating material 10 in the package, the substrate mounting process and substrate mounting cost of mounting the semiconductor package on the substrate 9 can be reduced. Other effects are the same as those of the fourth embodiment. In addition, even when the insulating material 10 is packaged by the resin 13, in order to ensure the spatial distance between the chip pads 3a to 3d and between the lead terminals 6a to 6f, it is necessary to provide the groove 8 so that the insulating material 10 enters the groove 8.

[0047] Implementation 6

[0048] Fig.14 It is a cross-sectional view showing a semiconductor package according to the sixth embodiment. Fig.15 1 is a bottom view showing a semiconductor package according to Embodiment 6. In this embodiment, the lead frame 5 provided with the control chips 4a and 4b with low heat generation is not exposed from the bottom surface of the package 7. That is, only the die pads 3a to 3d provided with the semiconductor chips 1a to 1f and 2a to 2f as the main heat sources and the plurality of lead terminals 6a to 6f are exposed from the bottom surface of the package 7. The other structures are the same as those of Embodiment 2. Even in such a case, the heat dissipation can be improved as in Embodiment 2.

[0049] In addition, the semiconductor chips 1a~1f, 2a~2f are not limited to being formed by silicon, but can also be formed by a wide bandgap semiconductor having a larger bandgap than silicon. Wide bandgap semiconductors are, for example, silicon carbide, gallium nitride materials, or diamond. Semiconductor chips formed by such wide bandgap semiconductors can be miniaturized due to their high voltage resistance and allowable current density. By using the miniaturized semiconductor chip, the semiconductor package in which the semiconductor chip is assembled can also be miniaturized and highly integrated. In addition, since the semiconductor chip has high heat resistance, the heat dissipation fins of the radiator can be miniaturized, and the water cooling part can be air-cooled, so that the semiconductor package can be further miniaturized. In addition, since the power loss of the semiconductor chip is low and efficient, the semiconductor package can be made efficient.

[0050] Description of the label

[0051] 1a to 1f, 2a to 2f semiconductor chips, 3a to 3d chip pads, 4a, 4b control chip, 5 lead frame, 6a to 6f lead terminals, 7 package, 8 groove, 10 insulating material, 11 shunt resistor, 12 metal pattern, 13 resin.

Claims

1. A semiconductor package, characterized in that: have: Multiple chip pads; a plurality of semiconductor chips, which are respectively disposed on the plurality of chip pads; a plurality of lead terminals, which are respectively connected to the plurality of semiconductor chips; as well as a package that packages the plurality of chip pads, the plurality of semiconductor chips, and the plurality of lead terminals, The plurality of chip pads and the plurality of lead terminals are exposed from a lower surface of the package, The chip pad and the lead terminal are formed by processing a metal thin plate into a wiring shape. The plurality of die pads include a first die pad and a second die pad, The plurality of semiconductor chips include: a first semiconductor chip disposed on the first chip pad, the lower surface electrode being connected to the first chip pad; and a second semiconductor chip disposed on the second chip pad, the lower surface electrode being connected to the second chip pad. The plurality of lead terminals include: a first lead terminal formed integrally with the first chip pad; a second lead terminal formed integrally with the second chip pad; and a third lead terminal connected to an upper surface electrode of the first semiconductor chip via a wire. Grooves are provided on the lower surface of the package between adjacent groups of the first chip pad and the first lead terminal and the second chip pad and the second lead terminal, and between adjacent groups of the first chip pad and the first lead terminal and the third lead terminal.

2. The semiconductor package according to claim 1, wherein: The plurality of die pads and the plurality of lead terminals are coplanar at a lower surface of the package.

3. The semiconductor package according to claim 1 or 2, characterized in that: An insulating material is also provided, which is in close contact with the lower surface of the package and enters the groove, and has a higher thermal conductivity than the package.

4. The semiconductor package according to claim 1 or 2, wherein: The plurality of lead terminals further include a fourth lead terminal connected to the upper surface electrode of the second semiconductor chip via a wire. A shunt resistor is further provided, one end of which is connected to the adjacent third lead terminal and the fourth lead terminal, and the other end of which is grounded.

5. The semiconductor package according to claim 3, wherein: A metal pattern is also provided on the lower surface of the insulating material.

6. The semiconductor package according to claim 3, wherein: The invention also comprises a resin for encapsulating the insulating material.

7. The semiconductor package according to claim 5, wherein: The invention also comprises a resin for encapsulating the insulating material.

8. The semiconductor package according to claim 1 or 2, characterized in that: Also features: lead frame; and A control chip is disposed on the lead frame and controls the plurality of semiconductor chips. The lead frame does not expose from the lower surface of the package.

9. The semiconductor package according to claim 1 or 2, characterized in that: The plurality of semiconductor chips are formed of a wide bandgap semiconductor.

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