Substrate medium for active devices and processing method thereof

Abstract

The present application provides a substrate medium for active devices and a processing method thereof. It embeds two upper and lower metal layers in a dielectric substrate of insulating material, and respectively sets metal units and coupling units that correspond to each other and whose size and structure match the device in the two metal layers, so as to achieve absorption and shielding of interference signals between devices through the equivalent inductive reactance formed between the upper and lower metal layers. The upper and lower metal layers of the present application can also achieve isolation and shielding of external electromagnetic fields through the outer complete metal units and coupling units. The metal unit cooperates with the connection hole that provides electrical connection to the device, and can further provide electromagnetic isolation and signal protection for the device pins by surrounding the connection hole with the metal unit. The present application can effectively expand the linear operating frequency band range of active devices, thereby stabilizing the circuit signal output and reducing circuit system noise and electromagnetic interference.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a substrate medium for an active device and a processing method thereof. Background Art

[0002] The substrate medium of existing active devices usually has several doping regions with different depths and ion concentrations at several positions relative to the device pins, so that the ions are driven by the current and voltage signals introduced by the device pins to realize the circuit functions accordingly.

[0003] For high-power active devices, since their internal current and voltage signals are large, they are more likely to be superimposed on electromagnetic interference signals, causing the devices to enter a nonlinear working state, thereby affecting the circuit structure to achieve the corresponding functions originally designed. Summary of the invention

[0004] In view of the deficiencies of the prior art, the present application provides a substrate medium for active devices and a processing method thereof. The present application adds an extra layer of substrate dielectric plate between the bottom of the active device and the circuit substrate, or directly uses the substrate dielectric plate of the present application to realize the circuit substrate to build the corresponding circuit unit, thereby utilizing the metal units and coupling units arranged in equal intervals in the form of unit arrays added to the substrate dielectric plate to block the interference signals between the active devices. The present application can effectively expand the linear operating frequency band range of the active device, thereby stabilizing the circuit signal output and reducing the circuit system noise and electromagnetic interference. The present application specifically adopts the following technical solutions.

[0005] First, to achieve the above-mentioned purpose, a substrate medium for active devices is proposed, which includes: a dielectric substrate, which is an insulating medium; a first metal layer, which is arranged in the dielectric substrate, including a plurality of metal units arranged at equal intervals and covering the entire dielectric substrate, there is no direct electrical contact between the metal units, and a first coupling opening opened along a first direction is provided between two adjacent metal units; a second metal layer, which is arranged in the dielectric substrate, including a plurality of coupling units arranged at equal intervals and covering the entire dielectric substrate, each coupling unit is arranged directly below the metal unit in a one-to-one correspondence with each metal unit, there is no direct electrical contact between the coupling units, and a second coupling opening opened along a second direction is provided between two adjacent coupling units; a connecting hole, which vertically penetrates the metal unit and extends downward from the upper surface of the dielectric substrate to between the first metal layer and the second metal layer; and a circuit wiring, which is horizontally arranged between the first metal layer and the second metal layer, and is connected between corresponding connecting holes according to the circuit connection status between the devices, so as to form an electrical path between the devices.

[0006] Optionally, in any of the substrate media for active devices described above, the metal unit and the coupling unit are both regular hexagonal structures or both regular quadrilateral structures.

[0007] Optionally, a substrate medium for an active device as described in any of the above, wherein, between the metal unit of a regular hexagonal structure and the coupling unit, the opening angle between the first coupling opening and the second coupling opening differs by 60 degrees or 120 degrees; between the metal unit of a regular quadrilateral structure and the coupling unit, the opening angle between the first coupling opening and the second coupling opening differs by 90 degrees; the metal unit located at the outermost periphery of the first metal layer has only a single first coupling opening set at a position close to the inner metal unit; and the coupling unit located at the outermost periphery of the second metal layer has only a single second coupling opening set at a position close to the inner coupling unit.

[0008] Optionally, in any of the substrate media for active devices described above, a spacing d between adjacent metal units and a spacing d between adjacent coupling units is 1 / 8, 1 / 4 or 1 / 2 of a device operating wavelength.

[0009] Optionally, in the substrate medium for active devices as described above, a distance D between geometric centers of adjacent metal units and adjacent coupling units is half of a distance between device pins or is equal to a minimum distance between device pins.

[0010] Optionally, a substrate medium for an active device as described in any of the above, wherein the connection hole is arranged at the geometric center of the metal unit, the side wall surface of the connection hole is covered with metal, a metal disk is connected between the bottom and the circuit wiring, the metal disk is horizontally arranged in the plane where the circuit wiring is located, the diameter of the metal disk is larger than the width of the circuit wiring and is connected to the circuit wiring as a whole.

[0011] At the same time, in order to achieve the above-mentioned purpose, the present application also provides a substrate medium processing method for active devices, which is used to process the substrate medium for active devices described in any one of claims 1-6, and the steps include: a first step, covering the upper surface of the bottom dielectric substrate with a second metal layer, and printing a number of coupling units arranged at equal intervals and flattening the entire second metal layer in the second metal layer through an etching process; a second step, covering the upper surface of the second dielectric substrate with a circuit metal layer, and printing a circuit wiring corresponding to the circuit connection status between each device in the circuit metal layer through an etching process; a third step, covering the upper surface of the third dielectric substrate with a first metal layer, and printing a number of metal units arranged at equal intervals and flattening the entire first metal layer in the first metal layer through an etching process; a fourth step, sequentially stacking and aligning the above three dielectric substrates from bottom to top, and after further covering the upper surface of the first metal layer with a fourth dielectric substrate, pressing the four dielectric substrates through a hot pressing process to obtain a substrate dielectric board with a multi-layer structure; a fifth step, drilling holes on the substrate dielectric board corresponding to the positions of the connection points of each device in the circuit wiring to the depth of the second dielectric substrate to form connection holes.

[0012] Optionally, the substrate dielectric processing method for active devices as described in any of the above, wherein after forming the connection hole, it also includes: a sixth step of copper-plating the entire substrate dielectric plate with the connection hole, and then peeling off the copper plating on the upper surface of the fourth layer of dielectric substrate around the connection hole.

[0013] Optionally, in any of the above-described substrate dielectric processing methods for active devices, the thickness of the second dielectric substrate layer and the thickness of the third dielectric substrate layer are both smaller than the thickness of the bottom dielectric substrate layer or the fourth dielectric substrate layer.

[0014] Beneficial Effects

[0015] The present application embeds two upper and lower metal layers in a dielectric substrate of an insulating material, and respectively sets upper and lower structures in the two metal layers, metal units and coupling units with corresponding positions and sizes that match the device, so as to achieve absorption and shielding of interference signals between devices through the equivalent inductive reactance formed by the metal units and coupling units between the upper and lower metal layers. The upper and lower metal layers of the present application can also achieve isolation and shielding of external electromagnetic fields through the outermost complete metal units and coupling units. The metal unit cooperates with the connection hole that provides electrical connection to the device, and can further provide electromagnetic isolation and signal protection for the device pins through the metal unit surrounding the connection hole structure design. The present application can effectively expand the linear operating frequency band range of active devices, thereby stabilizing the circuit signal output and reducing circuit system noise and electromagnetic interference.

[0016] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or may be understood by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings:

[0018] Figure 1 is a schematic cross-sectional structure diagram of a substrate medium for an active device of the present application;

[0019] Figure 2 yes Figure 1 Schematic diagram of the A-A' cross-section structure;

[0020] Figure 3 yes Figure 1 Schematic diagram of the B-B' cross-section structure;

[0021] In the figure, 1 represents a dielectric substrate; 2 represents an active device; 21 represents a pin; 31 represents a connection hole; 32 represents a circuit wiring; 11 represents a first metal layer; and 12 represents a second metal layer. DETAILED DESCRIPTION

[0022] In order to make the purpose and technical solution of the embodiment of the present application clearer, the technical solution of the embodiment of the present application will be clearly and completely described in conjunction with the drawings of the embodiment of the present application. Obviously, the described embodiment is a part of the embodiment of the present application, not all of the embodiments. Based on the described embodiment of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0024] Figure 1 A substrate medium for an active device according to the present application is formed by pressing a four-layer dielectric substrate in the following manner:

[0025] First, a second metal layer 12 is covered on the upper surface of a bottom dielectric substrate with a thickness of 1-2 mm. Usually, the edge of the second metal layer 12 can maintain a distance of 2-5 mm from the edge of the bottom dielectric substrate. Then, a transfer glue is covered on the second metal layer. After irradiation and imaging, the metal layer at the corresponding position is peeled off through an etching process, so that a plurality of coupling units arranged at equal intervals and paving the entire second metal layer 12 are printed in the second metal layer 12. There is no direct electrical contact between the coupling units, and a second coupling opening opened along the second direction is provided between two adjacent coupling units.

[0026] Then, in a similar manner, a circuit metal layer is covered on the upper surface of a second dielectric substrate having a thickness of 0.5-1 mm, and circuit wiring 32 corresponding to the circuit connection status between various circuit components is printed in the circuit metal layer through an etching process;

[0027] Subsequently, in a similar manner, the first metal layer 11 is covered on the upper surface of the third dielectric substrate with a thickness of 0.5-1 mm, and a plurality of metal units arranged at equal intervals and paving the entire first metal layer 11 are printed in the first metal layer 11 through an etching process, wherein after the third dielectric substrate and the bottom dielectric substrate are aligned with each other, each coupling unit on the bottom dielectric substrate corresponds to each metal unit on the third dielectric substrate one by one, each coupling unit is arranged directly below the metal unit, and there is no direct electrical contact between the metal units, and a first coupling opening opened along the first direction is formed between two adjacent metal units;

[0028] Step 4: sequentially stack and align the three layers of dielectric substrates formed in the above three steps from bottom to top, wherein the bottom dielectric substrate is located at the bottom layer, and the first metal layer is located at the top layer, and then further cover the upper surface of the first metal layer 11 with a fourth dielectric substrate, and perform hot pressing on the overall structure of the four-layer dielectric substrate, and press the four-layer dielectric substrate by hot pressing to obtain a substrate dielectric plate with a multi-layer structure;

[0029] The fifth step is to drill vertically downward from the center of the metal unit in the first metal layer 11 to the depth of the second layer of dielectric substrate at the position of each device connection point in the circuit wiring 32 on the substrate dielectric board, thereby forming a connection hole 31 directly connected to the circuit wiring 32 at the bottom, thereby forming a substrate dielectric board capable of shielding electromagnetic coupling interference between active devices.

[0030] After the corresponding active device is installed and connected, the substrate medium can form a shielding structure for the electromagnetic resonance signal carried by the device pins through the metal units and coupling units in the upper and lower metal layers, and form an electrical path between the devices through the circuit wiring 32 arranged between the upper and lower metal layers. Therefore, after the active device or other circuit devices matched therewith are welded on the corresponding circuit wiring 32 through the connection hole, the resonance signal and electromagnetic interference between the devices can be limited to the vicinity of the device pins by the metal units and coupling units corresponding to the upper and lower metal layers, and directly absorbed and consumed by the equivalent reactance formed by the two metal layers.

[0031] refer to Figure 2 as well as Figure 3 As shown, the metal unit and the coupling unit can be specifically configured as a regular hexagonal structure, and its size structure can accommodate the pins of the device to pass through the middle of the metal unit without directly forming electrical contact with the metal unit.

[0032] In this implementation, each metal unit and coupling unit in the dielectric substrate of insulating material can be set to have the same size and spacing, and the entire metal layer is laid flat in a unit array manner and arranged inside the dielectric substrate. Under this structure, between each metal unit and coupling unit, the opening direction of the first coupling opening and the opening direction of the second coupling opening can be staggered to cut off the induction current loop and reduce the external radiation intensity of the electromagnetic field interference signal. The direction of the first coupling opening can be based on the length direction of the dielectric substrate and deviate 30 degrees or 60 degrees to the right; and correspondingly, the direction of the second coupling opening can be based on the length direction of the dielectric substrate and deviate 30 degrees or 60 degrees to the left. Therefore, the direction of the first coupling opening and the direction of the second coupling opening are set to be 60 degrees or 120 degrees apart. That is to say, if the first coupling opening between adjacent metal units is opened to the right along the length direction of the dielectric substrate, then the second coupling opening between the coupling units in the second metal layer can be opened to the left along the length direction of the dielectric substrate, and the two are staggered. The metal unit located at the outermost periphery of the first metal layer 11 is provided with a single first coupling opening along the length direction of the dielectric substrate only at a position close to the inner metal unit, and the coupling unit located at the outermost periphery of the second metal layer 12 is provided with a single second coupling opening along the width direction of the dielectric substrate only at a position close to the inner coupling unit. For each metal unit and coupling unit located in the inner layer of the metal layer, two openings can be provided in the same direction along the corresponding opening direction, so as to further block the generation and outward radiation of the induced current in the unit. Between a pair of metal units and a combination of coupling units that are vertically opposite, an equivalent capacitor is formed through two metal layers with the same structure to absorb circuit harmonics; and between adjacent metal units and adjacent coupling units, the resonant current generated by the induction can be blocked through relative coupling openings, so as to prevent the circuit harmonics from leaking to other pins of the device or leaking to other devices to affect the stability of the operation of other circuit devices.

[0033] In other implementations, each metal unit and coupling unit in the dielectric substrate of the insulating material can also be set to a regular quadrilateral structure with the same size and spacing. Different from the previous embodiment, in the regular quadrilateral structure, between each metal unit and coupling unit, the opening direction of the first coupling opening and the opening direction of the second coupling opening can be set to an opening angle of 90 degrees. In other words, if the first coupling opening between adjacent metal units is opened along the length direction of the dielectric substrate, then the second coupling opening between the coupling units in the second metal layer can be opened along the width direction of the dielectric substrate. The metal unit located at the outermost periphery of the first metal layer 11 is only provided with a single first coupling opening along the length direction of the dielectric substrate at a position close to the inner metal unit, and the coupling unit located at the outermost periphery of the second metal layer 12 is only provided with a single second coupling opening along the width direction of the dielectric substrate at a position close to the inner coupling unit. Between a pair of vertically facing metal units and a combination of coupling units, an equivalent capacitor is formed through two metal layers with the same structure to absorb circuit harmonics; and between adjacent metal units and adjacent coupling units, the resonant current can be blocked through relative coupling openings to prevent circuit harmonics from leaking to other pins of the device or leaking to other devices to affect the stability of operation of other circuit devices.

[0034] To achieve the best shielding effect, under the above schemes, the spacing d between adjacent metal units and adjacent coupling units can be specifically set to 1 / 8, 1 / 4 or 1 / 2 of the device operating wavelength. The distance D between the geometric centers of adjacent metal units and adjacent coupling units can be set to half the distance between two adjacent pins 21 of the device to facilitate device installation and welding between connection holes and circuit wiring. In this way, at least one metal unit and a corresponding resonant unit can be spaced between adjacent pins of the device to achieve a better interference shielding effect. Alternatively, to facilitate installation and reduce the processing accuracy requirements for the substrate medium, D can be directly set to be equal to the minimum distance between the device pins 21.

[0035] In a more preferred implementation, in order to shield external electromagnetic interference signals and prevent them from affecting the operation of various circuit components, the present application can further copper-plate the substrate dielectric plate with the connection holes on the substrate dielectric plate with a multi-layer structure obtained according to the above five steps, and then peel off the copper plating on the upper surface of the fourth dielectric substrate around the connection hole 31. As a result, the outside of the substrate dielectric is covered with a metal plating layer, which can effectively shield external electromagnetic interference signals and provide a larger area of ​​heat dissipation plane. At the same time, the inner wall surface of the connection hole 31 will be evenly covered with a layer of metal plating during the copper plating process, thereby increasing the soldering area between the connection hole itself and the device pin to which the solder can be effectively attached, thereby further ensuring that the electrical connection provided by the solder after soldering is firm and reliable.

[0036] In order to further ensure that the electrical connection path of the device pin is stable and reliable, in the design of the second step of the circuit metal layer, the circuit wiring 32 pin connection position can be set at the geometric center position of the corresponding metal unit, and the circuit wiring size can be expanded at this position to form a small metal disk. As a result, the connection hole 31 welded to the device pin has its side wall surface covered with metal to provide additional solder adhesion area, and its bottom is also connected to the circuit wiring 32 through the metal disk, which can further ensure reliable electrical connection with the circuit wiring connection position through the large diameter of the metal disk, avoiding the occurrence of cold solder joints or deformation of the connection position due to welding heating, which affects the reliability of the electrical connection. Generally, in order to simplify processing and improve the reliability of electrical connection, when etching the circuit wiring, the large-diameter metal disk and the relatively small-width circuit wiring can be directly designed to be horizontally integrated.

[0037] Therefore, the present application provides shielding for electromagnetic interference signals and resonant signals by setting the connection hole 31 of the connecting board device pin to vertically penetrate between the two metal layers through the first metal layer 11 located on the upper part of the dielectric substrate and the second metal layer 12 located on the lower part of the dielectric substrate. The device pin realizes the circuit connection structure through the circuit wiring horizontally arranged between the first metal layer 11 and the second metal layer 12, and limits and blocks the electromagnetic interference signal of the pin itself through the metal unit surrounding the periphery of the pin. The present application can realize the circuit layout matching the circuit principle design diagram according to the circuit connection requirements between devices, directly through the circuit wiring connected to the inside of the substrate medium and directly integrated with the connection holes corresponding to each device pin, thereby realizing each electrical signal path accordingly, further saving the processing cost and hardware cost of soldering high-power active devices to the circuit substrate.

[0038] The above is only an implementation method of the present application, and its description is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present application. It should be pointed out that for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application.

Claims

1. A substrate medium for an active device, characterized in that: include: A dielectric substrate (1), which is an insulating medium; A first metal layer (11) is arranged in the dielectric substrate (1), comprising a plurality of metal units arranged at equal intervals and paving the entire dielectric substrate (1), wherein there is no direct electrical contact between the metal units, and a first coupling opening is provided between two adjacent metal units along a first direction; A second metal layer (12) is arranged in the dielectric substrate (1), comprising a plurality of coupling units arranged at equal intervals and covering the entire dielectric substrate (1), each coupling unit being arranged directly below each metal unit in a one-to-one correspondence, each coupling unit having no direct electrical contact with each other, and a second coupling opening opened along a second direction between two adjacent coupling units; A connection hole (31) vertically penetrates the metal unit and extends downward from the upper surface of the dielectric substrate to between the first metal layer (11) and the second metal layer (12); The circuit wiring (32) is horizontally arranged between the first metal layer (11) and the second metal layer (12), and is connected between corresponding connection holes (31) according to the circuit connection status between the devices, so as to form an electrical path between the devices.

2. The substrate medium for active devices according to claim 1, characterized in that: The metal unit and the coupling unit are both regular hexagonal structures or regular quadrilateral structures.

3. The substrate medium for active devices according to claim 2, characterized in that: Between the metal unit and the coupling unit of the regular hexagonal structure, the opening angle between the first coupling opening and the second coupling opening differs by 60 degrees or 120 degrees; Between the regular quadrilateral structure metal unit and the coupling unit, the opening angles of the first coupling opening and the second coupling opening differ by 90 degrees; The metal unit located at the outermost periphery of the first metal layer (11) is provided with a single first coupling opening only at a position close to the inner metal unit; The outermost coupling unit of the second metal layer (12) is provided with only one second coupling opening at a position close to the inner coupling unit.

4. The substrate medium for active devices according to claim 2, characterized in that: The spacing d between adjacent metal units and between adjacent coupling units is 1 / 8, 1 / 4 or 1 / 2 of the working wavelength of the device.

5. The substrate medium for active devices according to claim 4, characterized in that: The distance D between the geometric centers of adjacent metal units and adjacent coupling units is half the distance between device pins (21) or is equal to the minimum distance between device pins (21).

6. The substrate medium for active devices according to claims 1 to 5, characterized in that: The connection hole (31) is arranged at the geometric center of the metal unit, the side wall surface of which is covered with metal, and a metal disk is connected between the bottom of the connection hole and the circuit wiring (32), the metal disk is horizontally arranged in the plane where the circuit wiring (32) is located, the diameter of the metal disk is greater than the width of the circuit wiring (32) and is connected to the circuit wiring (32) as a whole.

7. A substrate medium processing method for active devices, characterized in that: The method for processing a substrate medium for an active device according to any one of claims 1 to 6 comprises the following steps: The first step is to cover the upper surface of the bottom dielectric substrate with a second metal layer (12), and to print a plurality of coupling units arranged at equal intervals and covering the entire second metal layer (12) in the second metal layer (12) through an etching process; The second step is to cover the upper surface of the second dielectric substrate with a circuit metal layer, and to print circuit wiring (32) corresponding to the circuit connection status between the components in the circuit metal layer through an etching process; The third step is to cover the upper surface of the third dielectric substrate with the first metal layer (11), and to print a plurality of metal units arranged at equal intervals and covering the entire first metal layer (11) in the first metal layer (11) through an etching process; The fourth step is to sequentially stack and align the three dielectric substrates from bottom to top, and after further covering the upper surface of the first metal layer (11) with a fourth dielectric substrate, press the four dielectric substrates together by a hot pressing process to obtain a substrate dielectric plate with a multi-layer structure; In the fifth step, holes are drilled downwards to the depth of the second dielectric substrate at the positions of the connection points of each device in the circuit wiring (32) on the substrate dielectric board to form connection holes (31).

8. The substrate medium processing method for active devices according to claim 7, characterized in that: After forming the connection hole (31), the method further comprises: In the sixth step, the substrate dielectric plate with the connection hole is copper plated as a whole, and then the copper plating on the upper surface of the fourth dielectric substrate layer around the connection hole (31) is peeled off.

9. The substrate medium processing method for active devices according to claim 7, characterized in that: The thickness of the second dielectric substrate layer and the thickness of the third dielectric substrate layer are both smaller than the thickness of the bottom dielectric substrate layer or the fourth dielectric substrate layer.

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