Display panel

Abstract

The application discloses a display panel, which comprises a display area and a non-display area surrounding the display area, and comprises a substrate, a thin film transistor layer located on the substrate and in the display area, a shielding layer located between the substrate and the thin film transistor layer and in the display area, and a peripheral wire located in the non-display area and electrically connected to the shielding layer. The peripheral wire comprises a wire part and a resistance part. The resistance part comprises a first end connected to the shielding layer and a second end connected to the wire part. The resistance of the resistance part is greater than the resistance of the wire part with the shortest distance between the first end and the second end. The resistance value per unit length of the extension path of the peripheral wire is increased, and the total resistance value of the peripheral wire is increased, so that the anti-static ability of the peripheral wire is improved, and the yield or quality of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to the technical field of display panel manufacturing, and more particularly to a display panel. BACKGROUND

[0002] The BSM (Bottom Shield Metal) technology reduces the back channel phenomenon of the transistor caused by the electric charge in the substrate by setting a metal part between the substrate and the transistor.

[0003] The plurality of metal parts introduced in the BSM technology are generally connected to the peripheral wire to be loaded with voltage. However, the static electricity generated in the process of manufacturing or working the display panel can be conducted to the peripheral wire through the plurality of metal parts. The static electricity accumulated in the peripheral wire can be discharged to damage the display panel, thereby reducing the yield or quality of the display panel.

[0004] Therefore, the existing display panel manufactured by using the BSM technology has the risk of being damaged due to the accumulation of static electricity, and needs to be improved. SUMMARY

[0005] Embodiments of the present application provide a display panel to solve the problem of the existing display panel manufactured by using the BSM technology being damaged due to the accumulation of static electricity.

[0006] Embodiments of the present application provide a display panel, which includes a display area and a non-display area surrounding the display area, and comprises:

[0007] a substrate;

[0008] a thin film transistor layer located in the display area on the substrate;

[0009] a shielding layer located between the substrate and the thin film transistor layer and located in the display area;

[0010] a peripheral wire located in the non-display area and electrically connected to the shielding layer;

[0011] The peripheral wire includes a wire part and a resistance part. The resistance part includes a first end connected to the shielding layer and a second end connected to the wire part. The resistance of the resistance part is greater than the resistance of the wire part arranged at the shortest distance between the first end and the second end.

[0012] In an embodiment, the resistance part is arranged on both sides or the same side of the virtual connection line at the shortest distance between the first end and the second end.

[0013] In an embodiment, at least one side of the virtual connection line at the shortest distance between the first end and the second end is arranged in a curved shape.

[0014] In an embodiment, the resistive portion and the conductive portion are disposed in the same layer.

[0015] In an embodiment, the thin film transistor layer includes a plurality of thin film transistors in the display region, the shielding layer includes a shielding block corresponding to each of the plurality of thin film transistors and disposed overlapping the thin film transistors, and a shielding trace connecting two adjacent shielding blocks.

[0016] In an embodiment, the resistive portion of the peripheral trace is electrically connected to the shielding trace and disposed in the same layer.

[0017] In an embodiment, the shielding layer includes a plurality of shielding groups extending in a first direction and arranged in a second direction, one end of the shielding groups being electrically connected to one resistive portion, and the other end of the shielding groups being electrically connected to another resistive portion.

[0018] In an embodiment, the resistivity of the resistive portion is greater than the resistivity of the conductive portion.

[0019] In an embodiment, the thin film transistor layer includes:

[0020] an active layer disposed on a side of the shielding layer distal to the substrate;

[0021] a first insulating layer disposed on a side of the active layer distal to the substrate;

[0022] a gate layer disposed on a side of the first insulating layer distal to the substrate;

[0023] a second insulating layer disposed on a side of the gate layer distal to the substrate;

[0024] a source / drain layer disposed on a side of the second insulating layer distal to the substrate;

[0025] In an embodiment, the resistive portion includes a first resistive portion disposed in the same layer as the active layer, or a second resistive portion disposed in the same layer as the source / drain layer.

[0026] In an embodiment, the first resistive portion has the same resistivity as the active layer, and the second resistive portion has the same resistivity as the source / drain layer.

[0027] In an embodiment, the source / drain layer includes:

[0028] a first metal layer, a material of the first metal layer including titanium, the first resistive portion and the first metal layer being disposed in the same layer;

[0029] A second metal layer is located on the side of the first metal layer away from the substrate, and the second metal layer is composed of a material different from that of the first metal layer.

[0030] In an embodiment, the display panel further comprises:

[0031] A via hole is connected between the resistance part and the wire part.

[0032] A conductor part is filled in the via hole, and the conductor part is electrically connected to the resistance part and the wire part.

[0033] In an embodiment, the shielding layer is composed of the same material as the peripheral wire, and the shielding layer and the peripheral wire are arranged in the same layer.

[0034] In an embodiment, the resistance part and the wire part are arranged in different layers, the projection of the resistance part on the plane perpendicular to the substrate exceeds the layer where the shielding layer is located, and the resistance part comprises two parts arranged on the same side or on both sides of the wire part at the shortest distance between the first end and the second end and in a curved shape.

[0035] In an embodiment, the length of the wire part is greater than the shortest distance between the first end and the second end.

[0036] The display panel provided by the embodiment of the present application comprises a display area and a non-display area surrounding the display area, and the display panel comprises: a substrate; a thin film transistor layer located in the display area on the substrate; a shielding layer located between the substrate and the thin film transistor layer and in the display area; a peripheral wire located in the non-display area, and the peripheral wire is electrically connected to the shielding layer; the peripheral wire comprises a wire part and a resistance part, the resistance part comprises a first end connected to the shielding layer and a second end connected to the wire part, and the resistance of the resistance part is greater than the resistance of the wire part arranged at the shortest distance between the first end and the second end. The resistance value of the resistance part in a unit size is set to be larger, so as to increase the resistance value per unit length of the extension path of the peripheral wire, thereby increasing the total resistance value of the peripheral wire, improving the anti-static ability of the peripheral wire, and improving the yield or quality of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0037] The technical solutions and other beneficial effects of the present application will become apparent from the following detailed description of the specific embodiments of the present application, combined with the accompanying drawings.

[0038] Figure 1 A top view schematic diagram of part of the structure of the display panel provided by the embodiment of the present application.

[0039] Figure 2 FIG. 2 is a top view of a display panel according to an embodiment of the present application.

[0040] Figure 3 FIG. 3 is a cross-sectional view of a display panel according to an embodiment of the present application.

[0041] Figure 4 FIG. 4 is a cross-sectional view of a display panel according to an embodiment of the present application.

[0042] Figure 5 FIG. 5 is a cross-sectional view of a display panel according to an embodiment of the present application.

[0043] Figure 6 FIG. 6 is a cross-sectional view of a display panel according to an embodiment of the present application.

[0044] Figure 7 FIG. 7 is a cross-sectional view of a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be clearly and continuously described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative work fall within the scope of protection of the present application.

[0046] In the description of the present application, it should be understood that the terms “close”, “extend”, “side”, “end” and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms “first”, “second” and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as “first”, “second” can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of “a plurality of” is two or more, unless otherwise explicitly and specifically limited.

[0047] Reference to an "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.

[0048] Embodiments of the application provide display panels, including but not limited to the following embodiments and combinations of the following embodiments.

[0049] In an embodiment, in combination with Figures 1 to 5 As shown in FIG. 1, the display panel 100 includes a display area A1 and a non-display area A2 surrounding the display area A1, and the display panel 100 includes: a substrate 10; a thin film transistor layer 20 located in the display area A1 on the substrate 10; a shielding layer 30 located between the substrate 10 and the thin film transistor layer 20 and in the display area A1; a peripheral wire 40 located in the non-display area A2, the peripheral wire 40 being electrically connected to the shielding layer 30; wherein the peripheral wire 40 includes a wire part 401 and a resistance part 402, the resistance part 402 including a first end connected to the shielding layer 30 and a second end connected to the wire part 401, the resistance of the resistance part 402 being greater than the resistance of the wire part 401 at the shortest distance between the first end and the second end. It can be understood that in the connection direction of the wire part 401 and the resistance part 402, the resistance value of the resistance part 402 per unit size is greater than the resistance value of the corresponding wire part 401 in series.

[0050] The substrate 10 can be a flexible substrate or a rigid substrate, and the composition of the flexible substrate can include but is not limited to polyimide, and the composition of the rigid substrate can include but is not limited to silicon dioxide. In particular, in combination with Figures 1 to 5 As shown in FIG. 1, the display area A1 can be provided with a thin film transistor layer 20, a pixel layer located on the thin film transistor layer 20, the thin film transistor layer 20 including a plurality of transistors 201, and the pixel layer can include a plurality of sub-pixels corresponding one-to-one to the plurality of transistors 201, each sub-pixel being electrically connected to a corresponding transistor 201, and each transistor 201 controlling the light-emitting condition of the corresponding sub-pixel to enable the display area A1 of the display panel 100 to display a picture. Of course, the non-display area A2 can be provided with a line or circuit electrically connected to at least one of the thin film transistor layer 20, the peripheral wire 40, and the shielding layer 30.

[0051] It should be noted that a large number of polarizable charges in the substrate 10 are easily affected by external influences or internal electric fields of the display panel 100, and are polarized to form a large number of polarization charges. A large number of polarization charges in the substrate 10 close to the thin film transistor layer 20 can have a polarizing effect on the thin film transistor layer 20, which can affect the movement of charges in the transistor 201 and reduce the reliability of the transistor 201. On this basis, the display area A1 between the substrate 10 and the thin film transistor layer 20 in the embodiment is provided with a shielding layer 30. The shielding layer 30 can reduce the polarization effect on the thin film transistor layer 20 to improve the reliability of the thin film transistor. For example, the shielding layer 30 can be a conductor or a semiconductor, which can be loaded with a shielding potential by being electrically connected to the peripheral wiring 40 to reduce the polarization effect on the thin film transistor layer 20.

[0052] Specifically, the shielding potential loaded on the shielding layer 30 and the peripheral wiring 40 can be equal to a first voltage, and the first voltage is not equal to a ground voltage. Further, the first voltage can be greater than 0 and not greater than 4.6 volts. Alternatively, as shown in Figure 7 The shielding layer 30 and the peripheral wiring 40 can also be electrically connected to the source or drain of the corresponding transistor 201 to be loaded with the voltage of the source or the voltage of the drain as the corresponding first voltage. Specifically, the second contact layer 902 is electrically connected to the source or the drain, and the peripheral wiring 40 can be electrically connected to the source or the drain in sequence through the first conductor 903 penetrating the buffer layer 50 and the first insulating layer 206, the first contact layer 901 provided in the same layer as the gate layer 203, the second conductor 904 penetrating the interlayer dielectric layer 208, and the second contact layer 902 provided in the same layer as the source and the drain to be loaded with the first voltage. The shielding layer 30 is electrically connected to the source or the drain through the peripheral wiring 40 to be loaded with the first voltage. It should be noted that since the first voltage is not equal to the ground voltage, static electricity generated during the manufacture or operation of the display panel 100 can be conducted to the peripheral wiring 40 through the shielding layer 30. In addition, the high light transmittance requirement of the display area A1 results in a small size of the shielding layer 30, so that the shielding layer 30 cannot share more static electricity to reduce the static electricity flowing into the peripheral wiring 40, resulting in continuous accumulation of static electricity in the peripheral wiring 40 and then discharging to damage the display panel 100, thereby reducing the yield or quality of the display panel.

[0053] It can be understood that, as shown in Figure 1 and Figure 2As shown, in the embodiment, the peripheral wire 40 includes a wire part 401 and a resistance part 402 connected in series with the wire part 401, and the resistance of the resistance part 402 is greater than the resistance of the wire part 401 with the shortest distance between the first end and the second end. The resistance of the wire part 401 with the shortest distance between the first end and the second end can be understood as the corresponding resistance value when the length of the wire part 401 is the shortest distance between the first end and the second end. In the embodiment, the resistance part 402 has a greater resistance relative to the wire part 401 with the shortest distance between the first end and the second end, so that the peripheral wire 40 formed has a greater resistance. Alternatively, it can be understood that in the connection direction, the resistance value of the resistance part 402 within a unit size is greater than the resistance value of the corresponding wire part 401 connected in series, wherein each connection direction corresponds to one resistance part 402 and at least one wire part 401. It can be understood that each resistance part 402 is connected to at least one wire part 401 in the corresponding connection direction. Of course, there are also wire parts 401 that are not connected in series with the resistance part 402. At this time, there is no “connection direction” mentioned above, that is, under the premise that the extension path length of the peripheral wire 40 is basically unchanged, the embodiment increases the resistance value of the resistance part 402 within a unit size in the connection direction, so that the resistance value per unit length of the extension path of the peripheral wire 40 containing the resistance part 402 is greater than the resistance value per unit length of the extension path of the peripheral wire 40 not containing the resistance part 402. Therefore, the total resistance value of the peripheral wire 40 located in the non-display area A2 is increased, the anti-static ability of the peripheral wire 40 is improved, and thus the yield or quality of the display panel 100 is improved.

[0054] In an embodiment, as Figure 1 and Figure 2As shown, one end of the shielding group 301 is electrically connected to one of the resistance parts 402, and the other end of the shielding group 301 is electrically connected to another of the resistance parts. It should be noted that the resistance of a conductor to current is called the resistance of the conductor, and the regular directional motion of free charges in the conductor under the action of electric field force forms an electric current, that is, the greater the resistance value of the conductor, the greater the resistance to static electricity. Specifically, the peripheral traces 40 in the non-display area A2 are electrically connected to the shielding layer 30 as a whole, and it can be understood that in this embodiment, the plurality of resistance parts 402 in the peripheral traces 40 are dispersed and respectively connected to both ends of the shielding layer 30, that is, the plurality of resistance parts 402 are dispersed in the two regions oppositely arranged in the non-display area A2, so that the distribution of the resistance parts 402 in the peripheral traces 40 that have a "greater resistance to current" is more uniform, avoiding the accumulation of resistance parts 402 in one region in the non-display area A2, which causes the resistance in the other regions of the peripheral traces 40 in the non-display area A2 to be smaller and unable to resist more static electricity, resulting in discharge and damage to the display panel 100.

[0055] It should be noted that the extension path of the peripheral traces 40 in the present application is not limited, as long as it meets the requirements of "being located in the non-display area A2" and "being electrically connected to the shielding layer 30", for example, as shown in Figure 1 and Figure 2 , which are taken as examples to illustrate the peripheral traces 40 arranged around the left side, the lower side, and the right side of the shielding layer 30. Further, the part of the peripheral traces 40 located on the left side of the shielding layer 30 can be connected to the left side of the shielding layer 30, the part of the peripheral traces 40 located on the right side of the shielding layer 30 can be connected to the right side of the shielding layer 30, and the part of the peripheral traces 40 located on the left side of the shielding layer 30 and the part of the peripheral traces 40 located on the right side of the shielding layer 30 can be connected to the lower side of the shielding layer 30. Still further, for the part of the peripheral traces 40 located on the left side or the right side of the shielding layer 30, it includes the main trunk trace and the plurality of branch trunk traces corresponding to the plurality of shielding groups 301, one end of each branch trunk trace is electrically connected to the corresponding shielding group 301, the other end of each trunk trace is electrically connected to the corresponding main trunk trace close to the edge of the display panel 100, and each branch trunk trace includes a resistance part 402 and at least a conductor part 401 connected in series at one end of the resistance part 402. In combination with the above discussion, for the resistance part 402 and the conductor part 401 included in the same main trunk trace, the connection direction is parallel to the first direction D1.

[0056] In an embodiment, in combination with Figure 1 and Figure 3As shown, the resistance portion 402 is arranged on both sides or the same side of the virtual line with the shortest distance between the first end and the second end. For example, when the resistance portion 402 is arranged on the same side of the virtual line with the shortest distance between the first end and the second end, the resistance portion 402 can be arranged in a curved shape or a straight line shape not parallel to the first direction D1 to increase the resistance; for another example, as shown in FIG. 4B, when the resistance portion 402 is arranged on both sides of the virtual line with the shortest distance between the first end and the second end, the connecting line between the two parts of the resistance portion 402 arranged on both sides of the virtual line with the shortest distance between the first end and the second end has a projection in at least the second direction D2 to increase the resistance, and thus the part of the resistance portion 402 arranged on the same side of the virtual line with the shortest distance between the first end and the second end is not limited to be arranged in a straight line shape parallel to the first direction D1. Figure 1 As shown, when the resistance portion 402 is arranged on both sides of the virtual line with the shortest distance between the first end and the second end, the connecting line between the two parts of the resistance portion 402 arranged on both sides of the virtual line with the shortest distance between the first end and the second end has a projection in at least the second direction D2 to increase the resistance, and thus the part of the resistance portion 402 arranged on the same side of the virtual line with the shortest distance between the first end and the second end is not limited to be arranged in a straight line shape parallel to the first direction D1.

[0057] In an embodiment, the resistance portion 402 arranged on at least one side of the virtual line with the shortest distance between the first end and the second end is in a curved shape. Specifically, the resistance portion 402 arranged on both sides of the virtual line with the shortest distance between the first end and the second end is taken as an example for illustration, and the resistance portion 402 includes a plurality of sub-resistance portions 4021 arranged in connection, and the sub-resistance portions 4021 are in a curved shape. Here, the bending direction of the sub-resistance portions 4021 and the arrangement direction of the plurality of sub-resistance portions 4021 are not limited, and in combination with the above description, the bending direction of the sub-resistance portions 4021 can be parallel to the second direction D2, and the plurality of sub-resistance portions 4021 in a curved shape can be arranged along the first direction D1.

[0058] It can be understood that, in the case that the size of the non-display area A2 in the first direction D1 is certain, the extension path of the resistance portion 402 makes a reciprocating motion in the second direction D2 in the embodiment, which can make the total length of the resistance portion 402 longer, and when the constituent materials at different positions of the peripheral trace 40 are the same, the resistance value of the resistance portion 402 is larger, thereby realizing the above-mentioned “in the connection direction (parallel to the first direction D1), the resistance value of the resistance portion 402 in a unit size is larger than the resistance value of the corresponding serially connected conductive portion 401”.

[0059] Further, the shape and number of the plurality of sub-resistance portions 4021 arranged in each resistance portion 402 can be the same, i.e., the shape and size of the plurality of resistance portions 402 can be the same, i.e., the plurality of resistance portions 402 have the same capacity of accommodating and hindering static electricity. When the plurality of resistance portions 402 in the peripheral wire 40 are evenly distributed, the above arrangement can further evenly distribute the capacity of accommodating and hindering static electricity of the part of the peripheral wire 40 provided with the resistance portion 402, and can reduce the difference in the capacity of accommodating and hindering static electricity of different resistance portions 402, so as to avoid the risk of discharging and damaging the display panel 100 due to the small resistance of some parts of the peripheral wire 40 and the incapability of hindering more static electricity.

[0060] In an embodiment, as shown in Figure 1 and Figure 3 , the resistance portion 402 and the wire portion 401 are arranged in the same layer. It can be understood that, in the embodiment, the resistance portion 402 and the wire portion 401 arranged in the same layer can avoid increasing the thickness of the display panel 100. Further, the composition material of the resistance portion 402 and the composition material of the wire portion 401 are the same, wherein the resistance portion 402 and the wire portion 401 can be prepared at the same time, or even integrally formed, so as to save the process, and in combination with the above description, the plurality of sub-resistance portions 4021 arranged in connection and in a curved shape, the wire portion 401 connected to the plurality of sub-resistance portions 4021 can be formed by the same process, so as to be formed at one time.

[0061] It can be understood that, in combination with the above description, when the composition materials at different parts of the peripheral wire 40 are the same, the resistance value of the resistance portion 402 is large, i.e., on the basis of the embodiment that the resistance portion 402 comprises the plurality of sub-resistance portions 4021 arranged in connection and in a curved shape, the resistance value of the resistance portion 402 can be large. Specifically, the composition material of the resistance portion 402 and the composition material of the wire portion 401 can be but not limited to a conductor material and a semiconductor material, the conductor material can include but not limited to a metal element, and the semiconductor material can include but not limited to a silicon element, an oxide, and an oxide containing silicon element, wherein the metal element can be but not limited to molybdenum and titanium.

[0062] In an embodiment, as shown in Figure 1 and Figure 3 , the composition material of the shielding layer 30 and the composition material of the peripheral wire 40 are the same, and the shielding layer 30 and the peripheral wire 40 are arranged in the same layer. Specifically, the composition material of the shielding layer 30 and the composition material of the peripheral wire 40 can be but not limited to a conductor material and a semiconductor material, the conductor material can include but not limited to a metal element, and the semiconductor material can include but not limited to a silicon element, an oxide, and an oxide containing silicon element, wherein the metal element can be but not limited to molybdenum.

[0063] It can be understood that, in the embodiment, the shielding layer 30 and the peripheral wiring 40 are arranged in the same layer, which can avoid increasing the thickness of the display panel 100. Further, the shielding layer 30 and the peripheral wiring 40 can be prepared at the same time, or even integrally formed, so as to save the process, that is, the plurality of sub-resistance portions 4021 connected and arranged in a curved shape, the wire portion 401 connected to the plurality of sub-resistance portions 4021, and the plurality of shielding portions connected and arranged at both ends of the peripheral wiring 40 can be formed at the same time, so as to form the peripheral wiring 40 and the shielding layer 30 at one time.

[0064] In an embodiment, the length of the wire portion 401 is greater than the shortest distance between the first end and the second end. In combination with the above description, the peripheral wiring 40 includes the wire portion 401 and the resistance portion 402 connected in series with the wire portion 401. Each resistance portion 402 is connected in series with at least one wire portion 401 in the corresponding connection direction. There is also a wire portion 401 that is not connected in series with the resistance portion 402. It can be understood that the wire portion 401 is arranged in a curved shape in the extension direction, that is, the wire portion 401 arranged in a curved shape in the extension direction can refer to the wire portion 401 connected in series or not connected in series with the resistance portion 402.

[0065] Specifically, as shown in Figure 1 and Figure 2 The wire portion 401 includes a portion extending along the first direction D1 and a portion extending along the second direction D2. The wire portion 401 is arranged in a curved shape in the extension direction. The bending direction of each part of the wire portion 401 is not limited, for example, the portion extending along the first direction D1 can be bent towards the second direction D2, that is, arranged in a non-straight line in the first direction D1. The portion extending along the second direction D2 can be bent towards the first direction D1, that is, arranged in a non-straight line in the second direction D2. It can be understood that, in the case that the size of the non-display area A2 in the first direction D1 or the second direction D2 is certain, the wire portion 401 is arranged in a curved shape in any direction in the embodiment, which can make the total length of the wire portion 401 longer, so as to make the resistance value of the wire portion 401 larger, thereby increasing the path that can accommodate static electricity in the wire portion 401, or increasing the ability of the wire portion 401 to hinder static electricity, thereby improving the overall anti-static ability of the peripheral wiring 40, so as to improve the yield or quality of the display panel 100.

[0066] In an embodiment, the shielding group 301 is arranged in a curved shape in the extension direction. Specifically, in combination with the above description, each shielding group 301 can be arranged opposite to the plurality of transistors 201 arranged along the first direction D1. The plurality of shielding portions connected in each shielding group 301 can correspond to the plurality of transistors 201 one by one. Each shielding portion can be arranged opposite to the corresponding transistor 201, that is, the shielding group 301 extends along the first direction D1.

[0067] Specifically, the shielding group 301 is arranged in a curved manner in the extending direction. Here, the direction of each curve in the shielding group 301 is not limited, for example, the shielding group 301 can be curved in the second direction D2, that is, the shielding group 301 is arranged in a non-straight line in the first direction D1. It can be understood that, in the case that the size of the display area A1 in the first direction D1 is certain, in the embodiment, the shielding group 301 is arranged in a curved manner in any direction, so that the total length of the shielding group 301 is relatively long, so that the resistance value of the shielding group 301 is relatively large, thereby increasing the path in the shielding layer 30 that can accommodate static electricity, or increasing the hindering ability of the shielding layer 30 to static electricity, thereby improving the overall anti-static ability of the shielding layer 30 and the peripheral wire 40, so as to improve the yield or quality of the display panel 100.

[0068] In an embodiment, as shown in Figure 2 , Figure 4 and Figure 5 , the resistance part 402 and the wire part 401 are arranged in different layers, and the resistivity of the resistance part 402 is greater than the resistivity of the wire part 401. Specifically, the shape of the resistance part 402 and the shape of the wire part 401 are not limited, and the composition material of the resistance part 402 and the composition material of the wire part 401 are also not limited. Here, the resistivity can be understood as the resistance of a conductor with a length of 1 meter and a cross-sectional area of 1 square meter after being straightened. It can be considered that under the same external factors such as temperature, pressure and magnetic field, the resistivity of the resistance part 402 is greater than the resistivity of the wire part 401.

[0069] It can be understood that when the shape and size of the resistance part 402 are the same as the shape and size of the wire part 401, in the embodiment, the resistivity of the resistance part 402 is greater than the resistivity of the wire part 401, which can achieve the above-mentioned "in the connecting direction (parallel to the first direction D1), the resistance value of the resistance part 402 per unit size is greater than the resistance value of the corresponding wire part 401 in series". Of course, under the premise that the resistivity of the resistance part 402 is greater than the resistivity of the wire part 401, the parameters of the resistance part 402 and the parameters of the wire part 401 can be reasonably set to achieve "in the connecting direction (parallel to the first direction D1), the resistance value of the resistance part 402 per unit size is greater than the resistance value of the corresponding wire part 401 in series". The embodiment aims to emphasize that "the resistivity of the resistance part 402 is greater than the resistivity of the wire part 401" is helpful to achieve "in the connecting direction (parallel to the first direction D1), the resistance value of the resistance part 402 per unit size is greater than the resistance value of the corresponding wire part 401 in series".

[0070] In an embodiment, as shown in Figure 1 , Figure 2 , Figure 4 andFigure 5 As shown, the thin film transistor layer 20 includes a plurality of thin film transistors 201 in the display area A1, the shielding layer 30 includes a shielding block corresponding to each of the plurality of transistors 201 and arranged in overlap with each other, and a shielding trace connected to two adjacent shielding blocks; and the resistance part 402 of the peripheral trace 40 is electrically connected to the shielding trace and arranged in the same layer. Specifically, the shielding layer 30 can include a plurality of shielding groups 301 extending along a first direction D1 and arranged along a second direction D2, at least one end of each of the shielding groups 301 is electrically connected to a resistance part 402, and the resistance part 402 and the thin film transistor layer 20 are arranged in the same layer. The shielding trace can be arranged in the same layer as at least one layer of the thin film transistor layer 20.

[0071] Here, the first direction D1 is parallel to the first side of the display panel 100, the second direction D2 is parallel to the second side of the display panel 100, and the first direction D1 is perpendicular to the second direction D2, and the specific implementation is described in combination with Figure 4 and Figure 5 As shown, the plurality of transistors 201 in the thin film transistor layer 20 can be arranged in an array along the first direction D1 and the second direction D2. In combination with the above description, each of the shielding groups 301 can be arranged opposite to the plurality of transistors 201 arranged along the first direction D1. Further, each of the shielding groups 301 can include a plurality of shielding parts electrically connected to each other, and each of the shielding parts can be arranged opposite to a corresponding transistor 201. Specifically, each of the shielding groups 301 can be arranged opposite to the plurality of transistors 201 in the same row. Further, each of the shielding blocks can be arranged opposite to a corresponding transistor 201 in a corresponding row of transistors 201. The width of the shielding trace can be less than or equal to the width of the shielding block. It can be understood that, for the plurality of shielding blocks close to the non-display area A2, the corresponding shielding trace can be connected to the peripheral trace 40.

[0072] Specifically, the resistance value of the resistance part 402 in the unit size in the connection direction is large, that is, the resistance value of the resistance part 402 is greater than the resistance value of the conductive part 401 in the same size in the connection direction. It can be understood that, in the embodiment, at least one end of each of the shielding groups 301 is electrically connected to a resistance part 402, which can increase the resistance value in the extension direction of the plurality of shielding groups 301. By dispersing the distribution of the resistance part 402, the resistance value in the extension direction of one of the shielding groups 301 is avoided to be small and to accumulate more static electricity to discharge, thereby improving the anti-static ability of the peripheral trace 40, and thus improving the yield or quality of the display panel 100.

[0073] Further, the material of the resistance part 402, the material of the shielding trace and the material of the film layer in the thin film transistor layer 20 which is arranged in the same layer as the shielding trace are the same. In the embodiment, the resistance part 402 and the film layer in the thin film transistor layer 20 which is arranged in the same layer and has the same material are not limited, as long as the resistivity of the resistance part 402 is greater than the resistivity of the conductive part 401. It can be understood that, in the embodiment, the resistance part 402 and the thin film transistor layer 20 arranged in the same layer can avoid increasing the thickness of the display panel 100, and further, the resistance part 402 and the thin film transistor layer 20 can be prepared at the same time to save the process, that is, the resistance part 402 and the corresponding film layer in the thin film transistor layer 20 can be formed by the same process to form the resistance part 402 and the corresponding film layer in the thin film transistor layer 20 at one time.

[0074] Specifically, in combination with the above, the resistivity of the resistance part 402 is greater than the resistivity of the conductive part 401, that is, the material of the resistance part 402 is the same as the material of the thin film transistor layer 20 to realize that the material of the resistance part 402 is different from the material of the conductive part 401, and further, the material of one component in the thin film transistor layer 20 is selected to make the resistance part 402 to realize that the resistivity of the resistance part 402 is greater.

[0075] In an embodiment, as shown in Figure 4 and Figure 5 The thin film transistor layer 20 includes a gate layer 203, an active layer 202 arranged on one side of the gate layer 203 close to or away from the substrate 10, a first insulating layer 206 arranged between the gate layer 203 and the active layer 202, and a source-drain layer arranged on one side of the active layer 202 away from the substrate 10, electrically connected to the active layer 202 and insulated from the gate layer 203. Figure 4 The resistance part 402 is arranged in the same layer as the active layer 202, or as shown in Figure 5 The resistance part 402 is arranged in the same layer as the source-drain layer.

[0076] Specifically, the thin film transistor layer 20 in the embodiment is not limited to the transistors formed in the top-gate structure or the bottom-gate structure, and the transistors in the top-gate structure are taken as an example for illustration, that is, the gate layer 203 is located on the side of the active layer 202 away from the substrate 10. Specifically, in combination with the above description, each thin film transistor 201 in the thin film transistor layer 20 can include the active layer 202, the gate layer 203 located on the side of the active layer 202 away from the substrate 10, the source-drain layer located on the side of the gate layer 203 away from the substrate 10, the source-drain layer including the source portion 204 and the drain portion 205 arranged opposite to and electrically connected to the one end of the active layer 202. Further, the display panel 100 further includes the first insulating layer 206 located between the active layer 202 and the gate layer 203 and covering the active layer 202, the second insulating layer 207 covering the side of the gate layer 203 away from the substrate 10, and the interlayer dielectric layer 208 covering the side of the second insulating layer 207 away from the substrate 10. That is, the thin film transistor layer 20 includes the active layer 202 located on the side of the shielding layer 30 away from the substrate 10, the first insulating layer 206 located on the side of the active layer 202 away from the substrate 10, the gate layer 203 located on the side of the first insulating layer 206 away from the substrate 10, the second insulating layer 207 located on the side of the gate layer 203 away from the substrate 10, and the source-drain layer located on the side of the second insulating layer 207 away from the substrate 10. The resistance portion 402 includes the first resistance portion arranged in the same layer as the active layer 202, or the second resistance portion arranged in the same layer as the source-drain layer.

[0077] The material of the active layer 202 can include at least one of amorphous silicon and polycrystalline silicon, and the polycrystalline silicon can include low-temperature polycrystalline silicon. Further, the material of the active layer 202 can further include an oxide. Specifically, for example, the active layer 202 prepared by using the low-temperature polycrystalline silicon technology can have a high electron mobility, so that a large driving current can be generated when the thin film transistor 201 charges the corresponding pixel, so as to improve the charging speed. For example, the active layer 202 prepared by using amorphous silicon or an oxide can have a low leakage current, so as to prevent the leakage of the thin film transistor 201 from interfering with the signal in the exposure situation. Specifically, for example, when the material of the active layer 202 includes amorphous silicon, two doped regions can be formed in the active layer 202 by doping particles electrically connected to the source-drain layer, and the doping particles can include phosphorus ions. The concentration of the doping particles in the doped region can be set according to actual conditions. For example, when the material of the active layer 202 includes an oxide, the doping particles can be avoided to form the doped region.

[0078] Further, based on the above description, as Figure 4As shown, the first resistance part has the same resistivity as the active layer 202, and the second resistance part has the same resistivity as the source-drain layer. Specifically, for the first resistance part arranged in the same layer as the active layer 202, the first resistance part and the active layer 202 can be made of the same material at the same time. According to the above description, since the material of the active layer 202 is a semiconductor material, the material of the first resistance part is also a semiconductor material, which can refer to the above description of the material of the active layer 202. Generally, the material of the conductive part 401 is a conductor material, that is, the resistivity of the first resistance part can be relatively large. Specifically, a buffer layer 50 can be arranged between the shielding layer 30 and the thin film transistor layer 20. After the buffer layer 50 is formed, the resistance part 402 located in the non-display area A2 and the active layer 202 located in the display area A1 can be formed by the same process, so as to form the resistance part 402 and the active layer 202 at one time.

[0079] In an embodiment, as shown in Figure 5 The source-drain layer includes a first metal layer, and the material of the first metal layer includes titanium. A second metal layer is arranged on the side of the first metal layer away from the substrate 10, and the material of the second metal layer is different from that of the first metal layer. Further, the resistance part 402 and the first metal layer are arranged in the same layer. The material of the second metal layer can include aluminum, and further, the source-drain layer can further include a third metal layer arranged on the side of the second metal layer away from the substrate 10, and the material of the third metal layer can be the same as that of the first metal layer.

[0080] Specifically, the first insulating layer 206, the second insulating layer 207, and the interlayer dielectric layer 208 can be provided with a first via hole. The source-drain layer can extend to the active layer 202 through the first via hole from the side of the interlayer dielectric layer 208 away from the substrate 10. According to the above description, the first metal layer can extend to the active layer 202 through the first via hole from the side of the interlayer dielectric layer 208 away from the substrate 10. The second metal layer and the third metal layer can be sequentially formed on the first metal layer.

[0081] It can be understood that, as Figure 5As shown, in the embodiment, on one hand, the first metal layer and the resistance part 402 made of titanium can have higher resistivity than the shielding layer 30 and the wire part 401 made of titanium, which helps to realize that "in the connecting direction, the resistance value of the resistance part 402 in a unit size is greater than the resistance value of the corresponding series of the wire part 401", on the other hand, the first metal layer and the resistance part 402 can be prepared at the same time to save the process and avoid additional increase of the thickness of the display panel 100, after the interlayer dielectric layer 208 is formed, the resistance part 402 located in the non-display area A2, the plurality of source parts 204 located in the display area A1, and the plurality of drain parts 205 can be formed by the same process to form the resistance part 402 and the source-drain layer at one time.

[0082] In an embodiment, as shown in Figure 4 and Figure 5 , the display panel 100 further comprises: a second via hole communicating between the resistance part 402 and the wire part 401; a conductor part 60 filled in the second via hole, the conductor part 60 electrically connecting the resistance part 402 and the wire part 401. It should be noted that, as discussed above, when the resistance part 402 and the thin film transistor layer 20 are arranged in the same layer, the wire part 401 is generally arranged in the same layer as the shielding layer 30, resulting in that the resistance part 402 and the series of wire parts 401 are arranged in different layers.

[0083] As can be understood, for example Figure 4 , when the resistance part 402 and the active layer 202 are arranged in the same layer, the second via hole can penetrate the buffer layer 50 to communicate the resistance part 402 and the wire part 401, and the conductor part 60 filled in the second via hole can electrically connect the resistance part 402 located on the upper side of the buffer layer 50 and the wire part 401 located on the lower side of the buffer layer 50; for example Figure 5 , when the resistance part 402 and the source part 204 and the drain part 205 are arranged in the same layer, the second via hole can penetrate the buffer layer 50, the first insulating layer 206, the second insulating layer 207 and the interlayer dielectric layer 208 to communicate the resistance part 402 and the wire part 401, and the conductor part 60 filled in the second via hole can electrically connect the resistance part 402 located on the upper side of the interlayer dielectric layer 208 and the wire part 401 located on the lower side of the buffer layer 50.

[0084] In an embodiment, as shown in Figure 6 , the resistance part 402 and the wire part 401 are arranged in different layers, the projection of the resistance part 402 on the plane perpendicular to the substrate 10 exceeds the layer where the shielding layer 30 is located, and the resistance part 402 comprises two parts arranged on the same side or on both sides of the wire part 401 with the shortest distance between the first end and the second end and in a curved shape. Specifically, as shown in Figure 6As shown, here, taking the example that the resistance part 402 includes two parts 4021 located above the wire part 401 arranged at the shortest distance between the first end and the second end, in combination with the above discussion, the connection between the multiple resistance parts 402 and the wire part 401 can be realized by the conductor part 60.

[0085] Specifically, referring to Figure 1 , the resistance part 402 in the peripheral wire 40 is arranged in a curved manner to extend in the plane parallel to the substrate 10, which can make the total length of the resistance part 402 longer; similarly, the resistance part 402 in the embodiment is arranged in a curved manner to extend in the plane perpendicular to the substrate 10, which can also make the total length of the resistance part 402 longer, and when the constituent materials at different positions of the peripheral wire 40 are the same, the resistance value of the resistance part 402 is larger, thereby realizing the above-mentioned "in the connection direction (parallel to the first direction D1), the resistance value of the resistance part 402 in the unit size is larger than the resistance value of the corresponding wire part 401 in series". Specifically, in the embodiment, the projection of the resistance part 402 on the plane perpendicular to the substrate 10 does not have a limitation on which film layer in the display panel 100 the part overlapping the shielding layer 30 is located, as long as there is a part "overlapping" that can be located above the shielding layer 30 and a part "overlapping" that can be located below the shielding layer 30.

[0086] The embodiment of the present application provides a mobile terminal, which comprises a terminal main body part and a touch panel as described in any of the above, and the terminal main body part and the touch panel are combined into one.

[0087] The display panel provided by the embodiment of the present application comprises a display area and a non-display area surrounding the display area, and comprises: a substrate; a thin film transistor layer located in the display area on the substrate; a shielding layer located between the substrate and the thin film transistor layer and in the display area; a peripheral wire located in the non-display area, and electrically connected to the shielding layer; the peripheral wire comprises a wire part and a resistance part, the resistance part comprises a first end connected to the shielding layer and a second end connected to the wire part, and the resistance of the resistance part is greater than the resistance of the wire part arranged at the shortest distance between the first end and the second end. Wherein, the resistance value of the resistance part in the unit size is set to be larger, so as to increase the resistance value in the unit length of the extension path of the peripheral wire, thereby increasing the total resistance value of the peripheral wire, and improving the anti-static ability of the peripheral wire, and improving the yield or quality of the display panel.

[0088] The display panel and the mobile terminal provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof. It should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently, and the modification or replacement does not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area surrounding the display area, and comprises: substrate; a thin film transistor layer, located in the display area on the substrate; a shielding layer, located between the substrate and the thin film transistor layer and within the display area; a peripheral wiring, located in the non-display area and electrically connected to the shielding layer, the peripheral wiring being loaded with a shielding potential, the voltage value of the shielding potential being not equal to the voltage value of the ground voltage, and the shielding layer loaded with the shielding potential being used to reduce the polarization effect of the substrate on the thin film transistor layer; Among them, the peripheral routing includes a wire portion and a resistor portion, the resistor portion includes a first end connected to the shielding layer and a second end connected to the wire portion, and the resistance of the resistor portion is greater than the resistance of the wire portion set at the shortest distance between the first end and the second end.

2. The display panel according to claim 1, wherein The resistor portion is disposed on both sides or on the same side of a virtual connection line with the shortest distance between the first end and the second end.

3. The display panel according to claim 2, wherein: The resistor portion is disposed in a curved shape on at least one side of the virtual line that is the shortest distance between the first end and the second end.

4. The display panel according to claim 2 or 3, wherein: The resistor portion and the lead portion are provided in the same layer.

5. The display panel according to claim 1, wherein The thin film transistor layer includes a plurality of thin film transistors located in the display area, and the shielding layer includes shielding blocks corresponding to and overlapping the plurality of transistors one by one and shielding traces connected to two adjacent shielding blocks; The resistor portion of the peripheral wiring is electrically connected to the shielding wiring and is disposed on the same layer.

6. The display panel according to claim 5, wherein: The shielding layer includes a plurality of shielding groups extending along a first direction and arranged along a second direction. One end of the shielding group is electrically connected to one of the resistor parts, and the other end of the shielding group is electrically connected to another part of the resistor parts.

7. The display panel according to claim 1, wherein: The resistivity of the resistor portion is greater than the resistivity of the lead portion.

8. The display panel according to claim 7, wherein: The thin film transistor layer includes: an active layer, located on a side of the shielding layer away from the substrate; a first insulating layer, located on a side of the active layer away from the substrate; a gate layer, located on a side of the first insulating layer away from the substrate; a second insulating layer, located on a side of the gate layer away from the substrate; a source-drain electrode layer, located on a side of the second insulating layer away from the substrate; The resistor portion includes a first resistor portion provided in the same layer as the active layer, or a second resistor portion provided in the same layer as the source / drain layer.

9. The display panel according to claim 8, wherein: The first resistance portion has the same resistivity as that of the active layer, and the second resistance portion has the same resistivity as that of the source / drain layer.

10. The display panel according to claim 9, wherein: The source and drain layer includes: a first metal layer, wherein a constituent material of the first metal layer includes titanium, and the first resistor portion and the first metal layer are provided in the same layer; The second metal layer is located on a side of the first metal layer away from the substrate, and the constituent material of the second metal layer is different from the constituent material of the first metal layer.

11. The display panel according to claim 7, wherein: The display panel further includes: a via hole communicating between the resistor portion and the wire portion; The conductor portion is filled in the via hole and electrically connects the resistor portion and the wire portion.

12. The display panel according to claim 1, wherein The shielding layer is made of the same material as the peripheral wiring, and the shielding layer and the peripheral wiring are arranged on the same layer.

13. The display panel according to claim 1, wherein The resistor portion and the wire portion are arranged in different layers, the projection of the resistor portion on a plane perpendicular to the substrate exceeds the layer where the shielding layer is located, and the resistor portion includes two curved parts located on both sides or on the same side of the wire portion arranged at the shortest distance between the first end and the second end.

14. The display panel according to claim 1, wherein: The length of the wire portion is greater than the shortest distance between the first end and the second end.

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