Gallium nitride heterojunction pin and sbd pair tube integrated device

Abstract

The application discloses a gallium nitride heterojunction PIN and SBD diode integrated device, and mainly solves the problem that the power capacity is limited when the existing discrete PIN and SBD diodes are used in a multi-stage limiting circuit. The first-stage gallium nitride heterojunction PIN diode and the second-stage and third-stage SBD diodes are arranged side by side above a silicon carbide substrate (1), an isolation groove is arranged between the diodes for isolating the devices, and the anode of one single diode and the cathode of a symmetrical single diode are connected through an air bridge structure. The gallium nitride heterojunction PIN diode and the SBD diode are interconnected through the air bridge structure and the common cathode mode, and the integration of the three-stage diodes is realized. The device has the advantages of fast frequency response, good voltage resistance, high integration, and the like, and when the device is used in a limiting circuit, the power capacity can be obviously improved, the response time can be reduced, and the integration can be improved, and the device can be applied to a high-power limiting circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more specifically to a gallium nitride heterojunction PIN and SBD (Schottky Barrier Diode) integrated device in the field of semiconductor integrated circuit technology. This invention can be used in limiting circuits to attenuate large signals passing through the circuit, thereby protecting the circuit and achieving high-power, fast-response limiting characteristics. Background Technology

[0002] With the maturity of semiconductor technology, electronic devices are becoming increasingly integrated and miniaturized. Various precision components have enhanced circuit functionality, while simultaneously placing higher demands on the reliability of communication equipment. To ensure that communication equipment can withstand higher power, limiting circuits are typically designed at the front end of the circuit. This allows low-power microwave signals to pass through with minimal loss, while high-power microwave signals are attenuated to a low power level, thus protecting downstream circuitry. Currently, traditional limiting circuits use Si and GaAs PIN diodes. However, due to the inherently low bandgap properties of Si and GaAs semiconductor materials, the voltage withstand capability of these devices is limited, further restricting the performance of the limiter and making it difficult to increase its power capacity.

[0003] In his paper "Integrated High-Power PIN Limiting MMIC Technology with Vertical Current Flow" (Electronics & Packaging, 2021, 21(6)), Peng Longxin proposed a vertically conductive PIN diode structure with vertical current flow. This device uses a novel heterojunction Si PIN diode structure and a thermally conductive SiC substrate to achieve a high-power PIN diode structure with vertical current flow. However, the device still has shortcomings: the use of Si material with a narrow bandgap affects the limiting performance, and the response time in the limiting circuit is long.

[0004] The 55th Research Institute of China Electronics Technology Group Corporation proposed a bonding transfer-based ultra-high power limiter MMIC and its fabrication method in its patent application "Ultra-high power limiter MMIC and its fabrication method based on bonding transfer" (application number 201811024949.X, application date 2018.09.04, publication number CN109300892 A, publication date 2019.02.01). This invention integrates high-performance Si PIN diodes into the MMIC to achieve a highly integrated, high-power limiting MMIC circuit. However, the patented technology still has shortcomings: the use of Si-based all-PIN diodes for limiting results in a long circuit limiting response time.

[0005] Xi'an University of Electronic Science and Technology proposed a method for fabricating a gallium nitride-based wide-swing bidirectional limiting circuit in its patent application, "A Gallium Nitride-based Wide-Swing Bidirectional Limiting Circuit and Its Fabrication Method" (Application No. 201810811324.1, Application Date 2018.07.23, Publication No. CN110752185A, Publication Date 2020.02.04). This invention achieves self-protection of the circuit by using a circuit that connects a PIN diode and a Schottky diode in parallel to the gate layer. However, the patented technology has the following drawbacks: the PIN diode uses a homojunction structure, resulting in a relatively high turn-on voltage and a relatively high limiting level for the limiting circuit. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of the prior art by proposing a gallium nitride heterojunction PIN and SBD diode pair integrated device, which aims to solve the problems of long response time, limited power capacity, and low integration density of the existing discrete PIN diodes and SBD diodes used in limiting circuits.

[0007] The idea behind this invention is to arrange a first-stage PIN diode pair, a second-stage SBD diode pair, and a third-stage SBD diode pair in parallel on a silicon carbide substrate. The P-type layer of the first-stage PIN diode pair uses heavily doped nickel oxide or copper oxide, forming a heterojunction quasi-vertical structure. This heterojunction quasi-vertical structure reduces the turn-on voltage of the PIN diode, further shortening the device's response time. The Schottky anodes of the second and third-stage SBD diode pairs use different metal materials to ensure a progressively decreasing turn-on voltage, meeting the requirements for progressive limiting. The device of this invention connects the anode and cathode of the diode pairs through an air bridge structure, and then connects the three-stage diode pairs through a common cathode structure, thereby solving the problem of low integration density in the limiting circuit of this invention. The device of this invention has a three-stage limiting function; the first-stage heterojunction PIN diode pair acts as the first-stage limiting, and the second and third-stage SBD diode pairs act as the second and third-stage limiting, respectively. This allows the device to combine the high-power characteristics of PIN diodes with the fast response characteristics of SBD diodes, thus solving the problems of long response time and low power capacity in the limiting circuit of this invention.

[0008] The integrated device of this invention includes a silicon carbide substrate, a heavily doped gallium nitride (GaN) n+ layer, an intrinsic GaN n- layer, a nickel oxide or copper oxide (NiO) p+ layer, a common cathode, a PIN junction anode, a Schottky junction anode, an air bridge structure, and an isolation trench extending from the center of the n+ layer perpendicular to the cross-sectional direction of the device to the surface of the silicon carbide substrate. On the same silicon carbide substrate, a first-stage heterojunction PIN diode pair and second and third-stage SBD diode pairs are arranged side-by-side. The first-stage PIN diode pair consists of two structurally identical heterojunction PIN diodes, and the second and third-stage SBD diode pairs each consist of two structurally identical SBD diodes. The two diodes in each stage pair are symmetrically distributed along the center perpendicular to the cross-sectional direction of the device and have identical structures. The air bridge structure connects the anode of one side of the diode and the cathode of the symmetrical diode, realizing the diode pair structure. Each stage pair is cascaded through a common cathode structure on one side of the diode.

[0009] Compared with the prior art, the present invention has the following advantages:

[0010] First, the present invention sets the GaN PIN as a heterojunction quasi-vertical structure, which overcomes the defect of high turn-on voltage of PIN diodes in the prior art. This makes the first-stage PIN diode of the present invention have a lower turn-on voltage, reduces the leakage current of the device, reduces the response time of the first-stage PIN diode when it is working, and improves the operating frequency of the present invention. This is beneficial to improving the fast response characteristics of the present invention when it is used in a limiting circuit.

[0011] Secondly, the present invention integrates the first-stage heterojunction PIN pair, the second-stage and third-stage SBD pair on the same silicon carbide substrate through an anode pillar structure and a common cathode, overcoming the shortcomings of the existing discrete diode cascaded limiting circuits, which are not easy to integrate and have a large circuit volume. This makes the device of the present invention more integrated for limiting circuits, enhances the compactness of the circuit, and is beneficial for integrating the device into high-power limiting circuits.

[0012] Third, the present invention adopts a quasi-vertical structure of transistor integrated devices and a three-stage cascaded limiting structure, which overcomes the shortcomings of low power capacity of existing cascaded limiting circuits, giving the present invention the characteristic of high voltage resistance, which is beneficial for the use of the device in high-power limiting circuits. Attached Figure Description

[0013] Figure 1 This is a schematic cross-sectional view of the device structure of the present invention;

[0014] Figure 2 This is a process flow diagram of the device of the present invention;

[0015] Figure 3 This is a schematic diagram of the working principle of the high-power transistor limiting circuit of the present invention. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0017] Reference Figure 1 The structure of a gallium nitride heterojunction PIN and SBD pair integrated device of the present invention will be further described.

[0018] Figure 1 In this invention, the device has a first-stage PIN diode pair and second and third-stage SBD diode pairs arranged side-by-side on the same silicon carbide substrate 1. The first-stage PIN diode pair consists of two heterojunction PIN diodes with identical structures, and the second and third-stage SBD diode pairs each consist of two SBD diodes with identical structures.

[0019] The two single tubes of each stage are symmetrically distributed along the middle of the direction perpendicular to the cross-section of the device, and their structures are exactly the same. To ensure that the single tubes on both sides are isolated from each other, an isolation trench is set on the n+ layer 2 along the middle of the direction perpendicular to the cross-section of the device, extending to the surface of the silicon carbide substrate 1.

[0020] The structure of the device of the present invention will be described below using one side of the three-stage transistor as an example. The structure of the three-stage single transistor on the other side is exactly the same as that side.

[0021] The device of this invention is deposited from bottom to top as follows: a silicon carbide substrate 1, an n+ layer 2, and above the n+ layer 2, an n- layer 31, a common cathode 5, an n- layer 32, and an n- layer 33 are deposited side-by-side. Above the n- layer 31, a p+ layer 4 and a PIN junction anode 6 are deposited sequentially. Above the n-layer 32 and n-layer 33, Schottky anodes 7 and 8 are deposited, respectively. A PIN single transistor with a heterojunction quasi-vertical structure, consisting of the PIN junction anode 6, p+ layer 4, n-layer 31, n+ layer 2, and common cathode 5, is connected to the anode of the PIN single transistor and the cathode of a symmetrical PIN single transistor via an air bridge structure, forming a first-stage PIN pair. A SBD single transistor with a quasi-vertical structure, consisting of the Schottky junction anode 7, n-layer 32, n+ layer 2, and common cathode 5, is connected to the anode of the SBD single transistor and the cathode of a symmetrical SBD single transistor via an air bridge structure, forming a second-stage SBD pair. A single SBD tube with a quasi-vertical structure, consisting of a Schottky junction anode 8, an n-layer 33, an n+ layer 2, and a common cathode 5, is connected to the anode of a symmetrical SBD tube via an air bridge structure, forming a third-stage SBD pair. The single tubes on each side of the three-stage pair are cascaded through a common cathode structure.

[0022] The silicon carbide substrate 1 has a thickness of 100–5000 μm and a doping concentration of 10. 18 cm -3 -10 20 cm -3 The thickness of the heavily doped gallium nitride n+ layer 2 is 0.1–5 μm, and the doping concentration is 10.18 cm -3 ~10 20 cm -3 The thickness of the intrinsic gallium nitride n-layers 31, 32, and 33 ranges from 1 to 100 μm, with a doping concentration of 10. 14 cm -3 ~10 15 cm -3 The p+ layer 4 is made of p-type nickel oxide or p-type copper oxide, with a thickness of 0.1–5 μm and a doping concentration of 10. 18 cm -3 ~10 20 cm -3 .

[0023] In the device structure of Embodiment 1 of the present invention, the heavily doped P+ layer is made of nickel oxide with a thickness of 100 nm, the Schottky anode of the second-stage SBD pair is made of Ni / Au metal with a thickness of 50 / 100 nm, and the Schottky anode of the third-stage SBD pair is made of W metal with a thickness of 100 nm.

[0024] Reference Figure 2 The preparation process of Example 1 of the present invention will be further described below.

[0025] Step 1: Clean the epitaxial wafer.

[0026] Step 1.1: Select an epitaxial wafer.

[0027] Reference Figure 2 (a) Further description of the epitaxial wafer selected in Embodiment 1 of the present invention.

[0028] In this embodiment of the invention, an epitaxial wafer material is selected from bottom to top as follows: a heavily doped n-type silicon carbide substrate 1, a heavily doped gallium nitride n+ layer 2, and a gallium nitride intrinsic n- layer 3. The silicon carbide substrate 1 has a thickness of 100 μm and a doping concentration of 5 × 10⁻⁶. 18 cm -3 The thickness of the heavily doped gallium nitride n+ layer 2 is 2 μm, and the doping concentration is 2 × 10⁻⁶. 18 cm -3 The thickness of the intrinsic n-layer 3 of gallium nitride is 2 μm, and the doping concentration is 2 × 10⁻⁶. 14 cm -3 .

[0029] Step 1.2: Clean the epitaxial wafer.

[0030] The epitaxial wafer was ultrasonically cleaned in acetone, isopropanol, and deionized water for 5 minutes each. Then, the epitaxial wafer was immersed in 10% HF solution for 2 minutes. Finally, the epitaxial wafer was cleaned with deionized water and dried with nitrogen.

[0031] Step 2, etching the tabletop.

[0032] Step 2.1: Perform photolithography on the cleaned epitaxial wafer material. Use RIE or ICP etching equipment to etch an isolation trench on the n+ layer 2 along the middle of the direction perpendicular to the cross-section of the device, extending to the surface of the silicon carbide substrate, to expose the silicon carbide substrate for isolating the transistor.

[0033] Step 2.2, etch n-intrinsic layer 3.

[0034] Reference Figure 2 (b) The steps of etching the n-intrinsic layer 3 in Example 1 are further described.

[0035] Using RIE or ICP etching equipment, the n-intrinsic layer 3 of the patterned area is etched away, leaving three portions of the n-intrinsic layer 31, 32, and 33, exposing the gallium nitride n+ layer 2. The etched epitaxial wafer is then placed in an RTP rapid thermal annealing furnace and annealed in an N2 atmosphere at a low temperature of 400-500℃ for 5 minutes to repair the etching damage.

[0036] Step 3, make the common cathode 5.

[0037] Reference Figure 2 (c) The steps for fabricating the common cathode 5 in Example 1 are further described.

[0038] Step 3.1: On the clean epitaxial wafer, the following steps are performed sequentially: homogenization, baking, photolithography of the common cathode region 5, and development. Then, using electron beam evaporation, under the conditions of 30W power and 5E-4Pa vacuum, a 22 / 140 / 55 / 45nm Ti / Al / Ni / Au metal stack is deposited in the cathode region at an evaporation rate of 0.1nm / s.

[0039] Step 3.2: First, soak the epitaxial wafer with deposited Ti / Al / Ni / Au metal stack in acetone solution to remove the metal in the photoresist area. Then, put the epitaxial wafer into acetone, anhydrous ethanol and deionized water solution in sequence for ultrasonic cleaning for 5 minutes each. After drying with nitrogen, put it into a rapid annealing furnace for annealing to form a common cathode 5.

[0040] Step 4: Sputter a heavily doped P+ nickel oxide layer.

[0041] Reference Figure 2 (d) The steps of sputtering the P-type nickel oxide layer 4 in Example 1 are further described.

[0042] A pattern is formed on the n-intrinsic layer 31 by photolithography, and then a P-type nickel oxide layer 4 with a thickness of 100 nm is sputtered in the patterned area by magnetron sputtering.

[0043] Step 5, fabricate the PIN junction anode 6.

[0044] Reference Figure 2 (e) The steps for fabricating the PIN junction anode 6 in Example 1 are further described.

[0045] A pattern is formed by photolithography on the p-type nickel oxide layer 4, and then the epitaxial wafer is placed in an electron beam evaporation stage to deposit 15 / 20nm Ni / Au as the first-stage PIN junction anode electrode 6.

[0046] Step 6: Fabricate the Schottky junction anode.

[0047] Step 6.1, fabricate the Schottky junction anode 7.

[0048] Reference Figure 2 (f) The steps for preparing the Schottky junction 7 in Example 1 are further described.

[0049] A pattern is formed on the n-intrinsic layer 32 by photolithography, and then the epitaxial wafer is placed in an electron beam evaporation stage to deposit 50 / 100nm Ni / Au as the second-stage Schottky junction anode electrode 7.

[0050] Step 6.2, fabricate the Schottky junction anode 8

[0051] Reference Figure 2 (g) The steps for fabricating the Schottky junction anode 8 in Example 1 are further described.

[0052] A pattern is formed by photolithography on the n-intrinsic layer 33, and then the epitaxial wafer is placed in an electron beam evaporation stage to deposit 100nm W as the third-stage Schottky junction anode electrode 8.

[0053] Step 7: Construct the air bridge structure.

[0054] Step 7.1: Fabricate the air bridge structure for the first-stage PIN pair.

[0055] Reference Figure 2 (h) further describes the air bridge structure for fabricating the first-stage PIN pair in Example 1.

[0056] Using the standard air bridge process, photoresist is used to shape the bridge piers in the patterned area, a seed layer is sputtered, and metal plating is applied to the bridge surface. The anode 6 of the left PIN tube is connected to the cathode 5 of the right PIN tube to form an air bridge structure.

[0057] Step 7.2: Fabricate the air bridge structure for the second and third stage SBD tubes.

[0058] Reference Figure 2 (i) Further description of the air bridge structure for the second and third stage SBD pairs in Example 1.

[0059] Using the standard air bridge process, photoresist is used to shape the bridge piers in the patterned area, a seed layer is sputtered, and metal is electroplated on the bridge surface. The anodes 7 and 8 of the left single tube in the second and third stage SBD pairs are connected to the cathode 5 of the symmetrical right single tube to complete the fabrication of the device.

[0060] The device structure of Embodiment 2 of the present invention differs from that of Embodiment 1 in that the heavily doped P+ layer 4 in the device structure of Embodiment 2 is made of nickel oxide with a thickness of 200 nm, the Schottky anode 7 of the second-stage SBD pair is made of Ni metal with a thickness of 100 nm, and the Schottky anode 8 of the third-stage SBD pair is made of W metal with a thickness of 100 nm.

[0061] The device fabrication process in Embodiment 2 of the present invention is the same as that in Embodiment 1.

[0062] The device structure of Embodiment 3 of the present invention differs from that of Embodiments 1 and 2 in that the heavily doped P+ layer 4 in the device structure of Embodiment 1 of the present invention is made of copper oxide material with a thickness of 200 nm, the Schottky anode 7 of the second-stage SBD pair is made of Ni / Au metal with a thickness of 50 / 100 nm, and the Schottky anode 8 of the third-stage SBD pair is made of Mo metal with a thickness of 100 nm.

[0063] The device fabrication process in Example 3 of this invention is the same as that in Example 1.

[0064] Reference Figure 3 The working principle of the high-power three-stage transistor integrated device of the present invention integrated in the limiting circuit is further described.

[0065] The limiting circuit integrated by this invention consists of two parts: a gallium nitride heterojunction PIN and SBD transistor pair integrated device and a microstrip line L that serves as the connection. The device provides three levels of limiting: the first-level PIN transistor pair acts as the first-level limiting, and the second and third-level SBD transistor pairs act as the second and third-level limiting, respectively. The microstrip line L is divided into two segments with different parameters. The anode of the upper PIN transistor in the first-level pair is connected to microstrip line L1, and the anode of the upper SBD transistor in the third-level pair is connected to microstrip line L2. The common cathode at the top of the device is grounded, and the anodes of the lower PIN and SBD transistors are grounded respectively. The internal structure of the device is connected through an air bridge structure and a common cathode structure, achieving overall interconnection of the transistor pairs. Both the first segment L1 and the second segment L2 of the microstrip line are printed on a high-frequency circuit board.

[0066] When an RF signal is input via microstrip line L1, the signal first passes through the first-stage PIN diode pair. If the signal is less than the turn-on voltage of the PIN diode, the limiting effect is not achieved, and the signal passes through without loss, flowing to the second and third-stage SBD diode pairs. Since the turn-on voltage of the SBD diodes in this invention is very low, the limiting effect is achieved. If the signal is greater than the turn-on voltage of the PIN diode, the voltage at the output terminal is the turn-on voltage of the PIN diode, achieving the limiting purpose. At the same time, the second and third-stage SBD diodes will further limit the signal, thereby reducing the threshold level.

[0067] Because the first-stage PIN diode pair in this invention adopts a heterojunction structure, and the second and third-stage SBD diode pairs adopt Schottky anodes made of different metal materials, the limiting circuit based on the gallium nitride heterojunction PIN and SBD diode pair integrated device designed in this way greatly reduces the circuit response time, improves the threshold level, and significantly enhances the power capacity of the circuit compared with the conventional all-PIN diode cascaded limiting structure.

[0068] The above description is merely three specific examples of the present invention and does not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A gallium nitride heterojunction PIN and SBD pair integrated device, comprising a silicon carbide substrate (1), a heavily doped n+ layer of gallium nitride (2), a first n- layer of gallium nitride (31), a second n- layer of gallium nitride (32), a third n- layer of gallium nitride (33), a heavily doped p+ layer (4), a common cathode (5), a PIN junction anode (6), Schottky junction anodes (7) and (8), an air bridge structure and a separation groove along the vertical direction of the device cross section, which is in the middle of the n+ layer (2) and reaches the surface of the silicon carbide substrate (1); characterized in that, The first-stage heterojunction PIN pair tube and the second and third-stage SBD pair tubes are arranged side by side on the same silicon carbide substrate (1), wherein the first-stage PIN pair tube is composed of two heterojunction PIN single tubes with the same structure, and the second and third-stage SBD pair tubes are respectively composed of two SBD single tubes with the same structure; the two single tubes of each pair tube are symmetrically distributed along the middle of the direction perpendicular to the cross section of the device, and have the same structure; the anode of one single tube and the cathode of the symmetric single tube are connected by an air bridge structure to realize the pair tube structure; the devices are cascaded by the common cathode structure of the one-side single tubes between each pair tube. 2.The gallium nitride heterojunction PIN and SBD pair tube integrated device of claim 1, wherein: The n+ layer (2) is deposited above the silicon carbide substrate (1), the first gallium nitride n- layer (31), the common cathode (5), the second gallium nitride n- layer (32) and the third gallium nitride n- layer (33) are deposited side by side above the n+ layer (2); the p+ layer (4) and the PIN junction anode (6) are sequentially deposited above the first gallium nitride n- layer (31); the Schottky anodes (7) and (8) are respectively deposited above the second gallium nitride n- layer (32) and the third gallium nitride n- layer (33).

3. The GaN heterojunction PIN and SBD pair integrated device of claim 1, wherein: The PIN junction anode (6), the p+ layer (4), the first gallium nitride n- layer (31), the n+ layer (2) and the common cathode (5) constitute a quasi-vertical structure heterojunction PIN single tube, the anode of one PIN single tube and the cathode of the symmetric PIN single tube are connected by an air bridge structure to form the first-stage PIN pair tube; the Schottky junction anode (7), the second gallium nitride n- layer (32), the n+ layer (2) and the common cathode (5) constitute a quasi-vertical structure SBD single tube, the anode of one SBD single tube and the cathode of the symmetric SBD single tube are connected by an air bridge structure to form the second-stage SBD pair tube; the Schottky junction anode (7), the third gallium nitride n- layer (33), the n+ layer (2) and the common cathode (5) constitute a quasi-vertical structure SBD tube, the anode of one SBD single tube and the cathode of the symmetric SBD single tube are connected by an air bridge structure to form the third-stage SBD pair tube.

4. The GaN heterojunction PIN and SBD pair integrated device of claim 1, wherein: The thickness of the heavily doped gallium nitride n+ layer is 0.1-5 μm, and the doping concentration is 10 18 -10 20 cm -3 The thickness of the gallium nitride intrinsic n- layer is 1-100 μm, and the doping concentration is 10 14 -10 16 cm -3 .

5. The GaN heterojunction PIN and SBD pair integrated device of claim 1, wherein: The heavily doped P-type layer adopts nickel oxide material or copper oxide material, the thickness is 0.1-5 μm, the doping concentration is 10 18 -10 20 cm -3 .

6. The GaN heterojunction PIN and SBD pair integrated device of claim 1, wherein: The metal material of the common cathode (5) is Ti / Al, Ti / Al / Ni / Au, Ti / Al / Ti / Au or Ti / Al / Pt / Au; the thickness of each layer is 20-200 nm, and the total thickness is not more than 500 nm.

7. The GaN heterojunction PIN and SBD pair integrated device of claim 1, wherein: The metal material of the PIN junction anode (6) is Ti / Au, Ni / Au or Ti / Al, the thickness of the first layer of metal is 15-100 nm, and the thickness of the second layer of metal is 20-200 nm.

8. The GaN heterojunction PIN and SBD pair integrated device of claim 1, wherein: The metal material of the Schottky junction anode is any one or any combination of Ni, Pt, Pd, Au and W, the thickness of each layer of metal is 20-200 nm, and the total thickness is not more than 500 nm.

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