Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. A semiconductor device includes a gate structure including a plurality of conductive layers and a plurality of insulating layers alternately laminated, a channel layer penetrating the gate structure, a plurality of memory patterns respectively between the channel layer and the plurality of conductive layers, a plurality of air gaps between the plurality of memory patterns, and a sealing layer including a plurality of first portions respectively including the air gaps and a second portion extending between the plurality of memory patterns.

Description

Technical Field

[0001] This disclosure generally relates to electronic devices, and more specifically, to a semiconductor device and a method of manufacturing a semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. As improvements in the integration density of semiconductor devices with memory cells formed in a single layer on a substrate have reached their limits, three-dimensional semiconductor devices with memory cells stacked on top of a substrate have recently been proposed. Various structures and manufacturing methods have been developed to improve the operational reliability of three-dimensional semiconductor devices. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor device may be provided, the semiconductor device comprising: a gate structure including a plurality of conductive layers and a plurality of insulating layers alternately stacked; a channel layer penetrating the gate structure; a plurality of memory patterns respectively located between the channel layer and the plurality of conductive layers; a plurality of air gaps located between the plurality of memory patterns; and a sealing layer including a plurality of first portions respectively including air gaps and second portions extending between the plurality of memory patterns.

[0004] According to another aspect of this disclosure, a method for manufacturing a semiconductor device may be provided, the method comprising the steps of: forming a stacked structure comprising a plurality of alternatingly stacked first material layers and a plurality of second material layers; forming a first opening penetrating the stacked structure; forming a plurality of sacrificial patterns on the second material layers; forming a barrier layer surrounding the sacrificial patterns in the first opening; forming a memory pattern between the plurality of sacrificial patterns; exposing the sacrificial patterns by etching a portion of the barrier layer exposed by the memory pattern; forming an air gap by removing the sacrificial patterns; and forming a sealing layer in the air gap. Attached Figure Description

[0005] Examples of embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein.

[0006] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between those two elements, or there may be one or more intermediate elements. Similar reference numerals always indicate similar elements.

[0007] Figure 1A , Figure 1B and Figure 1C This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 4A , Figure 4B and Figure 4C This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F and Figure 5G This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 6A and Figure 6B This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 7A and Figure 7B This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 8A , Figure 8B and Figure 8C This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G , Figure 9H , Figure 9I , Figure 9J and Figure 9K This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 10A , Figure 10B and Figure 10C This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 11A , Figure 11B , Figure 11C , Figure 11D and Figure 11E This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 12 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0019] Figure 13 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0020] Figure 14 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0021] Figure 15 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0022] Figure 16 This is a diagram illustrating a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0023] The specific structural or functional descriptions disclosed herein are merely illustrative in order to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0024] The embodiments provide a semiconductor device with a stable structure and improved properties, and a method for manufacturing the semiconductor device.

[0025] Figures 1A to 1C This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0026] Reference Figures 1A to 1C The semiconductor device may include a gate structure GST, a channel layer 18, a memory pattern 16, a barrier layer 14, and an air gap AG. The semiconductor device may also include a tunnel insulating layer 17 or an insulating core 19, or a combination thereof. In embodiments, the air gap AG may include various gases such as air, but is not limited to oxygen and nitrogen; it may be any gas or combination of gases.

[0027] The gate structure GST may include alternating layers of conductive layers 11 and insulating layers 12. The conductive layers 11 may be gate electrodes for memory cells, select transistors, etc. The conductive layers 11 may include conductive materials such as polysilicon, tungsten, molybdenum, or metals. The insulating layers 12 may be used to insulate the stacked conductive layers 11 from each other. The insulating layers 12 may include insulating materials such as oxides, nitrides, or air gaps.

[0028] The channel layer 18 can penetrate the gate structure GST. The channel layer 18 can extend in the stacking direction of the conductive layer 11 and the insulating layer 12. The channel layer 18 can be a region forming a channel for a memory cell, selection transistor, etc. The channel layer 18 can include a semiconductor material. In embodiments, the channel layer 18 can include silicon, germanium, nanostructures, etc. The semiconductor device can include a conductive layer instead of the channel layer 18. The conductive layer can be an electrode layer, a vertical bit line, etc.

[0029] Memory patterns 16 may be located between channel layer 18 and conductive layer 11. Memory patterns 16 may be isolated from each other. Each memory pattern 16 may have sloping sidewalls SW. Sidewalls SW may have curved surfaces. Each memory pattern 16 may have a trapezoidal cross-section. Memory patterns 16 may include floating gates, charge trapping materials, polysilicon, nitrides, variable resistance materials, phase change materials, etc., or combinations thereof.

[0030] The barrier layer 14 may include a first portion 14_P1 located between the conductive layer 11 and the memory pattern 16, and a second portion 14_P2 extending between the memory patterns 16. The first portion 14_P1 and the second portion 14_P2 may be arranged alternately. The barrier layer 14 may extend in the stacking direction of the gate structure GST.

[0031] The air gap AG can be located between the barrier insulating layer 14 and the insulating layer 12. The air gap AG can be defined by the sidewalls 12_SW of the barrier layer 14 and the insulating layer 12. A second portion 14_P2 of the barrier layer 14 can be located between the air gap AG and the channel layer 18. The air gap AG can be closer to the channel layer 18 than the sidewall 11_SW of the conductive layer 11.

[0032] Each air gap AG may include a first surface S1 facing the insulating layer 12 and a second surface S2 facing the barrier layer 14. The first surface S1 may have a shape corresponding to the sidewall 12_SW of the insulating layer 12. The first surface S1 may be flat. The first surface S1 may be aligned with the sidewall 11_SW of the conductive layer 11. The second surface S2 may have a shape corresponding to the barrier layer 14. The second surface S2 may include a curved surface.

[0033] The tunnel insulation layer 17 may be formed around the trench layer 18. The tunnel insulation layer 17 may contact the memory pattern 16 and the barrier layer 14. The tunnel insulation layer 17 may contact the second portion 14_P2 of the barrier layer 14.

[0034] An insulating core 19 may be formed in the channel layer 18. The insulating core 19 may have a single-layer or multi-layer structure. The insulating core 19 may include an insulating material such as oxide, nitride, or air gap. In an embodiment, the insulating core 19 may be omitted, and the channel layer 18 may have a form in which the channel layer 18 is filled in its center.

[0035] Reference Figure 1B and Figure 1C The barrier layer 14 may include a barrier pattern 14P. The barrier patterns 14P may be isolated from each other. Each barrier pattern 14P may have a C-shaped cross section and surround the memory pattern 16 respectively. An air gap AG may be defined by the barrier pattern 14P, the sidewall 12_SW of the insulating layer 12, and the tunnel insulating layer 17. The second surface S2 of each air gap AG may face the barrier pattern 14P and the tunnel insulating layer 17.

[0036] Referring to 1C, the sidewall 12_SW of the insulating layer 12 may be farther from the channel layer 18 than the sidewall 11_SW of the conductive layer 11. The first surface S1 of each air gap AG may be farther from the channel layer 18 than the sidewall 11_SW of the conductive layer 11.

[0037] According to the above structure, memory cells or select transistors may be located at the intersection of the channel layer 18 and the conductive layer 11. A spatial region may be defined between the stacked memory cells, and an air gap AG may be located within the spatial region. The memory patterns 16 of the stacked memory cells may be isolated from each other via the air gap AG.

[0038] In this implementation, the air gap AG can be a blank space between layers and can be filled with air whose dielectric constant is lower than that of oxides and nitrides. Therefore, the cross-connections between stacked memory cells can be reduced by using the air gap AG.

[0039] Figures 2A to 2H This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Descriptions that are repeated above will be omitted in the following text.

[0040] Reference Figure 2A This forms a stacked structure ST. The stacked structure ST may include alternating layers of a first material layer 21 and a second material layer 22. The first material layer 21 may include a material with high etch selectivity relative to the second material layer 22. In one example, the first material layer 21 may include a sacrificial material such as a nitride, and the second material layer 22 may include an insulating material such as an oxide. In another example, the first material layer 21 may include a conductive material such as polysilicon, tungsten, or molybdenum, and the second material layer 22 may include an insulating material such as an oxide.

[0041] Subsequently, a first opening OP1 is formed that penetrates the stacked structure ST. The first opening OP1 may be a plane with a circular shape, an elliptical shape, a polygonal shape, etc. In an embodiment, multiple first openings OP1 may be formed, arranged in a first direction and a second direction intersecting the first direction.

[0042] Reference Figure 2B A first sacrificial pattern 23 is formed on the second material layer 22. The first sacrificial pattern 23 can be selectively deposited on the sidewall of the second material layer 22 exposed through the first opening OP1. Thus, first sacrificial patterns 23 can be formed that protrude into the interior of the first opening OP1 and are isolated from each other. Each first sacrificial pattern 23 may include a first surface 23_S1 facing the second material layer 22 and a second surface 23_S2 protruding into the interior of the first opening OP1. The second surface 23_S2 may include a curved surface. The first sacrificial pattern 23 can be used to ensure the area where an air gap is to be formed in subsequent processes. The first sacrificial pattern 23 may include an oxide.

[0043] Reference Figure 2C A sacrificial pad 24 is formed around a first sacrificial pattern 23 in a first opening OP1. The sacrificial pad 24 can be formed using a deposition process. The sacrificial pad 24 can be formed along the inner surface of the first opening OP1. The sacrificial pad 24 can be formed around the surface of the first sacrificial pattern 23 and the sidewalls of the first material layer 21. The sacrificial pad 24 may include a first portion 24_P1 surrounding the sidewalls of the first material layer 21 and a second portion 24_P2 surrounding the surface of the first sacrificial pattern 23. Each second portion 24_P2 may reflect the shape of the first sacrificial pattern 23. Similar to the first sacrificial pattern 23, each second portion 24_P2 may have a circular cross-section. The sacrificial pad 24 may include a material with high etch selectivity relative to the first sacrificial pattern 23. In embodiments, the sacrificial pad 24 may include nitride or polysilicon, and the first sacrificial pattern 23 may include oxide.

[0044] Reference Figure 2D A second sacrificial pattern 25 is formed between the first sacrificial patterns 23. The second sacrificial pattern 25 can be formed by depositing a second sacrificial layer along the inner surface of the first opening OP1 and then etching the second sacrificial layer. A sacrificial pad 24 may be partially exposed between the second sacrificial patterns 25. A first portion 24_P1 of the sacrificial pad 24 may be covered by the second sacrificial pattern 25, and a second portion 24_P2 of the sacrificial pad 24 may be partially exposed. When each of the second portions 24_P2 has a circular cross-section, the tip portion of the second portion 24_P2 that protrudes most towards the interior of the first opening OP1 may be exposed. The second sacrificial pattern 25 may comprise a material with high etch selectivity relative to the sacrificial pad 24. In an embodiment, the second sacrificial pattern 25 may comprise an oxide, and the sacrificial pad 24 may comprise a nitride.

[0045] Reference Figure 2E A hole H is formed by penetrating the sacrificial pad 24. The hole H can be formed by etching the sacrificial pad 24 using the second sacrificial pattern 25 as an etching barrier. Therefore, the portion of the sacrificial pad 24 exposed through the second sacrificial pattern 25 can be etched. The tip portion of the second portion 24_P2 that protrudes most towards the interior of the first opening OP1 can be etched.

[0046] The first sacrificial pattern 23 can be exposed through the aperture H. When each of the first sacrificial patterns 23 has a circular shape, the tip portion of the first sacrificial pattern 23 that protrudes most towards the interior of the first opening OP1 can be exposed. Therefore, only a very small portion of each of the first sacrificial patterns 23 can be exposed through the aperture H, which has a narrow width.

[0047] The first sacrificial pattern 23 is removed through the aperture H. An air gap AG can be formed between the sacrificial pad 24 and the second material layer 22 by selectively etching the first sacrificial pattern 23.

[0048] Reference Figure 2F The orifice H is sealed. In this embodiment, the sacrificial pad 24 is oxidized. The orifice H can be sealed by volume expansion according to the oxidation process. Because the orifice H has a narrow width, it can be sufficiently sealed by volume expansion. When the sacrificial pad 24 comprises a nitride, a free radical oxidation process can be used to oxidize the sacrificial pad 24. When the sacrificial pad 24 comprises polysilicon, a wet oxidation process or a dry oxidation process can be used to oxidize the sacrificial pad 24.

[0049] An oxidized sacrificial liner can be used as a barrier layer 24A. Barrier layer 24A may include a first portion 24A_P1 corresponding to the first material layer 21 and a second portion 24A_P2 corresponding to the second material layer 22. Air gaps AG may be located between the second portion 24A_P2 and the second material layer 22, respectively. Air gaps AG may be isolated from each other. The second portion 24A_P2 protrudes into the interior of the first opening OP1, thus defining a groove G between the second portions 24A_P2. Grooves G may correspond to the first portion 24A_P1, respectively.

[0050] Reference Figure 2G Memory patterns 26 are formed. Memory patterns 26 can be located between air gaps AG and are isolated from each other. In an embodiment, after depositing a memory layer along the inner surface of the first opening OP1, the memory layer is etched. Therefore, memory patterns 26 can be formed located in the recesses G. The barrier layer 24A can be partially etched during the etching process of the memory layer. Depending on the degree to which the barrier layer 24A is etched, the barrier layer 24A can maintain the air gap AG in a sealed state, or be isolated into a barrier pattern 24AP, leaving the air gap AG open.

[0051] Reference Figure 2H A tunnel insulating layer 27 is formed. The tunnel insulating layer 27 may be formed on the memory pattern 26 and the barrier pattern 24AP. Alternatively, the tunnel insulating layer 27 may be formed on the memory pattern 26 and the barrier layer 14 (see...). Figure 1A When the air gap AG is open during the process of forming the memory pattern 26, the air gap AG can be resealed through the tunnel insulation layer 27.

[0052] Subsequently, a trench layer 28 can be formed in the tunnel insulation layer 27. Subsequently, an insulating core 29 can be formed in the trench layer 28.

[0053] Subsequently, the first material layer 21 can be replaced with a third material layer 31. In one example, when the first material layer 21 is a sacrificial layer and the second material layer 22 is an insulating layer, the first material layer 21 can be replaced with a conductive layer. In another example, when the first material layer 21 is a conductive layer and the second material layer is an insulating layer, the first material layer 21 can be siliconized. Thus, a gate structure GST in which the third material layer 31 and the second material layer 22 are alternately stacked can be formed.

[0054] According to the manufacturing method described above, a narrow-width hole H can be formed using the shape of the first sacrificial pattern 23. An air gap AG can be formed by removing the first sacrificial pattern 23 through the hole H. Furthermore, the sacrificial gasket 24 is oxidized so that the air gap AG can be formed by sealing the hole H. Therefore, the process for forming the barrier layer 24A can be used to form the air gap AG.

[0055] Figures 3A to 3E This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Descriptions that are repeated above will be omitted in the following text.

[0056] Reference Figure 3A A stacked structure ST is formed. The stacked structure ST may include alternating layers of first material 21 and second material 22. Subsequently, a first opening OP1 penetrating the stacked structure ST is formed. Subsequently, a second opening OP2 is formed by etching the second material layer 22. The second opening OP2 may be connected to the first opening OP1.

[0057] Reference Figure 3B A seed pattern 23A is formed in the second opening OP2. The seed patterns 23A may be located in the second opening OP2 and isolated from each other. The seed patterns 23A can be formed by forming a seed layer in the first opening OP1 and the second opening OP2 and then etching the seed layer. The seed patterns 23A may include polysilicon.

[0058] Reference Figure 3CThe first sacrificial pattern 23B is formed by oxidizing the seed pattern 23A. The seed pattern 23A can be oxidized using a wet oxidation process. The first sacrificial pattern 23B may protrude further into the interior of the first opening OP1 than the sidewalls of the first material layer 21. The first sacrificial pattern 23B may include a second surface 23B_S2 protruding into the interior of the first opening OP1, and the second surface 23B_S2 may have a curved surface. Each first sacrificial pattern 23B may have a circular cross-section.

[0059] Reference Figure 3D A sacrificial pad 24 is formed around the first sacrificial pattern 23B in the first opening OP1. Subsequently, a second sacrificial pattern 25 is formed between the first sacrificial patterns 23B. Then, an aperture H is formed by etching the portion of the sacrificial pad 24 exposed through the second sacrificial pattern 25. The first sacrificial pattern 23B can be exposed through the aperture H.

[0060] Reference Figure 3E The first sacrificial pattern 23B is removed through the orifice H. Subsequently, a barrier layer 24A is formed by oxidizing the sacrificial liner 24. Thus, the orifice H can be sealed.

[0061] According to the manufacturing method described above, the seed pattern 23A is oxidized to form the first sacrificial pattern 23B. Subsequent processes can be referenced above. Figure 2G and Figure 2H The methods described are performed similarly. Furthermore, this implementation can be combined with the implementations described above.

[0062] Figures 4A to 4C This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Descriptions of portions that are repeated above will be omitted hereinafter.

[0063] Reference Figure 4A The semiconductor device may include a gate structure GST, a channel layer 48, a memory pattern 46, and an air gap AG. The semiconductor device may also include an insulating pad 44, a tunnel insulating layer 47, a barrier layer 45, or an insulating core 49, or a combination thereof.

[0064] The gate structure GST may include alternating layers of conductive layer 41 and insulating layer 42. A channel layer 48 may penetrate the gate structure GST. A memory pattern 46 may be located between the channel layer 48 and the conductive layer 41. An insulating core 49 may be formed in the channel layer 48.

[0065] The barrier layer 45 may include a first portion 45_P1 located between the conductive layer 41 and the memory pattern 46, and a second portion 45_P2 extending between the memory patterns 46. In one embodiment, each of the second portions 45_P2 may extend between the first portions 45_P1 and may be located between the insulating layer 42 and the corresponding air gap AG to space the insulating layer 42 from the corresponding air gap AG. The second portions 45_P2 may protrude toward the insulating layer 42 into the interior of the gate structure GST.

[0066] Air gaps AG may be located between the barrier layer 45 and the channel layer 48. Air gaps AG may be located between the tunnel insulation layer 47 and the second portion 45_P2. Each air gap AG may include a first region AG_R1 located in the second portion 45_P2 and a second region AG_R2 located between memory patterns 46. The first region AG_R1 may have a first width W1, and the second region AG_R2 may have a second width W2. When the second region AG_R2 has a circular cross-section, the second width W2 may be the maximum width of the second region AG_R2. The first width W1 and the second width W2 may be substantially the same as or different from each other. The first width W1 may be narrower than the second width W2.

[0067] The insulating pad 44 may be located between the tunnel insulation layer 47 and the barrier layer 45. The insulating pad 44 may be formed on the sidewall of the memory pattern 46 and may extend between the memory pattern 46 and the barrier layer 45.

[0068] A tunnel insulation layer 47 may be located between the trench layer 48 and the memory pattern 46, and between the trench layer 48 and the air gap AG. The tunnel insulation layer 47 may contact the memory pattern 46 and the insulating pad 44. Therefore, the air gap AG may be defined by the tunnel insulation layer 47, the insulating pad 44, and the barrier layer 45. Each air gap AG may include a second surface S2 facing the tunnel insulation layer 47, and the second surface S2 may be flat. Each air gap AG may include a third surface S3 facing the insulating pad 44, and the third surface S3 may include a curved surface.

[0069] Reference Figure 4B The insulating pad 44A can be formed only on the sidewall SW of the memory pattern 46. The structure other than the insulating pad 44A can be... Figure 4A The structure shown is similar.

[0070] Reference Figure 4C as well as Figure 4CAs shown by the dashed lines and arrows, each air gap AG can protrude into the interior of the tunnel insulation layer 47A. Therefore, the outer surface of the tunnel insulation layer 47A can have an unevenness. The air gap AG can protrude further toward the channel layer 48 than the memory pattern 46. Each air gap AG may include a second surface S2 facing the tunnel insulation layer 47A, and the second surface S2 may include a curved surface. Structures other than the tunnel insulation layer 47A can be... Figure 4A or Figure 4B The structure shown is similar.

[0071] According to the above structure, memory cells or select transistors can be located at the intersection of the channel layer 48 and the conductive layer 41. Spatial regions can be defined between the stacked memory cells, and air gaps AG can be located in these spatial regions. The memory patterns 46 of the stacked memory cells can be isolated from each other by the air gaps AG. Cross-connections between the stacked memory cells can be reduced by the air gaps AG.

[0072] Figures 5A to 5G This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Descriptions that are repeated above will be omitted in the following text.

[0073] Reference Figure 5A A stacked structure ST is formed. The stacked structure ST may include alternating layers of a first material layer 51 and a second material layer 52. The first material layer 51 may include a material with high etch selectivity relative to the second material layer 52. Subsequently, a first opening OP1 penetrating the stacked structure ST is formed. Subsequently, a second opening OP2 is formed by etching the second material layer 52. The second opening OP2 may be connected to the first opening OP1.

[0074] Reference Figure 5B A barrier layer 55 is formed in the first opening OP1 and the second opening OP2. A deposition process can be used to form the barrier layer 55. The barrier layer 55 can be formed along the inner surfaces of the first opening OP1 and the second opening OP2. The barrier layer 55 can completely fill or partially fill the second opening OP2. The barrier layer 55 may include a first portion 55_P1 formed in the first opening OP1 and a second portion 55_P2 formed in the second opening OP2. Each second portion 55_P2 may include a groove G caused by the second opening OP2.

[0075] Reference Figure 5CSacrificial patterns 53 are formed. The sacrificial patterns 53 can be formed in the grooves G of the barrier layer 55. In one embodiment, after a seed layer is formed in the first opening OP1, the seed layer is etched. Thus, seed patterns are formed in the grooves G. Subsequently, seed material is selectively deposited on the seed patterns. Therefore, the seed patterns can grow into sacrificial patterns 53. The sacrificial patterns 53 can protrude into the interior of the first opening OP1. Each sacrificial pattern 53 can have a circular cross-section.

[0076] The sacrificial pattern 53 may include a material that is etch-selective relative to the barrier layer 55. The sacrificial pattern 53 may include a material that is etch-selective relative to oxides and nitrides. In one embodiment, the barrier layer 55 may include an oxide, and the sacrificial pattern 53 may include polysilicon.

[0077] Reference Figure 5D An insulating pad 54 is formed around the sacrificial pattern 53 in the first opening OP1. The insulating pad 54 may be deposited along the inner surface of the first opening OP1. The insulating pad 54 may be formed on the surface of the sacrificial pattern 53 and the surface of the barrier layer 55. The insulating pad 54 may comprise a material with high etch selectivity relative to the sacrificial pattern 53. In an embodiment, the insulating pad 54 may comprise an oxide, and the sacrificial pattern 53 may comprise polysilicon. In an embodiment, the insulating pad 54 may be formed by oxidizing the surface of the sacrificial pattern 53.

[0078] Reference Figure 5E Memory patterns 56 can be formed between the sacrificial patterns 53. Memory patterns 56 can be formed by depositing a memory layer along the inner surface of the first opening OP1 and then etching the memory layer. Insulating pads 54 can be partially exposed between the memory patterns 56.

[0079] Reference Figure 5F A hole H is formed through the insulating pad 54. The hole H can be formed by etching the insulating pad 54 exposed through the memory pattern 56. The sacrificial pattern 53 can be exposed through the hole H.

[0080] Subsequently, the sacrificial pattern 53 is removed through the aperture H. An air gap AG can be formed between the insulating pad 54 and the barrier layer 55 by selectively etching the sacrificial pattern 53.

[0081] Reference Figure 5G A tunnel insulating layer 57 is formed. The via H can be sealed by the tunnel insulating layer 57. The tunnel insulating layer 57 can be formed using a deposition process. In one embodiment, the tunnel insulating layer 57 can be formed by oxidizing the memory pattern 56. Subsequently, a trench layer 58 can be formed in the tunnel insulating layer 57. Subsequently, an insulating core 59 can be formed in the trench layer 58.

[0082] Subsequently, the first material layer 51 can be replaced with a third material layer 61. In one example, when the first material layer 51 is a sacrificial layer and the second material layer 52 is an insulating layer, the first material layer 51 can be replaced with a conductive layer. In another example, when the first material layer 51 is a conductive layer and the second material layer 52 is an insulating layer, the first material layer 51 can be siliconized. Therefore, a gate structure GST in which the third material layer 61 and the second material layer 52 are alternately stacked can be formed.

[0083] According to the manufacturing method described above, the sacrificial pattern 53 is removed through the hole H to form an air gap AG. Furthermore, the hole H can be sealed by the tunnel insulation layer 57. Therefore, the process for forming the tunnel insulation layer 57 can be used to form the air gap AG.

[0084] Figure 6A and Figure 6B This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Descriptions that are repeated above will be omitted in the following text.

[0085] Reference Figure 6A A stacked structure ST is formed. The stacked structure ST may include alternating layers of first material 51 and second material 52. Subsequently, a first opening OP1 penetrating the stacked structure ST is formed. Subsequently, a second opening OP2 is formed by etching the second material layer 52. Subsequently, after forming a barrier layer 55, a sacrificial pattern 53 is formed.

[0086] Subsequently, insulating pads 54A are formed. An oxidation process can be used to form the insulating pads 54A. The surface of the sacrificial pattern 53 can be oxidized by the oxidation process. The insulating pads 54A can be formed to surround the sacrificial pattern 53 and be isolated from each other.

[0087] Reference Figure 6B Memory patterns 56 are formed between the sacrificial patterns 53. The memory patterns 56 can be in direct contact with the barrier layer 55. Each insulating pad 54A can be partially exposed between the memory patterns 56.

[0088] According to the manufacturing method described above, the sacrificial pattern 53 is oxidized to form the insulating pad 54A. Subsequent processes can be referred to above. Figures 5E to 5G The methods described are performed similarly. Furthermore, this implementation can be combined with the implementations described above.

[0089] Figure 7A and Figure 7B This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Descriptions that are repeated above will be omitted in the following text.

[0090] Reference Figure 7AA stacked structure ST is formed. The stacked structure ST may include alternating layers of first material 51 and second material 52. Subsequently, a first opening OP1 penetrating the stacked structure ST is formed. Subsequently, a second opening OP2 is formed by etching the second material layer 52. Subsequently, a barrier layer 55, a sacrificial pattern, an insulating pad 54, and a memory pattern 56 are formed. Subsequently, after forming an aperture H by etching the insulating pad 54, an air gap AG is formed by removing the sacrificial pattern through the aperture H.

[0091] Reference Figure 7B A tunnel insulating layer 57A is formed to seal the hole H. The tunnel insulating layer 57A can be formed using an oxidation process. The tunnel insulating layer 57A can be formed by oxidizing the surface of the memory pattern 56 via an oxidation process. The hole H can be sealed by volume expansion according to the oxidation process. Additionally, the portion of the tunnel insulating layer 57A that seals the hole H can have a relatively thinner thickness compared to the portion in contact with the memory pattern 56A. Each air gap AG can include a second surface facing the tunnel insulating layer 57A, and the second surface S2 can include a curved surface. The air gap AG can protrude further toward the first opening OP1 than the sidewall of the memory pattern 56A; therefore, the air gap AG can be closer to the first opening OP1 than the memory pattern 56A.

[0092] According to the manufacturing method described above, the memory pattern 56 is oxidized to form a tunnel insulating layer 57A that can seal the via H. Therefore, the process for forming the tunnel insulating layer 57A can be used to form the air gap AG. Subsequent processes can be referenced above. Figure 5G The described process is performed similarly. Furthermore, this embodiment can be combined with the embodiments described above.

[0093] Figures 8A to 8C This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Descriptions of portions that are repeated above will be omitted hereinafter.

[0094] Reference Figure 8A The semiconductor device may include a gate structure GST, a channel layer 88, a memory pattern 86, an air gap AG', and a sealing layer 84. The semiconductor device may also include a barrier pattern 85, a tunnel insulating layer 87, or an insulating core 89, or a combination thereof.

[0095] The gate structure GST may include alternating layers of conductive layer 81 and insulating layer 82. A channel layer 88 may penetrate the gate structure. A memory pattern 86 may be located between the channel layer 88 and the conductive layer 81. A barrier pattern 85 may be located between the memory pattern 86 and the conductive layer 81. An insulating core 89 may be located within the channel layer 88.

[0096] Air gap AG' may be located between memory patterns 86. Memory patterns 86 may be isolated from each other by air gap AG'. Air gap AG' may extend between blocking patterns 85. Blocking patterns 85 may be isolated from each other by air gap AG'.

[0097] Each sealing layer 84 may be located between memory patterns 86 and between barrier patterns 85. Each sealing layer 84 may include an air gap AG'. Each sealing layer 84 may include a first region 84_R1 located between barrier patterns 85 and a second region 84_R2 located between memory patterns 86. Each air gap AG' may be located in the first region 84_R1, in the second region 84_R2, or in both the first region 84_R1 and the second region 84_R2.

[0098] The second region 84_R2 may have a circular cross-section. The portion of the second region 84_R2 facing the tunnel insulation layer 87 may include a plane, and the portion of the second region 84_R2 facing the memory pattern 86 may include a curved surface.

[0099] The first region 84_R1 may have a first width W1, and the second region 84_R2 may have a second width W2. When the second region 84_R2 has a circular shape, the second width W2 may be the maximum width of the second region 84_R2. The first width W1 and the second width W2 may be substantially the same as or different from each other. The first width W1 may be narrower than the second width W2.

[0100] The tunnel insulation layer 87 may be located between the trench layer 88 and the memory pattern 86, and between the trench layer 88 and the sealing layer 84. The tunnel insulation layer 87 may contact the memory pattern 86 and the sealing layer 84.

[0101] Reference Figure 8B The sealing layer 84A may include a first portion 84A_P1 and a second portion 84A_P2. The sealing layer 84A may be a single layer comprising the first portion 84A_P1 and the second portion 84A_P2. The first portion 84A_P1 may each include an air gap AG'. The first portion 84A_P1 may correspond to the above reference. Figure 8A The sealing layer 84 is described. A second portion 84A_P2 may extend between the memory pattern 86 and the channel layer 88, and connects the first portion 84A_P1 to each other. The second portion 84A_P2 may surround the sidewall of the channel layer 88. The second portion 84A_P2 may serve as a tunnel insulation layer. In an embodiment, the second portion 84A_P2 may contact the air gap AG'. In an embodiment, the sealing layer 84A may be a single continuous layer comprising the first portion 84A_P1 and the second portion 84A_P2. Structures other than the sealing layer 84A may be... Figure 8A The structure shown is similar.

[0102] Reference Figure 8C Each sealing layer 84B can protrude toward the insulating layer 82 into the interior of the gate structure GST. The air gap AG' can also extend into the interior of the gate structure GST. The structure other than the sealing layer 84B can be integrated with... Figure 8A or Figure 8B The structure shown is similar.

[0103] According to the above structure, memory cells or select transistors can be located at the intersection of the channel layer 88 and the conductive layer 81. A spatial region can be defined between the stacked memory cells, and an air gap AG' can be located within the spatial region. The memory patterns 86 of the stacked memory cells can be isolated from each other by the air gap AG'. The cross-connections between the stacked memory cells can be reduced by the air gap AG'.

[0104] Figures 9A to 9K This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Descriptions that are repeated above will be omitted in the following text.

[0105] Reference Figure 9A A stacked structure ST is formed. The stacked structure ST may include alternating layers of a first material layer 91 and a second material layer 92. The first material layer 91 may include a material with high etch selectivity relative to the second material layer 92. Subsequently, a first opening OP1 is formed that penetrates the stacked structure ST.

[0106] Subsequently, first material patterns 91A are formed on the first material layer 91. The first material patterns 91A can be formed by selectively depositing the first material on the sidewalls of the first material layer 91 exposed through the first opening OP1. Each first material pattern 91A may have a circular cross-section resulting from the deposition process. The first material pattern 91A may substantially comprise the same material as the first material layer 91.

[0107] Reference Figure 9B A sacrificial pattern 93 is formed between the first material patterns 91A. In one embodiment, the sacrificial pattern 93 can be formed by forming a sacrificial layer in the first opening OP1 and then etching the sacrificial layer so that the sacrificial layer remains only between the first material patterns 91A. Each sacrificial pattern 93 may include a protrusion P projecting toward the first material pattern 91A at the surface of the sacrificial pattern 93 that contacts the first material pattern 91A. The protrusion P may be caused by the circular shape of the first material pattern 91A. The sacrificial pattern 93 may include a material that has etch selectivity relative to oxides and nitrides. The sacrificial pattern 93 may include polysilicon.

[0108] Reference Figure 9C The first material pattern 91A is removed. The first material pattern 91A can be selectively etched. Therefore, the sacrificial pattern 93 can protrude into the first opening OP1.

[0109] Reference Figure 9D The sacrificial pattern 93 can be etched. Therefore, the protrusion P of the sacrificial pattern 93 can be removed, and each sacrificial pattern 93 can be smoothed to have a circular cross-section.

[0110] Reference Figure 9E A barrier layer 95 is formed in the first opening OP1. In one embodiment, a deposition process can be used to form the barrier layer 95. The barrier layer 95 can be deposited along the surface of the sacrificial pattern 93 exposed through the first opening OP1 and the sidewalls of the first material layer 91. In another embodiment, an oxidation process can be used to form the barrier layer 95. The oxidation process can be a free radical oxidation process. The barrier layer 95 can be formed by oxidizing the surface of the sacrificial pattern 93 exposed through the first opening OP1 and the sidewalls of the first material layer 91. The barrier layer 95 may include a first portion 95_P1 formed on the sacrificial pattern 93 and a second portion 95_P2 formed on the first material layer 91. The first portion 95_P1 and the second portion 95_P2 may have the same thickness or different thicknesses. The second portion 95_P2 may each include a groove G located between the sacrificial patterns 93.

[0111] Reference Figure 9F Memory patterns 96 are formed. Memory patterns 96 can be formed in the recesses G of the barrier layer 95. In this embodiment, after the memory layer is formed in the first opening OP1, the memory layer is etched. Therefore, memory patterns 96 located in the recesses G can be formed. Furthermore, the respective first portions 95_P1 of the barrier layer 95 can be partially exposed between the memory patterns 96.

[0112] Reference Figure 9G The barrier layer 95 exposed by the memory pattern 96 is etched. Thus, an aperture H exposing the sacrificial pattern 93 can be formed. Depending on the degree to which the barrier layer 95 is etched, each first portion 95_P1 can be partially or completely etched. The exposed area of ​​the sacrificial pattern 93 can increase with the amount of etching of the barrier layer 95. However, the width of the aperture H is determined to be the distance between the memory patterns 96, so the width W of the aperture does not need to be increased.

[0113] In one embodiment, a first portion 95_P1 of the barrier layer 95 can be etched, and a second portion 95_P2 can be retained. The remaining second portion 95_P2 can be used as a barrier pattern 95A. The barrier pattern 95A can be located between the memory pattern 96 and the first material layer 91.

[0114] Reference Figure 9H The sacrificial pattern 93 is removed through the hole H. The air gap AG (i.e., the first air gap AG) can be formed by selectively etching the sacrificial pattern 93.

[0115] Each air gap AG may include a first region AG_R1 located between blocking patterns 95A and a second region AG_R2 located between memory patterns 96. The first region AG_R1 may have a first width W1, and the second region AG_R2 may have a second width W2. The first width W1 and the second width W2 may be substantially the same as or different from each other. The second width W2 may be wider than the first width W1.

[0116] Reference Figure 9I A sealing layer 94 is formed. The sealing layer 94 may include a first portion 94_P1 formed in the air gap AG and a second portion 94_P2 formed in the first opening OP1. The first portion 94_P1 may be sealed by the air gap AG. Therefore, the air gap AG' (i.e., the second air gap AG') may be defined in the first portion 94_P1, and the first portion 94_P1 may include the air gap AG'.

[0117] A deposition process can be used to form the sealing layer 94. A chemical vapor deposition process with a stepped coverage relative to a reference stepped coverage can be used to form a sealing layer 94 with a film quality lower than a reference film quality. A first portion 94_P1 can be formed along the surface of the barrier pattern 95A, the surface of the memory pattern 96, and the sidewall of the second material layer 92. A second portion 94_P2 can be formed by connecting the first portions 94_P1 to each other and along the surface of the memory pattern 96. The sealing layer 94 may include an insulating material such as an oxide.

[0118] Reference Figure 9J The sealing layer 94 is etched. The second portion 94_P2 of the sealing layer 94 can be etched, and the first portion 94_P1 of the sealing layer 94 can be retained. The remaining first portion 94_P1 can become the sealing layer 94A, and the sealing layer 94A can include the air gap AG'. In the process of etching the sealing layer 94, the air gap AG' can be maintained in a sealed state, or the air gap AG' can be reopened.

[0119] Reference Figure 9K A tunnel insulating layer 97 is formed in the first opening OP1. The tunnel insulating layer 97 can contact the sealing layer 94A and the memory pattern 96. The tunnel insulating layer 97 can be formed by depositing an oxide layer with relatively excellent film quality. When the air gap AG' is open, the air gap AG' can be sealed again by the tunnel insulating layer 97. Subsequently, a channel layer 98 can be formed in the tunnel insulating layer 97. Subsequently, an insulating core 99 can be formed in the channel layer 98.

[0120] Subsequently, the first material layer 91 can be replaced with the third material layer 101. In one example, when the first material layer 91 is a sacrificial layer and the second material layer 92 is an insulating layer, the first material layer 91 can be replaced with a conductive layer. In another example, when the first material layer 91 is a conductive layer and the second material layer 92 is an insulating layer, the first material layer 91 can be siliconized. Therefore, a gate structure GST in which the third material layer 101 and the second material layer 92 are alternately stacked can be formed.

[0121] According to the manufacturing method described above, the sacrificial pattern 93 is removed through the hole H to form the air gap AG. Furthermore, the air gap AG can be sealed using a sealing layer 94A or a tunnel insulation layer 97. Therefore, the process for forming the sealing layer 94A or the tunnel insulation layer 97 can be used to form the air gap AG'.

[0122] Figures 10A to 10C This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Descriptions that are repeated above will be omitted in the following text.

[0123] Reference Figure 10A A stacked structure GST is formed. The stacked structure GST may include alternating layers of first material 91 and second material 92. Subsequently, a first opening OP1 penetrating the stacked structure GST is formed. Subsequently, a barrier pattern 95A, a memory pattern 96, and an air gap AG' are formed.

[0124] Reference Figure 10B A sealing layer 94 is formed. The sealing layer 94 may include a first portion 94_P1 formed in the air gap AG' and a second portion 94_P2 formed in the first opening OP1. The sealing layer 94 may be formed using a deposition process. The air gap AG' may be sealed by the first portion 94_P1. The second portion 94_P2 may be used as a tunnel insulation layer.

[0125] Reference Figure 10C A channel layer 98 and an insulating core 99 can be formed in the first opening OP1. Subsequently, the first material layer 91 can be replaced with a third material layer 101. Thus, a gate structure GST in which the third material layer 101 and the second material layer 92 are alternately stacked can be formed.

[0126] According to the manufacturing method described above, the air gap AG' can be sealed using the sealing layer 94, and the second portion 94_P2 of the sealing layer 94 can be used as a tunnel insulation layer. Therefore, the process for forming the sealing layer 94 can be used to form the tunnel insulation layer and the air gap AG'. Furthermore, this embodiment can be combined with the embodiments described above.

[0127] Figures 11A to 11E This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Descriptions that are repeated above will be omitted in the following text.

[0128] Reference Figure 11A A stacked structure ST is formed. The stacked structure ST may include alternating layers of first material 91 and second material 92. Subsequently, a first opening OP1 penetrating the stacked structure ST is formed. Subsequently, a second opening OP2 is formed by etching the second material layer 92.

[0129] Reference Figure 11B Seed patterns 93A are formed in the second opening OP2. Seed patterns 93A may include polysilicon.

[0130] Reference Figure 11C Seed material is selectively deposited on seed pattern 93A. Thus, seed pattern 93A can grow into sacrificial pattern 93B. Sacrificial pattern 93B can protrude into the interior of the first opening OP1. Additionally, sacrificial pattern 93B can protrude towards the second material layer 92 into the interior of the stacked structure ST. Subsequently, barrier layer 95 and memory pattern 96 are formed.

[0131] Reference Figure 11D The hole H exposing the sacrificial pattern 93B is formed by etching the barrier layer 95. Subsequently, the sacrificial pattern 93B is removed. Thus, an air gap AG is formed between the barrier patterns 95A and between the memory patterns 96.

[0132] Reference Figure 11E A sealing layer 94 is formed. The sealing layer 94 may include a first portion 94_P1 formed in the air gap AG and a second portion 94_P2 formed in the first opening OP1. The first portion 94_P1 may protrude toward the interior of the laminated structure ST toward the second material layer 92.

[0133] The first part 94_P1 may include an air gap AG'. The shape of the air gap AG' may vary depending on the thickness of the sealing layer 94. The air gap AG' may be located between the memory patterns 96 and extend between the blocking patterns 95A or extend toward the interior of the stacked structure ST towards the second material layer 92.

[0134] According to the manufacturing method described above, a sealing layer 94 can be formed in the air gap AG. Subsequent processes can be referenced above. Figures 9A to 9K Those described are similar to those mentioned above, or refer to them. Figures 10A to 10C The methods described are performed similarly. Furthermore, this implementation can be combined with the implementations described above.

[0135] Figure 12 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0136] Reference Figure 12The memory system 1000 may include a memory device 1200 configured to store data and a controller 1100 configured to communicate between the memory device 1200 and the host 2000.

[0137] The host 2000 can be a device or system that stores data in or retrieves data from the memory system 1000. The host 2000 can generate requests for various operations and output these requests to the memory system 1000. Requests may include programming requests for programming operations, read requests for read operations, erase requests for erase operations, etc. The host 2000 can communicate with the memory system 1000 through various interfaces such as PCI-E, Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), or High-Speed ​​Non-Volatile Memory (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Form Factor Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0138] The host 2000 may include at least one of a computer, portable digital device, tablet computer, digital camera, digital audio player, television, wireless communication device and cellular phone, but the embodiments disclosed herein are not limited thereto.

[0139] The controller 1100 controls the overall operation of the memory system 1000. The controller 1100 can control the memory device 1200 upon request from the host 2000. The controller 1100 can control the memory device 1200 to perform programming operations, read operations, erase operations, etc., upon request from the host 2000. Alternatively, in the absence of any request from the host 2000, the controller 1100 can perform background operations, etc., to improve the performance of the memory system 1000.

[0140] The controller 1100 can send control signals and data signals to the memory device 1200 to control the operation of the memory device 1200. The control signals and data signals can be sent to the memory device 1200 via different input / output lines. Data signals may include commands, addresses, or data. Control signals can be used to distinguish the time periods of input data signals.

[0141] The memory device 1200 can perform programming operations, read operations, erase operations, etc., under the control of the controller 1100. The memory device 1200 can be implemented using a volatile memory device whose stored data is lost when power is interrupted, or a non-volatile memory device that retains stored data even when power is interrupted. The memory device 1200 can be a device with the above-mentioned reference... Figures 1A to 1C , Figures 4A to 4C or Figures 8A to 8CThe semiconductor device described herein. The memory device 1200 can be configured as described by reference to... Figures 2A to 3E , Figures 5A to 7B or Figures 9A to 11E The semiconductor device is manufactured by the above-described manufacturing method. In an embodiment, the semiconductor device may include: a gate structure comprising alternating layers of conductive and insulating layers; a channel layer penetrating the gate structure; memory patterns located between the channel layer and the conductive layer; an air gap located between the memory patterns; and a sealing layer comprising a first portion including the air gap and a second portion extending between the memory patterns.

[0142] Figure 13 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0143] Reference Figure 13 The memory system 30000 can be implemented as a cellular phone, smartphone, tablet PC, personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100 capable of controlling the operation of the memory device 2200.

[0144] The controller 2100 can control the data access operations (e.g., programming operations, erasing operations, reading operations, etc.) of the memory device 2200 under the control of the processor 3100.

[0145] The data programmed in the memory device 2200 can be output through the display 3200 under the control of the controller 2100.

[0146] The radio transceiver 3300 can transmit / receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and send the processed signals to the controller 2100 or the display 3200. The controller 2100 can send the signals processed by the processor 3100 to the memory device 2200. Alternatively, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 is a device capable of inputting control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200, so that data output from the controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 can be output through the display 3200.

[0147] In some implementations, the controller 2100, which controls the operation of the memory device 2200, may be implemented as part of the processor 3100 or as a separate chip from the processor 3100.

[0148] Figure 14 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0149] Reference Figure 14 The memory system 40000 can be implemented as a personal computer (PC), tablet PC, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player or MP4 player.

[0150] The memory system 40000 may include a memory device 2200 and a controller 2100, the controller 2100 being able to control the data processing operations of the memory device 2200.

[0151] The processor 4100 can output data stored in the memory device 2200 via the display 4300 based on data input through the input device 4200. For example, the input device 4200 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0152] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the controller 2100. In some embodiments, the controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 4100 or as a separate chip from the processor 4100.

[0153] Figure 15 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0154] Reference Figure 15 The memory system 50000 can be implemented as, for example, a digital camera, a mobile terminal with a digital camera attached, a smartphone with a digital camera attached, or an image processing device for a tablet PC with a digital camera attached.

[0155] The memory system 50000 may include a memory device 2200 and a controller 2100 capable of controlling data processing operations (e.g., programming operations, erasing operations, or read operations) of the memory device 2200.

[0156] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals, and the converted digital signals can be sent to the processor 5100 or the controller 2100. Under the control of the processor 5100, the converted digital signals can be output through the display 5300 or stored in the memory device 2200 through the controller 2100. In addition, data stored in the memory device 2200 can be output through the display 5300 under the control of the processor 5100 or the controller 2100.

[0157] In some implementations, the controller 2100, which is capable of controlling the operation of the memory device 2200, may be implemented as part of the processor 5100 or as a separate chip from the processor 5100.

[0158] Figure 16 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0159] Reference Figure 16 The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 2200, a controller 2100, and a card interface 7100.

[0160] The controller 2100 controls the data exchange between the memory device 2200 and the card interface 7100. In some embodiments, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but this disclosure is not limited thereto.

[0161] Card interface 7100 can interface for data exchange between host 60000 and controller 2100 according to the protocol of host 60000. In some embodiments, card interface 7100 can support Universal Serial Bus (USB) protocol and chip-to-chip (IC) USB protocol. Card interface 7100 can refer to hardware, software embedded in hardware, or signal transmission scheme capable of supporting the protocol used by host 60000.

[0162] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (e.g., PC, tablet PC, digital camera, digital audio player, cellular phone, console video game hardware, or digital set-top box), the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the controller 2100 under the control of the microprocessor 6100.

[0163] According to this disclosure, memory cells are stacked in a three-dimensional manner to improve the integration density of the semiconductor device. Furthermore, the semiconductor device can have a stable structure and improved reliability.

[0164] Examples of embodiments of the present disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is for illustrative purposes only. Therefore, the present disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure in addition to the embodiments disclosed herein.

[0165] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the meaning commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms with dictionary definitions shall be understood to have a meaning consistent with the context of the relevant art. Unless clearly defined in this application, terms shall not be interpreted in an ideal or overly formal manner.

[0166] Cross-reference to related applications

[0167] This application claims priority to Korean Patent Application No. 10-2021-0022173, filed with the Korean Intellectual Property Office on February 18, 2021, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure comprising alternatingly stacked conductive layers and insulating layers; A channel layer that penetrates the gate structure; Multiple memory patterns are respectively located between the channel layer and the multiple conductive layers; Multiple air gaps are located between the multiple memory patterns; as well as A sealing layer comprising a plurality of first portions each including the air gap and a second portion extending between the plurality of memory patterns and the channel layer. The sealing layer does not overlap perpendicularly with the conductive layer.

2. The semiconductor device according to claim 1, wherein, The sealing layer is a single layer comprising the first part and the second part.

3. The semiconductor device of claim 1, further comprising a plurality of blocking patterns located between the memory pattern and the conductive layer.

4. The semiconductor device according to claim 3, wherein, Each of the first portions includes a first region located between the plurality of blocking patterns and a second region located between the plurality of memory patterns.

5. The semiconductor device according to claim 4, wherein, The width of the first region is narrower than the width of the second region.

6. The semiconductor device according to claim 4, wherein, The second region has a circular cross-section.

7. The semiconductor device according to claim 1, wherein, Each of the plurality of memory patterns includes a first surface and a second surface having a concave shape, and The first surface and the second surface are in contact with the sealing layer.

8. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a laminated structure comprising alternating layers of first material and layers of second material; Forming a first opening that penetrates the stacked structure; Multiple sacrificial patterns are formed on the second material layer; A barrier layer is formed around the sacrificial pattern in the first opening; A memory pattern is formed between the plurality of sacrifice patterns; The sacrificial pattern is exposed by etching the portion of the barrier layer that is exposed by the memory pattern. An air gap is formed by removing the sacrificial pattern; as well as A sealing layer is formed in the air gap. The sealing layer does not overlap perpendicularly with the first material layer.

9. The method according to claim 8, wherein, The steps for forming the sacrificial pattern include: A plurality of first material patterns are formed on the first material layer; and The sacrificial pattern is formed between the plurality of first material patterns.

10. The method according to claim 8, wherein, The steps for forming the sealing layer include: The sealing layer comprises a first portion formed in the air gap and a second portion formed in the first opening; and The second portion of the sealing layer is etched.

11. The method of claim 10, further comprising the step of: A tunnel insulation layer is formed in the first opening; as well as A trench layer is formed in the tunnel insulation layer.

12. The method according to claim 8, wherein, In the step of forming the barrier layer, the barrier layer is formed by oxidizing the sacrificial pattern and the first material layer.

13. The method according to claim 8, wherein, In the step of forming the sealing layer, the sealing layer is formed including a first portion formed in the air gap and a second portion formed in the first opening, and the second portion serves as a tunnel insulation layer.

14. The method according to claim 8, wherein, When forming the memory pattern, each of the memory patterns includes a first surface and a second surface having a concave shape, and During the formation of the sealing layer, the first surface and the second surface come into contact with the sealing layer.

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