TFT device

Abstract

Embodiments of the present application disclose a TFT device, which includes a substrate, a semiconductor channel layer, an ohmic contact layer, and a source-drain layer that are sequentially disposed on one side of the substrate. In the channel region, a compensation pattern is disposed on the surface of the semiconductor channel layer away from the substrate, and the compensation pattern and the semiconductor channel layer are semiconductors of different types. By disposing the compensation pattern on the surface of the semiconductor channel layer away from the substrate, and the compensation pattern and the semiconductor channel layer are semiconductors of different types; the compensation pattern can further improve the conductivity of the PNP structure, or the compensation pattern can further reduce the leakage current of the NPN structure.

Description

Technical Field

[0001] This application relates to the field of display technologies, and more particularly to a TFT device. Background Art

[0002] Existing TFT devices do not select different types of semiconductor structures according to their functions. For example, for a PNP-type semiconductor structure, a negative voltage needs to be applied to the gate to turn it off, which will make the gate drive circuit very complex. This not only increases the design cost but also results in additional power consumption. For an NPN-type semiconductor structure, its conductivity is poor, and current cannot flow quickly from the source to the drain.

[0003] Therefore, existing TFT devices have technical problems such as poor conductivity or large leakage current. Summary of the Invention

[0004] Embodiments of this application provide a TFT device, which can alleviate the technical problems of poor conductivity or large leakage current existing in existing TFT devices.

[0005] Embodiments of this application provide a TFT device, including:

[0006] A substrate;

[0007] A semiconductor channel layer, which is disposed above the substrate. The semiconductor channel layer includes a channel region, a first doping region and a second doping region located on both sides of the channel region;

[0008] An ohmic contact layer, which is disposed on the surface of the semiconductor channel layer away from the substrate. The ohmic contact layer includes a first pattern attached to the first doping region and a second pattern attached to the second doping region;

[0009] A source-drain layer, which includes a source and a drain. The source is disposed on the surface of the first pattern away from the substrate, and the drain is disposed on the surface of the second pattern away from the substrate;

[0010] Wherein, in the channel region, a compensation pattern is disposed on the surface of the semiconductor channel layer away from the substrate. The compensation pattern is a semiconductor of a different type from the semiconductor channel layer, and the compensation pattern is a semiconductor of the same type as the first pattern and the second pattern.

[0011] Optionally, in some embodiments of this application, the semiconductor channel layer is a hole-type semiconductor, and the first pattern, the second pattern, and the compensation pattern are electron-type semiconductors.

[0012] Optionally, in some embodiments of the present application, the semiconductor channel layer is an n-type semiconductor, and the first pattern, the second pattern, and the compensation pattern are p-type semiconductors.

[0013] Optionally, in some embodiments of the present application, the compensation pattern is disposed on the same layer as the first pattern and the second pattern.

[0014] Optionally, in some embodiments of the present application, the thickness of the compensation pattern, the thickness of the first pattern, and the thickness of the second pattern are equal.

[0015] Optionally, in some embodiments of the present application, the distance between the compensation pattern and the first pattern is equal to the distance between the compensation pattern and the second pattern.

[0016] Optionally, in some embodiments of the present application, the compensation pattern includes at least two sub-compensation patterns, and the thicknesses of adjacent sub-compensation patterns are equal.

[0017] Optionally, in some embodiments of the present application, the sub-compensation patterns are uniformly arranged, and the distances between adjacent sub-compensation patterns are equal.

[0018] Optionally, in some embodiments of the present application, in the channel region, a blocking member is disposed on the side of the semiconductor channel layer away from the substrate, and the resistance of the overlapping portion of the semiconductor channel layer and the blocking member in the film thickness direction is lower than the resistance of the non-overlapping portion of the semiconductor channel layer and the blocking member in the film thickness direction.

[0019] Optionally, in some embodiments of the present application, the preparation material of the compensation pattern includes at least one of amorphous silicon, phosphorus, and boron.

[0020] Advantageous effects: By making the normally-off TFT device have an NPN structure and the normally-on TFT device have a PNP structure, and at the same time, in the channel region, a compensation pattern is disposed on the surface of the semiconductor channel layer on the side away from the substrate, the compensation pattern and the semiconductor channel layer are semiconductors of different types, and the compensation pattern and the first pattern and the second pattern are semiconductors of the same type; the compensation pattern can further improve the conductivity of the PNP structure, or the compensation pattern can further reduce the leakage current of the NPN structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 is the first cross-sectional schematic diagram of the TFT device provided by the embodiment of the present application;

[0023] Figure 2 is the second cross-sectional schematic diagram of the TFT device provided by the embodiment of the present application;

[0024] Figure 3 is the cross-sectional schematic diagram of the array substrate provided by the embodiment of the present application.

[0025] Explanation of reference numerals:

[0026] Detailed implementation manners

[0027] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described here are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; and "inner" and "outer" refer to the outline of the device.

[0028] For existing TFT devices, the TFT devices with PNP structures still have the problem of insufficient conductivity, and the TFT devices with NPN structures still have the problem of large leakage current.

[0029] Therefore, there is an urgent need to provide a TFT device that can alleviate the technical problems of poor conductivity or large leakage current existing in existing TFT devices.

[0030] Please refer to Figure 1, this application provides a TFT device, which includes a substrate 10, a semiconductor channel layer 40, an ohmic contact layer 50, and a source-drain layer 60. The semiconductor channel layer 40 is disposed above the substrate 10. The semiconductor channel layer 40 includes a channel region H1, a first doped region H2 and a second doped region H3 located on both sides of the channel region H1. The ohmic contact layer 50 is disposed on the surface of the semiconductor channel layer 40 away from the substrate 10. The ohmic contact layer 50 includes a first pattern 501 attached to the first doped region H2 and a second pattern 502 attached to the second doped region H3. The source-drain layer 60 includes a source electrode 601 and a drain electrode 602. The source electrode 601 is disposed on the surface of the first pattern 501 away from the substrate 10, and the drain electrode 602 is disposed on the surface of the second pattern 502 away from the substrate 10. Wherein, in the channel region H1, a compensation pattern 503 is disposed on the surface of the semiconductor channel layer 40 away from the substrate 10. The compensation pattern 503 and the semiconductor channel layer 40 are semiconductors of different types, and the compensation pattern 503 and the first pattern 501, the second pattern 502 are semiconductors of the same type.

[0031] Wherein, a gate electrode 20 is further disposed above the substrate, and a gate insulating layer 30 is further disposed on the side of the gate electrode away from the substrate. The semiconductor channel layer 40 is disposed on the side of the gate insulating layer 30 away from the substrate 10.

[0032] Wherein, the hole-type semiconductor is a P-type semiconductor, and the electron-type semiconductor is an N-type semiconductor.

[0033] It can be understood that the P-type semiconductor and the N-type semiconductor are connected to form a PN junction. When an external voltage makes the current flow from the P-type semiconductor to the N-type semiconductor, the PN junction is in a low-resistance state at this time, so the current is large and the conductivity is good; conversely, when an external voltage makes the current flow from the N-type semiconductor to the P-type semiconductor, the PN junction is in a high-resistance state at this time, and the leakage current is small; therefore, in the channel region, by disposing a compensation pattern on the surface of the semiconductor channel layer away from the substrate, the compensation pattern selects an N-type semiconductor or a P-type semiconductor according to the function of the TFT device, which can further distinguish the TFT device according to the normally-open or normally-closed function; that is, improve the conductivity of the normally-open TFT device, or reduce the leakage current of the normally-closed TFT device to make its turn-off more strict.

[0034] It can be understood that the normally-closed TFT device is an NPN structure, and the normally-open TFT device is a PNP structure.

[0035] Among them, the NPN structure means that the semiconductor channel layer 40 is a P-type semiconductor, the first pattern 501 where the ohmic contact layer 50 contacts the source electrode 601 is an N-type semiconductor, and the second pattern 502 where the ohmic contact layer 50 contacts the drain electrode 602 is also an N-type semiconductor.

[0036] Among them, the PNP structure means that the semiconductor channel layer 40 is an N-type semiconductor, the first pattern 501 where the ohmic contact layer 50 contacts the source electrode 601 is a P-type semiconductor, and the second pattern 502 where the ohmic contact layer 50 contacts the drain electrode 602 is also a P-type semiconductor.

[0037] In this embodiment, in the channel region H1, a compensation pattern 503 is further provided on the surface of the semiconductor channel layer 40 away from the substrate 10. The compensation pattern 503 and the semiconductor channel layer 40 are semiconductors of different types, and the compensation pattern 503 and the first pattern 501, the second pattern 502 are semiconductors of the same type; the compensation pattern 503 can further improve the conductivity of the PNP structure, or the compensation pattern 503 can further reduce the leakage current of the NPN structure; making the conductivity of the PNP structure TFT device better, while the leakage current of the NPN structure TFT device is smaller.

[0038] Now, the technical solutions of the present application will be described in combination with specific embodiments.

[0039] In one embodiment, the semiconductor channel layer 40 is a hole-type semiconductor, and the first pattern 501, the second pattern 502, and the compensation pattern 503 are electron-type semiconductors.

[0040] Among them, the semiconductor channel layer 40 is a hole-type semiconductor, the first pattern 501 and the second pattern 502 are electron-type semiconductors, and the TFT device can be used as a normally-off semiconductor device.

[0041] It can be understood that for a normally-off semiconductor device, it is necessary to reduce its leakage current to make the turn-off more strict. It can be understood that when a positive voltage V1 is applied to the gate 20, the first threshold voltage of the TFT device is Vth1. When V1 > Vth1, a reverse channel will appear, enabling current to flow from the source electrode 601 to the drain electrode 602, and the TFT device is in an open state. However, due to the addition of the compensation pattern 503 of the hole-type semiconductor, it is equivalent to adding a PN junction with reverse high resistance, making the threshold voltage of the TFT device larger. According to V1 > Vth1 and the appearance of a reverse channel, it can be known that when Vth1 increases, the gate 20 voltage V1 required to turn on the TFT device is larger. Therefore, the NPN structure TFT device has a more strict turn-off and reduces the leakage current.

[0042] In this embodiment, for normally-off TFT devices, not only are TFT devices with an NPN structure used, but also, in channel region H1, a compensation pattern 503 of N-type semiconductor is further provided on the side of the semiconductor channel layer 40 away from the substrate 10, further increasing the threshold voltage, making the turn-off more stringent and reducing the leakage current.

[0043] In one embodiment, the semiconductor channel layer 40 is an electron-type semiconductor, and the first pattern 501, the second pattern 502, and the compensation pattern 503 are hole-type semiconductors.

[0044] Among them, the semiconductor channel layer 40 is an electron-type semiconductor, the first pattern 501 and the second pattern 502 are hole-type semiconductors, and the TFT device can be used as a normally-on semiconductor device.

[0045] It can be understood that for a normally-on semiconductor device, it is necessary to improve the conductivity of the TFT device so that current can be transmitted from the source electrode 601 to the drain electrode 602 more quickly.

[0046] It can be understood that when a positive voltage V2 is applied to the gate 20, the second threshold voltage of the TFT device is Vth2. When V2 > Vth2, an inverse channel will appear, enabling current to flow from the source electrode 601 to the drain electrode 602, and the TFT device is in an open state. However, due to the addition of the compensation pattern of P-type semiconductor, it is equivalent to adding a forward low-resistance PN junction in the channel region, making the TFT device easier to open, that is, the threshold voltage of the TFT device is smaller, the gate 20 voltage V2 required to open the TFT device is smaller, and it has a higher on-channel current, that is, the conductivity of the PNP structure TFT device is improved.

[0047] In this embodiment, for normally-on TFT devices, a PNP semiconductor structure is adopted. At the same time, in channel region H1, a compensation pattern 503 of P-type semiconductor is further provided on the side of the semiconductor channel layer 40 away from the substrate 10, further reducing the threshold voltage, reducing the power consumption, and increasing the on-channel current.

[0048] In one embodiment, the compensation pattern 503 is provided on the same layer as the first pattern 501 and the second pattern 502.

[0049] Among them, the compensation pattern 503 and the first pattern 501, the second pattern 502 may be made of the same material.

[0050] Among them, the compensation pattern 503 and the first pattern 501, the second pattern 502 may all be hole-type semiconductors, or they may all be electron-type semiconductors.

[0051] It can be understood that the compensation pattern 503 and the first pattern 501 and the second pattern 502 are of the same type of semiconductor, so they can be arranged in the same layer; further, the compensation pattern 503, the first pattern 501, and the second pattern 502 can be prepared by a single-step process, which can simplify the preparation process and reduce costs.

[0052] In this embodiment, by preparing the compensation pattern 503 in the same layer as the first pattern 501 and the second pattern 502, the cost is further reduced.

[0053] In one embodiment, the thickness of the compensation pattern 503, the thickness of the first pattern 501, and the thickness of the second pattern 502 are equal.

[0054] Among them, the same thickness facilitates the synchronous process and the preparation of the compensation pattern 503, the first pattern 501, and the second pattern 502 with the same material.

[0055] In one embodiment, the distance between the compensation pattern 503 and the first pattern 501 is equal to the distance between the compensation pattern 503 and the second pattern 502.

[0056] It can be understood that when only one compensation pattern 503 is provided, the distances between the compensation pattern 503 and the first pattern 501 and the second pattern 502 on both sides are equal, making the influence of the PN junction formed by the compensation pattern 503 in the channel region H1 on the TFT device more uniform, and further improving the compensation effect of the compensation pattern 503.

[0057] In one embodiment, by increasing the thickness of the compensation pattern 503, the compensation effect of the compensation pattern 503 can also be further improved.

[0058] Specifically, making the thickness of the compensation pattern 503 greater than the thickness of the first pattern 501 or the second pattern 502. For the NPN structure, by setting the compensation pattern 503 of the N-type semiconductor with a greater thickness, the leakage current of the TFT device can be further reduced; for the PNP structure, by setting the compensation pattern 503 of the P-type semiconductor with a greater thickness, the conductivity of the TFT device can be further improved.

[0059] Please refer to Figure 2 , in one embodiment, the compensation pattern 503 includes at least two sub-compensation patterns 503, and the thicknesses of adjacent sub-compensation patterns 503 are equal.

[0060] Among them, the thicknesses of adjacent sub-compensation patterns can be different; further, multiple sub-compensation patterns can be periodically arranged according to different thicknesses;

[0061] Among them, the compensation pattern 503 may include a first sub-compensation pattern 503, a second sub-compensation pattern 503, and a third sub-compensation pattern 503. The thicknesses of the first sub-compensation pattern 503, the second sub-compensation pattern 503, the third sub-compensation pattern 503, the first pattern 501, and the second pattern 502 are all equal.

[0062] It can be understood that the first pattern 501 and the second pattern 502 are used to reduce the potential barrier between the source-drain layer 60 and the semiconductor channel layer 40, so that electrons can more easily enter the semiconductor channel layer 40 directly from the source-drain layer 60.

[0063] It can be understood that the equal thickness of adjacent sub-compensation patterns 503 can further improve the uniformity of the compensation effect.

[0064] In this embodiment, multiple sub-compensation patterns 503 and the first pattern 501 and the second pattern 502 are prepared by a one-step process, which simplifies the process and reduces the cost.

[0065] Furthermore, in one embodiment, the sub-compensation patterns 503 are uniformly arranged, and the distance between adjacent sub-compensation patterns 503 is equal.

[0066] Among them, the distance between the first pattern 501 and its adjacent sub-compensation pattern 503 is equal to the distance between adjacent sub-compensation patterns 503.

[0067] Among them, the distance between the second pattern 502 and its adjacent sub-compensation pattern 503 is equal to the distance between adjacent sub-compensation patterns 503.

[0068] In this embodiment, by arranging the sub-compensation patterns 503, the first pattern 501, and the second pattern 502 at equal intervals, the uniformity of the compensation of the compensation pattern 503 for conductivity or turn-off is further improved.

[0069] In one embodiment, in the channel region H1, a blocking member 90 is provided on the side of the semiconductor channel layer 40 away from the substrate 10. The resistance of the overlapping part of the semiconductor channel layer 40 and the blocking member 90 in the film thickness direction is lower than the resistance of the non-overlapping part of the semiconductor channel layer 40 and the blocking member 90 in the film thickness direction.

[0070] Among them, the impedance of the part of the semiconductor channel layer 40 in the conductor state is lower than that of other parts of the semiconductor channel layer 40 in the semiconductor state, which can reduce the overall impedance of the semiconductor channel layer 40.

[0071] In this embodiment, by providing a barrier 90 on the side of the semiconductor channel layer 40 away from the substrate 10, the dark current of the TFT device is reduced and the sensitivity of the TFT device is improved.

[0072] In one embodiment, the barrier 90 may be in a ring structure.

[0073] Wherein, in the film thickness direction of the substrate, the cross-sectional shape of the barrier 90 may be in a ring shape.

[0074] It can be understood that the portion of the semiconductor channel layer 40 in the conductor state corresponding to the barrier 90 is also in a ring structure; this portion is overlapped with the barrier 90 in the film thickness direction.

[0075] In one embodiment, the preparation material of the compensation pattern 503 includes at least one of amorphous silicon, phosphorus, and boron.

[0076] Among them, the composition materials of the P-type semiconductor include amorphous silicon and boron, and the composition materials of the N-type semiconductor include amorphous silicon and phosphorus; in terms of process, doping boron into the amorphous silicon semiconductor material makes the semiconductor a P-type semiconductor, and doping phosphorus into the amorphous silicon semiconductor material makes the semiconductor an N-type semiconductor.

[0077] In the above embodiments, the ultimate goal is to separate the normally-on and normally-off functions of the TFT device and enhance the effective use of the TFT device; it can be understood that in the fields where normally-off semiconductor devices are required, the NPN structure is adopted, and by providing the compensation pattern 503 of the N-type semiconductor, the leakage current of the NPN structure can be further reduced; while in the fields where normally-on semiconductor devices are required, the PNP structure is adopted, and by providing the compensation pattern 503 of the N-type semiconductor, the conductivity of the PNP structure is further enhanced.

[0078] In one embodiment, the contact area between the compensation pattern 503 and the semiconductor channel layer 40 is larger than the contact area between the first pattern 501 and the semiconductor channel layer 40.

[0079] In one embodiment, the contact area between the compensation pattern 503 and the semiconductor channel layer 40 is larger than the contact area between the second pattern 502 and the semiconductor channel layer 40.

[0080] It can be understood that by increasing the contact area between the compensation pattern 503 and the semiconductor channel layer 40, the compensation effect of the compensation pattern 503 can be further improved; for the N-type semiconductor compensation pattern 503, the larger the contact area between the N-type semiconductor compensation pattern 503 and the semiconductor channel layer 40, the smaller the leakage current of the TFT device; for the P-type semiconductor compensation pattern 503, the larger the contact area between the P-type semiconductor compensation pattern 503 and the semiconductor channel layer 40, the better the conductivity of the TFT device.

[0081] Please refer to Figure 3 , the present application further provides an array substrate, the array substrate includes the above-mentioned TFT device, and the array substrate further includes a passivation layer disposed on a side of the TFT device away from the substrate 10, and an anode 80 disposed on a side of the passivation layer 70 away from the substrate 10, and the anode 80 is connected to the source electrode 601 through a via hole penetrating through the passivation layer 70.

[0082] It should be noted that the array substrate includes a plurality of TFT devices. According to the required functions of the TFT devices, an NPN structure TFT device or a PNP structure TFT device is selected, and by setting corresponding compensation patterns, the leakage current of the TFT device can be further reduced or the conductivity of the TFT device can be improved.

[0083] The present application also proposes a display panel, a display module, and a display device. The display panel, the display module, and the display device all include the above-mentioned TFT device or array substrate, which will not be elaborated here.

[0084] The TFT device provided in this embodiment includes a substrate, a semiconductor channel layer, an ohmic contact layer, and a source-drain layer. The semiconductor channel layer is disposed above the substrate. The semiconductor channel layer includes a channel region, a first doping region and a second doping region located on both sides of the channel region. The ohmic contact layer is disposed on the surface of the semiconductor channel layer away from the substrate. The ohmic contact layer includes a first pattern attached to the first doping region and a second pattern attached to the second doping region. The source-drain layer includes a source electrode and a drain electrode. The source electrode is disposed on the surface of the first pattern away from the substrate, and the drain electrode is disposed on the surface of the second pattern away from the substrate. Wherein, in the channel region, a compensation pattern is disposed on the surface of the semiconductor channel layer away from the substrate. The compensation pattern is a semiconductor of a different type from the semiconductor channel layer, and the compensation pattern is a semiconductor of the same type as the first pattern and the second pattern. By making the normally-off TFT device an NPN structure and the normally-on TFT device a PNP structure, setting the corresponding compensation pattern can further improve the conductivity of the PNP structure, or the compensation pattern can further reduce the leakage current of the NPN structure.

[0085] It should be noted that the corresponding compensation pattern refers to: the compensation pattern is a semiconductor of a different type from the semiconductor channel layer, and the compensation pattern is a semiconductor of the same type as the first pattern and the second pattern. Therefore, for the NPN structure, the compensation pattern is unique, that is, the compensation pattern is an N-type semiconductor; for the PNP structure, the compensation pattern is also unique, that is, the compensation pattern is a P-type semiconductor.

[0086] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0087] The TFT device and the array substrate provided in the embodiments of the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A TFT device, characterized in that, Comprising: A substrate; A semiconductor channel layer disposed above the substrate, the semiconductor channel layer including a channel region, a first doped region and a second doped region located on both sides of the channel region; An ohmic contact layer disposed on a surface of the semiconductor channel layer away from the substrate, the ohmic contact layer including a first pattern attached to the first doped region and a second pattern attached to the second doped region; A source-drain layer including a source and a drain, the source disposed on a surface of the first pattern away from the substrate, and the drain disposed on a surface of the second pattern away from the substrate; Wherein, in the channel region, a compensation pattern is disposed on a surface of the semiconductor channel layer away from the substrate, the compensation pattern is a semiconductor of a different conductivity type from the semiconductor channel layer, the compensation pattern is a semiconductor of the same type as the first pattern and the second pattern, and the compensation pattern is disposed on the same layer as the first pattern and the second pattern.

2. The TFT device according to claim 1, wherein The semiconductor channel layer is a p-type semiconductor, and the first pattern, the second pattern, and the compensation pattern are n-type semiconductors.

3. The TFT device according to claim 1, wherein The semiconductor channel layer is an n-type semiconductor, and the first pattern, the second pattern, and the compensation pattern are p-type semiconductors.

4. The TFT device according to claim 2 or 3, characterized in that, The thickness of the compensation pattern, the thickness of the first pattern, and the thickness of the second pattern are equal.

5. The TFT device according to claim 4, wherein The distance between the compensation pattern and the first pattern is equal to the distance between the compensation pattern and the second pattern.

6. The TFT device according to claim 2 or 3, characterized in that, The compensation pattern includes at least two sub-compensation patterns, and the thicknesses of adjacent sub-compensation patterns are equal.

7. The TFT device according to claim 6, wherein The sub-compensation patterns are uniformly arranged, and the distance between adjacent sub-compensation patterns is equal.

8. The TFT device according to claim 1, wherein In the channel region, a blocking member is disposed on a side of the semiconductor channel layer away from the substrate, and the resistance of the overlapping portion of the semiconductor channel layer and the blocking member in the film thickness direction is lower than the resistance of the non-overlapping portion of the semiconductor channel layer and the blocking member in the film thickness direction.

9. The TFT device according to claim 1, characterized in that, The preparation material of the compensation pattern includes at least one of amorphous silicon, phosphorus, and boron.

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