How to use semiconductor smart wire

Abstract

The present invention is a method for using a semiconductor smart line, which is to set the semiconductor smart line on the drain-source voltage axis of the output characteristic table of a first semiconductor, and has the function of using gate voltage setting to indicate the source current application limit on the output characteristic table.

Description

Technical field

[0001] The present invention relates to a method for using a semiconductor intelligence line, and more particularly to the field of electronic technology, wherein a gate voltage is set on the output characteristics of a first semiconductor. When the source current flowing through the first semiconductor exceeds the semiconductor intelligence line, the method has the function of indicating that the drain and source of the first semiconductor are open. [Background Technology]

[0002] Since the invention of the bipolar transistor in 1947, the semiconductor intelligence line of the present invention and the functions of the semiconductor intelligence line of the present invention have never appeared in the output characteristic table of the data sheet. Therefore, the present invention can be called a groundbreaking invention.

[0003] like Figure 1 As shown, please refer to Taiwan Patent Certificate No. I692163 "DC Power Supply Short Circuit Protection Device", the patentee of which is the same person as the applicant of this invention. Figure 1 It can be seen that it includes a first semiconductor 10 and a second semiconductor circuit; the second semiconductor circuit includes a second semiconductor 11, a first resistor 12 and a second resistor 13, the source S of the first semiconductor 10 is connected to the negative terminal of the DC power supply 100 and the source S of the second semiconductor 11, the drain D of the first semiconductor 10 is connected to the negative terminal V- of the circuit, and the gate G of the first semiconductor 10 is connected to the drain D of the second semiconductor 11; the drain D of the second semiconductor 11 is connected to the other end of the second resistor 13, the source S of the second semiconductor 11 is connected to the source S of the first semiconductor 10, the gate G of the second semiconductor 11 is connected to one end of the first resistor 12, the other end of the first resistor 12 is connected to the negative terminal V- of the circuit, and one end of the second resistor 13 is connected to the positive terminal V+ of the circuit. The first semiconductor 10 is an N-channel metal oxide semiconductor field effect transistor, and the second semiconductor 11 is an N-channel metal oxide semiconductor field effect transistor. The positive terminal of the DC power supply 100 is connected to the positive terminal V+ of the circuit, and the negative terminal of the DC power supply 100 is connected to the source S of the first semiconductor 10 and the source S of the second semiconductor 11. The positive terminal V+ of the circuit is connected to the positive terminal of the load 200, and the negative terminal V- of the circuit is connected to the negative terminal of the load 200. The invention patent specification shows that the first semiconductor 10 also includes the sixth semiconductor 15 (which is an N-type transistor) in Figure 6 and the seventh semiconductor 16 (which is an insulated gate bipolar transistor) in Figure 7. It is specifically stated that the first semiconductor 10 of the present invention includes a metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor, or an N-type transistor. The prior art "DC power supply short-circuit protection device" provides short-circuit protection for the load 200 during power supply by the DC power supply 100. [Summary of the invention]

[0004] exist Figure 1 The invention patent specification of the prior art does not mention the following establishment and application of the semiconductor smart line of the present invention related to the first semiconductor 10:

[0005] 1. The semiconductor intelligence line of the present invention is applied to an N-channel metal oxide semiconductor field effect transistor (N-Channel MOSFET). It uses various gate-source voltage settings to indicate the corresponding source current and its corresponding drain-source voltage. When a load is overloaded or short-circuited, because the corresponding drain current and corresponding drain-source voltage are exceeded, it indicates that the drain and source of the first semiconductor have become open circuits. Therefore, the semiconductor intelligence line of the present invention has the function of indicating that the drain and source of the first semiconductor are open circuits.

[0006] 2. The method for using the semiconductor intelligence line of the present invention is applied to an insulated gate bipolar transistor (IGBT) with various gate-emitter voltage settings to indicate its corresponding emitter current and its corresponding collector-emitter voltage. When the load is overloaded or short-circuited, because it exceeds the corresponding emitter current and the corresponding collector-emitter voltage, it indicates that the collector and emitter of the first semiconductor have become open circuits. Therefore, the semiconductor intelligence line of the present invention has the function of indicating that the collector (Collector) and emitter (Emitter) of the first semiconductor are open circuits.

[0007] 3. The method for using the semiconductor intelligence line of the present invention is applied to an N-type transistor with various base current settings to indicate its corresponding collector current and corresponding collector-emitter voltage. When the load is overloaded or short-circuited, because it exceeds the corresponding emitter current and corresponding collector-emitter voltage, it indicates that the collector and emitter of the first semiconductor have become open circuits. Therefore, the semiconductor intelligence line of the present invention has the function of indicating that the collector and emitter of the first semiconductor are open circuits.

[0008] Purpose of the present invention:

[0009] The method for using the semiconductor smart line of the present invention is applied to a first semiconductor, and has the function of setting the gate-source voltage to indicate that the drain and source of the first semiconductor are open when the load is overloaded or short-circuited.

[0010] The method for using the semiconductor smart line of the present invention is applied to a first semiconductor, and has the function of setting the gate-emitter voltage to indicate that the collector and emitter of the first semiconductor are open when the load is overloaded or short-circuited.

[0011] The method for using the semiconductor smart line of the present invention uses a first semiconductor, which has the function of setting the base current and indicating that the collector and emitter of the first semiconductor are open when the load is overloaded or short-circuited.

[0012] The present invention has the following features:

[0013] 1. The present invention's method for using a semiconductor smart line is a world first. It is applied to a metal oxide semiconductor field effect transistor and has a gate-source voltage setting function. When the load is overloaded or short-circuited, it has the function of indicating that the drain and source of the first semiconductor are open.

[0014] 2. The method of using the semiconductor smart line of the present invention is a world first. It is applied to insulated gate bipolar transistors and has the function of setting the gate-emitter voltage. When the load is overloaded or short-circuited, it has the function of indicating that the collector and emitter of the first semiconductor are open.

[0015] 3. The method of using the semiconductor smart line of the present invention is a world first. It is applied to N-type transistors and has the function of setting the base current. When the load is overloaded or short-circuited, it has the function of indicating that the collector and emitter of the first semiconductor are open.

[0016] The specific technology adopted by the present invention will be further described through the following embodiments and accompanying drawings.

Brief Description of the Drawings

[0017] Figure 1 This is an embodiment of a DC power supply short-circuit protection device in the prior art.

[0018] Figure 2 The first embodiment of the method for using a semiconductor intelligence line of the present invention.

[0019] Figure 3 The second embodiment of the method for using the semiconductor intelligence line of the present invention.

[0020] Figure 4 A third embodiment of the method for using a semiconductor intelligence line of the present invention.

[0021] Description of main component symbols:

[0022] VGS Gate-Source Voltage

[0023] VDS drain-source voltage

[0024] ID Drain current

[0025] VGE Gate-Emitter Voltage

[0026] VCE collector-emitter voltage

[0027] IC collector current

[0028] IB base current

[0029] 300 Semiconductor Intelligence Line [Specific implementation method]

[0030] In order to fully understand the purpose, features and effects of the present invention, the present invention is described in detail with reference to the following specific embodiments and the accompanying drawings.

[0031] Throughout the present invention, the terms "a" or "an" are used to describe units, components, and elements described herein. This is for convenience only and to provide a general understanding of the scope of the present invention. Therefore, unless otherwise apparent, such descriptions should be understood to include one, at least one, and the singular also includes the plural.

[0032] Throughout this disclosure, the terms "comprise," "include," "have," "contain," or any similar terms are intended to cover a non-exclusive inclusion. For example, a component, structure, article, or device comprising multiple elements is not limited to only those elements listed herein but may include additional elements not expressly listed but generally inherent to such component, structure, article, or device. Furthermore, unless expressly stated to the contrary, the term "or" refers to an inclusive or and not to an exclusive or.

[0033] like Figure 2 FIG. 1 is a first embodiment of the method for using the semiconductor smart line of the present invention. Figure 1 The first semiconductor 10 is NVHL060N090SC1 (MOSFET-SIC Power, Single N-Channal) as an example. Figure 2 As can be seen in the output characteristic table of NVHL060N090SC1, the semiconductor intelligent line 300 is placed.

[0034] The semiconductor intelligence line 300 is placed vertically on the drain-source voltage VDS (Drain-Source Voltage, VDS) axis, at a position of approximately 3.5V.

[0035] The gate-source voltage VGS lines crossed by the semiconductor intelligence line 300 are 7V, 9V, 10V, 12V, 13V, and 15V, respectively. The corresponding parallel, transversely crossing drain current ID (Drain Current, ID) axes are 2A, 8A, 12A, 25A, 32A, and 45A, respectively. For example, when VGS = 15V and ID = 45A, its VDS is 3.5V.

[0036] When VGS=12V and ID=25A, its VDS is 3.5V.

[0037] When VGS=9V and ID=12A, its VDS is 3.5V.

[0038] From the above, it can be seen that at the 3.5V position on the drain-source voltage VDS axis, the semiconductor smart line 300 can use three different gate-source voltages VGS, namely VGS=15V, 12V and 9V to obtain corresponding drain currents ID=45A, 25A and 12A.

[0039] The corresponding drain currents ID=45A, 25A, and 12A are the application-limited drain current values. If the drain current exceeds the application-limited drain current value during application, the drain and source of the first semiconductor 10 will be open, thereby achieving the function of indicating that the drain and source of the first semiconductor 10 are open.

[0040] From the above, it can be seen that although the semiconductor smart line 300 is vertically placed at a position of approximately 3.5V on the drain-source voltage VDS axis, the voltage value on the drain-source voltage VDS axis can be changed according to the actual application requirements of the first semiconductor 10 to meet the actual application requirements.

[0041] since Figure 2 It can be seen that the semiconductor intelligence line 300 vertically cuts through six different gate-source voltage VGS lines. Based on application requirements, the semiconductor intelligence line 100 can also vertically cut through only one gate-source voltage VGS line without being limited.

[0042] like Figure 3 FIG. 2 is a second embodiment of the method for using the semiconductor smart line of the present invention. Figure 1 The first semiconductor 10 is IRGP4266DPbF (IGBT) as an example. Figure 3 As can be seen from the figure, the semiconductor intelligent line 300 of the present invention is incorporated into the output characteristic table of IRGP4266DPbF.

[0043] The semiconductor intelligence line 300 is placed vertically on the collector-emitter voltage VCE axis, at a position of approximately 3.5V.

[0044] The gate-emitter voltage VGE lines crossed by the semiconductor intelligence line 300 are 8V, 10V, 12V and 15V respectively, and the corresponding parallel horizontally crossed collector current IC axes are 5A, 55A, 140A and 240A respectively. For example, when VGE=15V, ICE=240A, its VCE is 3.5V.

[0045] When VGE=12V and ICE=140A, VCE is 3.5V.

[0046] When VGE=10V and ICE=55A, VCE is 3.5V.

[0047] When VGE=8V and ICE=5A, VCE is 3.5V.

[0048] From the above, it can be seen that at the 3.5V position on the collector-emitter voltage VCE axis, the semiconductor intelligence line 300 can use four different gate-emitter voltages VGE, namely VGE = 15V, 12V, 10V and 8V to obtain corresponding collector-emitter currents IC = 240A, 140A, 50A and 5A.

[0049] The corresponding collector currents IC=240A, 140A, 50A and 5A are the collector current values ​​within the application limits. If the collector current exceeds the application limit during application, the collector and emitter of the first semiconductor 10 will be open, thereby achieving the function of indicating that the collector and emitter of the first semiconductor 10 are open.

[0050] From the above, it can be seen that although the semiconductor intelligence line 300 is vertically placed at a position of approximately 3.5V on the collector-emitter voltage VCE axis, the voltage value on the collector-emitter voltage VCE axis can be changed according to the actual application requirements of the first semiconductor 10 to meet actual application requirements.

[0051] since Figure 3 As can be seen from the figure, the semiconductor intelligence line 300 vertically cuts through four different gate-emitter voltage VGE lines. Based on application requirements, the semiconductor intelligence line 300 can also vertically cut through only one gate-emitter voltage VGE line without being limited.

[0052] like Figure 4 FIG. 3 is a third embodiment of the method for using the semiconductor smart line of the present invention. Figure 1 The first semiconductor 10 is 2SD880 (NPN Silicon Transistor) as an example. Figure 4 As can be seen from the table, the semiconductor intelligent line 300 of the present invention is incorporated into the output characteristic table of 2SD880.

[0053] The semiconductor intelligence line 300 is placed vertically on the collector-emitter voltage VCE axis, at a position of approximately 1.7V.

[0054] The base current IB lines crossed by the semiconductor intelligence line 300 are 10mA, 20mA, 30mA, 50mA and 60mA respectively, and the corresponding parallel horizontally crossed collector current IC axes are 1A, 1.3A, 1.5A, 1.7A and 2.3A respectively. For example, when IB = 60mA and IC = 2.3A, its VCE is 1.7V.

[0055] When IB=50mA and IC=1.7A, its VCE is 1.7V.

[0056] When IB=30mA and IC=1.5A, its VCE is 1.7V.

[0057] When IB=20mA and IC=1.3A, its VCE is 1.7V.

[0058] When IB=10mA and IC=1A, its VCE is 1.7V.

[0059] From the above, it can be seen that when the semiconductor intelligence line 300 is at the 1.7V position on the collector-emitter voltage VCE axis, five different base currents IB can be used, namely IB = 60mA, 50mA, 30mA, 20mA and 10mA, to obtain corresponding collector currents IC = 2.3A, 1.7A, 1.5A, 1.3A and 1A.

[0060] The corresponding collector currents IC=2.3A, 1.7A, 1.5A, 1.3A and 1A are the collector current values ​​limited by the application. If the collector current value exceeds the application limit during application, the collector and emitter of the first semiconductor 10 will be open, thereby achieving the function of indicating that the collector and emitter of the first semiconductor 10 are open.

[0061] From the above, it can be seen that although the semiconductor intelligence line 300 is vertically placed at a position of approximately 1.7V on the collector-emitter voltage VCE axis, the voltage value on the collector-emitter voltage VCE axis can be changed according to the actual application requirements of the first semiconductor 10 to meet actual application requirements.

[0062] since Figure 4 As can be seen from the figure, the semiconductor intelligence line 300 vertically cuts through five different base current IB lines. Based on application requirements, the semiconductor intelligence line 300 can also vertically cut through only one base current IB line without being limited.

[0063] From the above description, it can be seen that the semiconductor smart line 300 of the present invention can be implemented.

[0064] Although the embodiments of the present invention are disclosed as described above, they are not intended to limit the present invention. Anyone skilled in the relevant art may make slight changes to the shapes, structures, features, methods, and quantities described in the claims of the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be determined by the scope of the claims attached to this specification.

Claims

1. A method for using a semiconductor smart line, wherein the semiconductor smart line is used to indicate that when the drain current value exceeds the value of the semiconductor smart line under a set gate-source voltage, the drain and source of a first semiconductor are open-circuited, characterized in that: The method for using the semiconductor smart line includes: The semiconductor intelligence line is vertically arranged on the drain-source voltage axis of the output characteristic table of the first semiconductor; Cutting the semiconductor intelligence line vertically through at least one gate-source voltage line on the output characteristic table of the first semiconductor; as well as The semiconductor intelligence line and the at least one gate-source voltage line intersect to obtain an intersection point, and the intersection point extends horizontally and parallel to intersect the drain current axis on the output characteristic table of the first semiconductor.

2. The method for using a semiconductor intelligent line according to claim 1, wherein: The drain current value on the drain current axis has a function of indicating a drain current application limit.

3. The method for using a semiconductor intelligent line according to claim 1, wherein: The first semiconductor is an N-channel metal oxide semiconductor field effect transistor.

4. A method for using a semiconductor smart line, wherein the semiconductor smart line is used to indicate that the collector and emitter of a first semiconductor are open-circuited when the collector current value exceeds the value of the semiconductor smart line under a set gate-emitter voltage, characterized in that: The method for using the semiconductor smart line includes: The semiconductor intelligence line is vertically arranged on the collector-emitter voltage axis of the output characteristic table of the first semiconductor; Cutting the semiconductor intelligence line vertically through at least one gate-emitter voltage line on the output characteristic table of the first semiconductor; as well as The semiconductor wisdom line is crossed with the at least one gate-emitter voltage line to obtain an intersection point, and the intersection point extends horizontally and parallel to cross the collector current axis on the output characteristic table of the first semiconductor.

5. The method for using a semiconductor intelligent line according to claim 4, wherein: The collector current value on the collector current axis has a function of indicating a collector current application limit.

6. The method for using a semiconductor intelligent wire according to claim 4, wherein: The first semiconductor is an insulating gate bipolar transistor.

7. A method for using a semiconductor smart line, wherein the semiconductor smart line is used to indicate that when the collector current value exceeds the semiconductor smart line under a set base current, the collector and emitter of a first semiconductor are open-circuited, characterized in that: The method for using the semiconductor smart line includes: The semiconductor intelligence line is vertically arranged on the collector-emitter voltage axis of the output characteristic table of the first semiconductor; The semiconductor intelligence line vertically cuts through at least one base current line on the output characteristic surface of the first semiconductor; as well as The semiconductor wisdom line and the at least one base current line intersect to obtain an intersection point, and the intersection point extends horizontally and parallel to intersect the collector current axis on the output characteristic table of the first semiconductor.

8. The method for using a semiconductor intelligent line according to claim 7, wherein: The collector current value on the collector current axis has a function of indicating a collector current application limit.

9. The method for using a semiconductor intelligent line according to claim 7, wherein: The first semiconductor is an N-type transistor.

10. The method for using a semiconductor intelligent wire according to any one of claims 1, 4 or 7, wherein: There is at least one semiconductor intelligence line on the output characteristic table of the first semiconductor.

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