A control circuit with soft start and soft stop functions

Abstract

This invention discloses a control circuit with soft-start and soft-shutdown functions, belonging to the field of power management. It includes a charging / discharging module, a voltage clamping module, and a buffer module. The charging / discharging module charges and discharges the capacitor on the SS port of the soft-start and soft-shutdown configuration, controlling the capacitor voltage to rise or fall slowly. When the control circuit enters the off state, the voltage clamping module quickly clamps the capacitor voltage on the SS port and the output voltage of the buffer module, clamping them to fixed values. The buffer module buffers the capacitor voltage output on the SS port, ensuring that the output signal S_CTR of the soft-start and soft-shutdown function control circuit follows the voltage change of the capacitor on the SS port. This invention not only has soft-start control function but also soft-shutdown control function.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and in particular to a control circuit with soft-start and soft-shutdown functions. Background Technology

[0002] When a power conversion circuit is powered on, a soft-start circuit is often required to control the power-on startup in order to avoid inrush current at the input power port and to ensure a monotonous and smooth rise in the output voltage waveform. When the power conversion circuit is powered off, for certain special memories such as EEPROM, a "soft shutdown" function is required for the power supply to ensure normal storage. This means that when the power supply is powered off, it needs to maintain a certain voltage range for a period of time and meet certain timing requirements.

[0003] To address the issue of power conversion circuits starting up upon power-on and shutting down upon power-off, this invention proposes a control circuit with soft-start and soft-shutdown functions. Summary of the Invention

[0004] The purpose of this invention is to provide a control circuit with soft-start and soft-shutdown functions to solve the problems in the prior art.

[0005] To solve the above-mentioned technical problems, the present invention provides a control circuit with soft start and soft shutdown functions, including a charging and discharging module, a voltage clamping module and a buffer module;

[0006] The charging and discharging module charges and discharges the capacitor on the SS port of the soft-start and soft-shutdown configuration, and controls the capacitor voltage to rise or fall slowly.

[0007] When the control circuit enters the off state, the voltage clamping module quickly clamps the output voltage of the capacitor and buffer module on the soft start and soft stop configuration SS port, clamping the capacitor voltage and the output voltage of the buffer to a fixed voltage value.

[0008] The buffer module is used to buffer the capacitor voltage output on the SS port, so that the output signal S_CTR of the soft start and soft stop function control circuit follows the voltage change of the capacitor on the SS port.

[0009] Optionally, the charging and discharging module includes current sources I1~I2 and switches S1~S2; the first node of the current source I1 is connected to a power source, and the second node is connected to the first node of the switch S1; the second node of the switch S1 is connected to the first node of the current source I2, and the second node of the current source I2 is grounded.

[0010] The second node of switch S1 and the first node of switch S2 are both connected to an external SS port, which is connected to a capacitor C. SS Grounding.

[0011] Optionally, the voltage clamping module includes switches S3~S6 and a current source I3. The first nodes of switches S3, S4, and S5 are all connected to the external SS port. The second nodes of switches S5 and S6 are all connected to the second node of the current source I3. The first node of the current source I3 is connected to the clamping reference voltage VREF. The second nodes of switches S3, S4, and S6 are all connected to the buffer module.

[0012] Optionally, the buffer module includes a unity-gain buffer A1, the input of which is connected to the second node of switch S3 and the second node of switch S4, and the output is connected to the second node of switch S6.

[0013] Optionally, the charging and discharging module includes current sources I1~I2, PMOS transistor MP1, and NMOS transistors MN1~MN3; the first node of current source I1 is connected to a power supply, the second node is connected to the source terminal of PMOS transistor MP1, the drain terminal of PMOS transistor MP1 is connected to the drain terminal and gate terminal of NMOS transistor MN1; the source terminal of NMOS transistor MN1 is connected to the drain terminal of NMOS transistor MN2; the source terminal of NMOS transistor MN2 is grounded through current source I2; the gate terminals of PMOS transistor MP1 and NMOS transistor MN2 are both connected to SD1.

[0014] The drain of NMOS transistor MN3 is connected to the drain of NMOS transistor MN2, the source is grounded, and the gate is connected to the reset signal RESET.

[0015] The drain terminals of NMOS transistors MN2 and MN3 are simultaneously connected to an external SS port, which is connected via capacitor C. SS Grounding.

[0016] Optionally, the voltage clamping module includes a current source I3, an NMOS transistor MN4, a unity-gain buffer A2, and transmission gates TG1~TG3; the first node of the current source I3 is connected to the power supply, and the second node is simultaneously connected to the first input terminal of the transmission gate TG2, the gate terminal and the drain terminal of the NMOS transistor MN4; the source terminal of the NMOS transistor MN4 is connected to the output terminal of the unity-gain buffer A2.

[0017] The first input terminal of the transmission gate TG1 is connected to the gate and drain terminals of NMOS transistor MN1, the second input terminal is connected to SD1, and the third input terminal is connected to the source terminals of NMOS transistor MN2 and NMOS transistor MN1.

[0018] The first input terminal of the transmission gate TG2 is connected to the first node of the current source I3, the drain and gate of the NMOS transistor MN4, the second input terminal is connected to SD2, and the third input terminal is connected to the drain of the NMOS transistor MN2 and the source of the NMOS transistor MN1.

[0019] The first input terminal of the transmission gate TG3 is connected to the source terminal of the NMOS transistor MN4 and the output terminal of the unity-gain buffer A2, and the second input terminal is connected to SD2.

[0020] Optionally, the buffer module includes an NMOS transistor MN5 and a current source I4; the drain of the NMOS transistor MN5 is connected to a power supply, the source is connected to the first node of the current source I4, and the second node of the current source I4 is grounded; the third input of the transmission gate TG3 is connected between the source of the NMOS transistor MN5 and the first node of the current source I4.

[0021] In the control circuit with soft-start and soft-shutdown functions provided by this invention, when the circuit is powered on, the capacitor is first discharged and reset, and then the charging current source charges the capacitor. The voltage on the capacitor slowly rises from zero, and the output of the buffer module follows the rise in capacitor voltage. The output of the control power conversion circuit also rises accordingly. When the voltage at the SS port is higher than the internal reference voltage VREF, the branch controlled by the S_CTR input in the error amplifier is turned off, and the output voltage of the power conversion circuit starts to the normal output value. When the circuit is turned off, the selector switch is switched to enter the clamping state. The voltage clamping module clamps both the SS port voltage and the output of the buffer module to the internal reference voltage VREF. Then, the selector switch is switched again to enter the soft-shutdown state. The discharge current source discharges the capacitor, and the voltage on the capacitor slowly decreases from VREF. The output of the buffer module follows the decrease in capacitor voltage, and the output of the control power conversion circuit decreases accordingly until the output of the buffer module drops to zero, and the output of the power conversion circuit also drops to zero. Attached Figure Description

[0022] Figure 1 A schematic diagram of the control circuit structure with soft start and soft shutdown functions provided by the present invention;

[0023] Figure 2 For based on Figure 1 A schematic diagram illustrating the implementation and improvement of a control circuit with soft-start and soft-shutdown functions;

[0024] Figure 3 For based on Figure 2 The timing waveforms of the soft start and soft stop control functions. Detailed Implementation

[0025] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a control circuit with soft-start and soft-shutdown functions proposed in this invention. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0026] In this invention, terms such as “connection,” “linked,” “connected,” and “joined” that indicate electrical connection, unless otherwise specified, indicate direct or indirect electrical connection.

[0027] This invention proposes a control circuit with soft-start and soft-shutdown functions, as shown in Figure 1. It mainly consists of three parts: a charging / discharging module 1, a voltage clamping module 2, and a buffer module 3. In the charging / discharging module 1, the first node of current source I1 is connected to the power supply, and the second node is connected to the first node of switch S1. The second node of switch S1 and the first node of switch S2 are simultaneously connected to the external SS port. The second node of switch S2 is connected to the first node of current source I2, and the second node of current source I2 is connected to ground. In the voltage clamping module 2, the first nodes of switches S3, S4, and S5 are all connected to the external SS port. The second nodes of switches S3 and S4 are connected to the first node of the buffer module 3 (i.e., the input terminal of the unity-gain buffer A1). The first node of the current source I3 is connected to the clamping reference voltage VREF. The second node of the current source I3 is simultaneously connected to the second node of switch S5 and the first node of switch S6. The second node of switch S6 is connected to the second node of the buffer module 3 (i.e., the output terminal of the unity-gain buffer A1), S_CTR. The external SS port is connected via capacitor C. SS Grounding.

[0028] The specific working principle of the circuit of this invention is as follows:

[0029] When the circuit is powered on, switches S1 and S3 are closed, and switches S2 and S4-S6 are open. Current source I1 supplies current to capacitor C. SS Charging, capacitor C SS The voltage rises from zero in a buffered manner, and the output voltage V of the unity-gain buffer A1 is... S_CTR Follower capacitor C SS Voltage V on SS :

[0030]

[0031] When the external SS port voltage is higher than the internal reference voltage VREF, the branch controlled by S_CTR in the power conversion circuit is turned off, and the power conversion circuit output starts up to the normal output value. The soft start time is t. SSfor:

[0032]

[0033]

[0034] When the circuit is turned off, the circuit first enters the clamping state, switches S2 and S4-S6 are closed, switches S1 and S3 are open, and the voltage clamping module 2 clamps capacitor C. SS Voltage V on SS The output V of unity-gain buffer A1 S_CTR Clamping to V REF .

[0035]

[0036] Then, the selector switches are switched, with switches S2 and S4 closed and switches S1, S3, S5, and S6 open. The circuit enters a soft-shutdown state, and the discharge current source I2 discharges through capacitor C. SS Discharge occurs, capacitor C SS Voltage V on SS Starting from VREF, the output of unity-gain buffer A1 decreases slowly, and V... S_CTR Follower capacitor C SS Voltage V SS As the output of the power conversion circuit decreases, the output of the control power supply circuit also decreases until the output of the unity-gain buffer A1 drops to zero, at which point the output of the power conversion circuit also drops to zero. Soft-shutdown time t SS for:

[0037]

[0038]

[0039] Figure 2 For based on Figure 1 Implementation and improvement of a control circuit with soft-start and soft-shutdown functions. Figure 2 Implemented by PMOS transistor MP1 and NMOS transistor MN2 Figure 2 Switches S1 and S2 are implemented using transmission gates TG1 and TG3. Figure 1 Switches S5 and S6 in the snippet are implemented using NMOS transistor MN5 as a source follower buffer. This is to compensate for the gate-source voltage (V) of the source follower buffer using NMOS transistor MN4. GS ) loss, in Figure 1 In the circuit implementation of the branches containing switches S3 and S5 shown, gate-drain connected NMOS transistors are inserted respectively. Figure 2 Implemented using NMOS transistor MN1 Figure 1 Switch S3 in the diagram is implemented using NMOS transistor MN3 and transmission gate TG2. Figure 1 Switch S4 in the middle.

[0040] Figure 3 Verified Figure 2 Simulation timing waveforms of the embodiment. When the circuit powers on (at time V1), the RESET signal controls the NMOS transistor MN3 to conduct, affecting capacitor C. SS Perform a discharge reset, then charge the current source I1 to the capacitor C. SS During charging (at time V2), capacitor C SS Voltage V on SS Starting from zero, the output V of the source follows the buffer output. S_CTR Follower capacitor C SS As the voltage rises, the output voltage of the control power conversion circuit also rises accordingly. When the voltage at the SS port V... SS When the voltage is higher than the internal reference voltage VREF (at time V3), the output signal V of the unity-gain buffer A1 is... S_CTR When the controlled branch is turned off, the power conversion circuit output starts to the normal output value; when the circuit is turned off (at time V4), the selector switch enters the clamping state, and the voltage clamping module 2 clamps the SS port voltage and the source follower buffer output to the internal reference voltage VREF. Then, the selector switch is switched again to enter the soft shutdown state, and the discharge current source I2 discharges to capacitor C. SS Discharge occurs, capacitor C SS The voltage across the source follower buffer starts to decrease slowly from VREF, and the output follower capacitor C... SS The voltage drops, controlling the power conversion circuit to output V OUT Follow the decline until the capacitance C SS Voltage V on SS When the voltage drops to zero, the output of the power conversion circuit also drops to zero (at time V5).

[0041] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A control circuit with soft-start and soft-shutdown functions, characterized in that, It includes a charge / discharge module, a voltage clamping module, and a buffer module; The charging and discharging module charges and discharges the capacitor on the SS port of the soft-start and soft-shutdown configuration, and controls the capacitor voltage to rise or fall slowly. When the control circuit enters the off state, the voltage clamping module quickly clamps the output voltage of the capacitor and buffer module on the soft start and soft stop configuration SS port, clamping the capacitor voltage and the output voltage of the buffer to a fixed voltage value. The buffer module is used to buffer the capacitor voltage on the SS port, so that the output signal S_CTR of the soft start and soft stop function control circuit follows the voltage change of the capacitor on the SS port. The charging and discharging module includes current sources I1~I2, PMOS transistor MP1, and NMOS transistors MN1~MN3. The first node of current source I1 is connected to the power supply, and the second node is connected to the source terminal of PMOS transistor MP1. The drain terminal of PMOS transistor MP1 is connected to the drain terminal and gate terminal of NMOS transistor MN1. The source terminal of NMOS transistor MN1 is connected to the drain terminal of NMOS transistor MN2. The source terminal of NMOS transistor MN2 is grounded through current source I2. The gate terminals of PMOS transistor MP1 and NMOS transistor MN2 are both connected to SD1. The drain of NMOS transistor MN3 is connected to the drain of NMOS transistor MN2, the source is grounded, and the gate is connected to the reset signal RESET. The drain terminals of NMOS transistors MN2 and MN3 are simultaneously connected to an external SS port, which is connected via capacitor C. SS Grounding; The voltage clamping module includes a current source I3, an NMOS transistor MN4, a unity-gain buffer A2, and transmission gates TG1~TG3. The first node of the current source I3 is connected to the power supply, and the second node is simultaneously connected to the first input terminal of the transmission gate TG2, the gate terminal and the drain terminal of the NMOS transistor MN4. The source terminal of the NMOS transistor MN4 is connected to the output terminal of the unity-gain buffer A2. The first input terminal of the transmission gate TG1 is connected to the gate and drain terminals of NMOS transistor MN1, the second input terminal is connected to SD1, and the third input terminal is connected to the source terminals of NMOS transistor MN2 and NMOS transistor MN1. The first input terminal of the transmission gate TG2 is connected to the first node of the current source I3, the drain and gate of the NMOS transistor MN4, the second input terminal is connected to SD2, and the third input terminal is connected to the drain of the NMOS transistor MN2 and the source of the NMOS transistor MN1. The first input terminal of the transmission gate TG3 is connected to the source terminal of the NMOS transistor MN4 and the output terminal of the unity-gain buffer A2, and the second input terminal is connected to SD2.

2. The control circuit with soft-start and soft-shutdown functions as described in claim 1, characterized in that, The buffer module includes an NMOS transistor MN5 and a current source I4; the drain of the NMOS transistor MN5 is connected to the power supply, the source is connected to the first node of the current source I4, and the second node of the current source I4 is grounded; the third input of the transmission gate TG3 is connected between the source of the NMOS transistor MN5 and the first node of the current source I4.

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