Soft start circuit for power management chip

Abstract

The present disclosure relates to a soft start circuit for a power management chip. The soft start circuit comprises a slope voltage generating unit configured to generate a slope voltage according to an enable signal inside the power management chip; a reference voltage generating unit connected to the slope voltage generating unit, configured to receive the slope voltage and generate a reference voltage according to the slope voltage; and a comparison unit connected to the reference voltage generating unit, configured to output a control signal according to a preset reference voltage and a preset node voltage at a preset node in the reference voltage generating unit, so as to disable the switching action of the power management chip after the generation of the enable signal and before the generation of the reference voltage. Through the scheme of the present disclosure, the start oscillation problem caused by the repeated switching of the power management chip after the generation of the enable signal and before the generation of the reference voltage can be avoided.

Description

Technical Field

[0001] This disclosure generally relates to the field of power management technology. More specifically, this disclosure relates to a soft-start circuit for a power management chip. Background Technology

[0002] As people's demand for power increases, power management chips have developed rapidly and are widely used in power supplies for various electronic devices, daily lighting, and household appliances.

[0003] The BUCK circuit (step-down circuit) is one of the most commonly used circuits in power management chips. For the BUCK circuit, the existing soft-start circuit usually does not generate the reference voltage at the same time as the enable signal during the soft-start process. That is, the reference voltage will remain at 0 for a period of time after the enable signal is generated. This means that the feedback voltage should also remain at 0 for that period of time. However, since the enable signal causes the chip to switch, the feedback voltage will repeatedly rise and then return to zero. This oscillation is not conducive to the soft start of the power management chip. Summary of the Invention

[0004] In order to at least partially solve the technical problems mentioned in the background art, the present disclosure provides a soft-start circuit for a power management chip.

[0005] This disclosure provides a soft-start circuit for a power management chip. The soft-start circuit includes: a ramp voltage generation unit for generating a ramp voltage based on an enable signal within the power management chip; a reference voltage generation unit connected to the ramp voltage generation unit for receiving the ramp voltage and generating a reference voltage based on the ramp voltage; and a comparison unit connected to the reference voltage generation unit for outputting a control signal based on a preset reference voltage and a preset node voltage at a preset node in the reference voltage generation unit, thereby disabling the switching operation of the power management chip after the enable signal is generated and before the reference voltage is generated.

[0006] According to an embodiment of this disclosure, the ramp voltage generation unit includes a current source and a capacitor. The current source is connected to one end of the capacitor, and the other end of the capacitor is grounded. The current source charges the capacitor via a first node to generate a ramp voltage at the first node.

[0007] According to an embodiment of this disclosure, the reference voltage generation unit includes an NMOS transistor, a first resistor, and a second resistor. The gate of the NMOS transistor is connected to the first node in the ramp voltage generation unit, the drain of the NMOS transistor is connected to the drain voltage, the source of the NMOS transistor is connected to one end of the first resistor, one end of the second resistor is connected to the other end of the first resistor, and the other end of the second resistor is grounded.

[0008] According to an embodiment of this disclosure, when the ramp voltage is greater than the threshold voltage of the NMOS transistor, the NMOS transistor is turned on, and the voltage generated at the second node located between the first resistor and the second resistor is used as the reference voltage.

[0009] According to embodiments of this disclosure, the drain voltage is a bandgap reference voltage.

[0010] According to an embodiment of this disclosure, the slope of the reference voltage is the product of the slope of the ramp voltage and the voltage division ratio, wherein the voltage division ratio is the ratio of the resistance value of the second resistor to the sum of the resistance values ​​of the first resistor and the second resistor.

[0011] According to an embodiment of this disclosure, the comparison unit includes a comparator, the non-inverting input of the comparator receives the preset reference voltage, the negative input of the comparator receives the preset node voltage, and the output of the comparator outputs the control signal, wherein the preset node is located between the source of the NMOS transistor in the reference voltage generation unit and the first resistor.

[0012] According to an embodiment of this disclosure, when the preset node voltage is less than or equal to the preset reference voltage, the control signal is high to prevent the power management chip from switching on and off; when the preset node voltage is greater than the preset reference voltage, the control signal is low to allow the power management chip to switch on and off.

[0013] According to an embodiment of this disclosure, the comparison unit further includes a voltage divider circuit, through which the preset reference voltage is obtained from the drain voltage.

[0014] According to an embodiment of this disclosure, the preset reference voltage is 30mV.

[0015] The soft-start circuit for power management chips disclosed herein can avoid the startup oscillation problem caused by the power management chip repeatedly switching on and off after the enable signal is generated and before the reference voltage is generated. Attached Figure Description

[0016] The above and other objects, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the present disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0017] Figure 1 This is a structural framework diagram illustrating a soft-start circuit for a power management chip according to an embodiment of the present disclosure;

[0018] Figure 2 This is a schematic diagram illustrating the structure of a soft-start circuit for a power management chip according to an embodiment of the present disclosure;

[0019] Figure 3 This is a timing diagram illustrating the enable signal, ramp voltage, reference voltage, and control signal of a soft-start circuit for a power management chip according to an embodiment of the present disclosure. Detailed Implementation

[0020] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0021] To facilitate understanding of the technical solutions disclosed herein, the embodiments of the prior art are described below in conjunction with the accompanying drawings.

[0022] See Figure 1 , Figure 1 This is a structural framework diagram illustrating a soft-start circuit 1 for a power management chip according to an embodiment of the present disclosure. Figure 1 As shown, the soft-start circuit 1 includes a ramp voltage generation unit 10, a reference voltage generation unit 20, and a comparator unit 30. The ramp voltage generation unit 10 generates a ramp voltage VRAMP based on an enable signal within the power management chip. The reference voltage generation unit 20 is connected to the ramp voltage generation unit 10 and receives the ramp voltage VRAMP, generating a reference voltage VREF based on the ramp voltage. The comparator unit 30 is connected to the reference voltage generation unit 20 and outputs a control signal based on a preset reference voltage and a preset node voltage at a preset node in the reference voltage generation unit 20, thereby disabling the switching operation of the power management chip after the enable signal is generated and before the reference voltage VREF is generated.

[0023] Further, see Figure 2 , Figure 2 This is a schematic diagram illustrating the structure of a soft-start circuit 1 for a power management chip according to an embodiment of this disclosure. Figure 2 As shown, the ramp voltage generation unit 10 includes a current source 101 and a capacitor C. The power supply voltage VDD supplies power to the current source 101. The current source 101 is connected to one end of the capacitor C, and the other end of the capacitor C is grounded. The current source 101 charges the capacitor C through the first node N1 to generate a ramp voltage VRAMP at the first node N1.

[0024] The reference voltage generation unit 20 includes an NMOS transistor M, a first resistor R1, and a second resistor R2. The gate of the NMOS transistor M is connected to the first node N1 in the ramp voltage generation unit 10 to receive the ramp voltage VRAMP. The drain of the NMOS transistor M is connected to the drain voltage VBG. The source of the NMOS transistor M is connected to one end of the first resistor R1. One end of the second resistor R2 is connected to the other end of the first resistor R1, and the other end of the second resistor R2 is grounded.

[0025] When the ramp voltage VRAMP is greater than the threshold voltage of the NMOS transistor M, the NMOS transistor M is turned on, and the voltage generated at the second node N2 located between the first resistor R1 and the second resistor R2 is used as the reference voltage VREF.

[0026] According to embodiments of this disclosure, the drain voltage VBG is a bandgap reference voltage. This facilitates drain power supply for the NMOS transistor.

[0027] According to embodiments of this disclosure, the slope of the reference voltage VREF is the product of the slope of the ramp voltage VRAMP and the voltage division ratio, wherein the voltage division ratio is the ratio of the resistance value of the second resistor R2 to the sum of the resistance values ​​of the first resistor R1 and the second resistor R2. Thus, a reference voltage that meets the requirements can be formed, and this reference voltage can rise smoothly with the ramp voltage.

[0028] The comparison unit 30 includes a comparator 301. The positive input terminal of the comparator 301 receives the preset reference voltage VREF_LOW, the negative input terminal of the comparator 301 receives the preset node voltage VS, and the output terminal of the comparator 301 outputs the control signal NOREF. The preset node N3 is located between the source of the NMOS transistor M in the reference voltage generation unit 10 and the first resistor R1.

[0029] When the preset node voltage VS is less than or equal to the preset reference voltage VREF_LOW, the control signal NOREF is high to disable the switching operation of the power management chip. When the preset node voltage VS is greater than the preset reference voltage VREF_LOW, the control signal NOREF is low to enable the switching operation of the power management chip.

[0030] According to an embodiment of this disclosure, the comparison unit 30 further includes a voltage divider circuit 302, through which the preset reference voltage VREF_LOW is obtained from the drain voltage VBG by voltage divider circuit 302, thereby facilitating the formation of the preset reference voltage. The voltage divider circuit 302 may be a resistor voltage divider circuit.

[0031] According to embodiments of this disclosure, the preset reference voltage VREF_LOW is 30mV. This allows for a more accurate determination of the NMOS transistor's conduction status.

[0032] See Figure 3 , Figure 3 This is a timing diagram illustrating the enable signal, ramp voltage, reference voltage, and control signals of a soft-start circuit for a power management chip according to an embodiment of this disclosure. (In conjunction with...) Figure 2 ,like Figure 3 As shown, when the enable signal ENDC is generated inside the power management chip, that is, when the enable signal ENDC level goes high, the current source 101 starts charging the capacitor C, thereby generating a ramp voltage VRAMP at the first node N1. Before the ramp voltage VRAMP rises to the threshold voltage of the NMOS transistor, the NMOS transistor is not turned on, the preset node voltage VS at the preset node N3 remains 0, and the reference voltage VREF remains 0. Since the preset node voltage VS is less than the preset reference voltage at this time, the control signal NOREF remains at its initial high level. The high-level control signal can prevent the switching action of the power management chip. Therefore, during the period when the reference voltage VREF is 0, there is no phenomenon of the feedback voltage continuously rising and then returning to zero due to the switching action of the power management chip. After the ramp voltage VRAMP is higher than the threshold voltage of the NMOS transistor, the preset node voltage VS rises, and the reference voltage VREF also begins to rise. When the preset node voltage VS is greater than the preset reference voltage VREF_LOW, the control signal NOREF goes low, allowing the chip to switch, the feedback voltage begins to rise, and the soft-start process officially begins. As the ramp voltage VRAMP increases further, the NMOS transistor enters the linear region. The source voltage (preset node voltage VS) of the NMOS transistor can reach the drain voltage VBG. At this time, the reference voltage VREF also reaches a stable value. Thereafter, even if the ramp voltage VRAMP increases further, the reference voltage VREF will always remain stable.

[0033] The technical solution disclosed herein can generate a control signal after the enable signal is generated and before the reference voltage VREF caused by the threshold voltage of the NMOS transistor is generated, thereby shielding the switching action of the power management chip and avoiding oscillation at the start of soft start. Furthermore, due to the presence of the control signal, even if the enable signal is generated for any reason and the ramp voltage is 0, such as in the case of a short circuit to ground caused by a problem with capacitor C, the control signal will always remain in the state of shielding the chip's switching action, thus providing protection during soft start.

[0034] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0035] It should be understood that the terms "first" and "second," etc., in the claims, specification, and drawings of this disclosure are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0036] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0037] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this disclosure. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this disclosure, and on the specific implementation methods and application scope of this disclosure, are all within the scope of protection of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A soft start circuit for a power management chip, comprising: The soft start circuit comprises: a slope voltage generating unit for generating a slope voltage according to an enable signal inside the power management chip, the slope voltage generating unit comprising a current source and a capacitor, the current source being connected with one end of the capacitor, the other end of the capacitor being grounded, the current source charging the capacitor via a first node to generate a slope voltage at the first node; a reference voltage generating unit connected with the slope voltage generating unit for receiving the slope voltage and generating a reference voltage according to the slope voltage, the reference voltage generating unit comprising an NMOS tube, a first resistor and a second resistor, the gate of the NMOS tube being connected with the first node in the slope voltage generating unit, the drain of the NMOS tube being connected with a drain voltage, the source of the NMOS tube being connected with one end of the first resistor, one end of the second resistor being connected with the other end of the first resistor, the other end of the second resistor being grounded; a comparison unit connected with the reference voltage generating unit for outputting a control signal according to a preset reference voltage and a preset node voltage at a preset node in the reference voltage generating unit to inhibit switching action of the power management chip after the enable signal is generated and before the reference voltage is generated.

2. The soft start circuit for a power management chip as claimed in claim 1, wherein, When the slope voltage is greater than the threshold voltage of the NMOS tube, the NMOS tube is turned on, and a voltage generated at a second node between the first resistor and the second resistor is taken as the reference voltage.

3. The soft start circuit for a power management chip as recited in claim 2, wherein, The drain voltage is a bandgap reference voltage.

4. The soft start circuit for a power management chip as recited in claim 2, wherein, The slope of the reference voltage is a product of the slope of the slope voltage and a voltage division ratio, wherein the voltage division ratio is a ratio of a resistance value of the second resistor to a sum of resistance values of the first resistor and the second resistor.

5. The soft start circuit for a power management chip as recited in claim 2, wherein, The comparison unit comprises a comparator, a positive phase input end of the comparator receiving the preset reference voltage, a negative phase input end of the comparator receiving the preset node voltage, and an output end of the comparator outputting the control signal, wherein the preset node is between the source of the NMOS tube and the first resistor in the reference voltage generating unit.

6. The soft start circuit for a power management chip as recited in claim 5, wherein, When the preset node voltage is less than or equal to the preset reference voltage, the control signal is high to inhibit the switching action of the power management chip, and when the preset node voltage is greater than the preset reference voltage, the control signal is low to allow the switching action of the power management chip.

7. The soft start circuit for a power management chip as recited in claim 5, wherein, The comparison unit further comprises a voltage division circuit, and the preset reference voltage is obtained by voltage division from the drain voltage through the voltage division circuit.

8. The soft start circuit for a power management chip as recited in claim 7, wherein, The preset reference voltage is 30mv.

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