A discrete power semiconductor device parallelly integrated power cell and a manufacturing method thereof

Abstract

This invention discloses a parallel integrated power unit of discrete power semiconductor devices, including a power board and a driving board stacked on top of the power board. The power board has N bridge arms, each including M parallel discrete semiconductor devices. M / 2 discrete semiconductor devices of the first upper bridge arm and M / 2 discrete semiconductor devices of the first lower bridge arm are disposed in a first power region. The remaining M / 2 discrete semiconductor devices of the first upper bridge arm and the remaining M / 2 discrete semiconductor devices of the first lower bridge arm are disposed in a second power region. The first and second power regions are symmetrically arranged, and the power board and the driving board are electrically connected together. This integrated power unit uses parallel discrete semiconductor devices, resulting in good current sharing, low parasitic inductance in the DC power circuit, and small voltage spikes in the discrete power semiconductor devices during full-load operation. It also offers lower cost, better electromagnetic compatibility, and balanced current for each power device.

Description

Technical Field

[0001] This invention relates to the field of frequency converters and motor drivers, and in particular to a power unit for parallel integration of discrete power semiconductor devices and its fabrication method. Background Technology

[0002] Power semiconductor components commonly used in power electronic equipment can be categorized into discrete devices (single-chip wafer packages, commonly including TO247) and integrated modules (multi-chip wafer packages into modules, with various topologies available). Power modules offer high integration and small size, but their cost is higher than discrete device solutions for the same current capability. Discrete devices offer more dispersed layouts and better heat dissipation for the same current capability, but require solutions for power capacity expansion, layout, and installation.

[0003] Discrete power semiconductor devices mainly include MOSFETs and IGBTs. Existing inverter technologies have adopted solutions that use discrete power semiconductor devices instead of integrated inverter modules, but the power output of these inverters is very low. Each arm of the inverter unit uses only one discrete power semiconductor device, and the inverter power does not exceed 7.5kW. The cost of the power unit is high, and the power board uses a copper and aluminum busbar layout. This layout requires very large absorption capacitors, resulting in large parasitic inductance in the power circuit. Due to the parasitic inductance of the main power circuit, voltage spikes are generated across the power semiconductor devices when they are turned off. If the spike voltage is too high, it will break down the power semiconductor device. A common measure in existing inverter technologies is to add absorption capacitors across the positive and negative buses to suppress the spike voltage. However, this measure is only a temporary solution. The drive board and power board are not designed in separate layers, and the wiring of the drive board disrupts the positive and negative busbar layout of the power board, resulting in extremely uneven current distribution among the power devices.

[0004] There is an urgent need for a power unit that integrates discrete power semiconductor devices in parallel, which has good current sharing effect, low parasitic inductance of DC power circuit, small voltage spikes of discrete power semiconductor devices during full load operation, lower cost, better electromagnetic compatibility of power unit, and balances the current of each power device. Summary of the Invention

[0005] The technical problem to be solved by this invention is to propose a power unit that integrates discrete power semiconductor devices in parallel. This power unit integrates discrete power semiconductor devices in parallel, which has good current sharing effect, low parasitic inductance of DC power circuit, and small voltage spikes of discrete power semiconductor devices when running at full load. It also has lower cost, better electromagnetic compatibility of power unit, and balances the current of each power device.

[0006] To solve the above-mentioned technical problems, the present invention provides a discrete power semiconductor device parallel integrated power unit, characterized in that: it includes a power board and a driving board stacked with the power board, the power board is provided with N bridge arms, each of the bridge arms includes M discrete semiconductor devices connected in parallel, and the N bridge arms are: a first upper bridge arm, a first lower bridge arm, a second upper bridge arm, a second lower bridge arm, ..., the N / 2th upper bridge arm and the N / 2th lower bridge arm;

[0007] M / 2 discrete semiconductor devices of the first upper bridge arm and M / 2 discrete semiconductor devices of the first lower bridge arm are disposed in a first power region; the other M / 2 discrete semiconductor devices of the first upper bridge arm and the other M / 2 discrete semiconductor devices of the first lower bridge arm are disposed in a second power region; M / 2 discrete semiconductor devices of the second upper bridge arm and M / 2 discrete semiconductor devices of the second lower bridge arm are disposed in a third power region; the other M / 2 discrete semiconductor devices of the second upper bridge arm and the other M / 2 discrete semiconductor devices of the second lower bridge arm are disposed in a fourth power region; ...; the first and second discrete semiconductor devices of the N / 2th upper bridge arm and the first and second discrete semiconductor devices of the N / 2th lower bridge arm are disposed in the (N-1)th power region; the third and fourth discrete semiconductor devices of the N / 2th upper bridge arm and the third and fourth discrete semiconductor devices of the N / 2th lower bridge arm are disposed in the Nth power region;

[0008] The first power region and the second power region are symmetrically arranged, the third power region and the fourth power region are symmetrically arranged, ..., the (N-1)th power region and the Nth power region are symmetrically arranged;

[0009] The first power region, the second power region, ... and the Nth power region are each provided with output terminals that are equidistantly connected to the discrete semiconductor devices inside them. The discrete semiconductor devices inside the first power region, the second power region, ... and the Nth power region are connected to the positive and negative buses of the power board. The power board and the driver board are electrically connected together.

[0010] Preferably, the M / 2 discrete semiconductor devices of the first upper bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the first lower bridge arm, and the M / 2 discrete semiconductor devices of the first lower bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the first upper bridge arm; the M / 2 discrete semiconductor devices of the second upper bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the second lower bridge arm, and the M / 2 discrete semiconductor devices of the second lower bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the second upper bridge arm; ...; the M / 2 discrete semiconductor devices of the N / 2th upper bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the N / 2th lower bridge arm, and the M / 2 discrete semiconductor devices of the N / 2th lower bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the N / 2th upper bridge arm;

[0011] Preferably, the power board includes a stacked structure composed of multiple PCBs, which ensures that the routing of the drive board does not affect the layout of the positive and negative bus power circuits. The stacked structure is formed by vertically stacking each layer of PCBs from top to bottom according to the corresponding positive and negative buses, with each layer of PCBs corresponding to the positive and negative buses being completely stacked.

[0012] Preferably, M is 4; each of the bridge arms includes four discrete semiconductor devices connected in parallel, the first and second discrete semiconductor devices of the first upper bridge arm and the first and second discrete semiconductor devices of the first lower bridge arm are disposed in the first power region, the third and fourth discrete semiconductor devices of the first upper bridge arm and the third and fourth discrete semiconductor devices of the first lower bridge arm are disposed in the second power region; the first and second discrete semiconductor devices of the second upper bridge arm and the first and second discrete semiconductor devices of the second lower bridge arm are disposed in the second power region. The third and fourth discrete semiconductor devices of the second upper bridge arm and the third and fourth discrete semiconductor devices of the second lower bridge arm are disposed in the third power region; ...; the first and second discrete semiconductor devices of the N / 2 upper bridge arm and the first and second discrete semiconductor devices of the N / 2 lower bridge arm are disposed in the N-1 power region, and the third and fourth discrete semiconductor devices of the N / 2 upper bridge arm and the third and fourth discrete semiconductor devices of the N / 2 lower bridge arm are disposed in the N power region.

[0013] Preferably, the M discrete semiconductor devices of the first upper bridge arm are connected to the positive bus of the power board, and the M discrete semiconductor devices of the first lower bridge arm are connected to the negative bus of the power board; the M discrete semiconductor devices of the second upper bridge arm are connected to the positive bus of the power board, and the M discrete semiconductor devices of the second lower bridge arm are connected to the negative bus of the power board; ...; the M discrete semiconductor devices of the Nth upper bridge arm are connected to the positive bus of the power board, and the M discrete semiconductor devices of the Nth lower bridge arm are connected to the negative bus of the power board; the power board and the driver board are connected together through the pins of the discrete power semiconductor devices, and a safety distance is maintained between the power board and the driver board.

[0014] Preferably, the output terminal is located in the middle of each corresponding power region, and the distance from the discrete power semiconductor device in each power region to the corresponding output terminal is equal.

[0015] Preferably, the discrete power semiconductor device parallel integrated power unit according to claim 1 is characterized in that: the driving board includes a driving circuit, and the driving traces from the driving circuit to each discrete power semiconductor device on the power board are of equal length.

[0016] Preferably, the discrete semiconductor device is a single-transistor IGBT.

[0017] Preferably, the collectors of the first, second, third, and fourth discrete semiconductor devices of the first upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the first lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the first upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices of the first lower bridge arm are connected to the corresponding output terminals. Terminals; the collectors of the first, second, third, and fourth discrete semiconductor devices of the first upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the first lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the first upper bridge arm are connected to the corresponding output terminals; the collectors of the first, second, third, and fourth discrete semiconductor devices of the first lower bridge arm are connected to the corresponding output terminals. The collectors of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the corresponding output terminals. The collectors of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the corresponding output terminals; ...The collectors of the first, second, third, and fourth discrete semiconductor devices in the N / 2 upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices in the N / 2 lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices in the N / 2 upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices in the N / 2 lower bridge arm are connected to the corresponding output terminals. The collectors of the first, second, third, and fourth discrete semiconductor devices in the N / 2 upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices in the N / 2 lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices in the N / 2 upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices in the N / 2 lower bridge arm are connected to the corresponding output terminals.

[0018] With the above structure, the discrete power semiconductor device parallel integrated power unit uses discrete semiconductor devices connected in parallel, with power devices grouped and symmetrically arranged, resulting in good output current sharing. The DC positive and negative buses are routed using a PCB board stack-up structure, with the positive and negative buses fully stacked, resulting in low parasitic inductance in the power circuit and small voltage spikes in the discrete power semiconductor devices during full-load operation. It does not use absorption capacitors, resulting in lower cost and better electromagnetic compatibility of the power unit. The driver board and power board are designed in layers, and the drive traces on the driver board do not affect the DC bus layout of the power board. The drive traces from the drive circuit to each discrete power semiconductor device are of equal length, thereby balancing the current of each power device. Attached Figure Description

[0019] Figure 1 This is an overall structural diagram of the discrete power semiconductor device parallel integrated power unit of the present invention;

[0020] Figure 2 This is a structural diagram of the discrete power semiconductor device of the present invention, which integrates a power unit in parallel with discrete power semiconductor devices;

[0021] Figure 3 This is a structural diagram of the driver board for the parallel integrated power unit of discrete power semiconductor devices according to the present invention;

[0022] Figure 4 This is an assembly diagram of the power board and driver board of the discrete power semiconductor device parallel integrated power unit of the present invention;

[0023] Figure 5 The waveform diagram shows the current balance test of the discrete power semiconductor device of the present invention, which is a discrete power semiconductor device with a parallel integrated power unit.

[0024] Figure 6 This is a peak voltage waveform diagram of the discrete power semiconductor device in operation, which is a discrete power semiconductor device with a parallel integrated power unit according to the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0026] Example 1

[0027] Please see Figure 1 , Figure 1 This is an overall structural diagram of the discrete power semiconductor device parallel integrated power unit of the present invention. This embodiment discloses a discrete power semiconductor device parallel integrated power unit, including a power board 1 and a driving board 11 stacked on the power board. The power board 1 is provided with N bridge arms, each of which includes M discrete semiconductor devices connected in parallel. The N bridge arms are: a first upper bridge arm, a first lower bridge arm, a second upper bridge arm, a second lower bridge arm, ..., an N / 2th upper bridge arm and an N / 2th lower bridge arm. The M / 2 discrete semiconductor devices of the first upper bridge arm and the M / 2 discrete semiconductor devices of the first lower bridge arm are disposed in a first power region 71. The other M / 2 discrete semiconductor devices of the first upper bridge arm and the other M / 2 discrete semiconductor devices of the first lower bridge arm are disposed in a first power region 71. The devices are disposed in the second power region 72; M / 2 discrete semiconductor devices of the second upper bridge arm and M / 2 discrete semiconductor devices of the second lower bridge arm are disposed in the third power region, and the other M / 2 discrete semiconductor devices of the second upper bridge arm and the other M / 2 discrete semiconductor devices of the second lower bridge arm are disposed in the fourth power region; ...; the first and second discrete semiconductor devices of the N / 2th upper bridge arm and the first and second discrete semiconductor devices of the N / 2th lower bridge arm are disposed in the (N-1)th power region, and the third and fourth discrete semiconductor devices of the N / 2th upper bridge arm and the third and fourth discrete semiconductor devices of the N / 2th lower bridge arm are disposed in the Nth power region;

[0028] The first power region 71 and the second power region 72 are symmetrically arranged, the third power region and the fourth power region are symmetrically arranged, ..., the (N-1)th power region and the Nth power region are symmetrically arranged;

[0029] The first power region, the second power region, ... and the Nth power region are each provided with output terminals that are equidistantly connected to the discrete semiconductor devices inside them. The discrete semiconductor devices inside the first power region, the second power region, ... and the Nth power region are connected to the positive and negative buses of the power board. The power board and the driver board are electrically connected together.

[0030] The M / 2 discrete semiconductor devices of the first upper bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the first lower bridge arm; the M / 2 discrete semiconductor devices of the first lower bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the first upper bridge arm; the M / 2 discrete semiconductor devices of the second upper bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the second lower bridge arm; the M / 2 discrete semiconductor devices of the second lower bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the second upper bridge arm; ...; the M / 2 discrete semiconductor devices of the N / 2th upper bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the N / 2th lower bridge arm; the M / 2 discrete semiconductor devices of the N / 2th lower bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the N / 2th upper bridge arm.

[0031] The M discrete semiconductor devices of the first upper bridge arm are connected to the positive bus of the power board, and the M discrete semiconductor devices of the first lower bridge arm are connected to the negative bus of the power board; the M discrete semiconductor devices of the second upper bridge arm are connected to the positive bus of the power board, and the M discrete semiconductor devices of the second lower bridge arm are connected to the negative bus of the power board; ...; the M discrete semiconductor devices of the Nth upper bridge arm are connected to the positive bus of the power board, and the M discrete semiconductor devices of the Nth lower bridge arm are connected to the negative bus of the power board; the power board and the driver board are connected together through the pins of the discrete power semiconductor devices, and a safety distance is maintained between the power board and the driver board.

[0032] The output terminals are located in the middle of each corresponding power region, and the distance from the discrete power semiconductor device in each power region to the corresponding output terminal is equal.

[0033] In this embodiment, the collectors of the first, second, third, and fourth discrete semiconductor devices of the first upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the first lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the first upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices of the first lower bridge arm are connected to the corresponding output terminals. Output terminals; the collectors of the first, second, third, and fourth discrete semiconductor devices of the first upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the first lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the first upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices of the first lower bridge arm are connected to the corresponding output terminals. The collectors of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the corresponding output terminals. The collectors of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the corresponding output terminals; ...The collectors of the first, second, third, and fourth discrete semiconductor devices in the N / 2 upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices in the N / 2 lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices in the N / 2 upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices in the N / 2 lower bridge arm are connected to the corresponding output terminals. The collectors of the first, second, third, and fourth discrete semiconductor devices in the N / 2 upper bridge arm are connected to the positive bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices in the N / 2 lower bridge arm are connected to the negative bus of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices in the N / 2 upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices in the N / 2 lower bridge arm are connected to the corresponding output terminals.

[0034] Example 2

[0035] This embodiment is based on Embodiment 1. In this embodiment, the driving board includes a driving circuit 12, and the driving traces from the driving circuit 12 to each discrete power semiconductor device on the power board are of equal length.

[0036] The power board includes a multi-layer PCB board structure that ensures the routing of the drive board does not affect the layout of the positive and negative bus power circuits. The multi-layer PCB board is vertically stacked from top to bottom according to the corresponding positive and negative bus, and the PCB boards corresponding to the positive and negative bus are completely stacked.

[0037] In this embodiment, the power circuits of the positive and negative DC buses are arranged on the PCB layered layout of the power board. The interlayer spacing of the layered layout is small, and the positive and negative bus traces are fully overlapped during layout. When the inverter is running, the magnetic induction lines of the positive and negative buses are in opposite directions and cancel each other out. According to the principles of electromagnetics, the parasitic inductance of the bus circuit will be very small. The Vce (collector-emitter) voltage of a single IGBT is tested using a double-pulse method under the condition of 800V bus voltage and high output current. Figure 6The figure shows the peak voltage waveform at the turn-off moment of a single IGBT. The peak voltage is very small, so the absorption capacitor between the positive and negative buses can be omitted, reducing costs. Moreover, the low peak voltage also results in better electromagnetic compatibility of the power unit.

[0038] Example 3

[0039] In this embodiment, the discrete power semiconductor device parallel integrated power unit is the inverter power unit of the frequency converter. The inverter power unit adopts a three-phase two-level inverter topology with a total of 6 bridge arms. Each bridge arm is composed of 4 discrete power semiconductor devices connected in parallel. The discrete semiconductor device is a single-tube IGBT2. The pins of the single-tube IGBT2 extend out of the power board 1 and the driver board 11 and are respectively soldered to the power board 1 and the driver board 11. The discrete power semiconductor device parallel integrated power unit also includes an insulating structure 3 for fixing the single-tube IGBT.

[0040] The first and second discrete semiconductor devices of the first upper bridge arm and the first and second discrete semiconductor devices of the first lower bridge arm are disposed in the first power region 71. The third and fourth discrete semiconductor devices of the first upper bridge arm and the third and fourth discrete semiconductor devices of the first lower bridge arm are disposed in the second power region 72. The first power region 71 and the second power region 72 form one phase 7 of the integrated power unit. The first and second discrete semiconductor devices of the second upper bridge arm and the first and second discrete semiconductor devices of the second lower bridge arm are disposed in the third power region. The third and fourth discrete semiconductor devices of the third upper bridge arm and the third and fourth discrete semiconductor devices of the third lower bridge arm are disposed in the fourth power region; the third and fourth power regions form one phase of the integrated power unit; the first and second discrete semiconductor devices of the third upper bridge arm and the first and second discrete semiconductor devices of the third lower bridge arm are disposed in the fifth power region; the third and fourth discrete semiconductor devices of the third upper bridge arm and the third and fourth discrete semiconductor devices of the third lower bridge arm are disposed in the sixth power region; the fifth and sixth power regions form one phase of the integrated power unit.

[0041] The output terminal 51 is placed between the four single-tube IGBT2, which can lead out the inverter output current with the shortest distance and reduce the heat generation of the power board.

[0042] The collectors of the first, second, third, and fourth discrete semiconductor devices in the first upper bridge arm are connected to the positive busbar of power board 1. The emitters of the first, second, third, and fourth discrete semiconductor devices in the first lower bridge arm are connected to the negative busbar of power board 1. The emitters of the first, second, third, and fourth discrete semiconductor devices in the first upper bridge arm are connected to the corresponding output terminals 51. The collectors of the first, second, third, and fourth discrete semiconductor devices in the first lower bridge arm are connected to the corresponding output terminals. The collectors of the first, second, third, and fourth discrete semiconductor devices of the first upper bridge arm are connected to the positive bus of power board 1; the emitters of the first, second, third, and fourth discrete semiconductor devices of the first lower bridge arm are connected to the negative bus of power board 1; the emitters of the first, second, third, and fourth discrete semiconductor devices of the first upper bridge arm are connected to the corresponding output terminals 51; and the collectors of the first, second, third, and fourth discrete semiconductor devices of the first lower bridge arm are connected to the corresponding output terminals 51. The collectors of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the positive busbar of power board 1; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the negative busbar of power board 1; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the corresponding output terminals. The collectors of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the positive busbar of the power board; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the negative busbar of the power board 1; the emitters of the first, second, third, and fourth discrete semiconductor devices of the second upper bridge arm are connected to the corresponding output terminals; and the collectors of the first, second, third, and fourth discrete semiconductor devices of the second lower bridge arm are connected to the corresponding output terminals; ...The collectors of the first, second, third, and fourth discrete semiconductor devices of the third upper bridge arm are connected to the positive bus of the power board 1. The emitters of the first, second, third, and fourth discrete semiconductor devices of the third lower bridge arm are connected to the negative bus of the power board. The emitters of the first, second, third, and fourth discrete semiconductor devices of the third upper bridge arm are connected to the corresponding output terminals 51. The collectors of the first, second, third, and fourth discrete semiconductor devices of the third lower bridge arm are connected to the corresponding output terminals 51. The collectors of the first, second, third, and fourth discrete semiconductor devices in the third upper bridge arm are connected to the positive busbar of the power board. The emitters of the first, second, third, and fourth discrete semiconductor devices in the third lower bridge arm are connected to the negative busbar of the power board. The emitters of the first, second, third, and fourth discrete semiconductor devices in the third upper bridge arm are connected to the corresponding output terminals 51. The collectors of the first, second, third, and fourth discrete semiconductor devices in the third lower bridge arm are connected to the corresponding output terminals 51.

[0043] Please see Figure 4 In this embodiment, the upper and lower bridge arms of the power board 1 are each composed of four single-transistor IGBTs 2 connected in parallel. A conductive bus 13 is connected to the two sets of output terminals, and the inverter current is led out at the midpoint of the current bus 13. The distance from each of the single-transistor IGBTs to the final output terminal is equal. At this time, a double-pulse method is used to test the current balance of the four IGBTs connected in parallel. Figure 5 As shown, under the condition of high output current, the current imbalance is less than 5%, and the current sharing effect is good.

[0044] Example 4

[0045] This embodiment discloses a method for fabricating a parallel integrated power unit of a discrete power semiconductor device as described in Embodiment 1. The method includes the following steps:

[0046] The PCB body of the power board and the PCB body of the driver board are respectively assembled with the materials and then passed through the furnace for the first time to form the first power board PCBA and the driver board PCBA.

[0047] Discrete power devices are passed through the pre-drilled mounting holes on the PCB of the power board, and then fixed by tooling and reflowed together with the first power board PCBA. The discrete power devices are then soldered to the first power board PCBA to form the second power board PCBA.

[0048] Align the pre-drilled mounting holes on the driver board PCBA with the pins of the discrete power devices exposed on the second power board PCBA, and assemble them together with the second power board PCBA.

[0049] The second power board PCBA and the driver board PCBA are reflowed together, and the driver board PCBA and the second power board PCBA are soldered together to form an integrated power unit of discrete power semiconductor devices.

[0050] A certain gap is maintained between the driver board PCBA and the second power board PCBA through tooling control. This gap is used to ensure the safety distance requirements between the driver board PCBA and the second power board PCBA, and this gap helps the second power board PCBA to dissipate heat.

[0051] This discrete power semiconductor device parallel integrated power unit adopts discrete semiconductor devices in parallel, with power devices grouped and symmetrically arranged, resulting in good output current sharing. The DC positive and negative buses are routed using a PCB board stack-up structure, with the positive and negative buses fully stacked, resulting in low parasitic inductance in the power circuit and small voltage spikes in the discrete power semiconductor devices during full-load operation. It does not use absorption capacitors, resulting in lower cost and better electromagnetic compatibility of the power unit. The driver board and power board are designed in layers, and the drive traces on the driver board do not affect the DC bus layout of the power board. The drive traces from the drive circuit to each discrete power semiconductor device are of equal length, thereby balancing the current of each power device.

[0052] It should be understood that the above are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A discrete power semiconductor device parallel integrated power cell, characterized by: The power plate and the driving plate arranged in the power plate, the power plate includes the laminated structure of the multilayer PCB plate, so that the driving plate wiring does not affect the positive and negative bus power loop layout, the power plate is provided with N bridge arms, each bridge arm includes M parallel discrete semiconductor devices, the N bridge arms are: the first upper bridge arm, the first lower bridge arm, the second upper bridge arm, the second lower bridge arm, the N / 2 upper bridge arm and the N / 2 lower bridge arm; The M / 2 discrete semiconductor devices of the first upper bridge arm and the M / 2 discrete semiconductor devices of the first lower bridge arm are arranged in the first power area, and the other M / 2 discrete semiconductor devices of the first upper bridge arm and the other M / 2 discrete semiconductor devices of the first lower bridge arm are arranged in the second power area; the M / 2 discrete semiconductor devices of the second upper bridge arm and the M / 2 discrete semiconductor devices of the second lower bridge arm are arranged in the third power area, and the other M / 2 discrete semiconductor devices of the second upper bridge arm and the other M / 2 discrete semiconductor devices of the second lower bridge arm are arranged in the fourth power area; …; the first discrete semiconductor device and the second discrete semiconductor device of the N / 2 upper bridge arm and the first discrete semiconductor device and the second discrete semiconductor device of the N / 2 lower bridge arm are arranged in the N-1 power area, and the third discrete semiconductor device and the fourth discrete semiconductor device of the N / 2 upper bridge arm and the third discrete semiconductor device and the fourth discrete semiconductor device of the N / 2 lower bridge arm are arranged in the N power area; The first power area and the second power area are symmetrically arranged, the third power area and the fourth power area are symmetrically arranged, …, the N-1 power area and the N power area are symmetrically arranged; The first power area, the second power area, …, and the N power area are all provided with output terminals which are equidistantly connected with the discrete semiconductor devices inside them, and the output terminals are arranged in the middle of each corresponding power area, the output terminals of the two power areas symmetrically arranged in the same bridge arm are connected through a conductive busbar, and the inverse variable output current is led out at the midpoint of the conductive busbar; The discrete semiconductor devices inside the first power area, the second power area, …, and the N power area are connected with the positive and negative buses of the power plate, the discrete semiconductor devices have bent pins, and the power plate and the driving plate are electrically connected together through the pins of the discrete semiconductor devices; The parallel connection of the discrete power semiconductor devices also includes an insulating structure for fixing the discrete semiconductor devices.

2. The discrete power semiconductor device parallel connected integrated power cell of claim 1, wherein: The M / 2 discrete semiconductor devices of the first upper bridge arm and the other M / 2 discrete semiconductor devices of the first lower bridge arm are symmetrically arranged, and the M / 2 discrete semiconductor devices of the first lower bridge arm and the other M / 2 discrete semiconductor devices of the first upper bridge arm are symmetrically arranged; the M / 2 discrete semiconductor devices of the second upper bridge arm and the other M / 2 discrete semiconductor devices of the second lower bridge arm are symmetrically arranged, and the M / 2 discrete semiconductor devices of the second lower bridge arm and the other M / 2 discrete semiconductor devices of the second upper bridge arm are symmetrically arranged; ; the M / 2 discrete semiconductor devices of the N / 2th upper bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the N / 2th lower bridge arm, and the M / 2 discrete semiconductor devices of the N / 2th lower bridge arm are symmetrically arranged with the other M / 2 discrete semiconductor devices of the N / 2th upper bridge arm.

3. The discrete power semiconductor device parallel connected integrated power cell of claim 1, wherein: The stacked structure is that each layer of the PCB is vertically stacked from top to bottom according to the corresponding positive and negative bus bars, and the corresponding PCB of each layer of positive and negative bus bars is completely stacked.

4. The discrete power semiconductor device parallel connected integrated power cell of claim 1, wherein: Wherein, M is 4; each of the bridge arms includes 4 parallel discrete semiconductor devices, the first and second discrete semiconductor devices of the first upper bridge arm and the first and second discrete semiconductor devices of the first lower bridge arm are arranged in a first power area, and the third and fourth discrete semiconductor devices of the first upper bridge arm and the third and fourth discrete semiconductor devices of the first lower bridge arm are arranged in a second power area; The first and second discrete semiconductor devices of the second upper bridge arm and the first and second discrete semiconductor devices of the second lower bridge arm are arranged in a third power area, and the third and fourth discrete semiconductor devices of the second upper bridge arm and the third and fourth discrete semiconductor devices of the second lower bridge arm are arranged in a fourth power area;… ； The first and second discrete semiconductor devices of the N / 2th upper bridge arm and the first and second discrete semiconductor devices of the N / 2th lower bridge arm are arranged in an N-1 power area, and the third and fourth discrete semiconductor devices of the N / 2th upper bridge arm and the third and fourth discrete semiconductor devices of the N / 2th lower bridge arm are arranged in an N power area.

5. The discrete power semiconductor device parallel connected integrated power cell of claim 1, wherein: The M discrete semiconductor devices of the first upper bridge arm are connected to the positive bus bar of the power plate, and the M discrete semiconductor devices of the first lower bridge arm are connected to the negative bus bar of the power plate; the M discrete semiconductor devices of the second upper bridge arm are connected to the positive bus bar of the power plate, and the M discrete semiconductor devices of the second lower bridge arm are connected to the negative bus bar of the power plate;…; the M discrete semiconductor devices of the N / 2th upper bridge arm are connected to the positive bus bar of the power plate, and the M discrete semiconductor devices of the N / 2th lower bridge arm are connected to the negative bus bar of the power plate; the power plate and the driving plate are left with a safety distance.

6. The discrete power semiconductor device parallel connected integrated power cell of claim 2, wherein: The distance from the discrete power semiconductor devices in each power area to the corresponding output terminal is equal.

7. The discrete power semiconductor device parallel connected integrated power cell of claim 1, wherein: The driving circuit of the driving plate is equal in length to the driving traces of the discrete power semiconductor devices of the power plate.

8. The discrete power semiconductor device parallel connected integrated power cell of claim 1, wherein: The discrete semiconductor devices are single-tube IGBTs.

9. The discrete power semiconductor device parallel connected integrated power cell of claim 4, wherein: the collector of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the first upper bridge arm are connected with the positive bus of the power board, the emitter of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the first lower bridge arm are connected with the negative bus of the power board, the emitter of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the first upper bridge arm are connected with the corresponding output terminal, and the collector of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the first lower bridge arm are connected with the corresponding output terminal; the collector of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the second upper bridge arm are connected with the positive bus of the power board, the emitter of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the second lower bridge arm are connected with the negative bus of the power board, the emitter of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the second upper bridge arm are connected with the corresponding output terminal, and the collector of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the second lower bridge arm are connected with the corresponding output terminal; …； the collector of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the N / 2th upper bridge arm are connected with the positive bus of the power board, the emitter of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the N / 2th lower bridge arm are connected with the negative bus of the power board, the emitter of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the N / 2th upper bridge arm are connected with the corresponding output terminal, and the collector of the first discrete semiconductor device, the second discrete semiconductor device, the third discrete semiconductor device and the fourth discrete semiconductor device of the N / 2th lower bridge arm are connected with the corresponding output terminal.

10. A method of fabricating a parallel-connected power cell of discrete power semiconductor devices as defined in claim 1, characterized by: comprising: the PCB body of the power board and the PCB body of the driving board are respectively assembled with materials and subjected to first furnace treatment, and first power board PCBA and driving board PCBA are formed by welding; the discrete power device is passed through the mounting hole reserved on the PCB of the power board, and then fixed by a tool and subjected to furnace treatment together with the first power board PCBA, the discrete power device is welded to the first power board PCBA, and second power board PCBA is formed; the mounting hole reserved on the driving board PCBA is aligned with the pin of the discrete power device exposed on the second power board PCBA, and the second power board PCBA is assembled together with the second power board PCBA; The second power plate PCBA is passed through the furnace together with the drive plate PCBA, and the drive plate PCBA and the second power plate PCBA are welded together to form a power module of the discrete power semiconductor device.

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