Amplifier circuit and method for reducing output voltage overshoot in an amplifier circuit

Abstract

An amplifier circuit and a method for reducing output voltage overshoot in an amplifier circuit are disclosed. The amplifier circuit includes an amplifier and an output transistor. The amplifier circuit is coupled to an output node of the output transistor to provide an output voltage to a load device. The amplifier circuit also includes a slew rate control circuit coupled to a gate node of the output transistor and configured to control a voltage rise of the gate node of the output transistor during power up to reduce output voltage overshoot.

Description

Technical Field

[0001] This invention relates to an electronic circuit, and more particularly, to an embodiment of a capacitorless linear voltage regulator circuit. Some embodiments described herein are used in capacitorless voltage regulator circuits to reduce power-on overload problems. However, the circuits and methods described herein can also be used to reduce power-on overload in other amplifier circuits. Background Technology

[0002] A linear regulator acts as a variable resistor between the input power supply and the output to reduce the voltage applied to the load. Therefore, linear regulators are inefficient. Unlike DC-DC converters that switch power supplies, linear regulators offer continuous operation and are cheaper and easier to use.

[0003] Figure 1 This is a simplified schematic diagram of a well-known linear voltage regulator circuit. For example... Figure 1 As shown, linear regulator 100 is a low dropout (LDO) regulator that receives an input voltage VIN and generates a regulated output voltage VOUT. A low dropout regulator is a DC linear voltage regulator capable of adjusting the output voltage. Low dropout regulator 100 includes an amplifier 110 and an output transistor MP. Amplifier 110 is a differential amplifier acting as an error amplifier, while output transistor MP can be a power field-effect transistor (FET). Differential amplifier 110 is configured to amplify the difference between a reference voltage Vref and a feedback voltage Vfb, which is a portion of the regulated output voltage VOUT sampled by a voltage divider formed by resistors R1 and R2. The output of differential amplifier 110 is coupled to the gate node 122 of output transistor MP. The regulated output voltage VOUT is derived from the output node 124 of output transistor MP. The gate voltage at gate node 122 is as follows: Figure 1 The Vmcg referred to in the text. Figure 1 It also shows the input voltage VIN that provides operating power to the low-dropout regulator 100. This is achieved by drawing current I... load The load device shown receives power from the low-dropout regulator 100.

[0004] For an ideal operational amplifier gain, the output voltage is given by the following formula:

[0005]

[0006] The reference voltage VREF can be, for example, a bandgap reference voltage of 1.205V.

[0007] Figure 1As is known, compensated linear voltage regulators (LDOs) require relatively large external capacitors C. ext Typically, this ranges from microfarads to control stability. In this case, the integrated circuit chip needs a pin to connect to an external capacitor C. ext This increases the cost and area of ​​the circuit board. Figure 1 In the middle, the equivalent series resistance ESR and the external capacitance C ext Series connection. To avoid the problems of having additional pins on the chip and using external low equivalent series resistance (ESR) capacitors, a capacitor-free linear regulator is used, but the challenge lies in the stability of the load and the transient response.

[0008] Therefore, there is a need for improved methods and systems that can overcome the above limitations. Summary of the Invention

[0009] According to embodiments of the present invention, circuits and methods are provided to reduce overload of amplifier circuitry during power-up. In some embodiments, a current source is coupled to the gate node of the output transistor to control the slew rate of the gate current rise, preventing output voltage leakage. A detection circuit monitors the output voltage and disables slew rate control for normal operation of the amplifier circuitry.

[0010] According to an embodiment of the present invention, the amplifier circuit includes a linear regulator having an amplifier and an output transistor to form a feedback loop. The amplifier is configured to receive a reference voltage and a feedback voltage from the feedback loop, and the output transistor has an output node to provide an output voltage to a load device. The amplifier circuit also includes a slew rate control circuit coupled to the gate node of the output transistor and configured to control the slew rate of the gate node to control the voltage rise during power-up to reduce output voltage overshoot.

[0011] In some embodiments, when the output voltage reaches a preset voltage level, the amplifier circuit is configured to disable the slew rate control circuit.

[0012] In some embodiments, the slew rate control circuit includes a switching transistor and a diode-connected transistor, wherein the gate node of the diode-connected transistor is coupled to the gate node of the output transistor to form a current mirror, and the gate node of the diode-connected transistor is coupled to the drain node of the diode-connected transistor.

[0013] In some embodiments, the diode-connected transistor and the switching transistor are P-type metal-oxide-semiconductor (PMOS) transistors.

[0014] In some embodiments, the slew rate is determined by the bias current in the diode-connected transistor and the size of the diode-connected transistor.

[0015] In some embodiments, the amplifier circuit further includes an output voltage level detection circuit coupled to the output node of the output transistor. When the output voltage reaches a preset voltage level, the output voltage level detection circuit is configured to turn off the switching transistor to disable the slew rate control circuit.

[0016] In some embodiments, the output voltage level detection circuit includes a first current source, a first transistor, and a bias resistor, connected in series between a voltage supply node and a ground node. The gate node of the first transistor is coupled to the output node of the output transistor. The output voltage level detection circuit also includes a second transistor coupled between the source node of the first transistor and the ground node, and a third transistor having a gate node coupled to the drain node of the first transistor and a drain node coupled to the gate node of the second transistor and the switching transistor of the slew rate control circuit.

[0017] In some embodiments, when the output voltage reaches a preset voltage level, the output voltage level detection circuit is configured to disable the slew rate control circuit, wherein the preset voltage level is determined based on the first current source, the bias resistor, and the threshold voltage of the first transistor.

[0018] In some embodiments, the first transistor, the second transistor, and the third transistor are n-type metal-oxide-semiconductor (NMOS) transistors.

[0019] In some embodiments, the amplifier circuit further includes an amplifier bias selection circuit configured to select a first bias current of the amplifier during power-up and a second bias current of the amplifier during normal operation, wherein the first bias current is greater than the second bias current.

[0020] According to an embodiment of the present invention, the amplifier circuit includes an amplifier and an output transistor. The amplifier is coupled to the output node of the output transistor and provides an output voltage to a load device. The amplifier circuit also includes a slew rate control circuit coupled to the gate node of the output transistor and configured to control the slew rate of the gate node of the output transistor, thereby controlling the voltage rise during power-up to reduce output voltage overshoot.

[0021] In some embodiments, the amplifier circuit further includes an output voltage level detection circuit, which is configured to disable the slew rate control circuit when the output voltage reaches a preset voltage level.

[0022] In some embodiments, the slew rate control circuit includes a switching transistor and a diode-connected transistor. The gate node of the diode-connected transistor is coupled to the gate node of the output transistor to form a current mirror, and the gate node of the diode-connected transistor is coupled to the drain node of the diode-connected transistor.

[0023] In some embodiments, the output voltage level detection circuit is coupled to the output node of the output transistor. When the output voltage reaches a preset voltage level, the output voltage level detection circuit is configured to turn off the switching transistor to disable the slew rate control circuit.

[0024] In some embodiments, the output voltage level detection circuit includes a first current source, a first transistor, and a bias resistor, connected in series between a voltage supply node and a ground node. The gate node of the first transistor is coupled to the output node of the output transistor. The output voltage level detection circuit also includes a second transistor coupled between the source node of the first transistor and the ground node, and a third transistor having a gate node coupled to the drain node of the first transistor and a drain node coupled to the gate node of the second transistor and the switching transistor of the slew rate control circuit.

[0025] According to an embodiment of the present invention, a method for reducing output voltage overshoot in an amplifier circuit is provided. The amplifier circuit includes an amplifier and an output transistor, the amplifier being coupled to the output node of the output transistor to provide an output voltage to a load device. The method includes coupling the gate node of the output transistor to a slew rate control circuit to control the slew rate at the gate node, thereby reducing output voltage overshoot during power-up.

[0026] In some embodiments, the method further includes disabling the slew rate control circuit when the output voltage reaches a preset voltage level.

[0027] In some embodiments, the method further includes using a slew rate control circuit comprising a diode-connected transistor connected in series with a switching transistor, the diode-connected transistor and the output transistor forming a current mirror.

[0028] In some embodiments, the method further includes turning off the switching transistor when the output voltage reaches a preset voltage level.

[0029] In some embodiments, the method further includes selecting a first bias current for the amplifier during power-up and selecting a second bias current for the amplifier during normal operation. The first bias current is greater than the second bias current. Attached Figure Description

[0030] The nature and advantages of this invention can be further understood by referring to the following drawings. In the drawings, similar components or features may have the same component symbols. Furthermore, various components of the same type may be distinguished from similar components by adding a second reference numeral after the component symbol. If only the first component symbol is used in the specification, the description is applicable to any similar component having the same first component symbol, regardless of the second component symbol.

[0031] Figure 1This is a simplified schematic diagram of a well-known linear voltage regulator circuit;

[0032] Figure 2A This is a schematic diagram showing the equivalent circuit of a capacitorless linear voltage regulator circuit. Figure 2B It is shown Figure 2A Gain and frequency distribution of the pole locations of a medium-linear voltage regulator;

[0033] Figure 3A This is a simplified schematic diagram illustrating the output response of a linear voltage regulator circuit with waveforms during power-up, according to an embodiment of the present invention.

[0034] Figure 3B This is illustrated in the embodiments of the present invention. Figure 3A Simulation waveforms of the gate voltage and output voltage states of the output transistor MP of the medium linear regulator during chip power-up;

[0035] Figure 4 This is a schematic diagram illustrating a linear regulator circuit according to an embodiment of the present invention;

[0036] Figure 5 This is a simplified schematic diagram illustrating the selection of amplifier bias current according to an embodiment of the present invention;

[0037] Figure 6 This is a waveform diagram illustrating amplifier operation during power-up according to an embodiment of the present invention; and

[0038] Figure 7 This is a simplified flowchart illustrating a method for reducing output voltage overshoot in an amplifier circuit according to an embodiment of the present invention.

[0039] Icon labels:

[0040] 100: Low dropout voltage regulator

[0041] 110, A1: Amplifier

[0042] 122,412,422,433: Gate nodes

[0043] 124,411: Output nodes

[0044] 200, 300, 410: Linear regulators

[0045] 310, 320, 610, 620, 630, 640: Waveforms

[0046] 311,322,611,622: Sudden Wave

[0047] 400: Amplifier Circuit

[0048] 420: Slew Rate Control Circuit

[0049] 430: Output voltage level detection circuit

[0050] 431: First Current Source

[0051] 432: Second Current Source

[0052] 434: Drain node

[0053] 510, Ib, ibias0, ibias1: Bias current

[0054] 520: Amplifier Bias Current Selection Circuit

[0055] 700: Method

[0056] 710,720,730,740,750,760,770: Steps

[0057] C GS C GD Parasitic capacitance

[0058] C ext External capacitor

[0059] C1: Capacitor

[0060] ESR: Equivalent Series Resistance

[0061] Error Amp: Error Amplifier

[0062] GND: Grounding node

[0063] Gm1: Gain

[0064] I load Current

[0065] MD: Diode connected to transistor

[0066] MP, Mp: Output transistors

[0067] MS: Switching transistor

[0068] M1: First transistor

[0069] M2: Second transistor

[0070] M3: Third transistor

[0071] P1: First pole

[0072] P2: Second pole

[0073] Rb: Bias resistor

[0074] R DS Parasitic resistance

[0075] R1,R2,R 11 ,R 12 :resistance

[0076] R 1n Internal resistance

[0077] VIN, VDDMIC, VDDB: Supply voltage

[0078] Vfb: Feedback voltage

[0079] Vg, Vmcg: Gate voltage

[0080] Vout: Output voltage

[0081] Vref: Reference voltage

[0082] V0, V1: Voltage

[0083] V2: Source voltage

[0084] V3: Source voltage Detailed Implementation

[0085] The aspects of the invention will be described more fully below with reference to the accompanying drawings, which form part of the invention and illustrate exemplary features by way of illustration. However, the features may be implemented in many different forms and should not be construed as limited to the combinations listed herein; rather, these combinations are provided to make the invention more thorough and complete, and to convey its scope. In other respects, the features of the invention may be achieved by methods, apparatus and / or embodied in goods. Therefore, the following detailed description should not be construed as limiting.

[0086] Figure 2A This is a schematic diagram showing the equivalent circuit of a capacitorless linear voltage regulator circuit. Figure 2B It is shown Figure 2A Gain and frequency plots of a medium-linear voltage regulator, showing pole locations. Figure 2A As shown, the linear regulator 200 receives an input voltage VIN and produces an adjusted output voltage VOUT. The linear regulator 200 includes an error amplifier Error Amp, which has a gain Gm1 and an internal resistance R. 1n And capacitor C1. The linear regulator 200 also includes an output transistor Mp, which can also be used as a transmission transistor, and the feedback loop is formed by resistor R. 11 and resistance R 12 The midpoint of the voltage divider is connected to the input node of the error amplifier Error Amp. The output transistor Mp has an associated parasitic capacitance C. GS C GD and parasitic resistance R DS The external load device is powered by current I. load express.

[0087] The linear regulator 200 is an uncompensated capacitor-free regulator with two main poles, such as... Figure 2B As shown, the first pole P1 is the output pole of the error amplifier, and the second pole P2 is the load-dependent output pole. The dominant first pole P1 is shown below:

[0088]

[0089] Among them, A pass This is the voltage gain of the output transistor Mp. Therefore, the first pole P1 resides at low frequencies, typically a few kHz, because the output resistance of the error amplifier is relatively large enough to provide sufficient DC loop gain.

[0090] The second pole P2 is located at the output VOUT, as shown in the following formula:

[0091]

[0092] Among them, G mp Mp is the transconductance gain of the output transistor, Rout is the equivalent resistance generated by the current load effect, and Cout is the load capacitance on the chip, which is usually less than 100pF due to chip area limitations.

[0093] Transconductance gain G of the transfer transistor mp and parasitic capacitance R DS The position of the second pole P2 can change with increasing load current, making it sensitive to load conditions. Larger load currents can drive the second pole P2 to higher frequencies, far exceeding the first pole P1. At low currents, the effective load resistance increases significantly, and the second pole P2 can be pushed to lower frequencies. With changes in pole position, loop stability cannot be guaranteed. In addition, the parasitic capacitance C... GD The side effect is the formation of a right half-plane (RHP) zero that reduces the phase margin of the circuit. Therefore, the design of capacitorless regulator circuits must be more careful to ensure the stability of the circuit.

[0094] Figure 3A This is a simplified schematic diagram illustrating the output response of a linear voltage regulator circuit with waveforms during power-up, according to an embodiment of the present invention. The components of the linear regulator 300 are... Figure 1 Similar to what is shown, therefore, it will not be described in detail here.

[0095] As mentioned earlier, regarding the issue of capacitorless regulators, stability becomes more challenging without external capacitors. Therefore, we swapped the feedback response speed to achieve sufficient phase margin. As a result, when the chip powers on, it takes some time to bring the error amplifier from the cutoff region to linear operation before it begins controlling the gate voltage Vg of the output transistor MP. This output transistor is very large, and the glitch on the gate of the output transistor MP, such as... Figure 3B As shown in waveform 310, in the power-on state, the full-rail input voltage VIN, for example 3.6V, appears on the output voltage Vout, as shown in waveform 320. This can cause problems when designing a regulator to drive 1.8V logic circuitry. If the output voltage reaches 1.8V + 200mV, the 1.8V logic circuitry will experience overvoltage stress on the gate oxide layer of the transistors. As a result, the circuit performance will degrade over time.

[0096] Figure 3B The simulation waveform of the gate voltage Vg of the output transistor MP during chip power-up is shown. Figure 3B The supply voltages VDDMIC and VDDB rapidly rose to 3.6V and 3.3V, respectively. Figure 3B The waveforms 310 of the gate voltage Vg and 320 of the output voltage Vout of the output transistor in a known capacitorless regulator circuit without slew rate control are also shown. In this example, there is a negative surge 311 on the gate voltage Vg of the output transistor MP, causing a surge 322 in the output voltage Vout to reach 3.6V of the full rail voltage.

[0097] In some embodiments of the invention, the amplifier circuit may include feedback circuitry added to the amplifier to address power-up surge problems. The amplifier circuit may include an amplifier and an output transistor. The amplifier is coupled to the output node of the output transistor to provide an output voltage to a load device. The amplifier circuit also includes a slew rate control circuit coupled to the gate node of the output transistor, configured to control the voltage rise at the gate node of the output transistor during power-up, reducing output voltage overshoot or surges.

[0098] Slew rate is generally defined as the rate of change of a waveform, which is the same as the slope. In this article, "slew rate control circuit" refers to a circuit that controls the rate of voltage rise at a circuit node. The linear regulator used is as follows: Figure 4 An example is shown.

[0099] Figure 4 This is a schematic diagram illustrating a linear regulator circuit according to an embodiment of the present invention. Figure 4As shown, the amplifier circuit 400 includes a linear regulator 410, which includes an amplifier A1 and an output transistor MP, and forms a feedback loop with a feedback resistor divider formed by resistors R1 and R2. The amplifier A1 is configured to receive a reference voltage Vref and a feedback voltage Vfb from the feedback loop. The output transistor MP has an output node 411 to provide an output voltage Vout to the load device. Figure 4 (Not shown in the diagram). The amplifier circuit 400 also includes a slew rate control circuit 420 coupled to the gate node 412 of the output transistor MP, and configured to control the voltage rise of the gate node 412 during power-up to reduce output voltage overshoot.

[0100] The slew rate control circuit 420 includes a switching transistor MS and a diode-connected transistor MD, connected in series between the supply voltage VIN (also referred to as the input voltage) and the gate node 412 of the output transistor MP. The gate node of the diode-connected transistor MD is coupled to the gate node 412 of the output transistor MP to form a current mirror. The gate node of the diode-connected transistor MD is coupled to its drain node, and both are connected to the gate node 412 of the output transistor MP. The supply voltage VIN is a power supply voltage introduced by an external power supply and is used for the power supply of the amplifier circuitry. In this embodiment, the diode-connected transistor MD and the switching transistor MS are P-type metal-oxide-semiconductor (PMOS) transistors.

[0101] In some embodiments, the slew rate is determined by the bias current in the diode-connected transistor and the size of the diode-connected transistor. In this example, a current mirror, formed by the diode-connected transistor MD and the output transistor MP, can serve as a current source. The current in the output transistor MP can be varied by changing the size of the diode-connected transistor.

[0102] Amplifier circuit 400 is configured to disable the slew rate control circuit when the output voltage reaches a preset voltage level. Figure 4 In this example, the amplifier circuit 400 also includes an output voltage level detection circuit 430, coupled to the output node 411 of the output transistor MP. The output voltage level detection circuit 430 is configured to turn off the switching transistor MS when the output voltage reaches a preset voltage level, thereby disabling the slew rate control circuit 420.

[0103] exist Figure 4In this example, the output voltage level detection circuit 430 includes a first current source 431, a first transistor M1, and a bias resistor Rb, which are connected in series between the source of the first transistor M1 and the ground node GND. The gate node of the first transistor M1 is coupled to the output node 411 of the output transistor MP. The second transistor M2 serves as a shunt path for the first transistor M1. The third transistor M3 is coupled to the second current source 432. The third transistor M3 has a gate node 433 coupled to the drain node of the first transistor M1, while the drain node 434 of the third transistor M3 is coupled to the second transistor M2. The drain node 434 of the third transistor M3 is also coupled to the gate node 422 of the switching transistor MS of the slew rate control circuit 420.

[0104] The output voltage level detection circuit 430 is configured to disable the slew rate control circuit 420 when the output voltage Vout reaches a preset voltage level. The preset voltage level is determined based on the bias current Ib of the first current source 431, the resistance value of the bias resistor Rb, and the threshold voltage of the first transistor M1. Figure 4 In the example, the first transistor M1, the second transistor M2, and the third transistor M3 are n-type metal-oxide-semiconductor (NMOS) transistors.

[0105] like Figure 4 As shown, amplifier circuit 400 is a linear regulator. Amplifier circuit 400 can be configured to function as a low-dropout (LDO) regulator when the input voltage VIN is coupled to the output transistor MP, as... Figures 1 to 3B As shown in the example.

[0106] exist Figure 4 In this configuration, amplifier A1 can function as an error amplifier, coupled between the power supply and ground. For example, the error amplifier can function as a differential amplifier, configured to provide a gate voltage differential between a reference voltage and an adjusted output voltage. The differential amplifier may include a pair of input transistors, a pair of bias transistors, and a pair of current mirror transistors. The output transistor MP includes a gate node coupled to the output node of the differential amplifier, receiving the gate voltage and providing the adjusted output voltage to the output node of the output transistor.

[0107] The operation of amplifier circuit 400 as a linear regulator is described below. First, all node voltages are zero. When the power is turned on, the supply voltage VIN begins to rise rapidly. The voltage V1 at the drain node of the first transistor M1 in the output voltage level detection circuit 430 also rises rapidly and is set by the bias current Ib at the drain of the first transistor M1. As voltage V1 rises rapidly and connects to the gate of the third transistor M3, the voltage V0 at the drain of the third transistor M3 remains at a low level. As voltage V0 remains at a low level, slew rate control circuit 420 turns on by switching transistor MS. This allows the source voltage V3 to be transferred to the drain of diode-connected transistor MD, which is coupled to the gate node 412 of output transistor MP. At this time, diode-connected transistor MD is connected to output transistor MP, acting as a current mirror, thus limiting and controlling the current flowing excessively into transistor MP. Additionally, the diode-connected transistor MD acts as a clamp to limit the voltage at the gate node 412 of the output transistor MP to VIN-Vthp, where Vthp is the threshold voltage of the P-type metal-oxide-semiconductor diode-connected transistor MD. This allows the regulator circuit to smoothly increase the voltage Vout without causing surges at the gate of the first transistor M1.

[0108] If the output voltage Vout at output node 411, which is the gate node of the first transistor M1, reaches the preset voltage level Vt+IR, the first transistor M1 is turned on. Here, Vt is the threshold voltage of the first transistor M1, I is the bias current Ib of the first current source 431, and R is the resistance value of the bias resistor Rb. When the first transistor M1 is turned on, the voltage V1 at the gate node 433 goes low, turning off the third transistor M3. The voltage V0 at the drain node 434 of the third transistor M3 goes high, turning off the switching transistor MS, thus disabling the slew rate control circuit 420. At the same time, the second transistor M2 turns on, pulling the source voltage V2 of the first transistor M1 to ground. Simultaneously, the feedback loop begins to track the output voltage Vout, and the error amplifier A1 enters the linear region.

[0109] The amplifier circuit described above may also include an amplifier bias current selection circuit, configured to select a first bias current for the amplifier during power-up and a second bias current for the amplifier during normal operation, wherein the first bias current is greater than the second bias current.

[0110] Figure 5 This is a simplified schematic diagram illustrating an amplifier with amplifier bias current selection according to an embodiment of the present invention. Figure 5 As shown, amplifier A1 and Figure 4 Similar to amplifier A1 in the above, and can be used in linear regulators, such as... Figure 4A linear regulator 410. Amplifier A1 is configured to receive bias current 510. Figure 5 The amplifier bias current selection circuit 520 is also shown, which in this embodiment is a 2:1 multiplexer circuit with two bias current inputs, ibias0 and ibias1, and a selection control signal voltage V0. Voltage V0 is used to turn off... Figure 4 The signal of the medium voltage slew rate control circuit 420.

[0111] During the power-up phase of the circuit, the control signal voltage V0 is also used as the selection input for the 2:1 multiplexer. With V0 = 0, the bias current for amplifier A1 can be selected as the bias current ibias1, where ibias1 > ibias0. The bias current ibias0 is the bias current used for the normal operation of amplifier A1. With a higher bias current ibias1 during the power-up phase, amplifier A1 can react more quickly to change the feedback loop and track the output voltage.

[0112] Figure 6 This is a waveform diagram illustrating amplifier operation during power-on according to an embodiment of the present invention. Figure 6 The diagram shows simulated waveforms of the gate voltage Vg on the output transistor MP during chip power-up. The top figure shows waveform 610 of the output transistor gate voltage Vg and waveform 620 of the output voltage Vout in a known capacitorless regulator circuit without slew-rate (SR) control. In this example, a negative surge 611 occurs on waveform 610 of the gate voltage Vg on the output transistor MP, causing a surge 622 in waveform 620 of the output voltage Vout to reach the full-rail voltage (3.6V). The bottom figure shows waveform 630 of the output transistor gate voltage Vg and waveform 640 of the output voltage Vout in a capacitorless regulator circuit as described above with slew-rate (SR) control. Slew-rate and threshold level control prevent surge generation. Therefore, the circuit described above allows amplifiers, such as regulators, to smoothly boost the voltage on the output transistor to the correct level without overshoot.

[0113] In the amplifier circuit embodiments described above, for example... Figure 4 The slew rate of the gate voltage Vg of the output transistor MP gate node 412 in the amplifier circuit 400 during power-on can be changed by altering the area ratio of the diode-connected transistor MD to the output transistor MP. The preset voltage level used to shut down the slew rate control circuit 420 can be adjusted by changing the resistance value of the resistor Rb connected in series with the first transistor M1 in the output voltage level detection circuit 430. Further combining the above... Figure 5The first bias current ibias1 can be selected as the bias current of amplifier A1 during power-up, while the second bias current ibias0 can be selected as the bias current of amplifier A1 during normal operation. The second bias current ibias0 is lower than the first bias current ibias1. By selecting a higher second bias current ibias0, the amplifier can respond more quickly to changes in the feedback loop and track the output voltage.

[0114] Figure 7 This is a simplified flowchart illustrating a method for reducing output voltage overshoot in an amplifier circuit according to an embodiment of the present invention. Figure 7 As shown, this method 700 is a method for reducing output voltage overshoot in an amplifier circuit including an amplifier and an output transistor. The amplifier is coupled to the output node of the output transistor to provide an output voltage to a load device. Method 700 includes step 710: using a slew rate control circuit coupled to the gate node of the output transistor to control the voltage rise of the gate node of the output transistor to reduce output voltage overshoot. Method 700 also includes step 720: disabling the slew rate control circuit when the output voltage reaches a preset voltage level. Method 700 also includes step 730: using a series diode to connect the slew rate control circuit of the transistor and the switching transistor, the diode connecting the transistor and the output transistor forming a current mirror; and step 740: turning off the switching transistor when the output voltage reaches the preset voltage level. In step 750, the method may include changing the slew rate of the gate voltage of the output transistor during power-up by changing the area ratio of the diode connecting the transistor and the output transistor. In step 760, the preset voltage level used to shut down the slew rate control circuit can be adjusted by changing the resistance value of the transistor series-coupled to the output voltage level detection circuit. Additionally, method 700 may also include step 770: selecting a first bias current for the amplifier during power-up and selecting a second bias current for the amplifier during normal operation. The first bias current is greater than the second bias current. By selecting a larger first bias current, the amplifier can respond more quickly to changes in the feedback loop and track the output voltage.

[0115] The methods and steps described herein can be implemented, in part or in whole, by codes and / or data stored in a computer-readable storage medium or device, which the computer system can perform when it reads and executes the codes and / or data. The methods and steps can also be implemented, in part or in whole, in hardware modules or devices, which perform the methods and steps when the hardware modules or devices are started. The methods and steps disclosed herein can be implemented using a combination of codes, data, hardware modules, or devices.

[0116] Some embodiments of the present invention have been described. However, various modifications to these embodiments are possible, and the principles set forth herein can also be applied to other embodiments. Furthermore, various components and / or method steps / blocks may be implemented in configurations different from those specifically disclosed without departing from the scope of this application. Other embodiments or modifications will be readily apparent to those skilled in the art from these teachings. Therefore, when considered in conjunction with the foregoing description and drawings, the claims of this application are intended to cover all embodiments and modifications.

Claims

1. An amplifier circuit, characterized by A linear voltage regulator includes: a linear regulator having an amplifier configured to receive a reference voltage and a feedback voltage from a feedback loop and an output transistor having an output node to provide an output voltage to a load device; and a slew rate control circuit coupled to a gate node of the output transistor and configured to control a slew rate of the gate node; wherein the slew rate control circuit includes a switching transistor and a diode-connected transistor connected in series, the switching transistor and the diode-connected transistor coupled in series between an input voltage and the gate node of the output transistor, a gate node of the diode-connected transistor coupled to the gate node of the output transistor to form a current mirror, and a gate node of the diode-connected transistor coupled to a drain node of the diode-connected transistor. The amplifier circuit is configured to disable the slew rate control circuit when the output voltage reaches a predetermined voltage level. The slew rate control circuit is enabled by the switching transistor.

2. The amplifier circuit of claim 1, wherein The diode-connected transistor and the switching transistor are P-type metal-oxide-semiconductor transistors.

3. The amplifier circuit of claim 1, wherein, The slew rate is determined by a bias current in the diode-connected transistor and a size of the diode-connected transistor.

4. The amplifier circuit of claim 3, wherein, The output voltage level detection circuit includes:

5. The amplifier circuit of claim 3, wherein, a first current source, a first transistor, and a bias resistor connected in series between a voltage supply and a ground node, a gate node of the first transistor coupled to the output node of the output transistor; 6. The amplifier circuit of claim 3, wherein, a second transistor coupled between a source node of the first transistor and the ground node; and 7. The amplifier circuit of claim 6, wherein a third transistor having a gate node coupled to a drain node of the first transistor and having a drain node coupled to a gate node of the switching transistor of the slew rate control circuit. The output voltage level detection circuit is configured to disable the slew rate control circuit when the output voltage reaches the predetermined voltage level, wherein the predetermined voltage level is determined based on the first current source, the bias resistor, and a threshold voltage of the first transistor. The first transistor, the second transistor, and the third transistor are n-type metal-oxide-semiconductor transistors. The amplifier bias selection circuit is configured to select: a first bias current for the amplifier during power-up; and 8. The amplifier circuit of claim 7, wherein, a second bias current for the amplifier during normal operation, wherein the first bias current is greater than the second bias current.

9. The amplifier circuit of claim 7, wherein, A linear voltage regulator includes:

10. The amplifier circuit of claim 1, wherein, an amplifier; an output transistor, the amplifier coupled to an output node of the output transistor to provide an output voltage to a load device; and a slew rate control circuit coupled to a gate node of the output transistor and configured to control a slew rate of the gate node of the output transistor.

11. An amplifier circuit, characterized by ​ ​ ​ ​ The slew rate control circuit includes a switching transistor and a diode-connected transistor connected in series, the switching transistor and the diode-connected transistor connected in series are coupled between an input voltage and the gate node of the output transistor, a gate node of the diode-connected transistor is coupled to the gate node of the output transistor to form a current mirror, and a drain node of the diode-connected transistor is coupled to a gate node of the switching transistor of the slew rate control circuit.

12. The amplifier circuit of claim 11, wherein, Further including an output voltage level detection circuit configured to disable the slew rate control circuit when the output voltage reaches a preset voltage level.

13. The amplifier circuit of claim 12, wherein, The slew rate control circuit is enabled by the switching transistor.

14. The amplifier circuit of claim 13, wherein, The output voltage level detection circuit is coupled to the output node of the output transistor, and is configured to disable the slew rate control circuit by turning off the switching transistor when the output voltage reaches the preset voltage level.

15. The amplifier circuit of claim 14, wherein, The output voltage level detection circuit includes: a first current source, a first transistor, and a bias resistor coupled in series between a voltage supply and a ground node, a gate node of the first transistor is coupled to the output node of the output transistor; a second transistor coupled between a source node of the first transistor and the ground node; and a third transistor having a gate node coupled to a drain node of the first transistor and having a drain node coupled to the gate node of the switching transistor of the slew rate control circuit. The amplifier circuit includes an amplifier and an output transistor, the amplifier is coupled to an output node of the output transistor to provide an output voltage to a load device, and the method includes:

16. A method of reducing output voltage overshoot in an amplifier circuit, comprising: coupling a gate node of the output transistor to a slew rate control circuit to control a slew rate on the gate node; The slew rate control circuit includes a switching transistor and a diode-connected transistor connected in series, the switching transistor and the diode-connected transistor connected in series are coupled between an input voltage and the gate node of the output transistor, a gate node of the diode-connected transistor is coupled to the gate node of the output transistor to form a current mirror, and a drain node of the diode-connected transistor is coupled to a gate node of the switching transistor of the slew rate control circuit. Further including disabling the slew rate control circuit when the output voltage reaches a preset voltage level.

17. The method of claim 16, wherein, Further including enabling the slew rate control circuit by the switching transistor.

18. The method of claim 17, wherein, Further including turning off the switching transistor when the output voltage reaches the preset voltage level.

19. The method of claim 18, wherein, Further including: selecting a first bias current for the amplifier during power-up; and 20. The method of claim 19, wherein, selecting a second bias current for the amplifier during normal operation; wherein the first bias current is greater than the second bias current. ​

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