A high-speed two-to-one selector with an active inductor load

Abstract

The present invention discloses a high-speed two-to-one selector with an active inductor load, belonging to the field of integrated circuit chips. Two pairs of switch enable transistor pairs serve as the selection frequency band enable switch transistors to control the output frequency band required for selection; two pairs of signal input transistor pairs serve as the input transistor pairs for the selector to connect to the previous circuit and provide input signals for the selector; two DC bias transistors serve as the DC bias transistors of the active inductor load structure to provide an appropriate DC bias voltage for the resonance of the active inductor circuit; a pair of inductor resonance input transistor pairs serve as the inductor resonance tuning voltage input transistors of the active inductor load structure, and by adjusting different voltages, the inductor resonance peak is shifted to expand the frequency selection range; two positive transconductance transistors serve as the resonance transistors of the active inductor load structure, and by receiving different resonance voltages, different magnitudes of positive transconductance are generated to form resonance peaks of different magnitudes. The present invention can achieve a wider bandwidth selection range and has a larger gain under a wide bandwidth.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit chips, and particularly relates to a high-speed two-way one-selector with an active inductor load. Background Art

[0002] A multiplexer (MUX) is a circuit that can select any one of multiple data channels and send it to the output end as needed during the multi-channel data transmission process. In a communication system, switch switching technology is usually used to implement signal on / off and control. A multiplexer can generally be implemented using basic NAND gates. The multiplexer can be used as a radio frequency switch to switch signals and control on / off in a communication system. In traditional communication systems, integrated switch chips are usually used for frequency selection. However, the traditional method has relatively large losses and a narrow frequency selection range, and it is not easy to integrate monolithically. At present, how to design a high-speed two-way one-selector with a wide bandwidth is one of the difficulties in this field.

[0003] For a multiplexer, the paper "Y-H. Liu, C-L Li and T-H Lin. A 200-pJ / b MUX-Based RF Transmitter for Implantable Multichannel Neural Recording [J]. IEEE Transactions on Microwave Theory and Techniques, 2009.10.1109." adopted a differential structure, which can make the circuit change very little due to changes in PVT parameters. However, the frequency selection range of this selector is not wide and it is not applicable in high-frequency circuits.

[0004] In summary, currently, the adjustable resonance peak of an adjustable active inductor can be used to achieve a wide bandwidth and low power consumption of the selector. Nevertheless, for a two-way one-phase selector based on an adjustable active inductor, it is still very difficult to achieve a wide bandwidth range. Summary of the Invention

[0005] The purpose of the present invention is to provide a high-speed two-way one-selector with an active inductor load to solve the problems in the background art.

[0006] To solve the above technical problems, the present invention provides a high-speed two-way one-selector with an active inductor load, including a selector structure and an active inductor load structure;

[0007] The selector structure includes two pairs of switch enable transistor pairs and two pairs of signal input transistor pairs; the two pairs of switch enable transistor pairs serve as selection frequency band enable switch transistors to control the selection of the required output frequency band;

[0008] Two pairs of signal input pairs of transistors are connected as selectors to the input pairs of transistors of the previous circuit to provide input signals for the selector;

[0009] The active inductor load structure includes two DC bias transistors, a pair of inductor resonance input pairs of transistors, and two positive transconductance transistors; the two DC bias transistors serve as the DC bias transistors of the active inductor load structure to provide an appropriate DC bias voltage for the resonance of the active inductor circuit;

[0010] A pair of inductor resonance input pairs of transistors serve as the inductor resonance tuning voltage input transistors of the active inductor load structure. By adjusting different voltages, the inductor resonance peak is shifted to expand the frequency selection range;

[0011] The two positive transconductance transistors serve as the resonance transistors of the active inductor load structure. By receiving different resonance voltages, different magnitudes of positive transconductance are generated to form resonance peaks of different magnitudes.

[0012] In an implementation manner, the selector structure includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4;

[0013] The first PMOS transistor MP1 and the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 form the two pairs of switch enable pairs of transistors. Among them, the first PMOS transistor MP1 and the second PMOS transistor MP2 serve as the enable switch <0>, and their gates receive the enable signal and are connected to the first enable port EN<0>. The third PMOS transistor MP3 and the fourth PMOS transistor MP4 serve as the enable switch <1>, and their gates receive the enable signal and are connected to the second enable port EN<1>;

[0014] The first NMOS transistor MN1 and the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 form the two pairs of signal input pairs of transistors. Among them, the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are respectively connected to the first input positive port VIN1 and the first input negative port VIP1, and the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are respectively connected to the second input positive port VIN2 and the second input negative port VIP2.

[0015] In one embodiment, the sources and substrates of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are all connected to the power supply voltage AVDD; the substrates of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all grounded to AVSS;

[0016] The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3, and the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4;

[0017] The sources of the first NMOS transistor MN1 and the third NMOS transistor MN3 are interconnected, and the sources of the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are interconnected.

[0018] In one embodiment, the active inductor load structure includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8;

[0019] The fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 serve as two DC bias transistors, wherein the drain of the fifth PMOS transistor MP5 is connected to both the source of the first NMOS transistor MN1 and the source of the third NMOS transistor MN3, and the drain of the sixth PMOS transistor MP6 is connected to both the source of the second NMOS transistor MN2 and the source of the fourth NMOS transistor MN4;

[0020] The seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 serve as two positive transconductance transistors, wherein the source of the seventh NMOS transistor MN7 is connected to the drain of the fifth PMOS transistor MP5, and the source of the eighth NMOS transistor MN8 is connected to the drain of the sixth PMOS transistor MP6;

[0021] The fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 serve as a pair of inductor resonance input pair transistors, wherein the gates of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are commonly connected to the tuning voltage Vtune.

[0022] In one embodiment, the sources of the fifth PMOS transistor MP5, the sources of the sixth PMOS transistor MP6, the drains of the fifth NMOS transistor MN5, and the drains of the sixth NMOS transistor MN6 are all connected to a bias voltage Vbias;

[0023] The source of the fifth NMOS transistor MN5 is simultaneously connected to the gate of the fifth PMOS transistor MP5, the gate of the seventh NMOS transistor MN7, and the drain of the eighth NMOS transistor MN8; the source of the sixth NMOS transistor MN6 is simultaneously connected to the gate of the sixth PMOS transistor MP6, the gate of the eighth NMOS transistor MN8, and the drain of the seventh NMOS transistor MN7;

[0024] The gate of the seventh NMOS transistor MN7 is connected to the first output terminal Vout1; the gate of the eighth NMOS transistor MN8 is connected to the second output terminal Vout2.

[0025] In the high-speed two-way selector with an active inductor load provided by the present invention, two pairs of switch enabling transistors serve as the selection frequency band enabling switch transistors to control the selection of the required output frequency band; two pairs of signal input transistors serve as the input transistors of the selector connected to the previous circuit to provide input signals for the selector; two DC bias transistors serve as the DC bias transistors of the active inductor load structure to provide an appropriate DC bias voltage for the resonance of the active inductor circuit; a pair of inductor resonance input transistors serve as the inductor resonance tuning voltage input transistors of the active inductor load structure to shift the inductor resonance peak by adjusting different voltages and expand the frequency selection range; two positive transconductance transistors serve as the resonance transistors of the active inductor load structure to generate different magnitudes of positive transconductance to form different magnitudes of resonance peaks by receiving different resonance voltages. The present invention has the following beneficial effects:

[0026] (1) After adding the adjustable active inductor, a wider bandwidth can be achieved through the shift of the resonance peak, enabling better phase selection in the subsequent stage;

[0027] (2) The adjustable active inductor can achieve a larger gain under a wider bandwidth through a larger resonance peak;

[0028] (3) The adjustable active inductor has a high integration level and a small area. Description of the Drawings

[0029] Figure 1 It is a complete structure diagram of a high-speed two-way selector circuit with an active inductor load provided by the present invention;

[0030] Figure 2 It is a small-signal model of the active inductor load part of the present invention;

[0031] Figure 3 It is an equivalent schematic diagram of the active inductor load part of the present invention. Detailed implementation mode

[0032] The following further describes in detail a high-speed two-way selector with an active inductor load proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description and the claims, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0033] The present invention provides a high-speed two-way selector circuit with an active inductor load, as Figure 1 shown, including two pairs of switch pairs of transistors 1 and two pairs of input pairs of transistors 2. Among them,

[0034] The switch pairs of transistors 1 receive the enable signal to select the frequency band, and the input pairs of transistors 2 receive the frequency signals generated by the previous circuit;

[0035] Two input bias transistors 3, a pair of resonant input pairs of transistors 4, and two positive cross transistors 5 form an active inductor circuit. Among them, the input bias transistors 3 are used to receive the DC bias signal to provide an appropriate DC bias for the positive cross transistors 5 for resonance. The input pairs of transistors 2 are used to receive the output signal of the selector. The resonant input pairs of transistors 4 receive resonant voltage signals of different magnitudes to control the positive cross transistors 5 to resonate at different frequencies. The positive cross transistors 5 receive the frequency signals transmitted from the previous circuit. Through the re-selection of the active inductor, signals of different frequency bands can be output, and the gain of the output signal remains large under a relatively wide bandwidth.

[0036] The two pairs of switch enable pairs of transistors 1 include a first PMOS transistor MP1 and a second PMOS transistor MP2, a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The two pairs of signal input pairs of transistors 2 include a first NMOS transistor MN1 and a second NMOS transistor MN2, a third NMOS transistor MN3 and a fourth NMOS transistor MN4. The two pairs of switch enable pairs of transistors 1 and the two pairs of signal input pairs of transistors 2 form the selector structure in the high-speed two-way selector with an active inductor load. The two DC bias transistors 3 include a fifth PMOS transistor MP5 (i.e., M7) and a sixth PMOS transistor MP6 (i.e., M8). The pair of inductive resonant input pairs of transistors 4 includes a fifth NMOS transistor MN5 (i.e., M11) and a sixth NMOS transistor MN6 (i.e., M12). The two positive cross transistors 5 include a seventh NMOS transistor MN7 (i.e., M9) and an eighth NMOS transistor MN8 (i.e., M10). The two DC bias transistors 3, the pair of inductive resonant input pairs of transistors 4, and the two positive cross transistors 5 form the active inductor load structure in the high-speed two-way selector with an active inductor load.

[0037] The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are all connected to the power supply voltage AVDD. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the first enable port EN<0>. The gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the second enable port EN<1>. The drains of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are respectively connected to the drains of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4. The sources of the first NMOS transistor MN1 and the third NMOS transistor MN3 serve as the positive input signal of the active inductor and are simultaneously connected to the drain of the fifth PMOS transistor MP5 and the source of the seventh NMOS transistor MN7. The sources of the second NMOS transistor MN2 and the fourth NMOS transistor MN4 serve as the negative input signal of the active inductor and are simultaneously connected to the drain of the sixth PMOS transistor MP6 and the source of the eighth NMOS transistor MN8. The gate of the first NMOS transistor MN1 is connected to the first positive input port VIN1. The gate of the second NMOS transistor MN2 is connected to the first negative input port VIP1. The gate of the third NMOS transistor MN3 is connected to the second positive input port VIN2. The gate of the fourth NMOS transistor MN4 is connected to the second negative input port VIP2. The substrates of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all grounded to AVSS. The substrates of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are all connected to the power supply voltage AVDD.

[0038] The drains of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the sources of the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are all connected to the DC bias voltage Vbias. The gates of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are both connected to the tuning voltage Vtune. The gate of the fifth PMOS transistor MP5 is simultaneously connected to the source of the fifth NMOS transistor MN5, the gate of the seventh NMOS transistor MN7, and the drain of the eighth NMOS transistor MN8. The gate of the sixth PMOS transistor MP6 is simultaneously connected to the source of the sixth NMOS transistor MN6, the gate of the eighth NMOS transistor MN8, and the drain of the seventh NMOS transistor MN7. The gate of the seventh NMOS transistor MN7 is connected to the first output terminal Vout1. The gate of the eighth NMOS transistor MN8 is connected to the second output terminal Vout2. The first output terminal Vout1 and the second output terminal Vout2 serve as the output ports of the overall circuit and are the final frequency selection result.

[0039] The frequency is ω inThe differential injection signal is first injected via two pairs of signal input pair transistors (2) of the first input positive port VIN1, the first input negative port VIP1, the second input positive port VIN2, and the second input negative port VIP2. The on / off states of two pairs of switch-enabled transistors (1) are controlled by different enabling signals of the first enabling port EN<0> and the second enabling port EN<1>, and signals of different frequency bands are selected to enter an active inductor load structure through a pair of inductive resonant input pair transistors (4) to control the DC bias voltage. Then, by adjusting the magnitude of the tuning voltage, a pair of inductive resonant input pair transistors (4) are controlled, and resonant peaks of different magnitudes are obtained to expand the frequency selection range, so that two positive cross transistors (5) resonate and are connected to the first output terminal Vout1 and the second output terminal Vout2, and finally a frequency-divided output signal is output.

[0040] The small-signal model equivalent schematic diagram of the active inductor load part of the present invention is as Figure 2 shown, and it can be simplified to Figure 3 the RLC equivalent circuit shown, where the values of each component are:

[0041]

[0042]

[0043] g p = g ds11 (3)

[0044] C gs = C gs7 / 8 ||C gs9 / 10 (4)

[0045] In the above formula, C gs7 / 8 is the capacitance between the gate and source of M7 or M8, and C gs9 / 10 is the capacitance between the gate and source of M9 or M10. Figure 3 The C gs7 in ds7 is the capacitance between the gate and source of M7, and C eq is the capacitance between the drain and source of M7. This basic model ignores the influence of parasitic resistance and gives relatively instructive results. Since L eq is related to the transconductance of the MOS transistor, and the transconductance of the transistor is related to the DC bias of the circuit, the free resonance frequency can be changed by adjusting the DC bias. When the bias current increases, because the transconductance of all transistors increases accordingly, L

[0046] eq decreases and the free resonance frequency increases. On the contrary, when the bias current decreases, the decrease in transconductance will cause the free resonance frequency to decrease.In summary, a design guideline can be obtained through the small-signal model, that is, to increase the resonant frequency, the DC bias can be increased. However, this phenomenon is too simple. Especially for the active inductor, with too much bias signal, the equivalent inductance has a strong dependence on voltage, and it is necessary to further obtain how to adjust the voltage to control the free resonant frequency. Because only in this way can the voltage preset of the core oscillation circuit be effectively completed, and the most suitable voltage setting can be obtained based on these relationships. Otherwise, blindly increasing the bias current is neither practical nor useful.

[0047] Next, a semi-quantitative analysis of the TAI design is carried out from the perspective of the large-signal describing function.

[0048] First, clarify several relationships. g m9 = G m9 / 10 、g ds11 = G ds11 / 12 and g m7 = G m7 / 8 . The subscripts represent the transistor transconductance under consideration and the conductance between the ports under consideration, while the capital letters represent substituting the variables in the small-signal model with the large-signal average values.

[0049] Let I BIAS be the total bias current, I BIAS7 / 8 be the bias current flowing through M7 / M8. Similarly, the DC bias current for M9 / M10 is I BIAS9 / 10 . In this circuit structure, I BIAS9 / 10 flows through the active conductance G ds11 / 12 equivalent to M11 and M12 at the same time. At this time, G ds11 / 12 can be understood as a simple resistor, and its value is jointly determined by the amplitude V1 and the amplitude of the oscillation current flowing through transistors M11 and M12. Therefore, the expression can be obtained:

[0050]

[0051] where k represents the conversion coefficient between the current I BIAS9 / 10 and its fundamental frequency amplitude. At the same time, the following equation holds:

[0052]

[0053]

[0054] where N is defined as the ratio of the two bias currents. Then, according to the describing function, the following equations can be obtained:

[0055]

[0056]

[0057] The following briefly explains each numerical relationship:

[0058] (1) I BIAS is the total current bias. Due to the periodic switching action of the two branches of the circuit, the DC bias of each branch is thus I BIAS / 2;

[0059] (2) The determination of k requires using the characteristics of PMOS in the linear region. However, because of the large amplitude, the PMOS transistors cannot always be in the same region. Therefore, it is necessary to establish a waveform expression to obtain the frequency-domain components. Moreover, the gate currents of transistors M7, M8, M9, and M10 at high frequencies and the substrate injection of M9 and M10 themselves will make the determination of k complicated. Therefore, when establishing the model, in order to obtain simple and instructive conclusions, certain simplifications are needed.

[0060] (3) The parameter N is also relatively important. Although the current densities of the numerator and denominator of the ratio are different, the value of N is at least related to the transistor size ratio of M7 / 8 and M9 / 10. Therefore, the size of N can be adjusted through size design.

[0061] The above analysis involves many variables and it is not easy to derive useful design guidelines. The following discusses the relationships between the variables from another perspective.

[0062] (1) The purpose of analyzing the tunable active inductor is to obtain the relationship between the current bias and the free resonance frequency of the oscillation core circuit, because as long as the circuit size remains unchanged, the equivalent RLC capacitance also remains unchanged;

[0063] (2) Since there are too many variables, the analysis is very troublesome. To obtain an intuitive result, it can be simply assumed that I BIAS9 / 10 remains constant, especially when V1 is very large. At this time, transistors M11 and M12 enter the saturation region (of course, with the further increase of V1, I BIAS9 / 10 will also increase, but it can be ignored);

[0064] (3) It is not appropriate to continue using the previous method to calculate V1. Obviously, at this time, V1 is closely related to transistors M9 and M10;

[0065] (4) By estimating that I BIAS9 / 10 does not exceed I BIAS11 / 12 , so it may be assumed that the two are equal;

[0066] (5) It should be noted that both V1 and V2 are obtained from the describing function, where V2 is the maximum amplitude value. Therefore, it is for the fundamental frequency amplitude. Any quantity calculated from V1 and V2 is the sinusoidal steady-state solution for a specific frequency and does not represent any "DC", "average", and "root mean square" values.

[0067] Therefore, the following conclusions can be obtained:

[0068] (1) When I BIAS9 / 10 is constant, when I BIAS increases, N increases linearly accordingly;

[0069] (2) When I BIAS9 / 10 is constant, G ds11 / 12 decreases rapidly as V1 increases;

[0070] (3) When I BIAS increases, V2 will increase accordingly;

[0071] (4) The value of k in equation (5) decreases rapidly as V1 increases. Therefore, according to the L eq expression, it can be known that through simulation, L eq also increases as V1 increases. Of course, there is also the influence of N. Since N and both increase linearly with I BIAS , the downward trend of 1 / N is not sufficient to offset the increase.

[0072] (5) It can be deduced from (4) that in the current-limited region, that is, V1 and V2 can increase arbitrarily. When I BIAS increases, the oscillation frequency will decrease;

[0073] (6) If you want to obtain the desired trend, you need to adjust the bias in the voltage-limited region. Or only when V1 and V2 increase, find a way to increase G ds11 / 12 , that is, reduce the tuning voltage Vtune to offset the effect of the increase in V1.

[0074] The above conclusions seem to indicate that reducing I BIAS can effectively improve the circuit performance. However, on the one hand, the reduction of I BIAS will reduce V1 and V2, so no matter which position is used as the output, the output signal will become weaker, ultimately resulting in the failure of signal transmission; on the other hand, when I BIAS is reduced too much, the gain of the cross-coupled pair reaches its maximum value (i.e., the small-signal equivalent transconductance) and will no longer increase. At this time, continuing to reduce I BIAS will reduce the loop gain, ultimately resulting in the oscillation core being unable to start oscillating, which also indicates the failure of the design.

[0075] Therefore, it is necessary to make a compromise between the oscillation amplitude and frequency, or use the characteristics of the voltage-limited region to improve the energy utilization rate. Of course, the above conclusions have certain limitations: 1) I BIASThe increase does not necessarily indicate a decrease in frequency, but the direct relationship between V1 and frequency can be utilized to make predictions for the design; 2) Regarding the large-signal derivation among the various variables of the tunable active inductor, there are other uncertain conditions and variables, and there is still room for improvement, such as the relationship between V2 and V1, the relationship between V2 and the negative-resistance pair, etc. If the change trends among these variables can be determined, it is beneficial to make more accurate predictions.

[0076] In summary, by changing the load of the selector to a tunable active inductor load, the present invention broadens the frequency band tuning range, enables a large gain under a wide frequency band, and has a small active inductor area, facilitating integration.

[0077] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. A high-speed two-to-one selector with an active inductor load, characterized in that, It includes a selector structure and an active inductor load structure; The selector structure includes two pairs of switch enable transistor pairs (1) and two pairs of signal input transistor pairs (2); the two pairs of switch enable transistor pairs (1) serve as the selection frequency band enable switch transistors to control the selection of the required output frequency band; The two pairs of signal input transistor pairs (2) serve as the input transistor pairs for the selector to connect to the previous stage circuit and provide input signals for the selector; The active inductor load structure includes two DC bias transistors (3), a pair of inductor resonance input transistor pairs (4), and two positive transconductance transistors (5); the two DC bias transistors (3) serve as the DC bias transistors of the active inductor load structure to provide an appropriate DC bias voltage for the resonance of the active inductor circuit; A pair of inductor resonance input transistor pairs (4) serve as the inductor resonance tuning voltage input transistors of the active inductor load structure, and by adjusting different voltages, the inductor resonance peak is shifted to expand the frequency selection range; The two positive transconductance transistors (5) serve as the resonance transistors of the active inductor load structure, and by receiving different resonance voltages, different magnitudes of positive transconductance are generated to form resonance peaks of different magnitudes.

2. The high-speed two-to-one selector with an active inductor load according to claim 1, wherein The selector structure includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4; The first PMOS transistor MP1 and the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 constitute the two pairs of switch enable transistor pairs (1), where the first PMOS transistor MP1 and the second PMOS transistor MP2 serve as the enable switch <0>, whose gates receive the enable signal and are connected to the first enable port EN<0>, and the third PMOS transistor MP3 and the fourth PMOS transistor MP4 serve as the enable switch <1>, whose gates receive the enable signal and are connected to the second enable port EN<1>; The first NMOS transistor MN1 and the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 constitute the two pairs of signal input transistor pairs (2), where the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are respectively connected to the first input positive port VIN1 and the first input negative port VIP1, and the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are respectively connected to the second input positive port VIN2 and the second input negative port VIP2.

3. The high-speed two-to-one selector with an active inductor load as described in claim 2, wherein The sources and substrates of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are all connected to the power supply voltage AVDD; the substrates of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all grounded to AVSS; The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3, and the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4; The sources of the first NMOS transistor MN1 and the third NMOS transistor MN3 are interconnected, and the sources of the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are interconnected.

4. The high-speed two-to-one selector with an active inductor load according to claim 2, characterized in that, The active inductor load structure includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8; The fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 serve as two DC bias transistors (3), wherein the drain of the fifth PMOS transistor MP5 is simultaneously connected to the source of the first NMOS transistor MN1 and the source of the third NMOS transistor MN3, and the drain of the sixth PMOS transistor MP6 is simultaneously connected to the source of the second NMOS transistor MN2 and the source of the fourth NMOS transistor MN4; The seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 serve as two positive transconductance transistors (5), wherein the source of the seventh NMOS transistor MN7 is connected to the drain of the fifth PMOS transistor MP5, and the source of the eighth NMOS transistor MN8 is connected to the drain of the sixth PMOS transistor MP6; The fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 serve as a pair of inductive resonant input pair transistors (4), wherein the gates of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are commonly connected to the tuning voltage Vtune.

5. The high-speed two-to-one selector with an active inductor load according to claim 4, characterized in that, The sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the drain of the fifth NMOS transistor MN5, and the drain of the sixth NMOS transistor MN6 are all connected to the bias voltage Vbias; The source of the fifth NMOS transistor MN5 is simultaneously connected to the gate of the fifth PMOS transistor MP5, the gate of the seventh NMOS transistor MN7, and the drain of the eighth NMOS transistor MN8; the source of the sixth NMOS transistor MN6 is simultaneously connected to the gate of the sixth PMOS transistor MP6, the gate of the eighth NMOS transistor MN8, and the drain of the seventh NMOS transistor MN7; The gate of the seventh NMOS transistor MN7 is connected to the first output terminal Vout1; the gate of the eighth NMOS transistor MN8 is connected to the second output terminal Vout2.

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