digital to analog converter circuit

Abstract

A digital-to-analog conversion (DAC) circuit performing least significant bit (LSB) dithering is provided. The DAC circuit includes a first DAC, an auxiliary code generator configured to generate an auxiliary code, an auxiliary DAC configured to receive the auxiliary code and convert the auxiliary code to an analog version of the auxiliary code, and a summing circuit to dither LSBs of the first DAC using the auxiliary code. The auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a range less than a range of binary-weighted LSBs of the first DAC, and / or the auxiliary code generator is configured to generate the auxiliary code as a predetermined repeating sequence. Distortion due to linearity of the LSBs can be reduced using this technical solution.

Description

TECHNICAL FIELD

[0001] The technology described herein relates to dithering of the least significant bits (LSBs) of a segmented digital to analog converter (DAC). BACKGROUND

[0002] DACs convert digital signals to analog signals and are used in a variety of applications. Each bit can be coded with a "weight" that identifies the magnitude of the analog signal that the corresponding current source of the DAC contributes to the output of the DAC when the bit is high. The bits can be weighted using thermometer coding, in which each bit has the same weight, or can be weighted using binary coding, in which the bits are weighted in binary (i.e., each bit is a power of two of the other bit). SUMMARY

[0003] A digital to analog (DAC) circuit includes a main DAC, an auxiliary code generator, an auxiliary DAC, a first summing circuit, and a second summing circuit; wherein the auxiliary code generator is configured to produce an auxiliary code; the auxiliary DAC is configured to receive the auxiliary code and convert the auxiliary code to an analog version of the auxiliary code; the first summing circuit is configured to sum an input digital code and the auxiliary code and provide a sum of the input digital code and the auxiliary code to the main DAC; the second summing circuit is configured to subtract the analog version of the auxiliary code from an analog signal output by the main DAC, wherein the auxiliary code generator is configured to update the auxiliary code at a rate that is less than a sampling rate of the DAC circuit, the auxiliary code has a range that is smaller than a range of binary weighted LSBs of the main DAC, and / or the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence. Wherein the sampling rate of the DAC circuit can be a sampling frequency of the DAC circuit.

[0004] A digital to analog (DAC) circuit that performs least significant bit (LSB) dithering includes a first DAC, an auxiliary code generator, an auxiliary DAC, and a summing circuit; wherein the auxiliary code generator is configured to produce an auxiliary code; the auxiliary DAC is configured to receive the auxiliary code and convert the auxiliary code to an analog version of the auxiliary code; the summing circuit dithers LSBs of the first DAC using the auxiliary code, wherein the auxiliary code generator is configured to update the auxiliary code at a rate that is less than a sampling rate of the DAC circuit, the auxiliary code has a range that is smaller than a range of binary weighted LSBs of the first DAC, and / or the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence. Wherein the first DAC can be a main DAC.

[0005] The digital-to-analog circuit provided by embodiments of the application can reduce distortion caused by linearity of the LSBs.

[0006] The foregoing overview is provided as a general introduction to the subject matter described in the specification and is not intended to be limiting. BRIEF DESCRIPTION OF DRAWINGS

[0007] In the drawings, like or similar elements are denoted by the same reference numeral, with the prefix "like" or "similar" dropped for ease of understanding. Not every component is labeled in every drawing. The drawings are not necessarily to scale, emphasis instead being placed on illustrating the principles of the technology and devices described herein.

[0008] Figure 1 An example of a DAC circuit that performs LSB dithering is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0009] The technology described herein involves dithering the binary-weighted LSBs of a DAC. The DAC can be segmented so that one or more MSBs can have a thermometer- weighted scheme or another weighting scheme that is different from the weighting scheme of the LSBs. Ideally, LSB1 should be exactly 2x LSB0. LSB2 should be exactly 2x LSB1, and so on. If the LSBs are not scaled correctly, distortion can result when the digital signal is small. Dithering will smooth or linearize these scaling errors. Dithering the LSBs as described herein can have the benefit of reducing distortion caused by linearity of the LSBs.

[0010] Some embodiments of the application relate to radio frequency (RF) DACs for wireless communication. For example, the RF DACs can be used for communicating in accordance with WiFi 6 (also known as IEEE Standard 802.11ax). Such DACs can convert digital signals received through wireless communication into analog signals. In WiFi 6, there can be bandwidth limitations, but the sampling frequency fs can be greater than 8 GS / s, which can increase power consumption. Power can be reduced by using one or more of the following techniques.

[0011] In some embodiments, the dithering signal can be generated without a random number generator, which can reduce power consumption. For example, the dithering signal can be a predetermined repeating sequence generated by a counter or other circuit with low power consumption. However, other embodiments can use a random number generator to generate the dithering signal, as not all embodiments omit the random number generator.

[0012] In some embodiments, dithering can be performed at a rate less than full rate (e.g., less than the sampling frequency fs). Optionally, dithering can be performed at a rate of fs / N, where N is an integer greater than or equal to 2. Dithering at a rate less than full rate can reduce power consumption.

[0013] In some embodiments, dithering can be performed over a range less than the entire range of the binary-weighted LSBs. For example, if the LSBs encode over a range of values, the dithering signal can be a code over a range less than the range of the LSBs. Using a smaller range for dithering can reduce the amount of hardware required for the auxiliary DAC to process the dithering signal, thereby reducing power consumption.

[0014] Figure 1 An example of a DAC circuit 100 configured to perform LSB dithering is shown in accordance with some embodiments. The DAC circuit 100 includes a main DAC 2 for converting an input digital code to an analog value. The main DAC 2 can be a segmented DAC having different weighting schemes for different bit segments. For example, the LSBs can be binary-weighted, while the MSBs can be thermometer-weighted. However, the techniques and apparatus described herein are not limited to weighting schemes for the MSBs. The DAC circuit 100 also includes an auxiliary code generator 4 that generates an auxiliary code as a dithering signal. The auxiliary code generator 4 can be implemented in a number of ways, such as using a counter or another circuit configured to generate a repeating sequence of digital codes. In contrast to a random number generator that does not know the sequence in advance, the sequence can be determined prior to operating the auxiliary code generator 4. The sequence can include every number in the range of the auxiliary code. For example, if the auxiliary code has a range of 0 to 5, the sequence can include every integer between 0 and 5, inclusive. The sequence can count up (e.g., 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, etc.) or count down (e.g., 5, 4, 3, 2, 1, 0, 5, 4, 3, 2, 1, 0, etc.), or can have a more complex pattern. Advantageously, a counter or other circuit configured to generate a predetermined repeating sequence can have lower power consumption than a random number generator. However, the techniques and apparatus described herein are not limited in this respect, as in some embodiments the auxiliary code generator 4 can be implemented by a random number generator.

[0015] The DAC circuit 100 also includes an auxiliary DAC 6 configured to convert the auxiliary code to an analog signal. In operation, the auxiliary code is added to the input digital code by a summing circuit (e.g., adder 8) so that the digital signal provided to the main DAC 2 is the sum of the digital code and the auxiliary code. The auxiliary DAC 6 receives the auxiliary code and converts the auxiliary code to an analog signal. A summing circuit (e.g., adder 10) subtracts the analog signal version of the auxiliary code received from the auxiliary DAC 6 from the analog signal produced by the main DAC 2 so that the analog output signal is the analog version of the digital code. Alternatively, the polarity can be reversed so that adder 8 subtracts the auxiliary code from the digital code, the digital signal provided to the main DAC 2 is the result of the digital code minus the auxiliary code, and adder 10 adds the analog version of the auxiliary code to the output of the main DAC 2. Adders 8 and 10 can be performed by any circuit capable of summing signals in the digital or analog domain, respectively, and can perform addition and / or subtraction, as understood in the art, that adders can perform addition or subtraction, and are not limited to performing addition. In some embodiments, using LSB dithering can improve distortion caused by linearity of the LSBs.

[0016] As noted above, in some embodiments, the auxiliary code generator 4 can operate at less than full rate, which can reduce power consumption. For example, in some embodiments, the auxiliary code generator can update the auxiliary code at a rate of Fs / N, where Fs is the sampling frequency of the DAC circuit 100 and N is a positive integer greater than or equal to 2.

[0017] Alternatively or additionally, in some embodiments, the helper code generator 4 can generate the helper code in a range that is smaller than the full range of the LSBs. The inventors have recognized that helper codes with a reduced range are effective in reducing distortion while reducing power consumption. The full range of the LSBs is from 0 to the sum of the weights of the multiple binary-weighted LSBs. For example, if there are 4 binary-weighted LSBs, the weights of the 4 binary-weighted LSBs are 1, 2, 4, and 8, respectively, and the sum of the weights is 1+2+4+8=15, then the full range of the binary-weighted LSBs is from 0 to 15, while the range of the helper code can be narrower than 0 to 15. For example, if there are 4 binary-weighted LSBs, the helper code can have 3 bits, and the range of the helper code is from 0 to 7. Thus, because fewer bits are to be converted, the helper DAC 6 can have less hardware, which can reduce power consumption. However, this is an example, and the range of the helper code can be smaller than the range of the binary-weighted LSBs and / or the number of bits of the helper code can be fewer than the number of bits of the binary-weighted LSBs. In some embodiments, the range of the helper code can be greater than 5%, 10%, or 20% of the full range of the binary-weighted LSBs and less than 99.9%, 95%, or 80% of the full range of the binary-weighted LSBs. In some embodiments, the range of the helper code can be equal to the range of the binary-weighted LSBs of the main DAC, or, the range of the helper code can be more than 1 LSB than the range of the binary-weighted LSBs of the main DAC.

[0018] Various aspects of the devices and techniques described herein can be used alone, in combination, or in various arrangements not specifically discussed in the embodiments described in the foregoing description, and therefore, are not limited to the details and arrangements set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment can be combined with aspects described in other embodiments in any manner.

[0019] The use of the terms "first", "second", "third", etc. to modify a claim element does not imply any priority or order of one claim element over another claim element, or of one method act over another method act, but is merely used as a label to identify a claim element having a particular name.

[0020] In addition, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having," "containing," "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

Claims

1. A digital-to-analog converter (DAC) circuit, comprising: comprising: a main DAC, an auxiliary code generator, an auxiliary DAC, a first summing circuit and a second summing circuit; the auxiliary code generator configured to generate an auxiliary code; the auxiliary DAC configured to receive the auxiliary code and convert the auxiliary code to an analog version of the auxiliary code; the first summing circuit configured to sum an input digital code and the auxiliary code and provide a sum of the input digital code and the auxiliary code to the main DAC; the second summing circuit configured to subtract the analog version of the auxiliary code from an analog signal output from the main DAC, or the first summing circuit configured to subtract the auxiliary code from the input digital code and provide a result of the subtraction of the auxiliary code from the input digital code to the main DAC; the second summing circuit configured to sum the analog signal output from the main DAC and the analog version of the auxiliary code; wherein the auxiliary code generator is configured to perform at least one of: the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit; a range of the auxiliary code is less than a range of a binary-weighted LSB of the main DAC; the auxiliary code generator is configured to generate the auxiliary code as a predetermined repeating sequence.

2. The DAC circuit of claim 1, wherein, the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit.

3. The DAC circuit of claim 2, wherein, the auxiliary code generator is configured to update the auxiliary code at a rate that is a sampling rate of the DAC circuit divided by N, where N is an integer greater than or equal to 2.

4. The DAC circuit of claim 1, wherein, a range of the auxiliary code is less than a range of a binary-weighted LSB of the main DAC.

5. The DAC circuit of claim 4, wherein, a number of bits of the auxiliary code is less than a number of bits of a binary-weighted LSB of the main DAC; the auxiliary DAC is configured to convert a number of bits less than the number of bits of the binary-weighted LSB of the main DAC.

6. The DAC circuit of claim 1, wherein, the auxiliary code generator is configured to generate the auxiliary code as a predetermined repeating sequence.

7. The DAC circuit of claim 6, wherein, the auxiliary code generator comprises a counter.

8. The DAC circuit of claim 1, wherein, is configured to perform at least two of: i) the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit; ii) a range of the auxiliary code is less than a range of a binary-weighted LSB of the main DAC; iii) the auxiliary code generator is configured to generate the auxiliary code as a predetermined repeating sequence.

9. The DAC circuit of claim 1, wherein, the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, a range of the auxiliary code is less than a range of a binary-weighted LSB of the main DAC, and the auxiliary code generator is configured to generate the auxiliary code as a predetermined repeating sequence.

10. A digital-to-analog conversion (DAC) circuit that performs least significant bit (LSB) dithering, the DAC circuit comprising: the DAC circuit comprises: a first DAC; an auxiliary code generator configured to generate an auxiliary code; an auxiliary DAC configured to receive the auxiliary code and convert the auxiliary code to an analog version of the auxiliary code; and a summing circuit to dither a LSB of the first DAC using the auxiliary code, wherein the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a range less than a range of binary-weighted LSBs of the first DAC, and / or the auxiliary code generator is configured to generate the auxiliary code as a predetermined repeating sequence.

11. The DAC circuit of claim 10, wherein, The auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit.

12. The DAC circuit of claim 11, wherein, The auxiliary code generator is configured to update the auxiliary code at a rate of a sampling rate of the DAC circuit divided by N, where N is an integer greater than or equal to 2.

13. The DAC circuit of claim 10, wherein, The auxiliary code has a range less than a range of binary-weighted LSBs of the first DAC.

14. The DAC circuit of claim 13, wherein, The auxiliary code has a number of bits less than a number of binary-weighted LSBs of the first DAC; the auxiliary DAC is configured to convert a number of bits less than the number of binary-weighted LSBs of the first DAC.

15. The DAC circuit of claim 10, wherein, The auxiliary code generator is configured to generate the auxiliary code as a predetermined repeating sequence.

16. The DAC circuit of claim 15, wherein, The auxiliary code generator comprises a counter.

17. The DAC circuit of claim 10, wherein, is configured to perform at least two of: i) the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit; ii) the auxiliary code has a range less than a range of binary-weighted LSBs of the first DAC; iii) the auxiliary code generator is configured to generate the auxiliary code as a predetermined repeating sequence.

18. The DAC circuit of claim 10, wherein, The auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a range less than a range of binary-weighted LSBs of the first DAC, and the auxiliary code generator is configured to generate the auxiliary code as a predetermined repeating sequence.

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