Circuit for communication interface between two dies and method for managing communication interface

Abstract

The present invention provides a circuit for a communication interface between two tube cores and a method for managing the communication interface. The circuit includes: a first interface of a first tube core, having a serializer for serializing input data having N bits into serialized data for transmission; and a second interface of a second tube core, having a deserializer for receiving the serialized data and deserializing it into deserialized data. In addition, an interconnection structure is connected between the first tube core and the second tube core to connect the serializer and the deserializer, wherein the interconnection structure is an insertion layer or a rewiring layer of a semiconductor structure so as to form a parallel bus between the first tube core and the second tube core for transmitting serialized data in one line of the parallel bus. A clock generator provides a first clock to a first ripple counter of the serializer and provides a second clock to a second ripple counter of the deserializer.

Description

Technical Field

[0001] The present invention relates to an interface between two integrated circuit (IC) dies for data communication, and more particularly, to a circuit for a communication interface between two dies and a method for managing the communication interface between two dies. Background Art

[0002] Digital electronic devices based on semiconductor integrated circuits (e.g., mobile phones, digital cameras, personal digital assistants (PDAs), etc.) are designed to have more powerful functionality to adapt to various applications in the modern digital world. However, with the trend of semiconductor manufacturing, digital electronic devices are intended to become smaller and lighter with improved functionality and higher performance. Semiconductor devices can be packaged into 2.5D semiconductor devices, in which several circuit chips can be integrated into a larger integrated circuit, in which contact elements, interposers, or RDL layers are used to connect between chips.

[0003] Integrated Fan-Out (InFO) and chip-on-wafer-on-substrate (CoWoS) packaging technologies have been proposed to package multiple chips assembled side by side.

[0004] Regarding the entire electronic circuit, the main circuit can be manufactured based on 2.5D packaging technology. In addition, multiple application-specific integrated circuit (ASIC) dies and serializer / deserialized (SerDes) dies can be additionally arranged on the main circuit to be connected to each other through an interconnection interface including a parallel bus.

[0005] The interfaces of the two dies to be connected usually respectively contain contact element patterns for connecting to each other. The contact element pattern of a die contains a plurality of contact elements for connecting to contact elements of another die.

[0006] In communication, the contact elements of one die are connected to the contact elements of another die in a parallel communication mode. Here, the communication physical layer in each die usually includes a serializer that converts parallel data into serial data. A set of serial data is transmitted to another die through a contact element. Then, the communication physical layer also includes a deserializer that converts serial data into parallel data.

[0007] Each die includes a serializer and a deserializer as a slice. Each die may include multiple slices. Two dies are connected based on packaging technology, where the serializer and deserializer of one die are connected to the deserializer and serializer of the other die, respectively. The serializer is responsible for transmitting data and the deserializer is responsible for receiving data. However, clocks of different rates are used for serializers and deserializers corresponding to multiple stages, thereby serializing and deserializing data at each stage. Based on 2.5D packaging technology, how to efficiently provide an appropriate clock rate for the clock at each stage remains a problem in the design. Summary of the invention

[0008] The present invention provides a circuit for a communication interface between a first tube core and a second tube core based on a parallel bus. However, the data transmitted on the channel of the parallel bus is serialized data. Each tube core is implemented using at least one serializer and one deserializer to transmit data between the two tube cores. The clock-based serializer and deserializer can perform serialization and deserialization of data.

[0009] In an embodiment, a circuit for a communication interface between a first die and a second die is provided. The circuit includes: a first interface of the first die, having a serializer that serializes input data having N bits in parallel form into serialized data for transmission out; and a second interface of the second die, having a deserializer that receives the serialized data and deserializes it into deserialized data having N bits in parallel form. In addition, an interconnect structure is connected between the first die and the second die to connect the serializer and the deserializer, wherein the interconnect structure is an insertion layer or a rewiring layer of the semiconductor structure so as to form a parallel bus between the first die and the second die for transmitting the serialized data in one line of the parallel bus. The clock generator provides a first clock separated from the input data to a first ripple counter of the serializer and provides a second clock separated from the input data to a second ripple counter of the deserializer, wherein the serializer and the deserializer use the first clock and the second clock, respectively, in operation.

[0010] In an embodiment, a method for managing a communication interface between a first die and a second die is provided. The method includes: implementing a first interface of the first die, including a serializer for serializing input data having N bits in parallel form into serialized data for transmission out; implementing a second interface of the second die, including a deserializer for receiving the serialized data and deserializing it into deserialized data having N bits in parallel form. In addition, the method includes implementing an interconnect structure connected between the first die and the second die to connect the serializer and the deserializer, wherein the interconnect structure is an insertion layer or a rewiring layer of a semiconductor structure so as to form a parallel bus between the first die and the second die for transmitting the serialized data in one line of the parallel bus. A clock generator is also implemented to provide a first clock separated from the input data to a first ripple counter of the serializer and a second clock separated from the input data to a second ripple counter of the deserializer, wherein the serializer and the deserializer use the first clock and the second clock, respectively, in operation.

[0011] In order to make the foregoing content easier to understand, several embodiments of the drawings are described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0013] Figure 1 is a diagram schematically showing a cross-sectional stacking structure of a 2.5D semiconductor device having an interface according to an embodiment of the present invention;

[0014] Figure 2 is a diagram schematically showing an interface through which a die is connected to a plurality of other dies according to an embodiment of the present invention;

[0015] Figure 3 is a diagram schematically illustrating an interface for connection between a plurality of dies according to an embodiment of the present invention;

[0016] Figure 4 is a diagram schematically illustrating communication between two dies based on an interface with an interposer or RLD according to an embodiment of the present invention;

[0017] Figure 5 is a diagram schematically showing a structure of a contact element pattern according to an embodiment of the present invention;

[0018] Figure 6 is a diagram schematically illustrating a mechanism of a serializer and a deserializer according to an embodiment of the present invention;

[0019] Figure 7is a diagram schematically showing a structure of a serializer according to an embodiment of the present invention;

[0020] Figure 8 is a diagram schematically showing a structure of a deserializer according to an embodiment of the present invention;

[0021] Fig. 9 is a diagram schematically showing the structure of a serialization block according to an embodiment of the present invention;

[0022] Fig.10 is a diagram schematically showing the structure of a deserialization block according to an embodiment of the present invention;

[0023] Fig.11 is a diagram schematically showing a structure of a deserializer having a clock recovery (CR) logic according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The present invention is directed to an interface between two integrated circuit (IC) dies for data communication. Depending on the packaging process adopted, the contact elements of the two dies are correspondingly connected through a connection interface such as an insertion layer or a redistribution layer (RDL). The parallel data of one die is serialized into serial data and then transmitted to the target die through the connection interface. The serial data received by the target die needs to be deserialized into parallel data. The clock used in the deserializer is also transmitted through a contact element of the connection interface. The phase of the clock needs to be appropriately adjusted to correctly sample the serial data to deserialize into parallel data.

[0025] Phase adjustment of the clock for the deserializer is necessary to ensure that the data is deserialized correctly. A number of embodiments are provided to describe the present invention, but the present invention is not limited to the embodiments.

[0026] First, the packaging structure between the dies manufactured as semiconductor devices is described. For semiconductor manufacturing, the interface of the 2.5D semiconductor device can be used, in which the dies are placed on the interposer layer or RDL. The contact element pattern of the dies is configured to have a geometrically symmetrical relationship. The dies are connected more freely through the interface. The wiring length between the contact elements in the wiring can also be set more equally and shorter.

[0027] In communication through an interface, parallel data at a transmitting die is usually serialized into a bit string in serial form. Various signals containing the bit string are transmitted to another die, as a receiving die, through an interface. The interface provides a parallel bus for transmitting signals in serial form. Subsequently, the receiving die needs to correctly deserialize the input data signal to correctly obtain the communication data as transmitted.

[0028] Several embodiments are provided to describe the present invention, but the present invention is not limited to the embodiments.

[0029] The entire integrated circuit can be manufactured as a semiconductor device through a semiconductor manufacturing process, and the semiconductor device can be manufactured based on a stacked structure of a 2.5D semiconductor device. The interface of the tube die receiving data may include a frame decoding circuit associated with a deserialization circuit. In an embodiment, the interface in the semiconductor structure is integrated into the circuit of the entire tube die.

[0030] First, semiconductor manufacturing will be described. Figure 1 FIG. 1 is a diagram schematically showing a cross-sectional stacking structure of a 2.5D semiconductor device having an interface according to an embodiment of the present invention. Figure 1 In another application, a CoWoS or InFO platform 50 having a desired IC structure is formed based on 2.5D packaging technology. The CoWoS or InFO platform 50 may include a package substrate 100 having a bottom solder ball 104 and a top contact element 106. A through hole 102 may be used to connect from the bottom solder ball 104 to the top contact element 106. In addition, an interposer or RDL 110 may be further formed on the substrate 100 in connection with the contact element 106. The interposer or RDL 110 may also include TSV 112, interconnect wiring 114, and contact element 116. Here, depending on the manufacturing process used, the contact element 116 may be a through hole or a bump pad or any suitable connection structure for terminal-to-terminal contact. The present invention does not limit the contact element 106 to a specific type.

[0031] In practical applications, additional dies, such as ASIC die 130 and SerDes die 120, may also be used to implement the CoWoS or InFO platform 50. The ASIC die 130 and the SerDes die 120 are connected via wiring 114 and contact elements 116. One ASIC die 130 may be connected to multiple SerDes dies 120 for various peripheral communications.

[0032] Figure 2 FIG. 1 is a diagram schematically showing an interface through which a die is connected to multiple other dies according to an embodiment of the present invention. Figure 2 , one IC die 200 (e.g., a processor or ASIC die) can be connected to multiple dies 202 through an interface 204. The interface 204 contains a parallel bus to communicate between the die 200 and the die 202. The interface 204 can include wiring and contact elements in a contact element pattern so that the die 200 can be connected to the die 202.

[0033] Figure 3 FIG. 1 is a diagram schematically illustrating an interface for connection between multiple processor dies according to an embodiment of the present invention. Figure 3In another application, multiple processors 200 ′ can be connected together to form a large processor with more powerful functions. In this case, these processors 200 ′ are also connected via the interface 204 .

[0034] As described above, the 2.5D packaging process can be applied to stack various tube cores side by side without substantially further consuming device area. However, in order to allow the tube cores to be connected more freely, it is necessary to properly arrange the contact elements in the interface 204 in a compact manner and further symmetrically for receiving and transmitting signals. The communication between the two tube cores 200 to the tube core 202 can be easily arranged at the peripheral area. Here, the interface 204 can also refer to the Glink interface as provided on the market.

[0035] Figure 4 is a diagram schematically illustrating communication between two dies based on an interface with an interposer or RLD according to an embodiment of the present invention. Figure 4 In an example, the ASIC die 130 and the SerDes die 120 communicate through an interposer or RDL 110. The contact elements of the ASIC die 130 and the SerDes die 120 for contacting the interposer or RDL 110 are appropriately arranged. Each contact element can transmit a specific signal at the same time. Therefore, a parallel bus is set based on the contact elements. The signal of each contact element is in a serial form, such as a bit string.

[0036] Figure 5 FIG. 1 is a diagram schematically showing a structure of a contact element pattern according to an embodiment of the present invention. Figure 5 , the total number of contact elements contained in the interface can be the number of signals that can be communicated in parallel for transmission and reception.

[0037] The total number of bumps contained in the interface can be a larger number. Signals communicate in parallel between the dies for transmission and reception. Depending on the size of the data in a bus, the data size of 32 bits with operating voltage and other functional signals is set to refer to a slice of the contact element pattern 300. The contact element pattern 300 can be replicated to a certain number (e.g., 8) to adapt to the total data size in parallel communication. In an example, the data corresponds to 32 bits with a sequence of R_D0 to R_D31 and T_D0 to T_D31, in which T represents a bump for transmission and R represents a bump for reception. In addition, a plurality of low voltage signals VSS and a plurality of high voltage VDDP are also included in the contact element pattern 300. In addition, various functional signals are also included, including frame T / R_FR, clock T / R_DCK_P / N, flow control T / R_FC[1:0], DBIT / R_DBI[3:0], parity T / R_PAR, and path repair T / R_LR[1:0]. However, the bumps for the functional signals are not limited to the embodiment described.

[0038] Table 1 is an example of defining bumps of a transmission (T) group or a reception (R) group. The transmission group and the reception group have the same number of bumps.

[0039] Table 1

[0040]

[0041] Based on the above described interposer layer or RDL 110, various signals are communicated between the two dies. However, in an example, a set of parallel signals in communication can be converted into a serial form to be transmitted / received through one wiring with one contact element. Once the data signal in serial form is received by the IC die, the IC die deserializes the data signal into a parallel form.

[0042] In an embodiment, in order to ensure that the data signal is correctly deserialized into a parallel form, a frame signal is provided to define the N bit data in each group. In the example, N is 8, but the present invention is not limited to 8. The parameter N is determined according to the actual data transmission algorithm. Here, 8 bits of data form a byte. The following example uses an 8-bit signal as an example for description.

[0043] Based on the packaging process, the communication physical layers of the two dies may be connected through an interposer layer or RDL 110 that acts as a parallel bus. However, each contact element of the parallel bus transmits serialized data.

[0044] Based on the parallel bus at the interposer layer or RDL 110, the reference clock is used in the serializer of one die and is also transmitted through the parallel bus to the deserializer on the other die in communication. Since the reference clock and serialized data are transmitted simultaneously, the deserializer needs to properly align / track the reference clock to correctly sample the serialized data into parallel data. The mechanism of the serializer and deserializer based on the reference clock is described.

[0045] Figure 6 Schematically illustrates the mechanism of a serializer and a deserializer according to an embodiment of the present invention. Figure 6 , data transmission operation between the serializer 402 of the first die 400 to the deserializer 456 at the second die 450, which is connected to the first die 400 through the interposer layer or RDL 110. The reference clock from the phase locked loop (PLL) 350 is provided to the serializer 402 implemented in one die 400 and the deserializer 456 implemented in the other die 450. In an embodiment, the die 450 may also include a clock recovery circuit 452 to receive the forwarded clock from the phase locked loop (PLL) 350 and recover from the input clock as forwarded by appropriate phase adjustment. The clock is used in the deserializer 456 after the clock recovery circuit 452.

[0046] In an embodiment, the plurality of serializers 402 are used to serialize the corresponding plurality of parallel data to form TXD <0> TXD <1> ...etc. In operation, serialized data TXD is used. <0> As an example, parallel data is stored in a data processing block 406 indicated by PMAD. The parallel data in the example includes 16 bits in parallel. Corresponding to the example, four serialization units 408 are included in one serializer 402 for four serialization stages. The first serialization stage corresponding to 16 bits of processing receives a reference clock with a clock rate as indicated by CK 16t from a ripple counter 404 at the transmission side TX_Side. The serialization unit 408 at the first stage serializes the 16 bits in parallel into 8-bit parallel data signals. The ripple counter 404 provides four clock rates for the clock, wherein the frequency is divided by a factor of 2 in the four stages. Because 16 bits are transmitted in the same clock cycle, a smaller clock rate CK 16t is used in the serialization unit 408 at the first stage, wherein the serialization unit 408 at the first stage does not need a fast clock rate. The serialization unit 408 at the second serialization stage serializes the 8-bit parallel data signal into a 4-bit parallel data signal according to the clock rate CK 8t. Similarly, the final serialization stage includes a serialization unit 408 to serialize the 2-bit parallelized data signal into a 1-bit serialized data TXD. <0> , and transmits it to the deserializer 456 of the tube core 450 to recover the original parallel data. The serialized data TXD received by the tube core 450 <0> By RXD <0> Using the same mechanism, the serialized data TXD received by the die 450 <1> By RXD <1> instruct.

[0047] The clock from PLL 350 is also divided by ripple counter 454 in four stages at the receive side as indicated by RX_Side, which corresponds to 16 bits in the example. The clock frequency is sequentially divided by 2, similar to ripple counter 404. Clock recovery 452 may be included but is not absolutely required. Clock recovery 452 can modify the phase of the clock from PLL 350 to accurately sample the received data RXD in serialized or tandem form. <0> 、Data RXD <1> .

[0048] The deserialization unit 460 at the first stage deserializes one serialized data of 16 bits in the example into two temporarily parallel deserialized data signals by a 1 to 2 effect. The clock rate as indicated by CK 2t needs to be fast enough for sampling the serial data of 16 bits. Similarly, the deserialization unit 460 at the second stage deserializes two deserialized data signals into four deserialized data signals by a 2 to 4 effect of the clock rate CK 4t. Similarly, the deserialization unit 460 at the third stage has a 4 to 8 effect using a clock rate CK8t. The deserialization unit 460 at the last stage has an 8 to 16 effect of a clock rate CK 16t relative to the 16 bits in the example. The fully deserialized data is stored in the data processing block 458 as also indicated by PMAD. Received data RXD <1> Deserialization is performed by another deserializer 456 .

[0049] Figure 7 FIG. 1 is a diagram schematically showing a structure of a serializer according to an embodiment of the present invention. Figure 7 , further showing in detail a serializer with a data signal path. In addition, using 16 bits in operation as an example, the serialization unit 410 of the first stage receives 16 bits in parallel. The serialization unit 410 of the first stage has the serialization capability of serializing a 16-bit data signal into an 8-bit data signal, as indicated by 16:8. In the example, a second stage serialization unit 412, a third stage serialization unit 414, and a fourth stage serialization unit 416 are contained to serialize data signals as indicated by 8:4, 4:2, and 2:1, respectively. In the example, the frequency of the clock at the divider 422 is divided by 2 in four stages, wherein the fourth stage clock may be only the input clock CLK without frequency division.

[0050] The serialization function is described using the second stage serialization unit 412 as an example. Four serialization blocks 420 are included to serialize the data signal from 8 bits to 4 bits. Each serialization block 420 receives a two-bit input data signal and outputs a one-bit data signal, as indicated by 2:1, for the next serialization stage. Similarly, the third stage serialization unit 414 includes two serialization blocks 420 to serialize the data signal from 4 bits to 2 bits. The fourth stage serialization unit 416 includes one serialization block 420 to serialize the data signal from 2 bits to 1 bit.

[0051] Figure 8 Schematically shows the structure of a deserializer according to an embodiment of the present invention. Figure 8 , the embodiment has 16 bits of initial parallel data in Figure 7The input clock CLK may be divided by a frequency divider 432 according to actual needs in the deserialization unit, and the deserialization unit includes a first-stage deserialization unit 470, a second-stage deserialization unit 472, a third-stage deserialization unit 474, and a fourth-stage deserialization unit 476.

[0052] The first stage deserialization unit 470 indicated by 1:2 includes one deserialization block 430. Each deserialization block 430 deserializes a one-bit input data signal into a two-bit output data signal, as indicated by 1:2. Thus, the second stage deserialization unit 472 indicated by 2:4 includes two deserialization blocks 430. The third stage deserialization unit 474 indicated by 4:8 includes four deserialization blocks 430. The fourth stage deserialization unit 476 indicated by 8:16 includes eight deserialization blocks 430. As mentioned, parallel 16-bit data signals are output from the fourth stage deserialization unit 476.

[0053] With respect to the data size of 16 bits, the number of stages in serialization and deserialization is four stages but the present invention is not limited to four stages. It depends on the size of the data being transmitted.

[0054] Fig. 9 FIG. 1 is a diagram schematically showing the structure of a serialization block according to an embodiment of the present invention. Fig. 9 In an embodiment, as also in Figure 7 The serialization block 420 shown in the figure may include two flip-flops (FF) 500, which receive two input data signals D0 and input data signal D1 respectively. In an example, the data signal D1 is latched by a latch L 502 connected after the FF 500. The multiplexer Mux 504 receives the data signal D0 passing through the FF 500 and the data signal D1 passing through the FF 500 and the latch L 502. The clock CK is usually used to control the FF 500, the latch L 502 and the multiplexer Mux 504. Therefore, the data signal D0 and the data signal D1 in the multiplexer Mux 504 are sequentially output by the output terminal OUT of the multiplexer Mux 504 under the control of the clock CK. The serialization block 420 can be implemented in multiple stages to serialize parallel data into series data, that is, serialize data.

[0055] Fig.10 FIG. 1 is a diagram schematically showing the structure of a deserialization block according to an embodiment of the present invention. Fig.10 In an embodiment, as also in Figure 8The deserialization block 430 shown in the figure may include two flip-flops (FF) 508, which receive one input data signal IN respectively, but one input data signal IN enters latch L 506 before entering FF 508. The clock CK also controls latch L 506 and FF 508. In an example, data signal D1 is output from one FF 508 without latching. The data signal IN with latch L 506 will be deserialized into data signal D0 in real time. Therefore, the data signal D0 and the data signal D1 in two bits are in parallel form for output. The deserialization block 430 can be implemented in multiple stages to deserialize the serial data into parallel data, that is, deserialize the data.

[0056] Fig.11 Schematically shows the structure of a deserializer with clock recovery (CR) logic according to an embodiment of the present invention. Fig.11 Also refer to Figure 6 As part of the deserializer, the clock recovery (CR) logic 530 is included in the deserializer and can obtain the clock through the data signal itself. In general, the sampler 520 receives the reference clock DCKP, the reference clock DCKN and provides a clock rxclk that passes through multiple frequency dividers 526 in multiple stages. The deserializer also passes the data signal to the demultiplexer (Demux) 528 according to the clock rxclk with a clock rate to output 16-bit parallel information data rxdat[15:0] as an example. In order to obtain the clock from the information data itself, another demultiplexer (Demux) 524 can directly generate the rising edge and the falling edge as the edge data rxedge[15:0]. The clock recovery (CR) logic 530 samples the information data rxdat[15:0] and the edge data rxedge[15:0] to generate the phase value rx_phase. The phase value rx_phase from the CR logic 530 is input to the phase rotator 522, and the phase rotator 522 adjusts the phases of the reference clocks DCKP and DCKN according to the phase value rx_phase, so that the sampling edges of the reference clocks DCKP and DCKN are properly located at the middle edge of the data eye, thereby correctly sampling the data signal. Figure 6 , clock recovery (CR) logic 530 receives input clock 600CLK, and phase rotator 522 can provide appropriate modification to input clock 600CLK to provide a clock for sampling data. Clock 600CLK is applied separately from data. The sampling clock in the embodiment is the sampling clock used for all sampling and deserialization stages.

[0057] In the foregoing description, the following features can be achieved.

[0058] Typical Serializer / Deserializer (Serdes) recovers the clock from the data stream and uses the recovered clock to sample the data. The proposed invention transmits the clock as a separate net in addition to the data. The invention uses a clock forwarding scheme. Therefore, the clock may not necessarily be recovered from the data, but the sampling clock is recovered from the input forwarding clock. This approach can simplify many clock recoveries and achieve better sampling clock quality. The invention can provide a transmission clock separate from the data because CoWoS / InFO can transmit many routing tracks.

[0059] In a typical serializer / deserializer, each data lane is an independent interface. Each lane should recover the clock from its data stream in order to sample the data transmitted through this lane. In one embodiment of the present invention, one forwarding clock is shared by many data channels. Therefore, clock recovery can also be shared by many data channels. One recovered clock can be used to sample all data bits. It also simplifies many circuits and reduces circuit and power. The present invention can provide sampling of many data channels by the same clock because CoWoS / InFO allows accurate and identical routing traces and delays for all data channels and clock channels.

[0060] Typical serializer / deserializer uses data stream to recover clock. Therefore, data must be converted all the time. Even when there is no transmitted data. Data randomization is used to have higher conversion even when the transmitted data is not fully converted. The present invention recovers the clock from an independent forwarding clock. Data does not have to be converted. Data can be transmitted without randomization.

[0061] The present invention may also be implemented as a circuit for a communication interface between a first die and a second die and a method for managing a communication interface between the first die and the second die.

[0062] In an embodiment, the circuit includes: a first interface of a first die having a serializer for serializing input data having N bits in parallel form into serialized data for transmission out; and a second interface of a second die having a deserializer for receiving the serialized data and deserializing it into deserialized data having N bits in parallel form. In addition, an interconnect structure is connected between the first die and the second die to connect the serializer and the deserializer, wherein the interconnect structure is an interposer or a rewiring layer of the semiconductor structure so as to form a parallel bus between the first die and the second die for transmitting the serialized data in one line of the parallel bus. A clock generator provides a first clock to a first ripple counter of the serializer and a second clock to a second ripple counter of the deserializer.

[0063] In an embodiment, a method includes: implementing a first interface of a first die, including a serializer for serializing input data having N bits in parallel form into serialized data for transmission out; implementing a second interface of a second die, including a deserializer for receiving the serialized data and deserializing it into deserialized data having N bits in parallel form. In addition, the method includes implementing an interconnect structure connected between the first die and the second die to connect the serializer and the deserializer, wherein the interconnect structure is an interposer or a rewiring layer of a semiconductor structure so as to form a parallel bus between the first die and the second die for transmitting the serialized data in one line of the parallel bus. A clock generator is also implemented to provide a first clock to a first ripple counter of the serializer and a second clock to a second ripple counter of the deserializer.

[0064] In an embodiment, regarding circuits and methods of a communication interface and a method for managing a communication interface, a first ripple counter receives a first clock and sequentially provides a plurality of first divided clock signals corresponding to serialization stages by sequentially dividing the clock rate of the first clock by a factor of 2 in a plurality of serialization stages.

[0065] In an embodiment, regarding a circuit of a communication interface and a method for managing a communication interface, a serializer includes a plurality of first serialization units, which are used to receive input data having N bits and a first divided clock signal from a highest clock rate to a lowest clock rate, respectively, wherein each of the first serialization units serializes the input data by a factor of 2 until the N bits of the input data are serialized into serialized data.

[0066] In an embodiment, regarding a circuit of a communication interface and a method for managing a communication interface, a first serialization stage of a first serialization unit receives input data having N bits in parallel form and serializes it into N / 2 transient serialization data, wherein a second serialization stage of the first serialization unit sequentially receives the N / 2 transient serialization data and serializes it into N / 2 / 2 transient serialization data, wherein a last serialization stage of the first serialization unit receives two transient serialization data from a previous serialization stage into the serialized data.

[0067] In an embodiment, regarding a circuit of a communication interface and a method for managing a communication interface, N is the number 2 M , where M is an integer greater than or equal to 4.

[0068] In an embodiment, regarding a circuit of a communication interface and a method for managing a communication interface, each of the first serialization units comprises 2 L serialization blocks, where L is an integer corresponding to the operation of the corresponding serialization stage, wherein each of the serialization blocks serializes two input parallel data into two output concatenated data.

[0069] In an embodiment, regarding a circuit of a communication interface and a method for managing a communication interface, a second ripple counter receives a second clock and sequentially divides a clock rate of the second clock by a factor of 2 in a plurality of deserialization stages to sequentially provide a plurality of second divided clock signals corresponding to the deserialization stages.

[0070] In an embodiment, regarding a circuit of a communication interface and a method for managing a communication interface, a deserializer includes a plurality of deserialization units, which are used to receive serialized data and a second divided clock signal from a highest clock rate to a lowest clock rate, respectively, wherein each of the deserialization units deserializes the input data by a factor of 2 until N bits of the input data are deserialized into deserialized data in parallel form.

[0071] In an embodiment, regarding a circuit of a communication interface and a method for managing a communication interface, a first deserialization stage of a deserialization unit receives serialized data having N bits in a serial form and deserializes it into 2 transient deserialized data, wherein a second deserialization stage of the deserialization unit sequentially receives 2 transient deserialized data and deserializes them into 4 transient deserialized data, wherein a last deserialization stage of the deserialization unit receives N / 2 transient deserialized data from a previous deserialization stage into deserialized data having N bits in a parallel form.

[0072] In an embodiment, regarding a circuit of a communication interface and a method for managing a communication interface, N is the number 2 M , where M is an integer greater than or equal to 4.

[0073] In an embodiment, regarding the circuit of the communication interface and the method for managing the communication interface, each of the deserialization units includes 2 L serialization blocks, where L is an integer corresponding to the operation of the corresponding deserialization stage, wherein each of the deserialization blocks deserializes two input serial data into two output parallel data.

[0074] In an embodiment, regarding the circuit of a communication interface and a method for managing a communication interface, the second die further includes: clock recovery logic that samples the deserialized data and the rising edge of the deserialized data to determine a clock phase; and a phase rotator that receives the clock phase to determine a phase offset to modify the second clock of the deserializer.

[0075] In an embodiment, regarding the circuit of the communication interface and the method for managing the communication interface, the input data is transmitted via a double data rate (DDR).

[0076] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure encompasses modifications and variations provided that the modifications and variations fall within the scope of the appended claims and their equivalents.

Claims

1. A circuit for a communication interface between a first die and a second die, comprising: The first interface of the first die includes a serializer for serializing input data having N bits in parallel form into serialized data for transmission; A second interface of the second die includes a deserializer for receiving the serialized data and deserializing it into deserialized data having the N bits in parallel form; an interconnect structure connected between the first die and the second die to connect the serializer and the deserializer, wherein the interconnect structure is an interposer or a redistribution layer of a semiconductor structure so as to form a parallel bus between the first die and the second die for transmitting the serialized data in one line of the parallel bus; as well as a clock generator for providing a first clock separate from the input data to a first ripple counter of the serializer and providing a second clock separate from the input data to a second ripple counter of the deserializer, wherein the serializer and the deserializer use the first clock and the second clock, respectively, in operation, The first ripple counter receives the first clock and sequentially divides the clock rate of the first clock by a factor of 2 in a plurality of serialization stages to sequentially provide a plurality of first frequency-divided clock signals corresponding to the serialization stages.

2. The circuit of the communication interface according to claim 1, wherein the serializer comprises a plurality of first serialization units, which are used to receive the input data having the N bits and the first divided clock signal respectively from a lowest clock rate to a highest clock rate, wherein each of the first serialization units serializes the input data by a factor of 2 until the N bits of the input data are serialized into the serialized data.

3. The circuit of the communication interface according to claim 2, wherein a first serialization stage of the first serialization unit receives the input data having the N bits in parallel form and serializes it into N / 2 transient serialization data, wherein a second serialization stage of the first serialization unit sequentially receives the N / 2 transient serialization data and serializes it into N / 2 / 2 transient serialization data, wherein a last serialization stage of the first serialization unit receives two transient serialization data from a previous serialization stage into the serialized data.

4. The communication interface circuit according to claim 2, wherein N is the number 2 M , where M is an integer greater than or equal to 4.

5. The communication interface circuit according to claim 2, wherein each of the first serialization units comprises 2 L serialization blocks, where L is an integer corresponding to the operation of the corresponding serialization stage, wherein each of the serialization blocks serializes two input parallel data into two output concatenated data.

6. The circuit of the communication interface of claim 2, wherein the second ripple counter receives the second clock and sequentially divides the clock rate of the second clock by a factor of 2 in a plurality of deserialization stages to sequentially provide a plurality of second divided clock signals corresponding to the deserialization stages.

7. The circuit of the communication interface according to claim 6, wherein the deserializer comprises a plurality of deserialization units which receive the serialized data and the second divided clock signal respectively from a highest clock rate to a lowest clock rate, wherein each of the deserialization units deserializes the input data by a factor of 2 until the N bits of the input data are deserialized into the deserialized data in a parallel form.

8. The circuit of the communication interface according to claim 7, wherein a first deserialization stage of the deserialization unit receives the serialized data having the N bits in a serial form and deserializes it into two transient deserialized data, wherein a second deserialization stage of the deserialization unit sequentially receives the two transient deserialized data and deserializes it into four transient deserialized data, wherein a last deserialization stage of the deserialization unit receives N / 2 transient deserialized data from a previous deserialization stage into the deserialized data having the N bits in a parallel form.

9. The communication interface circuit according to claim 7, wherein N is the number 2 M , where M is an integer greater than or equal to 4.

10. The circuit of the communication interface according to claim 7, wherein each of the deserialization units comprises 2 L deserialization blocks, where L is an integer corresponding to the operation of the corresponding deserialization stage, wherein each of the deserialization blocks deserializes two input serial data into two parallel data.

11. The circuit of the communication interface according to claim 1, wherein the second die further comprises: clock recovery logic that receives the second clock to determine a clock phase; and A phase rotator receives the clock phase to determine a phase offset to modify the second clock of the deserializer.

12. The circuit of the communication interface according to claim 1, wherein the input data is transmitted via double data rate.

13. A method for managing a communication interface between a first die and a second die, comprising: A first interface implementing the first die includes a serializer for serializing input data having N bits in parallel form into serialized data for transmission outwardly; implementing a second interface of the second die, including a deserializer to receive the serialized data and deserialize it into deserialized data having the N bits in parallel form; implementing an interconnect structure connected between the first die and the second die to connect the serializer and the deserializer, wherein the interconnect structure is an interposer or a redistribution layer of a semiconductor structure to form a parallel bus between the first die and the second die for transmitting the serialized data in one line of the parallel bus; as well as implementing a clock generator for providing a first clock separate from the input data to a first ripple counter of the serializer and providing a second clock separate from the input data to a second ripple counter of the deserializer, wherein the serializer and the deserializer use the first clock and the second clock, respectively, in operation, The first ripple counter as implemented receives the first clock and sequentially divides the clock rate of the first clock by a factor of 2 in a plurality of serialization stages to sequentially provide a plurality of first divided clock signals corresponding to the serialization stages.

14. The method for managing a communication interface between a first die and a second die according to claim 13, wherein the serializer as implemented comprises a plurality of serialization units, which are used to receive the input data having the N bits and the first divided clock signal respectively from a lowest clock rate to a highest clock rate, wherein each of the serialization units serializes the input data by a factor of 2 until the N bits of the input data are serialized into the serialized data.

15. The method for managing a communication interface between a first die and a second die according to claim 14, wherein a first serialization stage of the serialization unit receives the input data having the N bits in parallel form and serializes it into N / 2 transient serialization data, wherein a second serialization stage of the serialization unit sequentially receives the N / 2 transient serialization data and serializes it into N / 2 / 2 transient serialization data, wherein a last serialization stage of the serialization unit receives two transient serialization data from a previous serialization stage into the serialized data.

16. The method for managing a communication interface between a first die and a second die according to claim 14, wherein N is a number 2 M , where M is an integer greater than or equal to 4.

17. The method for managing a communication interface between a first die and a second die according to claim 16, wherein each of the serialization units comprises 2 L serialization blocks, where L is an integer corresponding to the operation of the corresponding serialization stage, wherein each of the serialization blocks serializes two input parallel data into two output concatenated data.

18. The method for managing a communication interface between a first die and a second die according to claim 14, wherein the second ripple counter as implemented receives the second clock and sequentially divides the clock rate of the second clock by a factor of 2 in a plurality of deserialization stages to sequentially provide a plurality of second divided clock signals corresponding to the deserialization stages.

19. The method for managing a communication interface between a first die and a second die according to claim 18, wherein the deserializer as implemented comprises a plurality of deserialization units, which are used to receive the serialized data and the second divided clock signal respectively from a highest clock rate to a lowest clock rate, wherein each of the deserialization units deserializes the input data by a factor of 2 until the N bits of the input data are deserialized into the deserialized data in a parallel form.

20. The method for managing a communication interface between a first die and a second die according to claim 19, wherein a first deserialization stage of the deserialization unit receives the serialized data having the N bits in a serial form and deserializes it into 2 transient deserialized data, wherein a second deserialization stage of the deserialization unit sequentially receives the 2 transient deserialized data and deserializes it into 4 transient deserialized data, wherein a last deserialization stage of the deserialization unit receives N / 2 transient deserialized data from a previous deserialization stage into the deserialized data having the N bits in a parallel form.

21. The method for managing a communication interface between a first die and a second die according to claim 19, wherein N is the number 2 M , where M is an integer greater than or equal to 4.

22. The method for managing a communication interface between a first die and a second die according to claim 19, wherein each of the deserialization units comprises 2 L deserialization blocks, where L is an integer corresponding to the operation of the corresponding deserialization stage, wherein each of the deserialization blocks deserializes two input serial data into two output parallel data.

23. The method of managing a communication interface between a first die and a second die according to claim 13, wherein the second die further comprises: clock recovery logic that receives the second clock to determine a clock phase; and A phase rotator receives the clock phase to determine a phase offset to modify the second clock of the deserializer.

24. The method of managing a communication interface between a first die and a second die according to claim 13, wherein the input data is transmitted via a double data rate.

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