Controller, device control system and time synchronization method

Abstract

A controller, a device control system and a time synchronization method are provided. The controller includes: a master clock management unit, which is used to synchronize the master clock with an external global clock and set the master time based on the master clock; a controller clock management unit, which is used to synchronize the controller clock with the master clock, perform time synchronization to synchronize the controller time based on the controller clock with the master time, and send controller time data indicating the synchronized controller time to at least one local device; a window setting unit, which is used to set a plurality of time windows corresponding to a plurality of clock cycles of a clock signal for time synchronization; a determination unit, which is used to determine whether one of the plurality of clock cycles has started within one of the plurality of time windows, the one time window corresponding to the one clock cycle; and an update control unit, which is used to suspend the time synchronization corresponding to the one clock cycle in response to determining that the one clock cycle has not started within the one time window.

Description

Technical Field

[0001] One aspect of the present disclosure relates to a controller, a device control system, a time synchronization method, and a time synchronization program. Background Art

[0002] Japanese Patent No. 4840455 discloses a field control system that synchronizes and performs calculations for controlling field devices and data communications with the field devices at a time point according to a timer clock based on a network time. Summary of the invention

[0003] In one aspect of the present disclosure, it is desirable to achieve stable time synchronization.

[0004] A controller according to one aspect of the present disclosure includes: a master clock; a controller clock; a master clock management unit configured to synchronize the master clock with an external global clock and set a master time based on the master clock; a controller clock management unit configured to synchronize the controller clock with the master clock, perform time synchronization to synchronize a controller time based on the controller clock with the master time, and send controller time data indicating the synchronized controller time to at least one local device; a window setting unit configured to set a plurality of time windows corresponding to a plurality of clock cycles of a clock signal used for the time synchronization; a determination unit configured to determine whether one of the plurality of clock cycles has started within one of the plurality of time windows, the one time window corresponding to the one clock cycle; and an update control unit configured to suspend the time synchronization corresponding to the one clock cycle in response to determining that the one clock cycle has not started within the one time window.

[0005] A time synchronization method according to one aspect of the present disclosure includes: synchronizing a master clock in a controller with an external global clock and setting a master time based on the master clock; synchronizing a controller clock in the controller with the master clock and performing time synchronization to synchronize a controller time based on the controller clock with the master time; sending controller time data indicating the synchronized controller time to at least one local device; setting a plurality of time windows corresponding to a plurality of clock cycles of a clock signal used for the time synchronization; determining whether one of the plurality of clock cycles has started within one of the plurality of time windows, the one time window corresponding to the one clock cycle; and suspending the time synchronization corresponding to the one clock cycle in response to determining that the one clock cycle has not started within the one time window.

[0006] According to one aspect of the present disclosure, a computer-readable storage medium stores processor-executable instructions, the processor-executable instructions being used to: synchronize a master clock in a controller with an external global clock and set a master time based on the master clock; synchronize a controller clock in the controller with the master clock and perform time synchronization to synchronize a controller time based on the controller clock with the master time; send controller time data indicating the synchronized controller time to at least one local device; set a plurality of time windows corresponding to a plurality of clock cycles of a clock signal used for the time synchronization; determine whether one of the plurality of clock cycles has started within one of the plurality of time windows, the one time window corresponding to the one clock cycle; and in response to determining that the one clock cycle has not started within the one time window, suspend the time synchronization corresponding to the one clock cycle.

[0007] According to one aspect of the present disclosure, stable time synchronization can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram showing the overall configuration of an example device control system.

[0009] Figure 2 is a diagram illustrating example clock signals that may cause time lags.

[0010] Figure 3 is a diagram illustrating a functional configuration of an example main controller.

[0011] Figure 4 is a diagram showing a hardware configuration of an example computer used as a host controller.

[0012] Figure 5 is a timing diagram illustrating an example operation of the device control system.

[0013] Figure 6 is a diagram showing an example of setting of a time window.

[0014] Figure 7 is a diagram showing an example of monitoring and controlling time synchronization.

[0015] Figure 8 is a diagram showing another example of monitoring and controlling time synchronization. DETAILED DESCRIPTION

[0016] In the following description referring to the accompanying drawings, the same reference numerals are assigned to the same components or similar components having the same functions, and duplicate descriptions are omitted.

[0017] System Overview

[0018] Figure 1 1 is a diagram showing the overall configuration of a device control system 1 according to some examples. The device control system 1 is a mechanism for controlling a local device 3 placed in an actual working environment (i.e., a field). In some examples, the device control system 1 includes at least one main controller 10 and at least one local device 3. Each main controller 10 sends a command to at least one local device 3 to control the local device 3. One main controller 10 corresponds to at least one local device 3. Multiple main controllers 10 may correspond to one local device 3.

[0019] The device control system 1 may include various types of local devices 3 . Figure 1 A mobile robot 4, a fixed robot 5, a numerical control (NC) machine 6, an environmental sensor 7, and a conveyor 8 are shown as examples of local devices 3. The mobile robot 4 is a robot capable of autonomous movement. In some examples, the mobile robot 4 includes an automatic guided vehicle that autonomously moves according to a mobile command, and a robot that performs work on a workpiece according to a work command. For example, the automatic guided vehicle may be an electric AGV. The fixed robot 5 is a robot fixed in a work environment (e.g., a floor). Both the mobile robot 4 and the fixed robot 5 may be a 6-axis vertical multi-joint robot, a 7-axis redundant robot with an additional axis joint, a so-called scalar joint robot, or a so-called parallel link robot. In some examples, both the mobile robot 4 and the fixed robot 5 have an end portion to which a tool corresponding to a processing purpose is attached. Examples of tools include a suction nozzle, a manipulator, a processing tool, and a welding gun. The NC machine 6 is a device that performs processing (e.g., cutting) on ​​a workpiece according to a processing command. The environmental sensor 7 is a device that obtains information about the work environment according to a sensing command. For example, the environmental sensor 7 may be a camera that obtains an image of the work environment or a temperature sensor that obtains the temperature of the work environment. The conveyor 8 is a device that conveys the workpiece according to a conveyance command. Examples of the conveyor 8 include a belt conveyor and a roller conveyor.

[0020] In some examples, each local device 3 includes a device body 20 that performs the main functions of the local device 3, and a local controller 30 that controls the device body 20. The local controller 30 controls the device body 20 according to a command from the main controller 10, and sends a response to the command to the main controller 10. In this example, the local controller 30 is a component of the local device 3. As another example, the local controller 30 itself may exist in the device control system 1 as a local device 3. The local controller 30 that controls the mobile robot 4 or the stationary robot 5 is also referred to as a robot controller.

[0021] In some examples, the device control system 1 synchronizes the time between each main controller 10 and each local device 3 to operate each local device 3 based on periodic communication. When periodic communication is applied, the main controller 10 outputs a command in a given period, and the local device 3 operates based on the command in the period. The local device 3 outputs a response to the main controller 10 in the period, and the main controller 10 obtains the response in the period.

[0022] In some examples, the device control system 1 obtains the global time based on an external global clock, and performs time synchronization based on the global time. For example, the main controller 10 is connected to the time server 9 having a global clock via the first communication network Na, and obtains the global time from the time server 9. The main controller 10 and the local device 3 are connected to each other via the second communication network Nb, and communicate and control according to the synchronized time based on the global time. Various methods such as the Precision Time Protocol (PTP), the Generalized PTP (gPTP), and the Time Sensitive Network (TSN) can be adopted to achieve time synchronization in the device control system 1. The main controller 10 can obtain the global time through a device or method other than the time server 9.

[0023] Both the first communication network Na and the second communication network Nb can be a wired network, a wireless network or a combination thereof. Both the first communication network Na and the second communication network Nb can be constructed in such a way that at least a portion of them includes a mobile communication system. In some examples, the first communication network Na and the second communication network Nb are networks that adopt non-periodic communication. In this example, the device control system 1 utilizes the second communication network Nb (i.e., non-periodic communication) to perform time synchronization between the main controller 10 and the local device 3, and also realizes periodic communication. Periodic communication refers to a communication method that performs information communication at regular time intervals according to a predetermined format. On the other hand, non-periodic communication refers to a communication method that does not require determining the time point of data communication.

[0024] In some examples, a process of performing time synchronization based on a global time in the main controller 10 is considered to stabilize the time synchronization in the device control system 1. For example, in the main controller 10, the clock cycle of the clock signal generated for time synchronization may be disturbed by an unexpected phenomenon. For example, the cause of the unexpected phenomenon includes noise, reflection, and voltage changes occurring on the bus. In the case where the clock cycle has started at an unexpected time point, the time corresponding to the clock cycle may be set at an incorrect time point. As a result, the clock in the main controller 10 may become inaccurate, and jitter (fluctuation of the signal waveform) may appear in an internal signal (e.g., an interrupt signal) generated based on the time indicated by the internal clock.

[0025] Figure 22 is a diagram showing an example clock signal that may cause time lag. The clock signal 200 shown in this example has a clock period T, and the start of each clock period is indicated by a rising edge of the signal. It should be understood that in the present disclosure, the start of a clock period may be indicated by a falling edge of the signal. Figure 2 Clock loss 201, clock offset 202, and noise 203 are shown as examples of clock signal interference. Clock loss refers to a phenomenon in which a clock that should be observed is not observed due to factors such as unstable voltage and amplitude drop. Clock offset is a phenomenon in which a clock is observed at a different time point than the original time point. Noise is an irregular wave that is unrelated to the period and time point of the clock signal.

[0026] In some examples, the device control system 1 has a function for Figure 2 The unexpected phenomena shown in the figure can also stabilize the mechanism of time synchronization. Since the accuracy of time synchronization is improved by this mechanism, various processes (e.g., device control, response analysis, etc.) can be accurately performed based on a unified time in the entire device control system 1. This mechanism can be implemented by applying a controller according to one aspect of the present disclosure to the main controller 10.

[0027] In the present disclosure, a clock refers to a mechanism that indicates various points in a time stream, either discretely or continuously, along the time stream. A timer that indicates the passage of time is a clock. Time is a value that indicates a point in the time stream. Time can be indicated in common units such as hours, minutes, or seconds, or can be indicated by another method such as a counter value or a calendar value (system time). In the present disclosure, for example, "clock-based time" refers to the time indicated by a clock.

[0028] Main controller configuration

[0029] Figure 3 1 is a diagram showing an example of a functional configuration of the main controller 10. In some examples, the main controller 10 has three types of internal clocks for time synchronization. These internal clocks are a master clock Cm and two types of controller clocks: an intermediate controller clock Ci and a reference controller clock Cr. In some examples, the main controller 10 includes a master clock management unit 11, a controller clock management unit 12, and a monitoring unit 13 as functional modules.

[0030] The master clock management unit 11 is a functional module that synchronizes the master clock Cm with an external global clock and sets the master time based on the master clock Cm. In some examples, the master clock management unit 11 receives the global time from the time server 9 via the first communication network (non-periodic communication) Na, performs time synchronization based on the global time, and sets the master time. In some examples, the master clock management unit 11 receives global time data indicating the global time. The master clock management unit 11 generates a master clock signal corresponding to the master time and having a master clock period. The master clock signal is an example of a clock signal used for time synchronization.

[0031] The controller clock management unit 12 is a functional module that synchronizes the controller clock with the master clock Cm and performs time synchronization for setting the controller time based on the controller clock. It can also be said that the time synchronization is a process for synchronizing the controller time with the master time. In some examples, the controller clock management unit 12 includes an intermediate clock management unit 14, a reference clock management unit 15, and a notification unit 16.

[0032] The intermediate clock management unit 14 is a functional module that performs intermediate time synchronization. Intermediate time synchronization is a process of synchronizing the intermediate controller clock Ci with the master clock Cm based on the master clock signal, and setting the intermediate controller time based on the intermediate controller clock Ci. It can also be said that the intermediate time synchronization is a process of synchronizing the intermediate controller time with the master time. Intermediate time synchronization is referred to as "first time synchronization" in Japanese Patent Application No. 2021-030211. The intermediate clock management unit 14 generates an intermediate clock signal corresponding to the intermediate controller time and having an intermediate clock cycle shorter than the master clock cycle. The intermediate clock signal is an example of a clock signal used for time synchronization. It can also be said that the intermediate clock signal is an example of an internal signal corresponding to the controller time and having a given internal cycle. In this case, it can also be said that the intermediate clock management unit 14 generates an internal signal according to an internal cycle shorter than the clock cycle (master clock cycle).

[0033] The reference clock management unit 15 is a functional module that performs reference time synchronization. Reference time synchronization is a process of synchronizing the reference controller clock Cr with the intermediate controller clock Ci based on the intermediate clock signal and setting the reference controller time based on the reference controller clock Cr. It can also be said that reference time synchronization is a process of synchronizing the reference controller time with the intermediate controller time. Reference time synchronization is referred to as "second time synchronization" in Japanese Patent Application No. 2021-030211.

[0034] The notification unit 16 is a functional module that sends the controller time to at least one local device through periodic communication using the second communication network Nb. In some examples, the notification unit 16 sends controller time data indicating the controller time to at least one local device through periodic communication. For example, the notification unit 16 sends a reference controller time. In some examples, the notification unit 16 sends the synchronized reference controller time as the synchronized controller time.

[0035] The monitoring unit 13 is a functional module that monitors the time synchronization performed by the controller clock management unit 12 and intervenes in the time synchronization as needed. In some examples, the monitoring unit 13 includes a window setting unit 17, a determination unit 18, and an update control unit 19.

[0036] The window setting unit 17 is a functional module that sets the following time window: the time window is used to determine whether each clock cycle of the clock signal used for time synchronization has started correctly. For example, the window setting unit 17 sets a plurality of time windows corresponding to a plurality of clock cycles of the clock signal used for time synchronization. The time window can be represented by a time width. The window setting unit 17 sets a time window corresponding to the estimated start time point of each clock cycle. In some examples, the window setting unit 17 generates a time window for determining for each master clock cycle, and a time window for determining for each intermediate clock cycle.

[0037] The determination unit 18 is a functional module that determines whether each clock cycle of a clock signal used for time synchronization has started within a time window. For example, the determination unit 18 determines whether one of the multiple clock cycles has started within one of the multiple time windows. Here, the one time window corresponds to the one clock cycle. In some examples, the determination unit 18 determines whether each master clock cycle has started within a corresponding given time window. The determination unit 18 also determines whether each intermediate clock cycle has started within a corresponding given time window.

[0038] The update control unit 19 is a functional module that suspends the time synchronization corresponding to the clock cycle in response to determining that the clock cycle of the clock signal used for time synchronization does not start within the time window. "Suspending the time synchronization corresponding to the clock cycle" means that time synchronization is not performed in the clock cycle. The fact that a certain clock cycle does not start within the time window means that the clock cycle is abnormal. In the case where time synchronization is suspended, the time synchronization that has been performed for each clock cycle is temporarily stopped, and the time synchronization is resumed from the next or subsequent clock cycle. In some examples, in the case where a certain master clock cycle does not start within the corresponding time window, the update control unit 19 suspends the intermediate time synchronization corresponding to the master clock cycle. In the case where a certain intermediate clock cycle does not start within the corresponding time window, the update control unit 19 suspends the reference time synchronization corresponding to the intermediate clock cycle.

[0039] In the case where the clock cycle of the clock signal used for time synchronization has started within the time window, that is, when the clock cycle is normal, the update control unit 19 causes the controller clock management unit 12 to perform time synchronization corresponding to the clock cycle. In the case where the master clock cycle has started within the corresponding time window, the intermediate clock management unit 14 performs intermediate time synchronization corresponding to the master clock cycle. In the case where the intermediate clock cycle has started within the corresponding time window, the reference clock management unit 15 performs reference time synchronization corresponding to the intermediate clock cycle.

[0040] Figure 4 1 is a diagram showing an example of a hardware configuration of a computer 100 used as a main controller 10. The computer 100 has a circuit 110. The circuit 110 includes a processor 111, a memory 112, a storage device 113, a timer 114, an input / output port 115, and a communication port 116. The number of each of these hardware elements may be one or two or more. The storage device 113 records a program for configuring various functional modules on the computer 100. The storage device 113 is a computer-readable storage medium, such as a hard disk, a non-volatile semiconductor memory, a magnetic disk, or an optical disk. The memory 112 temporarily stores a program loaded from the storage device 113, a calculation result of the processor 111, and the like. The processor 111 implements various functional modules by executing the program in cooperation with the memory 112. The input / output port 115 inputs an electrical signal from a target device 120 and outputs the electrical signal to the target device 120 in response to a command from the processor 111, for example, the target device is a device body, a monitor, or an input device. The input / output port 115 may also be used to supply power to the device body. The communication port 116 performs data communication with another device via a communication network N (eg, at least one of the first communication network Na and the second communication network Nb) according to a command from the processor 111 .

[0041] System Operation

[0042] Will refer to Figures 5 to 8 Example operations of the main controller 10 are described as some examples of the time synchronization method according to the present disclosure. Figure 5 is a timing chart showing an example operation of the main controller 10 as the process flow S1. That is, in some examples, the main controller 10 performs the process flow S1. Figure 6 is a diagram showing an example of setting of a time window. Figure 7 and Figure 8 is a diagram showing an example of monitoring and controlling time synchronization.

[0043] Time Synchronization

[0044] Will refer to Figure 5 The time synchronization in the master controller 10 is described. In step S11, the master clock management unit 11 sets the start time Ts of the master clock Cm, and outputs the start time Ts to the intermediate clock management unit 14. In step S12, the intermediate clock management unit 14 obtains the start time Ts, and also obtains the internal delay Di associated with the intermediate clock management unit 14, and outputs these values ​​to the reference clock management unit 15. In step S13, the reference clock management unit 15 obtains the start time Ts and the internal delay Di, and also obtains the internal delay Dr associated with the reference clock management unit 15.

[0045] In step S14, the master clock management unit 11 sets a master clock period Tm of the master clock signal, and outputs the master clock period Tm to the intermediate clock management unit 14. In step S15, the intermediate clock management unit 14 sets an intermediate clock period Ti of the intermediate clock signal based on the master clock period Tm. In some examples, the intermediate clock management unit 14 sets the intermediate clock period Ti shorter than the master clock period Tm, for example, the intermediate clock period Ti is 1 / N (N is an integer of 2 or greater) of the master clock period Tm. The intermediate clock management unit 14 outputs the intermediate clock period Ti to the reference clock management unit 15. In step S16, the reference clock management unit 15 obtains the intermediate clock period Ti.

[0046] Then, the master clock management unit 11, the intermediate clock management unit 14, and the reference clock management unit 15 cooperate to perform time synchronization between the master clock Cm, the intermediate controller clock Ci, and the reference controller clock Cr. Hereinafter, a series of processes in the master clock management unit 11, the intermediate clock management unit 14, and the reference clock management unit 15 will be described as step S17, step S18, and step S19, respectively.

[0047] In step S17 , the master clock management unit 11 starts time synchronization and outputs a master clock signal having a master clock period Tm to the intermediate clock management unit 14 .

[0048] In step S18, the intermediate clock management unit 14 synchronizes the intermediate controller clock Ci with the master clock Cm based on the master clock signal. In the synchronization, the intermediate clock management unit 14 sets the sum of the start time Ts and the internal delay Di as the initial value of the intermediate controller time. Then, the intermediate clock management unit 14 updates the intermediate controller time by adding the master clock cycle Tm to the previous value of the intermediate controller time in each master clock cycle Tm. Figure 5 Such initialization and updating of the intermediate controller time based on the master clock signal is shown as step S18a. In step S18, the intermediate clock management unit 14 outputs the intermediate clock signal having the intermediate clock period Ti to the reference clock management unit 15. Figure 5 This output is shown as step S18b. It should be noted that in some examples, step S18a and step S18b are independent processes from each other.

[0049] In step S19, the reference clock management unit 15 synchronizes the reference controller clock Cr with the intermediate controller clock Ci based on the intermediate clock signal. In the synchronization, the reference clock management unit 15 sets the sum of the start time Ts, the internal delay Di, and the internal delay Dr (i.e., the sum of the intermediate controller time and the internal delay Dr) as the initial value of the reference controller time. Thereafter, the reference clock management unit 15 updates the reference controller time by adding the intermediate clock cycle Ti to the previous value of the reference controller time in each intermediate clock cycle Ti.

[0050] As shown in steps S18 and S19 , the controller clock management unit 12 (intermediate clock management unit 14 and reference clock management unit 15 ) may also perform time synchronization based on an internal delay in the master controller 10 (eg, at least one of the internal delay Di and the internal delay Dr).

[0051] The notification unit 16 notifies or sends the reference controller time to at least one local device 3 in a given communication cycle. The communication cycle can be longer, shorter or the same as the clock cycle of the clock signal (the main clock cycle Tm or the intermediate clock cycle Ti). The communication cycle can be synchronized with N times or 1 / N (N is an integer of 2 or greater) of the clock cycle, or asynchronous with the clock cycle.

[0052] Time window settings

[0053] Will refer to Figure 6An example of setting a time window is described. The example shows a correct clock signal 210 with a correct clock period T. The process of setting the time window is common to both the master clock signal and the intermediate clock signal, and the clock signal 210 can correspond to each of the master clock signal and the intermediate clock signal. The start of each clock period of the clock signal 210 is indicated by a rising edge of the signal. In some examples, the window setting unit 17 sets the following time width Tw as the time window 300: the time width Tw is from a time point before the estimated start time point 211 of the clock period to a time point after the estimated start time point 211. Figure 6 A set of time windows 300 provided as a window sequence 311 is shown.

[0054] The window setting unit 17 can set the time width Tw based on the period of the clock signal 210. For example, the window setting unit 17 can set the time width Tw consisting of the length of 1 / 4 period before the estimated start time point 211 and the length of 1 / 4 period after the estimated start time point 211 (that is, the time width Tw having a length of 1 / 2 period). Alternatively, the window setting unit 17 can set the internal period of the internal signal corresponding to the controller time as the time width Tw. The internal signal can be a clock signal corresponding to the controller time to be synchronized (for example, an intermediate clock signal) or another interrupt signal generated periodically. Therefore, the internal period can be a clock period of the clock signal (for example, an intermediate clock period) or a period of the interrupt signal.

[0055] The window setting unit 17 may also set a flag indicating whether the time window 300 is set. For example, the window setting unit 17 sets a flag for each of the plurality of time windows. With the flag, the determination unit 18 may recognize the existence of the time window 300 regardless of the start point, end point, and length of the time window 300. Figure 6 In the example of , the value of the flag is a value "OK" indicating that the time window 300 is set, or a value "NG" indicating that the time window 300 is not set. The flag can be represented by two other types of values. When the flag is set, the determination unit 18 refers to the flag at the beginning of the clock cycle to determine whether the clock cycle has started in the time window 300.

[0056] In some examples, in response to determining that a clock cycle has started in the time window 300, the window setting unit 17 can set the end point of the time window 300 based on the start time of the clock cycle. It can be said that such a termination setting is a process of changing the end point according to the initial setting. In the example shown as the window sequence 312, the window setting unit 17 sets (changes) the end point of the time window 300 in response to the start of the clock cycle. The starting point of each time window 300 is unchanged.

[0057] Monitoring time synchronization

[0058] Will refer to Figure 7 An example of monitoring and controlling time synchronization is described. In this example, the controller clock management unit 12 sets the controller time based on the clock signal 220 having a clock period Tp. This example shows a process common to the intermediate clock management unit 14 and the reference clock management unit 15.

[0059] The processing in the case where the clock signal 220 is a master clock signal will be described. Therefore, the clock cycle Tp means the master clock cycle. The intermediate clock management unit 14 performs the intermediate time synchronization corresponding to the master clock cycle 221 starting in the time window 321, and sets the intermediate controller time to Tn. The intermediate clock management unit 14 also performs the intermediate time synchronization corresponding to the master clock cycle 222 starting in the next time window 322, and sets the intermediate controller time to (Tn+Tp). For the next time window 323, the determination unit 18 determines that the master clock cycle 223 does not start in the time window 323, and the update control unit 19 suspends the intermediate time synchronization corresponding to the master clock cycle 223. The master clock cycle 224 has started in the next time window 324, but the update control unit 19 also suspends the intermediate time synchronization corresponding to the master clock cycle 224. The intermediate clock management unit 14 performs the intermediate time synchronization corresponding to the master clock cycle 225 starting in the next time window 325, and sets the intermediate controller time to (Tn+4×Tp). The intermediate clock management unit 14 performs an intermediate time synchronization corresponding to the master clock cycle 226 starting in the next time window 326 and sets the intermediate controller time to (Tn+5×Tp).

[0060] The processing in the case where the clock signal 220 is an intermediate clock signal will be described. Therefore, the clock cycle Tp means the intermediate clock cycle. The reference clock management unit 15 performs reference time synchronization corresponding to the intermediate clock cycle 221 starting in the time window 321, and sets the reference controller time to Tn. The reference clock management unit 15 also performs reference time synchronization corresponding to the intermediate clock cycle 222 starting in the next time window 322, and sets the reference controller time to (Tn+Tp). For the next time window 323, the determination unit 18 determines that the intermediate clock cycle 223 does not start in the time window 323, and the update control unit 19 suspends the reference time synchronization corresponding to the intermediate clock cycle 223. The intermediate clock cycle 224 has started in the next time window 324, but the update control unit 19 also suspends the reference time synchronization corresponding to the intermediate clock cycle 224. The reference clock management unit 15 performs reference time synchronization corresponding to the intermediate clock cycle 225 starting in the next time window 325, and sets the reference controller time to (Tn+4×Tp). The reference clock management unit 15 performs reference time synchronization corresponding to the intervening clock cycle 226 starting in the next time window 326 and sets the reference controller time to (Tn+5×Tp).

[0061] exist Figure 7 In the example of FIG. 2 , in response to determining that the master clock cycle (or intermediate clock cycle) 324 has started in the time window 324, the update control unit 19 may cause the intermediate clock management unit 14 (or the reference clock management unit 15) to perform time synchronization corresponding to the master clock cycle 224. In this case, the intermediate clock management unit 14 performs intermediate time synchronization and sets the intermediate controller time to (Tn+3×Tp) (or the reference clock management unit 15 performs reference time synchronization and sets the reference controller time to (Tn+3×Tp)).

[0062] Will refer to Figure 8 Another example of monitoring and controlling time synchronization is described. In this example, the controller clock management unit 12 sets the controller time based on the clock signal 230 having a clock period Tp. This example also shows processing common to the intermediate clock management unit 14 and the reference clock management unit 15.

[0063] The processing in the case where the clock signal 230 is a master clock signal will be described. Therefore, the clock cycle Tp means the master clock cycle. The intermediate clock management unit 14 performs the intermediate time synchronization corresponding to the master clock cycle 231 starting in the time window 331, and sets the intermediate controller time to Tn. The intermediate clock management unit 14 also performs the intermediate time synchronization corresponding to the master clock cycle 232 starting in the next time window 332, and sets the intermediate controller time to (Tn+Tp). For the next time window 333, the determination unit 18 determines that the master clock cycle 233 does not start in the time window 333, and the update control unit 19 suspends the intermediate time synchronization corresponding to the master clock cycle 233. The intermediate clock management unit 14 performs the intermediate time synchronization corresponding to the master clock cycle 234 starting in the next time window 334, and sets the intermediate controller time to (Tn+3×Tp). The intermediate clock management unit 14 performs intermediate time synchronization corresponding to the master clock cycle 235 starting in the next time window 335, and sets the intermediate controller time to (Tn+4×Tp). Thereafter, noise 236 is generated, but since this time point is outside the time window (because the flag is "NG"), the intermediate clock management unit 14 does not perform intermediate time synchronization. Thereafter, the intermediate clock management unit 14 performs intermediate time synchronization corresponding to the master clock cycle 237 starting in the next time window 336, and sets the intermediate controller time to (Tn+5×Tp).

[0064] The processing in the case where the clock signal 230 is an intermediate clock signal will be described. Therefore, the clock cycle Tp means the intermediate clock cycle. The reference clock management unit 15 performs reference time synchronization corresponding to the intermediate clock cycle 231 starting in the time window 331, and sets the reference controller time to Tn. The reference clock management unit 15 also performs reference time synchronization corresponding to the intermediate clock cycle 232 starting in the next time window 332, and sets the reference controller time to (Tn+Tp). For the next time window 333, the determination unit 18 determines that the intermediate clock cycle 233 does not start in the time window 333, and the update control unit 19 suspends the reference time synchronization corresponding to the intermediate clock cycle 233. The reference clock management unit 15 performs reference time synchronization corresponding to the intermediate clock cycle 234 starting in the next time window 334, and sets the reference controller time to (Tn+3×Tp). The reference clock management unit 15 performs reference time synchronization corresponding to the intervening clock cycle 235 starting in the next time window 335, and sets the reference controller time to (Tn+4×Tp). Thereafter, noise 236 is generated, but since this time point is outside the time window (because the flag is "NG"), the reference clock management unit 15 does not perform reference time synchronization. Thereafter, the reference clock management unit 15 performs reference time synchronization corresponding to the intervening clock cycle 237 starting in the next time window 336, and sets the reference controller time to (Tn+5×Tp).

[0065] exist Figure 8 In the example of FIG. 3 , in response to determining that the master clock cycle (or the intermediate clock cycle) 234 starts in the time window 334, the update control unit 19 may also suspend the time synchronization corresponding to the master clock cycle 234. In this case, the next intermediate time synchronization is performed in the master clock cycle 235 (or the next reference time synchronization is performed in the intermediate clock cycle 235).

[0066] exist Figure 7 In the example of , clock signal 220 includes clock cycle 223 that has not started in time window 323 and clock cycle 224 that has started in time window 324. Figure 8 In the example of , clock signal 230 includes clock cycle 233 that does not start within time window 333 and clock cycle 234 that has started within time window 334. As in these examples, the clock signal may include a first clock cycle that does not start within a first time window and a second clock cycle that has started within a second time window after the first time window. In some examples, update control unit 19 may cause controller clock management unit 12 (intermediate clock management unit 14 or reference clock management unit 15) to perform time synchronization corresponding to the second clock cycle (clock cycle 224 or clock cycle 234).

[0067] exist Figure 7 In the example of , clock signal 220 includes clock cycle 223 that has not started within time window 323, clock cycle 224 that has started within time window 324, and clock cycle 225 that has started within time window 325. Figure 8 In the example of , the clock signal 230 includes a clock cycle 233 that has not started within the time window 333, a clock cycle 234 that has started within the time window 334, and a clock cycle 235 that has started within the time window 335. In other words, the clock signal may include a first clock cycle that has not started within the first time window, a second clock cycle that has started within a second time window after the first time window, and a third clock cycle that has started within a third time window after the second time window. In some examples, the update control unit 19 may also suspend the time synchronization corresponding to the second clock cycle (clock cycle 224 or clock cycle 234) and cause the controller clock management unit 12 (intermediate clock management unit 14 or reference clock management unit 15) to perform the time synchronization corresponding to the third clock cycle (clock cycle 225 or clock cycle 235).

[0068] In response to the update control unit 19 suspending time synchronization, the controller clock management unit 12 may perform alternative time synchronization based on an internal cycle without using the clock cycle. As an example, in response to the update control unit 19 suspending intermediate time synchronization, the intermediate clock management unit 14 may perform a first alternative time synchronization based on an intermediate clock cycle without using a main clock cycle. As another example, in response to the update control unit 19 suspending reference time synchronization, the reference clock management unit 15 may perform a second alternative time synchronization based on a cycle of a related interrupt signal without using an intermediate clock cycle. As described above, the controller clock management unit 12 (intermediate clock management unit 14 or reference clock management unit 15) may perform time synchronization (intermediate time synchronization or reference time synchronization) based on the start time of the main clock Cm and based on at least one of the clock cycle and the internal cycle. Alternatively, in response to time synchronization being suspended, the controller clock management unit 12 may perform an alternative time synchronization based on a value estimated based on the clock cycle.

[0069] program

[0070] Each functional module of the main controller 10 is implemented by reading the time synchronization program on the processor 111 or the memory 112 and causing the processor 111 to execute the program. The time synchronization program includes codes for implementing each functional module of the main controller 10. The processor 111 operates the input / output port 115 or the communication port 116 according to the time synchronization program, and reads and writes data in the memory 112 or the storage device 113. Such processing implements each functional module of the device control system 1.

[0071] The time synchronization program may be provided after being fixedly stored on a non-transitory storage medium such as a CD-ROM, a DVD-ROM, or a semiconductor memory. Alternatively, the time synchronization program may be provided as a data signal superimposed on a carrier wave via a communication network.

[0072] As described above, a controller according to one aspect of the present disclosure includes a master clock; a controller clock; a master clock management unit, configured to synchronize the master clock with an external global clock and set a master time based on the master clock; a controller clock management unit, configured to synchronize the controller clock with the master clock, perform time synchronization to synchronize the controller time based on the controller clock with the master time, and send controller time data indicating the synchronized controller time to at least one local device; a window setting unit, configured to set a plurality of time windows corresponding to a plurality of clock cycles of a clock signal used for the time synchronization; a determination unit, configured to determine whether one of the plurality of clock cycles has started within one of the plurality of time windows, the one time window corresponding to the one clock cycle; an update control unit, configured to suspend the time synchronization corresponding to the one clock cycle in response to determining that the one clock cycle has not started within the one time window.

[0073] According to one aspect of the present disclosure, a time synchronization method includes: synchronizing a master clock in a controller with an external global clock and setting a master time based on the master clock; synchronizing a controller clock in the controller with the master clock and performing time synchronization to synchronize a controller time based on the controller clock with the master time; sending controller time data indicating the synchronized controller time to at least one local device; setting a plurality of time windows corresponding to a plurality of clock cycles of a clock signal used for the time synchronization; determining whether one of the plurality of clock cycles has started within one of the plurality of time windows, the one time window corresponding to the one clock cycle; in response to determining that the one clock cycle has not started within the one time window, pausing the time synchronization corresponding to the one clock cycle.

[0074] According to one aspect of the present disclosure, a computer-readable storage medium stores processor-executable instructions, which are used to: synchronize a master clock in a controller with an external global clock and set a master time based on the master clock; synchronize a controller clock in the controller with the master clock and perform time synchronization to synchronize a controller time based on the controller clock with the master time; send controller time data indicating the synchronized controller time to at least one local device; set a plurality of time windows corresponding to a plurality of clock cycles of a clock signal used for the time synchronization; determine whether one of the plurality of clock cycles has started within one of the plurality of time windows, the one time window corresponding to the one clock cycle; in response to determining that the one clock cycle has not started within the one time window, suspend the time synchronization corresponding to the one clock cycle.

[0075] According to such an example, since time synchronization is not performed when the start time point of a clock signal of one cycle is inappropriate, it is possible to avoid a situation where the controller time deviates from the master time, and the time synchronization can be stabilized.

[0076] In some examples, the master clock management unit may be configured to: receive global time data from a time server via aperiodic communication, wherein the global time data indicates a global time based on the external global clock; set the master time based on the global time, and the controller clock management unit may be configured to send the controller time data to the at least one local device via periodic communication. In this case, the controller time synchronized with the global time acquired via aperiodic communication is notified or sent to the local device via periodic communication. In other words, even when the global time is acquired via aperiodic communication, the local time in each of the one or more local devices controlled based on periodic communication may be appropriately set.

[0077] In some examples, the master clock management unit may be further configured to generate a master clock signal corresponding to the master time and having a plurality of master clock cycles as a clock signal for the time synchronization, the determination unit may be configured to determine whether one of the plurality of master clock cycles has started within the one time window, wherein the update control unit may be configured to suspend the time synchronization corresponding to the one master clock cycle in response to determining that the one master clock cycle has not started within the one time window. By not performing time synchronization when the start time point of the master clock is inappropriate, the situation where the controller time deviates from the master time can be avoided, and the time synchronization can be stabilized.

[0078] In some examples, the controller clock may include an intermediate controller clock and a reference controller clock, and the controller clock management unit may include: an intermediate clock management unit, configured to synchronize the intermediate controller clock with the master clock based on the master clock signal, perform intermediate time synchronization to set the intermediate controller time based on the intermediate controller clock, and generate an intermediate clock signal corresponding to the intermediate controller time and having multiple intermediate clock cycles as a clock signal for the time synchronization, wherein each of the multiple intermediate clock cycles is shorter than the master clock cycle; a reference clock management unit, configured to synchronize the reference controller clock with the intermediate controller clock based on the intermediate clock signal, and perform reference time synchronization to synchronize the reference controller time based on the reference controller clock with the intermediate controller time; and a notification unit, configured to send controller time data indicating the synchronized reference controller time to the at least one local device, wherein the synchronized reference controller time serves as the synchronized controller time. By synchronizing the time in the controller with the master time in two stages using an intermediate clock cycle that is shorter than the master clock cycle, the influence of fluctuations in the master clock signal can be more reliably suppressed, achieving robust time synchronization.

[0079] In some examples, the determination unit may also be configured to determine whether one of the plurality of intervening clock cycles has started within the one time window, and the update control unit may be configured to suspend the reference time synchronization corresponding to the one intervening clock cycle in response to determining that the one intervening clock cycle has not started within the one time window. By performing this determination in each of the master clock cycle and the intervening clock cycle, time synchronization may be more reliably stabilized.

[0080] In some examples, the multiple time windows may include a first time window and a second time window after the first time window, the clock signal may include: a first clock cycle that does not start within the first time window; and a second clock cycle that has started within the second time window, and the update control unit may also be configured to: suspend the first time synchronization corresponding to the first clock cycle; and enable the controller clock management unit to perform the second time synchronization corresponding to the second clock cycle. In this case, time synchronization can be quickly restored when it is estimated that the clock cycle returns to normal.

[0081] In some examples, the multiple time windows may include a first time window, a second time window after the first time window, and a third time window after the second time window, the clock signal may include: a first clock cycle that has not started in the first time window; a second clock cycle that has started in the second time window; and a third clock cycle that has started in the third time window, and the update control unit may also be configured to: suspend the first time synchronization corresponding to the first clock cycle; suspend the second time synchronization corresponding to the second clock cycle; and cause the controller clock management unit to perform the third time synchronization corresponding to the third clock cycle. In this case, since the time synchronization is restored when the estimated clock cycle reliably returns to normal, the time synchronization can be more reliably stabilized.

[0082] In some examples, the window setting unit may be configured to set a time window corresponding to the estimated start time point of each clock cycle in the plurality of clock cycles. Since a time window is set for each clock cycle, each clock cycle can be reliably monitored.

[0083] In some examples, the window setting unit can be configured to set the following time width as the time window for each clock cycle in the multiple clock cycles: the time width is from a time point before the estimated start time point of the clock cycle to a time point after the estimated start time point. By setting the time window in this way, the appropriate (correct) clock cycle can be reliably obtained.

[0084] In some examples, the window setting unit may be configured to set an internal period of an internal signal corresponding to the controller time as the time width. Since the length of the time window is set in consideration of the period of the internal signal, time synchronization may be controlled so as not to affect processing based on the internal signal.

[0085] In some examples, the window setting unit can be configured to set the end point of the one time window based on the start time of the clock cycle in response to determining that the one clock cycle has started within the one time window. By setting the end point of the time window in response to identifying the start of the appropriate (correct) clock cycle, the appropriate clock cycle can continue to be acquired.

[0086] In some examples, the window setting unit may be configured to set a flag indicating whether the time window is set for each of the multiple time windows, and the determination unit may be configured to refer to the flag at the start time of the clock cycle to determine whether the one clock cycle has started within the one time window. Since referring to the flag is sufficient to determine whether the clock cycle is appropriate, the determination process can be simplified.

[0087] In some examples, the controller clock management unit can be configured to: generate an internal signal corresponding to the controller time and having a plurality of internal cycles based on the clock cycle; perform the time synchronization based on a start time and based on at least one cycle selected from the group consisting of the plurality of clock cycles and the plurality of internal cycles, wherein the start time is based on a master clock. Accurate time synchronization can be achieved by generating an internal signal based on the cycle of the clock signal and performing synchronization using at least one of the two cycles.

[0088] In some examples, the controller clock management unit can also be configured to perform alternative time synchronization based on at least one cycle selected from the plurality of internal cycles instead of selecting any one of the plurality of clock cycles in response to time synchronization being suspended. Through such processing, time synchronization can be performed even when the appropriate (accurate) master time cannot be obtained.

[0089] In some examples, the controller clock management unit can be configured to generate the internal signal according to the internal cycle, wherein each of the multiple internal cycles is shorter than the clock cycle. By using the internal signal, the time in the controller can be synchronized with the master time at a shorter interval, so the influence of the fluctuation of the clock signal can be more reliably suppressed, and robust time synchronization can be performed.

[0090] In some examples, the controller clock management unit can be configured to perform the time synchronization based on internal delays in the controller.Since the internal delays of the controller are taken into account, the controller time can be synchronized with the master time more accurately.

[0091] In some examples, a device control system may include the above controller and at least one local device. In this case, in the device control system, the situation where the controller time deviates from the master time can be avoided, and the time synchronization can be stabilized.

[0092] In some examples, at least one of the at least one local device may be a robot controller. In this case, in a device control system having a robot controller, a situation where the controller time deviates from the master time can be avoided, and time synchronization can be stabilized.

[0093] According to another aspect of the present disclosure, a controller includes: a master clock management unit, configured to synchronize a master clock in the controller with an external global clock, set a master time based on the master clock, and generate a master clock signal corresponding to the master time and having a master clock cycle; an intermediate clock management unit, configured to synchronize an intermediate controller clock in the controller with the master clock based on the master clock signal, perform intermediate time synchronization to set an intermediate controller time based on the intermediate controller clock, and generate an intermediate clock signal corresponding to the intermediate controller time and having an intermediate clock cycle, wherein the intermediate clock cycle is shorter than the master clock cycle; a reference clock management unit, configured to synchronize a reference controller clock in the controller with the intermediate controller clock based on the intermediate clock signal, and perform reference time synchronization to set a reference controller time based on the reference controller clock.

[0094] A time synchronization method according to another aspect of the present disclosure includes: synchronizing a master clock in a controller with an external global clock, setting a master time based on the master clock, and generating a master clock signal corresponding to the master time and having a master clock cycle; synchronizing an intermediate controller clock in the controller with the master clock based on the master clock signal, performing intermediate time synchronization to set the intermediate controller time based on the intermediate controller clock, and generating an intermediate clock signal corresponding to the intermediate controller time and having an intermediate clock cycle, wherein the intermediate clock cycle is shorter than the master clock cycle; synchronizing a reference controller clock in the controller with the intermediate controller clock based on the intermediate clock signal, and performing reference time synchronization to set the reference controller time based on the reference controller clock.

[0095] According to another aspect of the present disclosure, a computer-readable storage medium storing processor-executable instructions is provided, wherein the processor-executable instructions are used to: synchronize a master clock in a controller with an external global clock, set a master time based on the master clock, and generate a master clock signal corresponding to the master time and having a master clock cycle; synchronize an intermediate controller clock in the controller with the master clock based on the master clock signal, perform intermediate time synchronization to set an intermediate controller time based on the intermediate controller clock, and generate an intermediate clock signal corresponding to the intermediate controller time and having an intermediate clock cycle, wherein the intermediate clock cycle is shorter than the master clock cycle; synchronize a reference controller clock in the controller with the intermediate controller clock based on the intermediate clock signal, and perform reference time synchronization to set a reference controller time based on the reference controller clock.

[0096] According to such an example, by synchronizing the time in the controller with the master time in two stages using an intermediate clock cycle shorter than the master clock cycle, the influence of fluctuations of the master clock signal can be more reliably suppressed, achieving robust time synchronization.

[0097] Additional Examples

[0098] It should be understood that not all aspects, advantages and features described herein will necessarily be achieved by or included in any one particular example. In fact, having described and illustrated various examples herein, it will be apparent that other examples may be modified in arrangement and details may be omitted.

[0099] In the above example, the main controller 10 includes two controller clocks, namely, the intermediate controller clock Ci and the reference controller clock Cr. However, the main controller 10 may include the reference controller clock Cr without the intermediate controller clock Ci. In this example, the controller clock management unit 12 performs time synchronization including: synchronizing the reference controller clock Cr with the master clock Cm based on the master clock signal, and setting the reference controller time based on the reference controller clock Cr.

[0100] In other words, in some examples, the controller clock may be a reference controller clock, and the controller clock management unit may be further configured to: synchronize the reference controller clock with the master clock based on the master clock signal; perform time synchronization to set the reference controller time based on the reference controller clock; and send controller time data indicating the synchronized reference controller time as the synchronized controller time to at least one local device. Since the intermediary controller clock is omitted, time synchronization can be stabilized while simplifying the controller configuration.

[0101] The hardware configuration of the system is not limited to the example of implementing each functional module by executing a program. In some examples, at least a portion of the above functional modules can be configured by a logic circuit dedicated to performing the function, or can be configured by an application-specific integrated circuit (ASIC) integrating a logic circuit.

[0102] The process of the method performed by at least one processor is not limited to the above examples. For example, some of the above steps or processes may be omitted or performed in a different order. In addition, two or more of the above steps may be combined, or a portion of the above steps may be modified or deleted. Alternatively, other steps other than the above steps may be performed.

[0103] When the magnitude relationship between two numerical values ​​is compared in a computer system or a computer, either of the two criteria of "greater than or equal to" and "greater than" may be used, and either of the two criteria of "less than or equal to" and "less than" may be used.

[0104] We claim all modifications and variations that fall within the spirit and scope of the subject matter claimed herein.

[0105] Regarding the above example, the following appendix is ​​provided as further explanation.

[0106] (Appendix 1) A controller comprising:

[0107] a master clock management unit configured to synchronize a master clock in the controller with an external global clock and to set a master time based on the master clock;

[0108] a controller clock management unit configured to synchronize a controller clock in the controller with the master clock and to perform time synchronization to set a controller time based on the controller clock;

[0109] a determining unit configured to determine whether each clock cycle of the clock signal used for the time synchronization has started within a given time window; and

[0110] The update control unit is configured to suspend the time synchronization corresponding to the clock cycle in response to determining that the clock cycle does not start within the time window.

[0111] (Appendix 2) The controller according to Appendix 1,

[0112] Wherein, the main clock management unit is configured as:

[0113] receiving a global time based on the external global clock from a time server through aperiodic communication; and

[0114] setting the master time based on the global time,

[0115] The controller clock management unit is further configured to send the controller time to at least one local device through periodic communication.

[0116] (Appendix 3) A controller according to Appendix 1 or 2,

[0117] The master clock management unit is further configured to generate a master clock signal corresponding to the master time and having a master clock period as a clock signal for the time synchronization.

[0118] The determining unit is configured to determine whether each master clock cycle has started within the given time window corresponding to the master clock cycle, and

[0119] The update control unit is configured to suspend the time synchronization corresponding to the master clock cycle in response to determining that the master clock cycle does not start within the corresponding time window.

[0120] (Appendix 4) The controller according to Appendix 3,

[0121] Wherein, the controller clock includes an intermediate controller clock and a reference controller clock,

[0122] Wherein, the controller clock management unit includes:

[0123] an intermediate clock management unit configured to synchronize the intermediate controller clock with the master clock based on the master clock signal, perform a first time synchronization (intermediate time synchronization) to set an intermediate controller time based on the intermediate controller clock, and generate an intermediate clock signal corresponding to the intermediate controller time and having an intermediate clock cycle as a clock signal for the time synchronization, wherein the intermediate clock cycle is shorter than the master clock cycle; and

[0124] A reference clock management unit is configured to synchronize the reference controller clock with the intermediate controller clock based on the intermediate clock signal, and perform a second time synchronization (reference time synchronization) to set a reference controller time based on the reference controller clock.

[0125] (Appendix 5) The controller according to Appendix 4,

[0126] The determining unit is further configured to determine whether each intervening clock cycle has started within a time window corresponding to the intervening clock cycle.

[0127] The update control unit is configured to suspend the second time synchronization (reference time synchronization) corresponding to the intermediate clock cycle in response to determining that the intermediate clock cycle does not start within the corresponding time window.

[0128] (Appendix 6) The controller according to Appendix 3,

[0129] Wherein, the controller clock is a reference controller clock,

[0130] Wherein, the controller clock management unit is configured as follows:

[0131] synchronizing the reference controller clock with the master clock based on the master clock signal; and

[0132] The time synchronization is performed to set a reference controller time based on the reference controller clock.

[0133] (Appendix 7) A controller according to any one of Appendices 1 to 6,

[0134] Wherein, the clock signal includes:

[0135] a first clock cycle that does not start within the first time window; and

[0136] a second clock cycle which has started within a second time window after said first time window,

[0137] The update control unit is further configured to enable the controller clock management unit to perform time synchronization corresponding to the second clock cycle.

[0138] (Appendix 8) A controller according to any one of Appendices 1 to 6,

[0139] Wherein, the clock signal includes:

[0140] a first clock cycle that does not start within the first time window;

[0141] a second clock cycle having started within a second time window after said first time window; and

[0142] a third clock cycle which has started in a third time window after said second time window,

[0143] Wherein, the update control unit is further configured to:

[0144] further suspending time synchronization corresponding to the second clock cycle; and

[0145] The controller clock management unit is caused to perform time synchronization corresponding to the third clock cycle.

[0146] (Appendix 9) The controller according to any one of Appendices 1 to 8 further includes: a window setting unit configured to set a time window corresponding to an estimated start time point of each clock cycle.

[0147] (Appendix 10) A controller according to Appendix 9, wherein the window setting unit is configured to set the following time width as the time window: the time width is from a time point before the estimated start time point of the clock cycle to a time point after the estimated start time point.

[0148] (Appendix 11) The controller according to Appendix 10, wherein the window setting unit is configured to set an internal cycle of an internal signal corresponding to the controller time as the time width.

[0149] (Appendix 12) A controller according to any one of Appendices 9 to 11, wherein the window setting unit is configured to set the end point of the time window based on the start time of the clock cycle in response to determining that the clock cycle has started within the time window.

[0150] (Appendix 13) A controller according to any one of Appendices 9 to 12,

[0151] The window setting unit is further configured to set a flag indicating whether the time window is set.

[0152] The determining unit is configured to refer to the flag at the start time of the clock cycle to determine whether the clock cycle has started within the time window.

[0153] (Appendix 14) A controller according to any one of Appendices 1 to 13,

[0154] Wherein, the controller clock management unit is configured as follows:

[0155] Based on the clock cycle, generating an internal signal corresponding to the controller time and having a given internal cycle; and

[0156] The time synchronization is performed based on a start time according to a master clock and based on at least one of the clock cycle and the internal cycle.

[0157] (Appendix 15) The controller according to Appendix 14, wherein the controller clock management unit is further configured to perform alternative time synchronization based on the internal cycle without using the clock cycle in response to time synchronization being suspended.

[0158] (Appendix 16) The controller according to Appendix 14 or 15, wherein the controller clock management unit is configured to generate the internal signal according to the internal cycle, wherein the internal cycle is shorter than the main clock cycle.

[0159] (Appendix 17) A controller according to any one of Appendices 1 to 16, wherein the controller clock management unit is configured to perform the time synchronization also based on an internal delay in the controller.

[0160] (Appendix 18) An equipment control system comprising:

[0161] A controller as described in any one of Appendices 1 to 17; and

[0162] At least one local device.

[0163] (Appendix 19) The device control system according to Appendix 18, wherein at least one of the at least one local device is a robot controller.

[0164] (Appendix 20) A time synchronization method comprising:

[0165] Synchronizing a master clock in the controller with an external global clock and setting a master time based on the master clock;

[0166] synchronizing a controller clock in the controller with the master clock and performing time synchronization to set the controller time based on the controller clock;

[0167] determining whether each clock cycle of a clock signal used for said time synchronization has started within a given time window; and

[0168] The time synchronization corresponding to clock cycles that do not start within the time window is suspended.

[0169] (Appendix 21) A time synchronization program, the time synchronization program is used to cause a computer to perform the following operations:

[0170] Synchronizing a master clock in the controller with an external global clock and setting a master time based on the master clock;

[0171] synchronizing a controller clock in the controller with the master clock and performing time synchronization to set the controller time based on the controller clock;

[0172] determining whether each clock cycle of a clock signal used for said time synchronization has started within a given time window; and

[0173] The time synchronization corresponding to clock cycles that do not start within the time window is suspended.

[0174] (Appendix 22) A controller comprising:

[0175] a master clock management unit configured to synchronize a master clock in the controller with an external global clock, set a master time based on the master clock, and generate a master clock signal corresponding to the master time and having a master clock period;

[0176] an intermediate clock management unit configured to synchronize an intermediate controller clock in the controller with the master clock based on the master clock signal, perform a first time synchronization (intermediate time synchronization) to set an intermediate controller time based on the intermediate controller clock, and generate an intermediate clock signal corresponding to the intermediate controller time and having an intermediate clock period, wherein the intermediate clock period is shorter than the master clock period; and

[0177] The reference clock management unit is configured to synchronize a reference controller clock in the controller with the intermediate controller clock based on the intermediate clock signal, and perform a second time synchronization (reference time synchronization) to set a reference controller time based on the reference controller clock.

[0178] (Appendix 23) A time synchronization method comprising:

[0179] Synchronize a master clock in the controller with an external global clock, set a master time based on the master clock, and generate a master clock signal corresponding to the master time and having a master clock period;

[0180] synchronizing an intermediate controller clock in the controller with the master clock based on the master clock signal, performing a first time synchronization (intermediate time synchronization) to set an intermediate controller time based on the intermediate controller clock, and generating an intermediate clock signal corresponding to the intermediate controller time and having an intermediate clock period, wherein the intermediate clock period is shorter than the master clock period; and

[0181] A reference controller clock in the controller is synchronized with the intermediate controller clock based on the intermediate clock signal, and a second time synchronization (reference time synchronization) is performed to set a reference controller time based on the reference controller clock.

[0182] (Appendix 24) A time synchronization program, the time synchronization program is used to cause a computer to perform the following operations:

[0183] Synchronize a master clock in the controller with an external global clock, set a master time based on the master clock, and generate a master clock signal corresponding to the master time and having a master clock period;

[0184] synchronizing an intermediate controller clock in the controller with the master clock based on the master clock signal, performing a first time synchronization (intermediate time synchronization) to set an intermediate controller time based on the intermediate controller clock, and generating an intermediate clock signal corresponding to the intermediate controller time and having an intermediate clock period, wherein the intermediate clock period is shorter than the master clock period; and

[0185] A reference controller clock in the controller is synchronized with the intermediate controller clock based on the intermediate clock signal, and a second time synchronization (reference time synchronization) is performed to set a reference controller time based on the reference controller clock.

Claims

1. A controller, include: Master clock; Controller clock; a master clock management unit configured to synchronize the master clock with an external global clock and set a master time based on the master clock; a controller clock management unit configured to synchronize the controller clock with the master clock, perform time synchronization to synchronize a controller time based on the controller clock with the master time, and send controller time data indicating the synchronized controller time to at least one local device; a window setting unit configured to set a plurality of time windows corresponding to a plurality of clock cycles of a clock signal used for the time synchronization; a determining unit configured to determine whether one of the multiple clock cycles has started within one of the multiple time windows, the one time window corresponding to the one clock cycle; as well as The update control unit is configured to suspend the time synchronization corresponding to the one clock cycle in response to determining that the one clock cycle does not start within the one time window.

2. The controller according to claim 1, in, The master clock management unit is configured as follows: receiving global time data from a time server through aperiodic communication, the global time data indicating a global time based on the external global clock; and setting the master time based on the global time, The controller clock management unit is configured to send the controller time data to the at least one local device through periodic communication.

3. The controller according to claim 1, in, The master clock management unit is further configured to generate a master clock signal corresponding to the master time and having a plurality of master clock cycles as a clock signal for the time synchronization. The determining unit is configured to determine whether one of the plurality of master clock cycles has started within the one time window, and The update control unit is configured to suspend the time synchronization corresponding to the one master clock cycle in response to determining that the one master clock cycle does not start within the one time window.

4. The controller according to claim 3, in, The controller clock includes an intermediate controller clock and a reference controller clock, Wherein, the controller clock management unit includes: an intermediate clock management unit configured to synchronize the intermediate controller clock with the master clock based on the master clock signal, perform intermediate time synchronization to set an intermediate controller time based on the intermediate controller clock, and generate an intermediate clock signal corresponding to the intermediate controller time and having a plurality of intermediate clock cycles as a clock signal for the time synchronization, wherein each of the plurality of intermediate clock cycles is shorter than the master clock cycle; a reference clock management unit configured to synchronize the reference controller clock with the intermediate controller clock based on the intermediate clock signal, and to perform reference time synchronization to synchronize a reference controller time based on the reference controller clock with the intermediate controller time; and A notification unit is configured to send the controller time data indicating a synchronized reference controller time to the at least one local device, wherein the synchronized reference controller time serves as the synchronized controller time.

5. The controller according to claim 4, in, The determining unit is further configured to determine whether an intervening clock cycle of the plurality of intervening clock cycles has started within the one time window, The update control unit is configured to suspend synchronization of the reference time corresponding to the one intermediate clock cycle in response to determining that the one intermediate clock cycle does not start within the one time window.

6. The controller according to claim 3, in, The controller clock is a reference controller clock, Wherein, the controller clock management unit is configured as follows: synchronizing the reference controller clock with the master clock based on the master clock signal; performing the time synchronization to synchronize a reference controller time based on the reference controller clock with the master time; and The controller time data indicating a synchronized reference controller time is sent to the at least one local device, wherein the synchronized reference controller time serves as the synchronized controller time.

7. A controller according to any one of claims 1 to 6, in, The multiple time windows include a first time window and a second time window after the first time window, Wherein, the clock signal includes: a first clock cycle that does not start within the first time window; and a second clock cycle which has started within said second time window, Wherein, the update control unit is further configured to: suspending a first time synchronization corresponding to the first clock cycle; and The controller clock management unit is enabled to perform a second time synchronization corresponding to the second clock cycle.

8. A controller according to any one of claims 1 to 6, in, The plurality of time windows include a first time window, a second time window after the first time window, and a third time window after the second time window, Wherein, the clock signal includes: a first clock cycle that does not start within the first time window; a second clock cycle that has started within said second time window; and a third clock cycle which has started in said third time window, Wherein, the update control unit is further configured to: suspending synchronization of a first time corresponding to the first clock cycle; pausing a second time synchronization corresponding to the second clock cycle; and The controller clock management unit is enabled to perform a third time synchronization corresponding to the third clock cycle.

9. A controller according to any one of claims 1 to 6, in, The window setting unit is configured to set, for each clock cycle of the plurality of clock cycles, a time window corresponding to an estimated start time point of the clock cycle.

10. The controller according to claim 9, in, The window setting unit is configured to set, for each of the plurality of clock cycles, a time width from a time point before an estimated start time point of the clock cycle to a time point after the estimated start time point as the time window.

11. The controller according to claim 10, in, The window setting unit is configured to set an internal cycle of an internal signal corresponding to the controller time as the time width.

12. The controller according to claim 9, in, The window setting unit is configured to, in response to determining that the one clock cycle has started within the one time window, set an end point of the one time window based on a start time of the clock cycle.

13. The controller according to claim 9, in, The window setting unit is configured to set a flag indicating whether the time window is set for each of the plurality of time windows, The determining unit is configured to refer to the flag at the start time of the clock cycle to determine whether the clock cycle has started within the time window.

14. A controller according to any one of claims 1 to 6, in, The controller clock management unit is configured to: Based on the clock cycle, generating an internal signal corresponding to the controller time and having a plurality of internal cycles; as well as The time synchronization is performed based on a start time and based on at least one cycle selected from the group consisting of the plurality of clock cycles and the plurality of internal cycles, wherein the start time is based on the master clock.

15. The controller according to claim 14, in, The controller clock management unit is further configured to, in response to the time synchronization being suspended, perform an alternative time synchronization based on at least one cycle selected from the plurality of internal cycles instead of selecting any one of the plurality of clock cycles.

16. The controller according to claim 14, in, The controller clock management unit is configured to generate the internal signal at the internal cycle, wherein each of the plurality of internal cycles is shorter than the clock cycle.

17. A controller according to any one of claims 1 to 6, in, The controller clock management unit is configured to perform the time synchronization also based on internal delays in the controller.

18. An equipment control system comprising the controller according to any one of claims 1 to 6, and further comprising at least one local equipment.

19. A time synchronization method, include: Synchronizing a master clock in the controller with an external global clock and setting a master time based on the master clock; synchronizing a controller clock in the controller with the master clock, and performing time synchronization to synchronize a controller time based on the controller clock with the master time; sending controller time data indicating the synchronized controller time to at least one local device; Setting a plurality of time windows corresponding to a plurality of clock cycles of a clock signal used for the time synchronization; determining whether one of the plurality of clock cycles has started within one of the plurality of time windows, the one time window corresponding to the one clock cycle; as well as In response to determining that the one clock cycle does not start within the one time window, suspending the time synchronization corresponding to the one clock cycle.

20. A computer-readable storage medium storing processor-executable instructions, wherein the instructions, when executed by a processor, cause the processor to: Synchronizing a master clock in the controller with an external global clock and setting a master time based on the master clock; synchronizing a controller clock in the controller with the master clock, and performing time synchronization to synchronize a controller time based on the controller clock with the master time; sending controller time data indicating the synchronized controller time to at least one local device; Setting a plurality of time windows corresponding to a plurality of clock cycles of a clock signal used for the time synchronization; determining whether one of the plurality of clock cycles has started within one of the plurality of time windows, the one time window corresponding to the one clock cycle; as well as In response to determining that the one clock cycle does not start within the one time window, suspending the time synchronization corresponding to the one clock cycle.

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